From 7f033d3c1f4604d303da237fbc7a38ee503416ad Mon Sep 17 00:00:00 2001 From: KrystalDelusion Date: Thu, 7 Jul 2022 11:10:33 +1200 Subject: More tests in memlib/generate.py Covers most of the todo list, at least functionally. Some minor issues with not always using hardware features. --- tests/memlib/memlib_lut.v | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'tests/memlib/memlib_lut.v') diff --git a/tests/memlib/memlib_lut.v b/tests/memlib/memlib_lut.v index 1f20a110a..2685d2337 100644 --- a/tests/memlib/memlib_lut.v +++ b/tests/memlib/memlib_lut.v @@ -9,6 +9,7 @@ module RAM_LUT( ); parameter INIT = 0; +parameter OPTION_INIT = "UNDEFINED"; parameter PORT_RW_CLK_POL = 1; reg [3:0] mem [0:15]; @@ -16,7 +17,13 @@ reg [3:0] mem [0:15]; integer i; initial for (i = 0; i < 16; i += 1) - mem[i] = INIT[i*4+:4]; + case (OPTION_INIT) + "NONE": mem[i] = mem[i]; //? + "ZERO": mem[i] = 4'h0; + "ANY": mem[i] = INIT[i*4+:4]; + "NO_UNDEF": mem[i] = INIT[i*4+:4]; + "UNDEFINED": mem[i] = 4'hx; + endcase assign PORT_R_RD_DATA = mem[PORT_R_ADDR]; assign PORT_RW_RD_DATA = mem[PORT_RW_ADDR]; -- cgit v1.2.3