From 982a11c709b4b363f85ae52a127f8a98bda30a3f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= Date: Fri, 6 May 2022 16:30:56 +0200 Subject: Add memory_libmap tests. --- tests/memlib/memlib_wide_write.v | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 tests/memlib/memlib_wide_write.v (limited to 'tests/memlib/memlib_wide_write.v') diff --git a/tests/memlib/memlib_wide_write.v b/tests/memlib/memlib_wide_write.v new file mode 100644 index 000000000..afed6d00c --- /dev/null +++ b/tests/memlib/memlib_wide_write.v @@ -0,0 +1,29 @@ +module RAM_WIDE_WRITE #( + parameter [63:0] INIT = 64'hx, + parameter PORT_A_RD_WIDTH = 2, + parameter PORT_A_WR_WIDTH = 8, + parameter PORT_A_WR_EN_WIDTH = 2 +) ( + input PORT_A_CLK, + input PORT_A_RD_EN, + input [5:0] PORT_A_ADDR, + output reg [1:0] PORT_A_RD_DATA, + input [1:0] PORT_A_WR_EN, + input [7:0] PORT_A_WR_DATA +); + +reg [63:0] mem; + +initial mem = INIT; + +always @(posedge PORT_A_CLK) begin + if (PORT_A_RD_EN) + PORT_A_RD_DATA <= mem[{PORT_A_ADDR[5:1],1'b0}+:2]; + if (PORT_A_WR_EN[0]) + mem[{PORT_A_ADDR[5:3],3'b000}+:4] <= PORT_A_WR_DATA[3:0]; + if (PORT_A_WR_EN[1]) + mem[{PORT_A_ADDR[5:3],3'b100}+:4] <= PORT_A_WR_DATA[7:4]; +end + +endmodule + -- cgit v1.2.3