From e75ca29b19e230bc829a369c7de9cbadb629f5a7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Dec 2019 11:26:54 -0800
Subject: Add test: 'Warning: ignoring initial value on non-register: \o'

---
 tests/sat/initval.ys | 10 ++++++++++
 1 file changed, 10 insertions(+)

(limited to 'tests/sat/initval.ys')

diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys
index 2079d2f34..337aa9343 100644
--- a/tests/sat/initval.ys
+++ b/tests/sat/initval.ys
@@ -2,3 +2,13 @@ read_verilog -sv initval.v
 proc;;
 
 sat -seq 10 -prove-asserts
+
+design -reset
+read_verilog -icells <<EOT
+module top(input clk, i, output o, p);
+(* init = 1'bx *)
+wire p = o;
+$_DFF_P_ dff (.C(clk), .D(i), .Q(o));
+endmodule
+EOT
+sat -seq 1
-- 
cgit v1.2.3


From 61a1f3f49b7bd0478b92c0933c487af5803c53f9 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Dec 2019 23:48:09 -0800
Subject: Make testcase clearer with \o having its own init

---
 tests/sat/initval.ys | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'tests/sat/initval.ys')

diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys
index 337aa9343..6cb68a8d3 100644
--- a/tests/sat/initval.ys
+++ b/tests/sat/initval.ys
@@ -6,6 +6,8 @@ sat -seq 10 -prove-asserts
 design -reset
 read_verilog -icells <<EOT
 module top(input clk, i, output o, p);
+(* init = 1'b0 *)
+wire o;
 (* init = 1'bx *)
 wire p = o;
 $_DFF_P_ dff (.C(clk), .D(i), .Q(o));
-- 
cgit v1.2.3


From 4a805108776f563bcd7550d1331a73a50512fbe2 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Dec 2019 23:52:05 -0800
Subject: Even more obvious testcase

---
 tests/sat/initval.ys | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

(limited to 'tests/sat/initval.ys')

diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys
index 6cb68a8d3..1436724b0 100644
--- a/tests/sat/initval.ys
+++ b/tests/sat/initval.ys
@@ -5,12 +5,11 @@ sat -seq 10 -prove-asserts
 
 design -reset
 read_verilog -icells <<EOT
-module top(input clk, i, output o, p);
-(* init = 1'b0 *)
-wire o;
-(* init = 1'bx *)
-wire p = o;
-$_DFF_P_ dff (.C(clk), .D(i), .Q(o));
+module top(input clk, i, output [1:0] o);
+(* init = 2'bx0 *)
+wire [1:0] o;
+assign o[1] = o[0];
+$_DFF_P_ dff (.C(clk), .D(i), .Q(o[0]));
 endmodule
 EOT
 sat -seq 1
-- 
cgit v1.2.3