From 6c84341f22b2758181164e8d5cddd23e3589c90b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 2 Jul 2015 11:14:30 +0200 Subject: Fixed trailing whitespaces --- tests/simple/loops.v | 6 +++--- tests/simple/mem2reg.v | 2 +- tests/simple/omsp_dbg_uart.v | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'tests/simple') diff --git a/tests/simple/loops.v b/tests/simple/loops.v index 77cdcd8e2..d7743a422 100644 --- a/tests/simple/loops.v +++ b/tests/simple/loops.v @@ -41,10 +41,10 @@ begin keysched_last_key_i = key_i; else keysched_last_key_i = keysched_new_key_o; - + if (round == 0 && addroundkey_start_i) begin - data_var = addroundkey_data_i; + data_var = addroundkey_data_i; round_key_var = key_i; round_data_var = round_key_var ^ data_var; next_addroundkey_data_reg = round_data_var; @@ -66,7 +66,7 @@ begin end else if (addroundkey_round == round && keysched_ready_o) begin - data_var = addroundkey_data_i; + data_var = addroundkey_data_i; round_key_var = keysched_new_key_o; round_data_var = round_key_var ^ data_var; next_addroundkey_data_reg = round_data_var; diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v index bed5528d4..40f490b75 100644 --- a/tests/simple/mem2reg.v +++ b/tests/simple/mem2reg.v @@ -47,7 +47,7 @@ endmodule // http://www.reddit.com/r/yosys/comments/28d9lx/problem_with_concatenation_of_two_dimensional/ module mem2reg_test3( input clk, input [8:0] din_a, output reg [7:0] dout_a, output [7:0] dout_b); -reg [7:0] dint_c [0:7]; +reg [7:0] dint_c [0:7]; always @(posedge clk) begin {dout_a[0], dint_c[3]} <= din_a; diff --git a/tests/simple/omsp_dbg_uart.v b/tests/simple/omsp_dbg_uart.v index dc8860dee..569a28adb 100644 --- a/tests/simple/omsp_dbg_uart.v +++ b/tests/simple/omsp_dbg_uart.v @@ -22,13 +22,13 @@ always @(uart_state or mem_burst) RX_DATA : uart_state_nxt = RX_SYNC; default : uart_state_nxt = RX_CMD; endcase - + always @(posedge dbg_clk or posedge dbg_rst) if (dbg_rst) uart_state <= RX_SYNC; else if (xfer_done | mem_burst) uart_state <= uart_state_nxt; assign cmd_valid = (uart_state==RX_CMD) & xfer_done; assign xfer_done = uart_state!=RX_SYNC; - + endmodule -- cgit v1.2.3