From acd47bbd52d11216b883b99f3e17ae4ffbd5f4a3 Mon Sep 17 00:00:00 2001 From: Xiretza Date: Wed, 16 Sep 2020 17:59:37 +0200 Subject: tests: Centralize test collection and Makefile generation --- tests/techmap/mem_simple_4x1_runtest.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests/techmap/mem_simple_4x1_runtest.sh') diff --git a/tests/techmap/mem_simple_4x1_runtest.sh b/tests/techmap/mem_simple_4x1_runtest.sh index e2c6303da..9c41fa56a 100644 --- a/tests/techmap/mem_simple_4x1_runtest.sh +++ b/tests/techmap/mem_simple_4x1_runtest.sh @@ -1,6 +1,6 @@ #!/bin/bash -set -ev +set -e ../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v -- cgit v1.2.3