From 88f59770932720cfc1e987c98e53faedd7388ed8 Mon Sep 17 00:00:00 2001
From: tux3 <barrdetwix@gmail.com>
Date: Wed, 5 Jun 2019 00:47:54 +0200
Subject: SystemVerilog support for implicit named port connections

This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
---
 tests/tools/autotest.sh | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

(limited to 'tests/tools/autotest.sh')

diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index 920474a84..0a511f29c 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -89,6 +89,13 @@ done
 
 compile_and_run() {
 	exe="$1"; output="$2"; shift 2
+	ext=${1##*.}
+	if [ "$ext" == "sv" ]; then
+		language_gen="-g2012"
+	else
+		language_gen="-g2005"
+	fi
+
 	if $use_modelsim; then
 		altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; )
 		/opt/altera/$altver/modelsim_ase/bin/vlib work
@@ -99,7 +106,7 @@ compile_and_run() {
 		/opt/Xilinx/Vivado/$xilver/bin/xvlog $xinclude_opts -d outfile=\"$output\" "$@"
 		/opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench
 	else
-		iverilog $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@"
+		iverilog $language_gen $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@"
 		vvp -n "$exe"
 	fi
 }
@@ -110,7 +117,7 @@ for fn
 do
 	bn=${fn%.*}
 	ext=${fn##*.}
-	if [[ "$ext" != "v" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then
+	if [[ "$ext" != "v" ]] && [[ "$ext" != "sv" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then
 		echo "Invalid argument: $fn" >&2
 		exit 1
 	fi
@@ -123,6 +130,10 @@ do
 		echo -n "Test: $bn "
 	fi
 
+	if [ "$ext" == sv ]; then
+		frontend="$frontend -sv"
+	fi
+
 	rm -f ${bn}.{err,log,skip}
 	mkdir -p ${bn}.out
 	rm -rf ${bn}.out/*
-- 
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