From c18b23f0559f2232186ce3b97b4ffb64877abd5c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 9 Jul 2019 20:58:59 +0200 Subject: Add tests/various/async.{sh,v} Signed-off-by: Clifford Wolf --- tests/various/async.v | 82 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) create mode 100644 tests/various/async.v (limited to 'tests/various/async.v') diff --git a/tests/various/async.v b/tests/various/async.v new file mode 100644 index 000000000..229b5b939 --- /dev/null +++ b/tests/various/async.v @@ -0,0 +1,82 @@ +`define MAXQ 2 +module uut ( + input clk, + input d, r, e, + output [`MAXQ:0] q +); + reg q0; + always @(posedge clk) begin + if (r) + q0 <= 0; + else if (e) + q0 <= d; + end + + reg q1; + always @(posedge clk, posedge r) begin + if (r) + q1 <= 0; + else if (e) + q1 <= d; + end + + reg q2; + always @(posedge clk, negedge r) begin + if (!r) + q2 <= 0; + else if (!e) + q2 <= d; + end + + assign q = {q2, q1, q0}; +endmodule + +`ifdef TESTBENCH +module testbench; + reg clk; + always #5 clk = (clk === 1'b0); + + reg d, r, e; + + wire [`MAXQ:0] q_uut; + uut uut (.clk(clk), .d(d), .r(r), .e(e), .q(q_uut)); + + wire [`MAXQ:0] q_syn; + syn syn (.clk(clk), .d(d), .r(r), .e(e), .q(q_syn)); + + task printq; + reg [5*8-1:0] msg; + begin + msg = "OK"; + if (q_uut != q_syn) msg = "SYN"; + $display("%6t %b %b %s", $time, q_uut, q_syn, msg); + if (msg != "OK") $stop; + end + endtask + + initial if(0) begin + $dumpfile("async.vcd"); + $dumpvars(0, testbench); + end + + initial begin + @(posedge clk); + d <= 0; + r <= 0; + e <= 0; + @(posedge clk); + e <= 1; + @(posedge clk); + e <= 0; + repeat (10000) begin + @(posedge clk); + printq; + d <= $random; + r <= $random; + e <= $random; + end + $display("OK"); + $finish; + end +endmodule +`endif -- cgit v1.2.3 From 513862148211401fe71fb7966c81773042665acd Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 9 Jul 2019 22:21:25 +0200 Subject: Improve tests/various/async, disable failing ffl test Signed-off-by: Clifford Wolf --- tests/various/async.v | 36 +++++++++++++++++++++++++++++++----- 1 file changed, 31 insertions(+), 5 deletions(-) (limited to 'tests/various/async.v') diff --git a/tests/various/async.v b/tests/various/async.v index 229b5b939..1e32a06b5 100644 --- a/tests/various/async.v +++ b/tests/various/async.v @@ -32,9 +32,23 @@ module uut ( endmodule `ifdef TESTBENCH +module \$ff #( + parameter integer WIDTH = 1 +) ( + input [WIDTH-1:0] D, + output reg [WIDTH-1:0] Q +); + wire sysclk = testbench.sysclk; + always @(posedge sysclk) + Q <= D; +endmodule + module testbench; + reg sysclk; + always #5 sysclk = (sysclk === 1'b0); + reg clk; - always #5 clk = (clk === 1'b0); + always @(posedge sysclk) clk = (clk === 1'b0); reg d, r, e; @@ -44,13 +58,25 @@ module testbench; wire [`MAXQ:0] q_syn; syn syn (.clk(clk), .d(d), .r(r), .e(e), .q(q_syn)); + wire [`MAXQ:0] q_prp; + prp prp (.clk(clk), .d(d), .r(r), .e(e), .q(q_prp)); + + wire [`MAXQ:0] q_a2s; + a2s a2s (.clk(clk), .d(d), .r(r), .e(e), .q(q_a2s)); + + wire [`MAXQ:0] q_ffl; + ffl ffl (.clk(clk), .d(d), .r(r), .e(e), .q(q_ffl)); + task printq; reg [5*8-1:0] msg; begin msg = "OK"; - if (q_uut != q_syn) msg = "SYN"; - $display("%6t %b %b %s", $time, q_uut, q_syn, msg); - if (msg != "OK") $stop; + if (q_uut !== q_syn) msg = "SYN"; + if (q_uut !== q_prp) msg = "PRP"; + if (q_uut !== q_a2s) msg = "A2S"; + // if (q_uut !== q_ffl) msg = "FFL"; + $display("%6t %b %b %b %b %b %s", $time, q_uut, q_syn, q_prp, q_a2s, q_ffl, msg); + if (msg != "OK") $finish; end endtask @@ -75,7 +101,7 @@ module testbench; r <= $random; e <= $random; end - $display("OK"); + $display("PASS"); $finish; end endmodule -- cgit v1.2.3 From 9546ccdbd348b1dc056884a536246801cdf1c4f1 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 9 Jul 2019 22:44:39 +0200 Subject: Fix tests/various/async FFL test Signed-off-by: Clifford Wolf --- tests/various/async.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests/various/async.v') diff --git a/tests/various/async.v b/tests/various/async.v index 1e32a06b5..c27e30c4b 100644 --- a/tests/various/async.v +++ b/tests/various/async.v @@ -74,7 +74,7 @@ module testbench; if (q_uut !== q_syn) msg = "SYN"; if (q_uut !== q_prp) msg = "PRP"; if (q_uut !== q_a2s) msg = "A2S"; - // if (q_uut !== q_ffl) msg = "FFL"; + if (q_uut !== q_ffl) msg = "FFL"; $display("%6t %b %b %b %b %b %s", $time, q_uut, q_syn, q_prp, q_a2s, q_ffl, msg); if (msg != "OK") $finish; end -- cgit v1.2.3