From a650d9079fa4732a6d118f2764d5abc2522a6b37 Mon Sep 17 00:00:00 2001
From: Zachary Snow <zach@zachjs.com>
Date: Mon, 30 May 2022 16:45:39 -0400
Subject: verilog: fix width/sign detection for functions

---
 tests/verilog/func_tern_hint.ys | 4 ++++
 1 file changed, 4 insertions(+)
 create mode 100644 tests/verilog/func_tern_hint.ys

(limited to 'tests/verilog/func_tern_hint.ys')

diff --git a/tests/verilog/func_tern_hint.ys b/tests/verilog/func_tern_hint.ys
new file mode 100644
index 000000000..ab8a1e032
--- /dev/null
+++ b/tests/verilog/func_tern_hint.ys
@@ -0,0 +1,4 @@
+read_verilog -sv func_tern_hint.sv
+proc
+opt
+sat -verify -seq 1 -prove-asserts -show-all
-- 
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