From 1ec5994100510d6fb9e18ff7234ede496f831a51 Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Thu, 25 Feb 2021 15:53:55 -0500 Subject: verilog: fix handling of nested ifdef directives - track depth so we know whether to consider higher-level elsifs - error on unmatched endif/elsif/else --- tests/verilog/include_self.v | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 tests/verilog/include_self.v (limited to 'tests/verilog/include_self.v') diff --git a/tests/verilog/include_self.v b/tests/verilog/include_self.v new file mode 100644 index 000000000..23ffc7104 --- /dev/null +++ b/tests/verilog/include_self.v @@ -0,0 +1,30 @@ +`ifdef GUARD_5 +module top; + wire x; +endmodule + +`elsif GUARD_4 +`define GUARD_5 +`include "include_self.v" + +`elsif GUARD_3 +`define GUARD_4 +`include "include_self.v" + +`elsif GUARD_2 +`define GUARD_3 +`include "include_self.v" + +`elsif GUARD_1 +`define GUARD_2 +`include "include_self.v" + +`elsif GUARD_0 +`define GUARD_1 +`include "include_self.v" + +`else +`define GUARD_0 +`include "include_self.v" + +`endif -- cgit v1.2.3