From b1a8e73a609d3065f1caf7a230529443b54295bc Mon Sep 17 00:00:00 2001 From: Zachary Snow Date: Wed, 3 Mar 2021 14:36:19 -0500 Subject: sv: fix some edge cases for unbased unsized literals - Fix explicit size cast of unbased unsized literals - Fix unbased unsized literal bound directly to port - Output `is_unsized` flag in `dumpAst` --- tests/verilog/unbased_unsized.ys | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 tests/verilog/unbased_unsized.ys (limited to 'tests/verilog/unbased_unsized.ys') diff --git a/tests/verilog/unbased_unsized.ys b/tests/verilog/unbased_unsized.ys new file mode 100644 index 000000000..e1bc99c64 --- /dev/null +++ b/tests/verilog/unbased_unsized.ys @@ -0,0 +1,7 @@ +read_verilog -sv unbased_unsized.sv +hierarchy +proc +flatten +opt -full +select -module top +sat -verify -seq 1 -tempinduct -prove-asserts -show-all -- cgit v1.2.3