From 2e911bc806d0a54e4d7e84ef2218ff088ea20b5f Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 4 May 2020 12:18:02 -0700
Subject: test: add failing test

---
 tests/verilog/upto.ys | 5 +++++
 1 file changed, 5 insertions(+)
 create mode 100644 tests/verilog/upto.ys

(limited to 'tests/verilog')

diff --git a/tests/verilog/upto.ys b/tests/verilog/upto.ys
new file mode 100644
index 000000000..d87f4424e
--- /dev/null
+++ b/tests/verilog/upto.ys
@@ -0,0 +1,5 @@
+read_verilog <<EOT
+module top(input [-128:-65] a);
+endmodule
+EOT
+dump
-- 
cgit v1.2.3


From 004999218f52cd5a1308023a474ee608b842a5b7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 5 May 2020 08:01:27 -0700
Subject: techlibs/common: more robustness when *_WIDTH = 0

---
 tests/verilog/upto.ys | 1 -
 1 file changed, 1 deletion(-)

(limited to 'tests/verilog')

diff --git a/tests/verilog/upto.ys b/tests/verilog/upto.ys
index d87f4424e..2f3394761 100644
--- a/tests/verilog/upto.ys
+++ b/tests/verilog/upto.ys
@@ -2,4 +2,3 @@ read_verilog <<EOT
 module top(input [-128:-65] a);
 endmodule
 EOT
-dump
-- 
cgit v1.2.3


From b11cf67a8170ee830beedadc7156c4e83e4f1134 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 11 May 2020 10:30:20 -0700
Subject: Setup tests/verilog properly

---
 tests/verilog/.gitignore  |  3 +++
 tests/verilog/run-test.sh | 20 ++++++++++++++++++++
 2 files changed, 23 insertions(+)
 create mode 100644 tests/verilog/.gitignore
 create mode 100755 tests/verilog/run-test.sh

(limited to 'tests/verilog')

diff --git a/tests/verilog/.gitignore b/tests/verilog/.gitignore
new file mode 100644
index 000000000..b48f808a1
--- /dev/null
+++ b/tests/verilog/.gitignore
@@ -0,0 +1,3 @@
+/*.log
+/*.out
+/run-test.mk
diff --git a/tests/verilog/run-test.sh b/tests/verilog/run-test.sh
new file mode 100755
index 000000000..ea56b70f0
--- /dev/null
+++ b/tests/verilog/run-test.sh
@@ -0,0 +1,20 @@
+#!/usr/bin/env bash
+set -e
+{
+echo "all::"
+for x in *.ys; do
+	echo "all:: run-$x"
+	echo "run-$x:"
+	echo "	@echo 'Running $x..'"
+	echo "	@../../yosys -ql ${x%.ys}.log $x"
+done
+for s in *.sh; do
+	if [ "$s" != "run-test.sh" ]; then
+		echo "all:: run-$s"
+		echo "run-$s:"
+		echo "	@echo 'Running $s..'"
+		echo "	@bash $s"
+	fi
+done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk
-- 
cgit v1.2.3


From e5ce5a4fd532f35cf8dd625b97aa426e4661e119 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 11 May 2020 11:05:19 -0700
Subject: tests: add #2042 testcase

---
 tests/verilog/bug2042.ys | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 tests/verilog/bug2042.ys

(limited to 'tests/verilog')

diff --git a/tests/verilog/bug2042.ys b/tests/verilog/bug2042.ys
new file mode 100644
index 000000000..009e2c20c
--- /dev/null
+++ b/tests/verilog/bug2042.ys
@@ -0,0 +1,12 @@
+logger -expect error "Non-ANSI style task/function arguments not currently supported" 1
+read_verilog <<EOT
+module Task_Test_Top
+(
+);
+
+    task SomeTaskName(a)
+    endtask
+
+endmodule
+EOT
+
-- 
cgit v1.2.3


From 0d2c33f9f4f8ca1bb507e3e688e0c7d372f0247b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 13 May 2020 10:11:45 -0700
Subject: tests: update/extend task argument tests

---
 tests/verilog/bug2042-sv.ys | 34 ++++++++++++++++++++++++++++++++++
 tests/verilog/bug2042.ys    |  3 +--
 2 files changed, 35 insertions(+), 2 deletions(-)
 create mode 100644 tests/verilog/bug2042-sv.ys

(limited to 'tests/verilog')

diff --git a/tests/verilog/bug2042-sv.ys b/tests/verilog/bug2042-sv.ys
new file mode 100644
index 000000000..9a0d419c8
--- /dev/null
+++ b/tests/verilog/bug2042-sv.ys
@@ -0,0 +1,34 @@
+read_verilog -sv <<EOT
+module Task_Test_Top
+(
+input a,
+output b
+);
+
+    task SomeTaskName(a);
+       b = ~a;
+    endtask
+
+    always @*
+        SomeTaskName(a);
+
+    assert property (b == ~a);
+
+endmodule
+EOT
+proc
+sat -verify -prove-asserts
+
+
+design -reset
+logger -expect error "syntax error, unexpected TOK_ENDTASK, expecting ';'" 1
+read_verilog -sv <<EOT
+module Task_Test_Top
+(
+);
+
+    task SomeTaskName(a)
+    endtask
+
+endmodule
+EOT
diff --git a/tests/verilog/bug2042.ys b/tests/verilog/bug2042.ys
index 009e2c20c..f9d8e2837 100644
--- a/tests/verilog/bug2042.ys
+++ b/tests/verilog/bug2042.ys
@@ -1,4 +1,4 @@
-logger -expect error "Non-ANSI style task/function arguments not currently supported" 1
+logger -expect error "task/function argument direction missing" 1
 read_verilog <<EOT
 module Task_Test_Top
 (
@@ -9,4 +9,3 @@ module Task_Test_Top
 
 endmodule
 EOT
-
-- 
cgit v1.2.3


From 56a5b1d2daf1b244990d81f32183034071ebd185 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 14 May 2020 08:36:36 -0700
Subject: test: add another testcase as per @nakengelhardt

---
 tests/verilog/bug2042-sv.ys | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

(limited to 'tests/verilog')

diff --git a/tests/verilog/bug2042-sv.ys b/tests/verilog/bug2042-sv.ys
index 9a0d419c8..e815d7fc5 100644
--- a/tests/verilog/bug2042-sv.ys
+++ b/tests/verilog/bug2042-sv.ys
@@ -20,6 +20,31 @@ proc
 sat -verify -prove-asserts
 
 
+design -reset
+read_verilog -sv <<EOT
+module Task_Test_Top
+(
+input a,
+output b, c
+);
+
+    task SomeTaskName(x, output y, z);
+       y = ~x;
+       z = x;
+    endtask
+
+    always @*
+        SomeTaskName(a, b, c);
+
+    assert property (b == ~a);
+    assert property (c == a);
+
+endmodule
+EOT
+proc
+sat -verify -prove-asserts
+
+
 design -reset
 logger -expect error "syntax error, unexpected TOK_ENDTASK, expecting ';'" 1
 read_verilog -sv <<EOT
-- 
cgit v1.2.3


From e7fd8912f041462bf044b6c93aa4b4db786d01c7 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 14 May 2020 16:09:41 -0700
Subject: tests: attributes before task enable

---
 tests/verilog/task_attr.ys | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 tests/verilog/task_attr.ys

(limited to 'tests/verilog')

diff --git a/tests/verilog/task_attr.ys b/tests/verilog/task_attr.ys
new file mode 100644
index 000000000..d6e75f85f
--- /dev/null
+++ b/tests/verilog/task_attr.ys
@@ -0,0 +1,28 @@
+read_verilog <<EOT
+module top;
+    task foo;
+    endtask
+
+    always @*
+        (* foo *) foo;
+
+    initial
+        if (0) $info("bar");
+endmodule
+EOT
+# Since task enables are not an RTLIL object,
+#   any attributes on their AST get dropped
+select -assert-none a:* a:src %d
+
+
+logger -expect error "syntax error, unexpected ATTR_BEGIN" 1
+design -reset
+read_verilog <<EOT
+module top;
+    task foo;
+    endtask
+
+    always @*
+        foo (* foo *);
+endmodule
+EOT
-- 
cgit v1.2.3


From 589775538c23975d79aa21050557a37b76acb1dd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 11 May 2020 09:33:11 -0700
Subject: tests: add #2037 testcase

---
 tests/verilog/bug2037.ys | 9 +++++++++
 1 file changed, 9 insertions(+)
 create mode 100644 tests/verilog/bug2037.ys

(limited to 'tests/verilog')

diff --git a/tests/verilog/bug2037.ys b/tests/verilog/bug2037.ys
new file mode 100644
index 000000000..afe92022e
--- /dev/null
+++ b/tests/verilog/bug2037.ys
@@ -0,0 +1,9 @@
+logger -expect warning "Attribute\(s\) attached to null statement\. Ignoring\." 1
+logger -expect-no-warnings
+read_verilog <<EOT
+module test ();
+	localparam y = 1;
+	always @(*)
+		if (y) (* foo *) ;
+endmodule
+EOT
-- 
cgit v1.2.3


From 29d84339bf9ec8f1d2be3fa20f81843f3ee08324 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 11 May 2020 10:26:08 -0700
Subject: tests: add an generate-else test too

---
 tests/verilog/bug2037.ys | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

(limited to 'tests/verilog')

diff --git a/tests/verilog/bug2037.ys b/tests/verilog/bug2037.ys
index afe92022e..42c4b8f5d 100644
--- a/tests/verilog/bug2037.ys
+++ b/tests/verilog/bug2037.ys
@@ -7,3 +7,37 @@ module test ();
 		if (y) (* foo *) ;
 endmodule
 EOT
+
+
+design -reset
+logger -expect warning "Attribute\(s\) attached to null statement\. Ignoring\." 3 # cumulative
+logger -expect-no-warnings
+read_verilog <<EOT
+module test ();
+	localparam y = 1;
+	always @(*)
+		if (y) (* foo *) ; else (* bar *) ;
+endmodule
+EOT
+
+
+design -reset
+logger -expect warning "Attribute\(s\) attached to null statement\. Ignoring\." 4 # cumulative
+logger -expect-no-warnings
+read_verilog <<EOT
+module test ();
+	localparam y = 1;
+    generate if (y) (* foo *) ; endgenerate
+endmodule
+EOT
+
+
+design -reset
+logger -expect warning "Attribute\(s\) attached to null statement\. Ignoring\." 6 # cumulative
+logger -expect-no-warnings
+read_verilog <<EOT
+module test ();
+	localparam y = 1;
+    generate if (y) (* foo *) ; else (* bar *); endgenerate
+endmodule
+EOT
-- 
cgit v1.2.3


From 1c117ac0236517d0d7150dcc8d1fed19288bd692 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 14 May 2020 10:46:40 -0700
Subject: verilog: do not warn for attributes on null statements

---
 tests/verilog/bug2037.ys | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'tests/verilog')

diff --git a/tests/verilog/bug2037.ys b/tests/verilog/bug2037.ys
index 42c4b8f5d..eb4f0fac4 100644
--- a/tests/verilog/bug2037.ys
+++ b/tests/verilog/bug2037.ys
@@ -1,4 +1,3 @@
-logger -expect warning "Attribute\(s\) attached to null statement\. Ignoring\." 1
 logger -expect-no-warnings
 read_verilog <<EOT
 module test ();
@@ -7,10 +6,10 @@ module test ();
 		if (y) (* foo *) ;
 endmodule
 EOT
+select -assert-none a:* a:src %d
 
 
 design -reset
-logger -expect warning "Attribute\(s\) attached to null statement\. Ignoring\." 3 # cumulative
 logger -expect-no-warnings
 read_verilog <<EOT
 module test ();
@@ -19,10 +18,10 @@ module test ();
 		if (y) (* foo *) ; else (* bar *) ;
 endmodule
 EOT
+select -assert-none a:* a:src %d
 
 
 design -reset
-logger -expect warning "Attribute\(s\) attached to null statement\. Ignoring\." 4 # cumulative
 logger -expect-no-warnings
 read_verilog <<EOT
 module test ();
@@ -30,10 +29,10 @@ module test ();
     generate if (y) (* foo *) ; endgenerate
 endmodule
 EOT
+select -assert-none a:*
 
 
 design -reset
-logger -expect warning "Attribute\(s\) attached to null statement\. Ignoring\." 6 # cumulative
 logger -expect-no-warnings
 read_verilog <<EOT
 module test ();
@@ -41,3 +40,4 @@ module test ();
     generate if (y) (* foo *) ; else (* bar *); endgenerate
 endmodule
 EOT
+select -assert-none a:*
-- 
cgit v1.2.3


From 95dcd7e785db44fd664fb7d5ac380fa642d0981c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 14 May 2020 16:32:14 -0700
Subject: test: add attribute-before-stmt test from @nakengelhardt

---
 tests/verilog/bug2037.ys | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

(limited to 'tests/verilog')

diff --git a/tests/verilog/bug2037.ys b/tests/verilog/bug2037.ys
index eb4f0fac4..4b629ba92 100644
--- a/tests/verilog/bug2037.ys
+++ b/tests/verilog/bug2037.ys
@@ -41,3 +41,18 @@ module test ();
 endmodule
 EOT
 select -assert-none a:*
+
+
+design -reset
+read_verilog <<EOT
+module test ();
+	localparam y = 1;
+	reg x = 1'b0;
+	always @(*) begin
+		if (y)
+			(* foo *) x <= 1'b1;
+		else
+			(* bar *) x = 1'b0;
+	end
+endmodule
+EOT
-- 
cgit v1.2.3


From 60aa8049157eb4f0417022182aeb8c1581efe404 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 25 May 2020 10:07:58 -0700
Subject: tests: fix some test warnings

---
 tests/verilog/bug2042-sv.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests/verilog')

diff --git a/tests/verilog/bug2042-sv.ys b/tests/verilog/bug2042-sv.ys
index e815d7fc5..91989f412 100644
--- a/tests/verilog/bug2042-sv.ys
+++ b/tests/verilog/bug2042-sv.ys
@@ -2,7 +2,7 @@ read_verilog -sv <<EOT
 module Task_Test_Top
 (
 input a,
-output b
+output reg b
 );
 
     task SomeTaskName(a);
-- 
cgit v1.2.3