From 975aaf190f0bbbeacc253397ccada6889c69e8f7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 09:24:19 -0700 Subject: Add xilinx_srl test --- tests/xilinx/xilinx_srl.ys | 67 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 tests/xilinx/xilinx_srl.ys (limited to 'tests/xilinx/xilinx_srl.ys') diff --git a/tests/xilinx/xilinx_srl.ys b/tests/xilinx/xilinx_srl.ys new file mode 100644 index 000000000..4e3c44a98 --- /dev/null +++ b/tests/xilinx/xilinx_srl.ys @@ -0,0 +1,67 @@ +read_verilog xilinx_srl.v +design -save read + +design -copy-to model $__XILINX_SHREG_ +hierarchy -top xilinx_srl_static_test +prep +design -save gold + +techmap +xilinx_srl -fixed +opt + +# stat +# show -width +select -assert-count 1 t:$_DFF_P_ +select -assert-count 2 t:$__XILINX_SHREG_ + +design -stash gate + +design -import gold -as gold +design -import gate -as gate +design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ +prep + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +dump gate +sat -verify -prove-asserts -show-ports -seq 5 miter + +#design -load gold +#stat + +#design -load gate +#stat + +########## + +design -load read +design -copy-to model $__XILINX_SHREG_ +hierarchy -top xilinx_srl_variable_test +prep +design -save gold + +simplemap t:$dff t:$dffe +xilinx_srl -variable +opt + +#stat +# show -width +# write_verilog -noexpr -norename +select -assert-count 1 t:$_DFF_P_ +select -assert-count 2 t:$__XILINX_SHREG_ + +design -stash gate + +design -import gold -as gold +design -import gate -as gate +design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ +prep + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports -seq 5 miter + +# design -load gold +# stat + +# design -load gate +# stat -- cgit v1.2.3 From 2e9e745efa03363f9f0d5cc47696401d55a8e5d2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 28 Aug 2019 09:26:08 -0700 Subject: Do not simplemap for variable test --- tests/xilinx/xilinx_srl.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests/xilinx/xilinx_srl.ys') diff --git a/tests/xilinx/xilinx_srl.ys b/tests/xilinx/xilinx_srl.ys index 4e3c44a98..b8df0e55a 100644 --- a/tests/xilinx/xilinx_srl.ys +++ b/tests/xilinx/xilinx_srl.ys @@ -40,14 +40,14 @@ hierarchy -top xilinx_srl_variable_test prep design -save gold -simplemap t:$dff t:$dffe xilinx_srl -variable opt #stat # show -width # write_verilog -noexpr -norename -select -assert-count 1 t:$_DFF_P_ +select -assert-count 1 t:$dff +select -assert-count 1 t:$dff r:WIDTH=1 %i select -assert-count 2 t:$__XILINX_SHREG_ design -stash gate -- cgit v1.2.3