From 6d021f04d4363c971d3a4d40948f89a4699f45f3 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Fri, 10 Feb 2023 19:17:16 +0100 Subject: tests: Fix path of yosys invocation in xprop tests For now xprop test failures are still expected and ignored, but without this change, they did not even run unless the yosys build was in path. --- tests/xprop/test.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests/xprop/test.py') diff --git a/tests/xprop/test.py b/tests/xprop/test.py index 84ad0a1f4..df355e7dc 100644 --- a/tests/xprop/test.py +++ b/tests/xprop/test.py @@ -47,7 +47,7 @@ if "clean" in steps: def yosys(command): - subprocess.check_call(["yosys", "-Qp", command]) + subprocess.check_call(["../../../yosys", "-Qp", command]) def remove(file): try: -- cgit v1.2.3 From 2a68eee5f164c1c028a386b090b63ca1e5ba5611 Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 13 Feb 2023 14:03:08 +0100 Subject: xprop: Test fixes and abort on test failure Use `$finish(0)` to silently exit even when using recent iverlog versions. Run `write_verilog -noexpr` before `write_verilog` as the latter can modify the design. This also enables checking the tests results, as xprop should be in a state where the existing tests pass. --- tests/xprop/test.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests/xprop/test.py') diff --git a/tests/xprop/test.py b/tests/xprop/test.py index df355e7dc..507e4e9e2 100644 --- a/tests/xprop/test.py +++ b/tests/xprop/test.py @@ -275,7 +275,7 @@ if "prepare" in steps: file=tb_file, ) - print(" $finish;", file=tb_file) + print(" $finish(0);", file=tb_file) print("end", file=tb_file) print("endmodule", file=tb_file) @@ -344,8 +344,8 @@ for mode in ["", "_xprop"]: read_rtlil wrapped{mode}.il chformal -remove dffunmap - write_verilog -noparallelcase vsim_expr{mode}.v write_verilog -noexpr vsim_noexpr{mode}.v + write_verilog -noparallelcase vsim_expr{mode}.v """ ) -- cgit v1.2.3 From 55ad3fe6c701607ce6b184d03241be38e894c2fd Mon Sep 17 00:00:00 2001 From: Jannis Harder Date: Mon, 13 Feb 2023 16:50:27 +0100 Subject: xprop tests: Make iverilog invocation more portable --- tests/xprop/test.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'tests/xprop/test.py') diff --git a/tests/xprop/test.py b/tests/xprop/test.py index 507e4e9e2..a275b0d93 100644 --- a/tests/xprop/test.py +++ b/tests/xprop/test.py @@ -357,15 +357,15 @@ for mode in ["", "_xprop"]: "-DSIMLIB_FF", "-DSIMLIB_GLOBAL_CLOCK=top.gclk", f"-DDUMPFILE=\"vsim_{expr}.vcd\"", + "-o", + f"vsim_{expr}", "verilog_sim_tb.v", f"vsim_{expr}.v", *simlibs, - "-o", - f"vsim_{expr}", ] ) with open(f"vsim_{expr}.out", "w") as f: - subprocess.check_call([f"./vsim_{expr}"], stdout=f) + subprocess.check_call(["vvp", f"./vsim_{expr}"], stdout=f) for mode in ["", "_xprop"]: if f"sim{mode}" not in steps: -- cgit v1.2.3