From 2c6aaef3db87fe7955eded675fac452705e5cd48 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 28 Jun 2019 13:32:09 -0700
Subject: Add test

---
 tests/various/script.ys | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 tests/various/script.ys

(limited to 'tests')

diff --git a/tests/various/script.ys b/tests/various/script.ys
new file mode 100644
index 000000000..6044ad9b3
--- /dev/null
+++ b/tests/various/script.ys
@@ -0,0 +1,17 @@
+read_verilog -formal <<EOT
+    module top;
+        foo bar();
+        foo asdf();
+        winnie the_pooh();
+
+        wire [1023:0] _RUNME0 = "select -assert-count 2 t:foo";
+        wire [1023:0] _RUNME1 = "select -assert-count 1 t:winnie";
+        wire [1023:0] _DELETE = "delete c:bar";
+    endmodule
+EOT
+
+script -select w:_RUNME*
+
+select w:_DELETE
+script -select
+select -assert-count 1 t:foo
-- 
cgit v1.2.3


From 64f6b0c747eb915be9205b36bd69745a2385aea1 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 28 Jun 2019 13:41:32 -0700
Subject: Try command in another module

---
 tests/various/script.ys | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'tests')

diff --git a/tests/various/script.ys b/tests/various/script.ys
index 6044ad9b3..9ccc727eb 100644
--- a/tests/various/script.ys
+++ b/tests/various/script.ys
@@ -6,6 +6,9 @@ read_verilog -formal <<EOT
 
         wire [1023:0] _RUNME0 = "select -assert-count 2 t:foo";
         wire [1023:0] _RUNME1 = "select -assert-count 1 t:winnie";
+    endmodule
+
+    module other;
         wire [1023:0] _DELETE = "delete c:bar";
     endmodule
 EOT
-- 
cgit v1.2.3


From d45936fe5f2c6fd1e6f371b2fc3d6d820868ef72 Mon Sep 17 00:00:00 2001
From: David Shah <dave@ds0.me>
Date: Tue, 2 Jul 2019 13:27:37 +0100
Subject: memory_dff: Fix checking of feedback mux input when more than one mux

Signed-off-by: David Shah <dave@ds0.me>
---
 tests/memories/read_two_mux.v | 16 ++++++++++++++++
 tests/memories/run-test.sh    |  4 ++++
 2 files changed, 20 insertions(+)
 create mode 100644 tests/memories/read_two_mux.v

(limited to 'tests')

diff --git a/tests/memories/read_two_mux.v b/tests/memories/read_two_mux.v
new file mode 100644
index 000000000..4f2e7e1cd
--- /dev/null
+++ b/tests/memories/read_two_mux.v
@@ -0,0 +1,16 @@
+// expect-wr-ports 1
+// expect-rd-ports 1
+// expect-no-rd-clk
+
+module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata);
+
+reg [7:0] bram[0:255];
+(* keep *) reg dummy;
+
+always @(posedge clk) begin
+	rdata <= re ? (reset ? 8'b0 : bram[addr]) : rdata;
+	if (we)
+		bram[addr] <= wdata;
+end
+
+endmodule
diff --git a/tests/memories/run-test.sh b/tests/memories/run-test.sh
index 76acaa9cd..8d1a8b413 100755
--- a/tests/memories/run-test.sh
+++ b/tests/memories/run-test.sh
@@ -31,6 +31,10 @@ for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
 		grep -q "connect \\\\RD_CLK \\$(gawk '/expect-rd-clk/ { print $3; }' $f)\$" ${f%.v}.dmp ||
 				{ echo " ERROR: Unexpected read clock."; false; }
 	fi
+	if grep -q expect-no-rd-clk $f; then
+		grep -q "connect \\\\RD_CLK 1'x\$" ${f%.v}.dmp ||
+				{ echo " ERROR: Expected no read clock."; false; }
+	fi
 	echo " ok."
 done
 
-- 
cgit v1.2.3


From 90382a0f6d1ad7dfd14ced95051e5e76de89491c Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 2 Jul 2019 08:19:23 -0700
Subject: Update test too

---
 tests/various/script.ys | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'tests')

diff --git a/tests/various/script.ys b/tests/various/script.ys
index 9ccc727eb..4152145e8 100644
--- a/tests/various/script.ys
+++ b/tests/various/script.ys
@@ -13,8 +13,8 @@ read_verilog -formal <<EOT
     endmodule
 EOT
 
-script -select w:_RUNME*
+script -scriptwire w:_RUNME*
 
 select w:_DELETE
-script -select
+script -scriptwire
 select -assert-count 1 t:foo
-- 
cgit v1.2.3


From 81a717e9b767792f64535757f905a5061c627fbd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 2 Jul 2019 08:22:31 -0700
Subject: Update test for Pass::call_on_module()

---
 tests/various/script.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/various/script.ys b/tests/various/script.ys
index 4152145e8..66b7b5caa 100644
--- a/tests/various/script.ys
+++ b/tests/various/script.ys
@@ -9,7 +9,7 @@ read_verilog -formal <<EOT
     endmodule
 
     module other;
-        wire [1023:0] _DELETE = "delete c:bar";
+        wire [1023:0] _DELETE = "cd; delete c:bar";
     endmodule
 EOT
 
-- 
cgit v1.2.3