From 9e072ec21f9985126e1cfeb04fa7f2bc963790b3 Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 5 Dec 2018 00:23:22 +0000
Subject: opt_lut: new pass, to combine LUTs for tighter packing.

---
 tests/opt/.gitignore    |  1 +
 tests/opt/ice40_carry.v |  3 +++
 tests/opt/opt_lut.v     | 18 ++++++++++++++++++
 tests/opt/opt_lut.ys    | 15 +++++++++++++++
 tests/opt/run-test.sh   |  6 ++++++
 5 files changed, 43 insertions(+)
 create mode 100644 tests/opt/.gitignore
 create mode 100644 tests/opt/ice40_carry.v
 create mode 100644 tests/opt/opt_lut.v
 create mode 100644 tests/opt/opt_lut.ys
 create mode 100755 tests/opt/run-test.sh

(limited to 'tests')

diff --git a/tests/opt/.gitignore b/tests/opt/.gitignore
new file mode 100644
index 000000000..397b4a762
--- /dev/null
+++ b/tests/opt/.gitignore
@@ -0,0 +1 @@
+*.log
diff --git a/tests/opt/ice40_carry.v b/tests/opt/ice40_carry.v
new file mode 100644
index 000000000..ed938932a
--- /dev/null
+++ b/tests/opt/ice40_carry.v
@@ -0,0 +1,3 @@
+module SB_CARRY (output CO, input I0, I1, CI);
+    assign CO = (I0 && I1) || ((I0 || I1) && CI);
+endmodule
diff --git a/tests/opt/opt_lut.v b/tests/opt/opt_lut.v
new file mode 100644
index 000000000..b13db367d
--- /dev/null
+++ b/tests/opt/opt_lut.v
@@ -0,0 +1,18 @@
+module top(
+    input [8:0] a,
+    input [8:0] b,
+    output [8:0] o1,
+    output [2:0] o2,
+    input [2:0] c,
+    input [2:0] d,
+    output [2:0] o3,
+    output [2:0] o4,
+    input s
+);
+
+assign o1 = (s ? 0 : a + b);
+assign o2 = (s ? a : a - b);
+assign o3 = (s ? 4'b1111 : d + c);
+assign o4 = (s ? d : c - d);
+
+endmodule
diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys
new file mode 100644
index 000000000..1c7dc1473
--- /dev/null
+++ b/tests/opt/opt_lut.ys
@@ -0,0 +1,15 @@
+read_verilog opt_lut.v
+synth_ice40
+ice40_unlut
+design -save preopt
+
+opt_lut
+design -stash postopt
+
+design -copy-from preopt -as preopt top
+design -copy-from postopt -as postopt top
+equiv_make preopt postopt equiv
+techmap -map ice40_carry.v
+prep -flatten -top equiv
+equiv_induct
+equiv_status -assert
diff --git a/tests/opt/run-test.sh b/tests/opt/run-test.sh
new file mode 100755
index 000000000..44ce7e674
--- /dev/null
+++ b/tests/opt/run-test.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+set -e
+for x in *.ys; do
+  echo "Running $x.."
+  ../../yosys -ql ${x%.ys}.log $x
+done
-- 
cgit v1.2.3


From 45cb6200af13469724de42656f2c1f0f61c8766a Mon Sep 17 00:00:00 2001
From: whitequark <whitequark@whitequark.org>
Date: Wed, 5 Dec 2018 15:26:40 +0000
Subject: opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.

---
 tests/opt/opt_lut.ys | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'tests')

diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys
index 1c7dc1473..86ad93bb3 100644
--- a/tests/opt/opt_lut.ys
+++ b/tests/opt/opt_lut.ys
@@ -3,7 +3,7 @@ synth_ice40
 ice40_unlut
 design -save preopt
 
-opt_lut
+opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3
 design -stash postopt
 
 design -copy-from preopt -as preopt top
-- 
cgit v1.2.3