From 90c5ca330c5e6c8eb45ad0b755b0049a34dc7534 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 19 Nov 2019 16:57:58 -0800 Subject: Add two tests --- tests/simple_abc9/abc9.v | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'tests') diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 64b625efe..58596d701 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -267,3 +267,15 @@ module abc9_test026(output [3:0] o, p); assign o = { 1'b1, 1'bx }; assign p = { 1'b1, 1'bx, 1'b0 }; endmodule + +module abc9_test029(input clk, d, r, output reg q); +always @(posedge clk or posedge r) + if (r) q <= 1'b0; + else q <= d; +endmodule + +module abc9_test030(input clk, d, r, output reg q); +always @(negedge clk or posedge r) + if (r) q <= 1'b1; + else q <= d; +endmodule -- cgit v1.2.3 From 1cc106452fb25d082ca9491c24df97cc51d4b992 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 19 Nov 2019 17:05:14 -0800 Subject: Add a equiv test too --- tests/various/abc9.v | 7 +++++++ tests/various/abc9.ys | 16 ++++++++++++++++ 2 files changed, 23 insertions(+) (limited to 'tests') diff --git a/tests/various/abc9.v b/tests/various/abc9.v index 30ebd4e26..e53dcdb21 100644 --- a/tests/various/abc9.v +++ b/tests/various/abc9.v @@ -9,3 +9,10 @@ wire w; unknown u(~i, w); unknown2 u2(w, o); endmodule + +module abc9_test031(input clk, d, r, output reg q); +initial q = 1'b0; +always @(negedge clk or negedge r) + if (r) q <= 1'b0; + else q <= d; +endmodule diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys index 5c9a4075d..9e732bdc8 100644 --- a/tests/various/abc9.ys +++ b/tests/various/abc9.ys @@ -22,3 +22,19 @@ abc9 -lut 4 select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i select -assert-count 1 t:unknown select -assert-none t:$lut t:unknown %% t: %D + +design -load read +hierarchy -top abc9_test031 +proc +async2sync +design -save gold + +abc9 -lut 4 +check +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -seq 10 -verify -prove-asserts -show-ports miter -- cgit v1.2.3 From cd9e830b67fdffcae88dba095548995a30988fa4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 20 Nov 2019 13:28:55 -0800 Subject: Add multi clock test --- tests/simple_abc9/abc9.v | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'tests') diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 64b625efe..1844bac20 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -267,3 +267,8 @@ module abc9_test026(output [3:0] o, p); assign o = { 1'b1, 1'bx }; assign p = { 1'b1, 1'bx, 1'b0 }; endmodule + +module abc9_test029(input clk1, clk2, input d, output reg q1, q2); +always @(posedge clk1) q1 <= d; +always @(negedge clk2) q2 <= q1; +endmodule -- cgit v1.2.3 From 911a152b39959137b26e68581a6cacbcabb4ab1d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 21 Nov 2019 16:13:28 -0800 Subject: Add test --- tests/simple_abc9/abc9.v | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 1844bac20..13c505eec 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -268,7 +268,12 @@ assign o = { 1'b1, 1'bx }; assign p = { 1'b1, 1'bx, 1'b0 }; endmodule -module abc9_test029(input clk1, clk2, input d, output reg q1, q2); +module abc9_test029(input clk1, clk2, d, output reg q1, q2); always @(posedge clk1) q1 <= d; always @(negedge clk2) q2 <= q1; endmodule + +module abc9_test030(input clk, d, output reg q1, q2); +always @(posedge clk) q1 <= d; +always @(posedge clk) q2 <= q1; +endmodule -- cgit v1.2.3 From 39fdcb892b1b65363fdf7c1bc6d9e2612c1c38e6 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 21 Nov 2019 16:27:34 -0800 Subject: async2sync -> clk2fflogic --- tests/various/abc9.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys index 9e732bdc8..f7a3f1fa0 100644 --- a/tests/various/abc9.ys +++ b/tests/various/abc9.ys @@ -26,7 +26,7 @@ select -assert-none t:$lut t:unknown %% t: %D design -load read hierarchy -top abc9_test031 proc -async2sync +clk2fflogic design -save gold abc9 -lut 4 -- cgit v1.2.3 From 6841e3b1c2b2bc3124810f3a8f96ed00a96e954c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 21 Nov 2019 16:33:20 -0800 Subject: Another sloppy mistake! --- tests/various/abc9.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/various/abc9.v b/tests/various/abc9.v index 85828bf30..f0b3f6837 100644 --- a/tests/various/abc9.v +++ b/tests/various/abc9.v @@ -13,6 +13,6 @@ endmodule module abc9_test032(input clk, d, r, output reg q); initial q = 1'b0; always @(negedge clk or negedge r) - if (r) q <= 1'b0; + if (!r) q <= 1'b0; else q <= d; endmodule -- cgit v1.2.3 From c761fa49b73e9ad3680b05e89442adb6fb22b543 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 22 Nov 2019 12:37:57 -0800 Subject: Missing endmodule --- tests/simple_abc9/abc9.v | 1 + 1 file changed, 1 insertion(+) (limited to 'tests') diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 596a52501..6bdd3bc32 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -288,3 +288,4 @@ endmodule module abc9_test033(input clk, d, output reg q1, q2); always @(posedge clk) q1 <= d; always @(posedge clk) q2 <= q1; +endmodule -- cgit v1.2.3 From 2ef2e2c040d9ff299f1bc6daca891a1236ed877e Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 22 Nov 2019 16:41:05 -0800 Subject: Add testcase --- tests/various/submod.ys | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 tests/various/submod.ys (limited to 'tests') diff --git a/tests/various/submod.ys b/tests/various/submod.ys new file mode 100644 index 000000000..54455b580 --- /dev/null +++ b/tests/various/submod.ys @@ -0,0 +1,26 @@ +read_verilog < Date: Fri, 22 Nov 2019 16:50:09 -0800 Subject: Cleanup spacing --- tests/various/submod.ys | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/various/submod.ys b/tests/various/submod.ys index 54455b580..271a8edef 100644 --- a/tests/various/submod.ys +++ b/tests/various/submod.ys @@ -13,9 +13,9 @@ EOT hierarchy -top top proc design -save gold + submod flatten - design -stash gate design -import gold -as gold @@ -23,4 +23,3 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter - -- cgit v1.2.3 From 74ea4381362d4f402e7fc262b960e14122128303 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 22 Nov 2019 16:52:55 -0800 Subject: Add testcase for signal used as part input part output --- tests/simple_abc9/abc9.v | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'tests') diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 6bdd3bc32..8314af211 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -289,3 +289,8 @@ module abc9_test033(input clk, d, output reg q1, q2); always @(posedge clk) q1 <= d; always @(posedge clk) q2 <= q1; endmodule + +module abc9_test034(input clk, d, output reg [1:0] q); +always @(posedge clk) q[0] <= d; +always @(negedge clk) q[1] <= q[0]; +endmodule -- cgit v1.2.3 From 4fdcf8f7d73d0e577815ab50a3e0255f4bfd2154 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 22 Nov 2019 17:23:34 -0800 Subject: Add another test with constant driver --- tests/various/submod.ys | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'tests') diff --git a/tests/various/submod.ys b/tests/various/submod.ys index 271a8edef..a9d3fe672 100644 --- a/tests/various/submod.ys +++ b/tests/various/submod.ys @@ -23,3 +23,31 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + + +design -reset +read_verilog < Date: Fri, 22 Nov 2019 20:53:48 -0800 Subject: Stray dump --- tests/various/submod.ys | 1 - 1 file changed, 1 deletion(-) (limited to 'tests') diff --git a/tests/various/submod.ys b/tests/various/submod.ys index a9d3fe672..451ced5e6 100644 --- a/tests/various/submod.ys +++ b/tests/various/submod.ys @@ -42,7 +42,6 @@ proc design -save gold submod -dump flatten design -stash gate -- cgit v1.2.3 From 5cd3d3db0aaa8642dad53f8fb629e3109cef5825 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 22 Nov 2019 22:22:56 -0800 Subject: Remove redundant flatten --- tests/various/submod.ys | 2 -- 1 file changed, 2 deletions(-) (limited to 'tests') diff --git a/tests/various/submod.ys b/tests/various/submod.ys index 451ced5e6..7c6f555ac 100644 --- a/tests/various/submod.ys +++ b/tests/various/submod.ys @@ -15,7 +15,6 @@ proc design -save gold submod -flatten design -stash gate design -import gold -as gold @@ -42,7 +41,6 @@ proc design -save gold submod -flatten design -stash gate design -import gold -as gold -- cgit v1.2.3 From dd317c92808a73e61e771a123fc4377d3fb78af2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 25 Nov 2019 16:07:35 -0800 Subject: Add testcase where \init is copied --- tests/various/submod.ys | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'tests') diff --git a/tests/various/submod.ys b/tests/various/submod.ys index 7c6f555ac..f50556d76 100644 --- a/tests/various/submod.ys +++ b/tests/various/submod.ys @@ -48,3 +48,21 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + + +design -reset +read_verilog -icells < Date: Tue, 26 Nov 2019 23:38:49 -0800 Subject: Fix wire width --- tests/various/submod.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/various/submod.ys b/tests/various/submod.ys index f50556d76..a0a3f2da5 100644 --- a/tests/various/submod.ys +++ b/tests/various/submod.ys @@ -1,8 +1,8 @@ read_verilog < Date: Wed, 27 Nov 2019 00:48:22 -0800 Subject: Revert "submod to bitty rather bussy, for bussy wires used as input and output" This reverts commit cba3073026711e7683c46ba091c56a5c5a041a45. --- tests/various/submod.ys | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/various/submod.ys b/tests/various/submod.ys index a0a3f2da5..552fd4e01 100644 --- a/tests/various/submod.ys +++ b/tests/various/submod.ys @@ -52,8 +52,10 @@ sat -verify -prove-asserts -show-ports miter design -reset read_verilog -icells < Date: Wed, 27 Nov 2019 13:22:26 -0800 Subject: Add multiple driver testcase --- tests/various/submod.ys | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'tests') diff --git a/tests/various/submod.ys b/tests/various/submod.ys index 552fd4e01..9d7dabdd7 100644 --- a/tests/various/submod.ys +++ b/tests/various/submod.ys @@ -15,6 +15,7 @@ proc design -save gold submod +check -assert design -stash gate design -import gold -as gold @@ -41,6 +42,7 @@ proc design -save gold submod +check -assert top design -stash gate design -import gold -as gold @@ -50,6 +52,35 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter +design -reset +read_verilog < Date: Wed, 4 Dec 2019 21:36:41 -0800 Subject: abc9_map.v to transform INIT=1 to INIT=0 --- tests/arch/xilinx/abc9_map.ys | 91 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 tests/arch/xilinx/abc9_map.ys (limited to 'tests') diff --git a/tests/arch/xilinx/abc9_map.ys b/tests/arch/xilinx/abc9_map.ys new file mode 100644 index 000000000..6823589f1 --- /dev/null +++ b/tests/arch/xilinx/abc9_map.ys @@ -0,0 +1,91 @@ +read_verilog < Date: Wed, 11 Dec 2019 11:26:54 -0800 Subject: Add test: 'Warning: ignoring initial value on non-register: \o' --- tests/sat/initval.ys | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'tests') diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 2079d2f34..337aa9343 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -2,3 +2,13 @@ read_verilog -sv initval.v proc;; sat -seq 10 -prove-asserts + +design -reset +read_verilog -icells < Date: Wed, 11 Dec 2019 16:26:19 -0800 Subject: Add testcase --- tests/various/bug1531.ys | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 tests/various/bug1531.ys (limited to 'tests') diff --git a/tests/various/bug1531.ys b/tests/various/bug1531.ys new file mode 100644 index 000000000..542223030 --- /dev/null +++ b/tests/various/bug1531.ys @@ -0,0 +1,34 @@ +read_verilog < Date: Wed, 11 Dec 2019 23:48:09 -0800 Subject: Make testcase clearer with \o having its own init --- tests/sat/initval.ys | 2 ++ 1 file changed, 2 insertions(+) (limited to 'tests') diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 337aa9343..6cb68a8d3 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -6,6 +6,8 @@ sat -seq 10 -prove-asserts design -reset read_verilog -icells < Date: Wed, 11 Dec 2019 23:52:05 -0800 Subject: Even more obvious testcase --- tests/sat/initval.ys | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'tests') diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 6cb68a8d3..1436724b0 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -5,12 +5,11 @@ sat -seq 10 -prove-asserts design -reset read_verilog -icells < Date: Thu, 12 Dec 2019 07:34:07 -0800 Subject: Make SV2017 compliant courtesy of @wsnyder --- tests/simple/mem_arst.v | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/simple/mem_arst.v b/tests/simple/mem_arst.v index 9bd38fcb3..88d0553b9 100644 --- a/tests/simple/mem_arst.v +++ b/tests/simple/mem_arst.v @@ -7,11 +7,9 @@ module MyMem #( input Clk_i, input [AddrWidth-1:0] Addr_i, input [DataWidth-1:0] Data_i, - output [DataWidth-1:0] Data_o, + output reg [DataWidth-1:0] Data_o, input WR_i); - reg [DataWidth-1:0] Data_o; - localparam Size = 2**AddrWidth; (* mem2reg *) -- cgit v1.2.3 From 937ec1ee78e5470c148d8c39387c7a80711af8a7 Mon Sep 17 00:00:00 2001 From: Diego H Date: Thu, 12 Dec 2019 13:50:36 -0600 Subject: Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 --- tests/arch/common/memory_params.v | 45 ++++++++++++++++++++++++++++++++++++++ tests/arch/xilinx/memory_params.ys | 45 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 90 insertions(+) create mode 100644 tests/arch/common/memory_params.v create mode 100644 tests/arch/xilinx/memory_params.ys (limited to 'tests') diff --git a/tests/arch/common/memory_params.v b/tests/arch/common/memory_params.v new file mode 100644 index 000000000..dbc6ca65c --- /dev/null +++ b/tests/arch/common/memory_params.v @@ -0,0 +1,45 @@ +`default_nettype none +module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) + (input wire write_enable, clk, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in] <= data_in; + data_out_r <= memory[address_in]; + end + + assign data_out = data_out_r; +endmodule // sync_ram_sp + + +`default_nettype none +module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) + (input wire clk, write_enable, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in_r, address_in_w, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in_w] <= data_in; + data_out_r <= memory[address_in_r]; + end + + assign data_out = data_out_r; +endmodule // sync_ram_sdp + diff --git a/tests/arch/xilinx/memory_params.ys b/tests/arch/xilinx/memory_params.ys new file mode 100644 index 000000000..f279a4a6e --- /dev/null +++ b/tests/arch/xilinx/memory_params.ys @@ -0,0 +1,45 @@ +# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +# Anything memory bits < 1024 -> LUTRAM +design -reset +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 0 t:RAMB18E1 +select -assert-count 4 t:RAM128X1D + +# More than 18K bits and addr <= 36: -> RAMB36E1 +design -reset +read_verilog ../common/memory_params.v +chparam -set ADDRESS_WIDTH 15 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB36E1 + -- cgit v1.2.3 From 1187e91c2f2684cb204c555cb3d53b68c7381c40 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Thu, 12 Dec 2019 20:51:59 +0100 Subject: add test and make help message more verbose --- tests/various/scratchpad.sh | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100755 tests/various/scratchpad.sh (limited to 'tests') diff --git a/tests/various/scratchpad.sh b/tests/various/scratchpad.sh new file mode 100755 index 000000000..4e92473f8 --- /dev/null +++ b/tests/various/scratchpad.sh @@ -0,0 +1,14 @@ +#!/bin/bash + +trap 'echo "ERROR in scratchpad.sh" >&2; exit 1' ERR + +../../yosys -qp "scratchpad -set foo \"bar baz\"; \ +scratchpad -copy foo oof; scratchpad -unset foo; \ +tee -o scratchpad1.log scratchpad -get oof; \ +tee -o scratchpad2.log scratchpad -get foo" + +test "$(cat scratchpad1.log)" = "bar baz" +test "$(cat scratchpad2.log)" = "\"foo\" not set" + +rm scratchpad1.log +rm scratchpad2.log -- cgit v1.2.3 From e33f407655fa516cb2f6754103973eb156ca90cf Mon Sep 17 00:00:00 2001 From: Diego H Date: Thu, 12 Dec 2019 16:06:46 -0600 Subject: Adding a note (TODO) in the memory_params.ys check file --- tests/arch/xilinx/memory_params.ys | 2 ++ 1 file changed, 2 insertions(+) (limited to 'tests') diff --git a/tests/arch/xilinx/memory_params.ys b/tests/arch/xilinx/memory_params.ys index f279a4a6e..657629e0f 100644 --- a/tests/arch/xilinx/memory_params.ys +++ b/tests/arch/xilinx/memory_params.ys @@ -1,3 +1,5 @@ +## TODO: Not running equivalence checking because BRAM models does not exists +## currently. Checking instance counts instead. # Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 read_verilog ../common/memory_params.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp -- cgit v1.2.3 From 47ac1b01e673c1fc6f0010237c66d9b20957dcd0 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Dec 2019 14:43:13 -0800 Subject: Add test --- tests/arch/xilinx/tribuf.sh | 5 +++++ 1 file changed, 5 insertions(+) create mode 100644 tests/arch/xilinx/tribuf.sh (limited to 'tests') diff --git a/tests/arch/xilinx/tribuf.sh b/tests/arch/xilinx/tribuf.sh new file mode 100644 index 000000000..636aed12a --- /dev/null +++ b/tests/arch/xilinx/tribuf.sh @@ -0,0 +1,5 @@ +! ../../../yosys ../common/tribuf.v -qp "synth_xilinx" +../../../yosys ../common/tribuf.v -qp "synth_xilinx -iopad; \ +select -assert-count 2 t:IBUF; \ +select -assert-count 1 t:INV; \ +select -assert-count 1 t:OBUFT" -- cgit v1.2.3 From 751a18d7e974123352e372c75bb17226e6fabec0 Mon Sep 17 00:00:00 2001 From: Diego H Date: Thu, 12 Dec 2019 17:32:58 -0600 Subject: Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. --- tests/arch/xilinx/memory_params.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/arch/xilinx/memory_params.ys b/tests/arch/xilinx/memory_params.ys index 657629e0f..c1b0ca489 100644 --- a/tests/arch/xilinx/memory_params.ys +++ b/tests/arch/xilinx/memory_params.ys @@ -37,10 +37,10 @@ cd sync_ram_sdp select -assert-count 0 t:RAMB18E1 select -assert-count 4 t:RAM128X1D -# More than 18K bits and addr <= 36: -> RAMB36E1 +# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 design -reset read_verilog ../common/memory_params.v -chparam -set ADDRESS_WIDTH 15 -set DATA_WIDTH 1 sync_ram_sdp +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp synth_xilinx -top sync_ram_sdp cd sync_ram_sdp select -assert-count 1 t:RAMB36E1 -- cgit v1.2.3 From caab66111e2b5052bd26c8fd64b1324e7e4a4106 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Dec 2019 17:44:37 -0800 Subject: Rename memory tests to lutram, add more xilinx tests --- tests/arch/anlogic/lutram.ys | 21 ++++++++++ tests/arch/anlogic/memory.ys | 21 ---------- tests/arch/common/lutram.v | 42 +++++++++++++++++++ tests/arch/common/memory.v | 21 ---------- tests/arch/ecp5/lutram.ys | 19 +++++++++ tests/arch/ecp5/memory.ys | 19 --------- tests/arch/efinix/lutram.ys | 18 ++++++++ tests/arch/efinix/memory.ys | 18 -------- tests/arch/gowin/lutram.ys | 18 ++++++++ tests/arch/gowin/memory.ys | 18 -------- tests/arch/ice40/lutram.ys | 15 +++++++ tests/arch/ice40/memory.ys | 15 ------- tests/arch/xilinx/lutram.ys | 99 ++++++++++++++++++++++++++++++++++++++++++++ tests/arch/xilinx/memory.ys | 17 -------- 14 files changed, 232 insertions(+), 129 deletions(-) create mode 100644 tests/arch/anlogic/lutram.ys delete mode 100644 tests/arch/anlogic/memory.ys create mode 100644 tests/arch/common/lutram.v delete mode 100644 tests/arch/common/memory.v create mode 100644 tests/arch/ecp5/lutram.ys delete mode 100644 tests/arch/ecp5/memory.ys create mode 100644 tests/arch/efinix/lutram.ys delete mode 100644 tests/arch/efinix/memory.ys create mode 100644 tests/arch/gowin/lutram.ys delete mode 100644 tests/arch/gowin/memory.ys create mode 100644 tests/arch/ice40/lutram.ys delete mode 100644 tests/arch/ice40/memory.ys create mode 100644 tests/arch/xilinx/lutram.ys delete mode 100644 tests/arch/xilinx/memory.ys (limited to 'tests') diff --git a/tests/arch/anlogic/lutram.ys b/tests/arch/anlogic/lutram.ys new file mode 100644 index 000000000..9ebb75443 --- /dev/null +++ b/tests/arch/anlogic/lutram.ys @@ -0,0 +1,21 @@ +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r +proc +memory -nomap +equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. +#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r + +select -assert-count 8 t:AL_MAP_LUT2 +select -assert-count 8 t:AL_MAP_LUT4 +select -assert-count 8 t:AL_MAP_LUT5 +select -assert-count 36 t:AL_MAP_SEQ +select -assert-count 8 t:EG_LOGIC_DRAM16X4 #Why not AL_LOGIC_BRAM? +select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D diff --git a/tests/arch/anlogic/memory.ys b/tests/arch/anlogic/memory.ys deleted file mode 100644 index 87b93c2fe..000000000 --- a/tests/arch/anlogic/memory.ys +++ /dev/null @@ -1,21 +0,0 @@ -read_verilog ../common/memory.v -hierarchy -top top -proc -memory -nomap -equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic -memory -opt -full - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. -#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter - -design -load postopt -cd top - -select -assert-count 8 t:AL_MAP_LUT2 -select -assert-count 8 t:AL_MAP_LUT4 -select -assert-count 8 t:AL_MAP_LUT5 -select -assert-count 36 t:AL_MAP_SEQ -select -assert-count 8 t:EG_LOGIC_DRAM16X4 #Why not AL_LOGIC_BRAM? -select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D diff --git a/tests/arch/common/lutram.v b/tests/arch/common/lutram.v new file mode 100644 index 000000000..9534b7619 --- /dev/null +++ b/tests/arch/common/lutram.v @@ -0,0 +1,42 @@ +module lutram_1w1r +#(parameter D_WIDTH=8, A_WIDTH=6) +( + input [D_WIDTH-1:0] data_a, + input [A_WIDTH:1] addr_a, + input we_a, clk, + output reg [D_WIDTH-1:0] q_a +); + // Declare the RAM variable + reg [D_WIDTH-1:0] ram[(2**A_WIDTH)-1:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + ram[addr_a] <= data_a; + q_a <= ram[addr_a]; + end +endmodule + + +module lutram_1w3r +#(parameter D_WIDTH=8, A_WIDTH=5) +( + input [D_WIDTH-1:0] data_a, data_b, data_c, + input [A_WIDTH:1] addr_a, addr_b, addr_c, + input we_a, clk, + output reg [D_WIDTH-1:0] q_a, q_b, q_c +); + // Declare the RAM variable + reg [D_WIDTH-1:0] ram[(2**A_WIDTH)-1:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + ram[addr_a] <= data_a; + q_a <= ram[addr_a]; + q_b <= ram[addr_b]; + q_c <= ram[addr_c]; + end +endmodule diff --git a/tests/arch/common/memory.v b/tests/arch/common/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/arch/common/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/arch/ecp5/lutram.ys b/tests/arch/ecp5/lutram.ys new file mode 100644 index 000000000..e1ae7abd5 --- /dev/null +++ b/tests/arch/ecp5/lutram.ys @@ -0,0 +1,19 @@ +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r +proc +memory -nomap +equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 24 t:L6MUX21 +select -assert-count 71 t:LUT4 +select -assert-count 32 t:PFUMX +select -assert-count 8 t:TRELLIS_DPR16X4 +select -assert-count 35 t:TRELLIS_FF +select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D diff --git a/tests/arch/ecp5/memory.ys b/tests/arch/ecp5/memory.ys deleted file mode 100644 index c82b7b405..000000000 --- a/tests/arch/ecp5/memory.ys +++ /dev/null @@ -1,19 +0,0 @@ -read_verilog ../common/memory.v -hierarchy -top top -proc -memory -nomap -equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 -memory -opt -full - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter - -design -load postopt -cd top -select -assert-count 24 t:L6MUX21 -select -assert-count 71 t:LUT4 -select -assert-count 32 t:PFUMX -select -assert-count 8 t:TRELLIS_DPR16X4 -select -assert-count 35 t:TRELLIS_FF -select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D diff --git a/tests/arch/efinix/lutram.ys b/tests/arch/efinix/lutram.ys new file mode 100644 index 000000000..dcf647ce0 --- /dev/null +++ b/tests/arch/efinix/lutram.ys @@ -0,0 +1,18 @@ +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r +proc +memory -nomap +equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#ERROR: Called with -verify and proof did fail! +#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter +sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 1 t:EFX_RAM_5K +select -assert-none t:EFX_GBUFCE t:EFX_RAM_5K %% t:* %D diff --git a/tests/arch/efinix/memory.ys b/tests/arch/efinix/memory.ys deleted file mode 100644 index 6f6acdcde..000000000 --- a/tests/arch/efinix/memory.ys +++ /dev/null @@ -1,18 +0,0 @@ -read_verilog ../common/memory.v -hierarchy -top top -proc -memory -nomap -equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix -memory -opt -full - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#ERROR: Called with -verify and proof did fail! -#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter -sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter - -design -load postopt -cd top -select -assert-count 1 t:EFX_GBUFCE -select -assert-count 1 t:EFX_RAM_5K -select -assert-none t:EFX_GBUFCE t:EFX_RAM_5K %% t:* %D diff --git a/tests/arch/gowin/lutram.ys b/tests/arch/gowin/lutram.ys new file mode 100644 index 000000000..56f69e7c5 --- /dev/null +++ b/tests/arch/gowin/lutram.ys @@ -0,0 +1,18 @@ +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r +proc +memory -nomap +equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#ERROR: Called with -verify and proof did fail! +#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter +sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 8 t:RAM16S4 +# other logic present that is not simple +#select -assert-none t:RAM16S4 %% t:* %D diff --git a/tests/arch/gowin/memory.ys b/tests/arch/gowin/memory.ys deleted file mode 100644 index 8f88cdd7c..000000000 --- a/tests/arch/gowin/memory.ys +++ /dev/null @@ -1,18 +0,0 @@ -read_verilog ../common/memory.v -hierarchy -top top -proc -memory -nomap -equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin -memory -opt -full - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#ERROR: Called with -verify and proof did fail! -#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter -sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter - -design -load postopt -cd top -select -assert-count 8 t:RAM16S4 -# other logic present that is not simple -#select -assert-none t:RAM16S4 %% t:* %D diff --git a/tests/arch/ice40/lutram.ys b/tests/arch/ice40/lutram.ys new file mode 100644 index 000000000..1ba40f8ec --- /dev/null +++ b/tests/arch/ice40/lutram.ys @@ -0,0 +1,15 @@ +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r +proc +memory -nomap +equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 1 t:SB_RAM40_4K +select -assert-none t:SB_RAM40_4K %% t:* %D diff --git a/tests/arch/ice40/memory.ys b/tests/arch/ice40/memory.ys deleted file mode 100644 index c356e67fb..000000000 --- a/tests/arch/ice40/memory.ys +++ /dev/null @@ -1,15 +0,0 @@ -read_verilog ../common/memory.v -hierarchy -top top -proc -memory -nomap -equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 -memory -opt -full - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter - -design -load postopt -cd top -select -assert-count 1 t:SB_RAM40_4K -select -assert-none t:SB_RAM40_4K %% t:* %D diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys new file mode 100644 index 000000000..9b2c30ba1 --- /dev/null +++ b/tests/arch/xilinx/lutram.ys @@ -0,0 +1,99 @@ +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r -chparam A_WIDTH 4 +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDRE +select -assert-count 8 t:RAM16X1D +select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D + + +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r -chparam A_WIDTH 5 +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDRE +select -assert-count 8 t:RAM32X1D +select -assert-none t:BUFG t:FDRE t:RAM32X1D %% t:* %D + + +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDRE +select -assert-count 8 t:RAM64X1D +select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D + + +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w3r +proc +memory -nomap +synth_xilinx +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w3r +select -assert-count 1 t:BUFG +select -assert-count 24 t:FDRE +select -assert-count 4 t:RAM32M +select -assert-none t:BUFG t:FDRE t:RAM32M %% t:* %D + + +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w3r -chparam A_WIDTH 6 +proc +memory -nomap +synth_xilinx +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w3r +select -assert-count 1 t:BUFG +select -assert-count 24 t:FDRE +select -assert-count 8 t:RAM64M +select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D diff --git a/tests/arch/xilinx/memory.ys b/tests/arch/xilinx/memory.ys deleted file mode 100644 index da1ed0e49..000000000 --- a/tests/arch/xilinx/memory.ys +++ /dev/null @@ -1,17 +0,0 @@ -read_verilog ../common/memory.v -hierarchy -top top -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter - -design -load postopt -cd top -select -assert-count 1 t:BUFG -select -assert-count 8 t:FDRE -select -assert-count 8 t:RAM64X1D -select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D -- cgit v1.2.3 From 037d1a03df20b9c445790728bb80e1818d1edafa Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Dec 2019 17:49:55 -0800 Subject: Add #1460 testcase --- tests/arch/xilinx/bug1460.ys | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 tests/arch/xilinx/bug1460.ys (limited to 'tests') diff --git a/tests/arch/xilinx/bug1460.ys b/tests/arch/xilinx/bug1460.ys new file mode 100644 index 000000000..2018071cc --- /dev/null +++ b/tests/arch/xilinx/bug1460.ys @@ -0,0 +1,34 @@ +read_verilog < Date: Thu, 12 Dec 2019 18:52:48 -0800 Subject: Add tests for these new models --- tests/arch/xilinx/lutram.ys | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'tests') diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys index 9b2c30ba1..36367eff1 100644 --- a/tests/arch/xilinx/lutram.ys +++ b/tests/arch/xilinx/lutram.ys @@ -97,3 +97,43 @@ select -assert-count 1 t:BUFG select -assert-count 24 t:FDRE select -assert-count 8 t:RAM64M select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D + + +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 6 +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 1 t:BUFG +select -assert-count 6 t:FDRE +select -assert-count 1 t:RAM32M +select -assert-none t:BUFG t:FDRE t:RAM32M %% t:* %D + + +design -reset +read_verilog ../common/lutram.v +hierarchy -top lutram_1w1r -chparam A_WIDTH 6 -chparam D_WIDTH 6 +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd lutram_1w1r +select -assert-count 1 t:BUFG +select -assert-count 6 t:FDRE +select -assert-count 2 t:RAM64M +select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D -- cgit v1.2.3 From d0ee4cd88f1f966c194fdc60e47ef67944882afb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 12 Dec 2019 19:00:26 -0800 Subject: Remove extraneous synth_xilinx call --- tests/arch/xilinx/lutram.ys | 2 -- 1 file changed, 2 deletions(-) (limited to 'tests') diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys index 36367eff1..a2ede75a5 100644 --- a/tests/arch/xilinx/lutram.ys +++ b/tests/arch/xilinx/lutram.ys @@ -62,7 +62,6 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w3r proc memory -nomap -synth_xilinx equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx memory opt -full @@ -83,7 +82,6 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w3r -chparam A_WIDTH 6 proc memory -nomap -synth_xilinx equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx memory opt -full -- cgit v1.2.3 From 1c9634558747bf5b92a309b6af013a54034c35d3 Mon Sep 17 00:00:00 2001 From: Diego H Date: Fri, 13 Dec 2019 09:33:18 -0600 Subject: Renaming BRAM memory tests for the sake of uniformity --- tests/arch/common/blockram_params.v | 45 ++++++++++++++++++++++++++++++++++ tests/arch/common/memory_params.v | 45 ---------------------------------- tests/arch/xilinx/blockram_params.ys | 47 ++++++++++++++++++++++++++++++++++++ tests/arch/xilinx/memory_params.ys | 47 ------------------------------------ 4 files changed, 92 insertions(+), 92 deletions(-) create mode 100644 tests/arch/common/blockram_params.v delete mode 100644 tests/arch/common/memory_params.v create mode 100644 tests/arch/xilinx/blockram_params.ys delete mode 100644 tests/arch/xilinx/memory_params.ys (limited to 'tests') diff --git a/tests/arch/common/blockram_params.v b/tests/arch/common/blockram_params.v new file mode 100644 index 000000000..dbc6ca65c --- /dev/null +++ b/tests/arch/common/blockram_params.v @@ -0,0 +1,45 @@ +`default_nettype none +module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) + (input wire write_enable, clk, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in] <= data_in; + data_out_r <= memory[address_in]; + end + + assign data_out = data_out_r; +endmodule // sync_ram_sp + + +`default_nettype none +module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) + (input wire clk, write_enable, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in_r, address_in_w, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in_w] <= data_in; + data_out_r <= memory[address_in_r]; + end + + assign data_out = data_out_r; +endmodule // sync_ram_sdp + diff --git a/tests/arch/common/memory_params.v b/tests/arch/common/memory_params.v deleted file mode 100644 index dbc6ca65c..000000000 --- a/tests/arch/common/memory_params.v +++ /dev/null @@ -1,45 +0,0 @@ -`default_nettype none -module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) - (input wire write_enable, clk, - input wire [DATA_WIDTH-1:0] data_in, - input wire [ADDRESS_WIDTH-1:0] address_in, - output wire [DATA_WIDTH-1:0] data_out); - - localparam WORD = (DATA_WIDTH-1); - localparam DEPTH = (2**ADDRESS_WIDTH-1); - - reg [WORD:0] data_out_r; - reg [WORD:0] memory [0:DEPTH]; - - always @(posedge clk) begin - if (write_enable) - memory[address_in] <= data_in; - data_out_r <= memory[address_in]; - end - - assign data_out = data_out_r; -endmodule // sync_ram_sp - - -`default_nettype none -module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) - (input wire clk, write_enable, - input wire [DATA_WIDTH-1:0] data_in, - input wire [ADDRESS_WIDTH-1:0] address_in_r, address_in_w, - output wire [DATA_WIDTH-1:0] data_out); - - localparam WORD = (DATA_WIDTH-1); - localparam DEPTH = (2**ADDRESS_WIDTH-1); - - reg [WORD:0] data_out_r; - reg [WORD:0] memory [0:DEPTH]; - - always @(posedge clk) begin - if (write_enable) - memory[address_in_w] <= data_in; - data_out_r <= memory[address_in_r]; - end - - assign data_out = data_out_r; -endmodule // sync_ram_sdp - diff --git a/tests/arch/xilinx/blockram_params.ys b/tests/arch/xilinx/blockram_params.ys new file mode 100644 index 000000000..27a94834e --- /dev/null +++ b/tests/arch/xilinx/blockram_params.ys @@ -0,0 +1,47 @@ +## TODO: Not running equivalence checking because BRAM models does not exists +## currently. Checking instance counts instead. +# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 +read_verilog ../common/blockram_params.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram_params.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram_params.v +chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram_params.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +# Anything memory bits < 1024 -> LUTRAM +design -reset +read_verilog ../common/blockram_params.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 0 t:RAMB18E1 +select -assert-count 4 t:RAM128X1D + +# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 +design -reset +read_verilog ../common/blockram_params.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB36E1 + diff --git a/tests/arch/xilinx/memory_params.ys b/tests/arch/xilinx/memory_params.ys deleted file mode 100644 index c1b0ca489..000000000 --- a/tests/arch/xilinx/memory_params.ys +++ /dev/null @@ -1,47 +0,0 @@ -## TODO: Not running equivalence checking because BRAM models does not exists -## currently. Checking instance counts instead. -# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 -read_verilog ../common/memory_params.v -chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 - -design -reset -read_verilog ../common/memory_params.v -chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 - -design -reset -read_verilog ../common/memory_params.v -chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 - -design -reset -read_verilog ../common/memory_params.v -chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 - -# Anything memory bits < 1024 -> LUTRAM -design -reset -read_verilog ../common/memory_params.v -chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 0 t:RAMB18E1 -select -assert-count 4 t:RAM128X1D - -# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 -design -reset -read_verilog ../common/memory_params.v -chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB36E1 - -- cgit v1.2.3 From a5764a12365073768edb822e893aa9c0a957e585 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 13 Dec 2019 10:28:13 -0800 Subject: Disable RAM16X1D test --- tests/arch/xilinx/lutram.ys | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) (limited to 'tests') diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys index a2ede75a5..6c9d1eae1 100644 --- a/tests/arch/xilinx/lutram.ys +++ b/tests/arch/xilinx/lutram.ys @@ -1,20 +1,20 @@ -read_verilog ../common/lutram.v -hierarchy -top lutram_1w1r -chparam A_WIDTH 4 -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter - -design -load postopt -cd lutram_1w1r -select -assert-count 1 t:BUFG -select -assert-count 8 t:FDRE -select -assert-count 8 t:RAM16X1D -select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D +#read_verilog ../common/lutram.v +#hierarchy -top lutram_1w1r -chparam A_WIDTH 4 +#proc +#memory -nomap +#equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +#memory +#opt -full +# +#miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter +# +#design -load postopt +#cd lutram_1w1r +#select -assert-count 1 t:BUFG +#select -assert-count 8 t:FDRE +#select -assert-count 8 t:RAM16X1D +#select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D design -reset -- cgit v1.2.3 From b35559fc335181d7c8f8046fa17bf05550c21ba7 Mon Sep 17 00:00:00 2001 From: Diego H Date: Sun, 15 Dec 2019 23:33:09 -0600 Subject: Merging attribute rules into a single match block; Adding tests --- .../common/memory_attributes/attributes_test.v | 88 + .../common/memory_attributes/attributes_test.ys | 47 + tests/arch/common/memory_attributes/log | 3238 ++++++++++++++++++++ 3 files changed, 3373 insertions(+) create mode 100644 tests/arch/common/memory_attributes/attributes_test.v create mode 100644 tests/arch/common/memory_attributes/attributes_test.ys create mode 100644 tests/arch/common/memory_attributes/log (limited to 'tests') diff --git a/tests/arch/common/memory_attributes/attributes_test.v b/tests/arch/common/memory_attributes/attributes_test.v new file mode 100644 index 000000000..275800dd0 --- /dev/null +++ b/tests/arch/common/memory_attributes/attributes_test.v @@ -0,0 +1,88 @@ +`default_nettype none +module block_ram #(parameter DATA_WIDTH=4, ADDRESS_WIDTH=10) + (input wire write_enable, clk, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in] <= data_in; + data_out_r <= memory[address_in]; + end + + assign data_out = data_out_r; +endmodule // block_ram + +`default_nettype none +module distributed_ram #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4) + (input wire write_enable, clk, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in] <= data_in; + data_out_r <= memory[address_in]; + end + + assign data_out = data_out_r; +endmodule // distributed_ram + +`default_nettype none +module distributed_ram_manual #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4) + (input wire write_enable, clk, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + (* ram_style = "block" *) reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in] <= data_in; + data_out_r <= memory[address_in]; + end + + assign data_out = data_out_r; +endmodule // distributed_ram + +`default_nettype none +module distributed_ram_manual_syn #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=4) + (input wire write_enable, clk, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + (* synthesis, ram_block *) reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in] <= data_in; + data_out_r <= memory[address_in]; + end + + assign data_out = data_out_r; +endmodule // distributed_ram + diff --git a/tests/arch/common/memory_attributes/attributes_test.ys b/tests/arch/common/memory_attributes/attributes_test.ys new file mode 100644 index 000000000..4e06a35e7 --- /dev/null +++ b/tests/arch/common/memory_attributes/attributes_test.ys @@ -0,0 +1,47 @@ +# Check that blockram memory without parameters is not modified +read_verilog attributes_test.v +hierarchy -top block_ram +synth_xilinx -top block_ram +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 + +# Check that distributed memory without parameters is not modified +design -reset +read_verilog attributes_test.v +hierarchy -top distributed_ram +synth_xilinx -top distributed_ram +cd distributed_ram # Constrain all select calls below inside the top module +select -assert-count 8 t:RAM32X1D + +# Set ram_style distributed to blockram memory; will be implemented as distributed +design -reset +read_verilog attributes_test.v +prep +setattr -mod -set ram_style "distributed" block_ram +synth_xilinx -top block_ram +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 32 t:RAM128X1D + +# Set synthesis, logic_block to blockram memory; will be implemented as distributed +design -reset +read_verilog attributes_test.v +prep +setattr -mod -set logic_block 1 block_ram +synth_xilinx -top block_ram +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 0 t:RAMB18E1 +select -assert-count 32 t:RAM128X1D + +# Set ram_style block to a distributed memory; will be implemented as blockram +design -reset +read_verilog attributes_test.v +synth_xilinx -top distributed_ram_manual +cd distributed_ram_manual # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 + +# Set synthesis, ram_block block to a distributed memory; will be implemented as blockram +design -reset +read_verilog attributes_test.v +synth_xilinx -top distributed_ram_manual_syn +cd distributed_ram_manual_syn # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 diff --git a/tests/arch/common/memory_attributes/log b/tests/arch/common/memory_attributes/log new file mode 100644 index 000000000..5d526e661 --- /dev/null +++ b/tests/arch/common/memory_attributes/log @@ -0,0 +1,3238 @@ + + /----------------------------------------------------------------------------\ + | | + | yosys -- Yosys Open SYnthesis Suite | + | | + | Copyright (C) 2012 - 2019 Clifford Wolf | + | | + | Permission to use, copy, modify, and/or distribute this software for any | + | purpose with or without fee is hereby granted, provided that the above | + | copyright notice and this permission notice appear in all copies. | + | | + | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | + | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | + | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | + | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | + | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | + | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | + | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | + | | + \----------------------------------------------------------------------------/ + + Yosys 0.9+932 (git sha1 26699340, clang 6.0.0-1ubuntu2 -fPIC -Os) + + +-- Executing script file `attributes_test.ys' -- + +1. Executing Verilog-2005 frontend: attributes_test.v +Parsing Verilog input from `attributes_test.v' to AST representation. +Generating RTLIL representation for module `\block_ram'. +Generating RTLIL representation for module `\distributed_ram'. +Generating RTLIL representation for module `\distributed_ram_manual'. +Generating RTLIL representation for module `\distributed_ram_manual_syn'. +Successfully finished Verilog frontend. + +2. Executing HIERARCHY pass (managing design hierarchy). + +2.1. Analyzing design hierarchy.. +Top module: \block_ram + +2.2. Analyzing design hierarchy.. +Top module: \block_ram +Removing unused module `\distributed_ram_manual_syn'. +Removing unused module `\distributed_ram_manual'. +Removing unused module `\distributed_ram'. +Removed 3 unused modules. + +3. Executing SYNTH_XILINX pass. + +3.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v' to AST representation. +Generating RTLIL representation for module `\VCC'. +Generating RTLIL representation for module `\GND'. +Generating RTLIL representation for module `\IBUF'. +Generating RTLIL representation for module `\IBUFG'. +Generating RTLIL representation for module `\OBUF'. +Generating RTLIL representation for module `\IOBUF'. +Generating RTLIL representation for module `\OBUFT'. +Generating RTLIL representation for module `\BUFG'. +Generating RTLIL representation for module `\BUFGCTRL'. +Generating RTLIL representation for module `\BUFHCE'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\LUT1'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\LUT3'. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\LUT5'. +Generating RTLIL representation for module `\LUT6'. +Generating RTLIL representation for module `\LUT6_2'. +Generating RTLIL representation for module `\MUXCY'. +Generating RTLIL representation for module `\MUXF7'. +Generating RTLIL representation for module `\MUXF8'. +Generating RTLIL representation for module `\XORCY'. +Generating RTLIL representation for module `\CARRY4'. +Generating RTLIL representation for module `\FDRE'. +Generating RTLIL representation for module `\FDSE'. +Generating RTLIL representation for module `\FDCE'. +Generating RTLIL representation for module `\FDPE'. +Generating RTLIL representation for module `\FDRE_1'. +Generating RTLIL representation for module `\FDSE_1'. +Generating RTLIL representation for module `\FDCE_1'. +Generating RTLIL representation for module `\FDPE_1'. +Generating RTLIL representation for module `\LDCE'. +Generating RTLIL representation for module `\LDPE'. +Generating RTLIL representation for module `\RAM16X1S'. +Generating RTLIL representation for module `\RAM16X1S_1'. +Generating RTLIL representation for module `\RAM32X1S'. +Generating RTLIL representation for module `\RAM32X1S_1'. +Generating RTLIL representation for module `\RAM64X1S'. +Generating RTLIL representation for module `\RAM64X1S_1'. +Generating RTLIL representation for module `\RAM128X1S'. +Generating RTLIL representation for module `\RAM128X1S_1'. +Generating RTLIL representation for module `\RAM256X1S'. +Generating RTLIL representation for module `\RAM512X1S'. +Generating RTLIL representation for module `\RAM16X2S'. +Generating RTLIL representation for module `\RAM32X2S'. +Generating RTLIL representation for module `\RAM64X2S'. +Generating RTLIL representation for module `\RAM16X4S'. +Generating RTLIL representation for module `\RAM32X4S'. +Generating RTLIL representation for module `\RAM16X8S'. +Generating RTLIL representation for module `\RAM32X8S'. +Generating RTLIL representation for module `\RAM16X1D'. +Generating RTLIL representation for module `\RAM16X1D_1'. +Generating RTLIL representation for module `\RAM32X1D'. +Generating RTLIL representation for module `\RAM32X1D_1'. +Generating RTLIL representation for module `\RAM64X1D'. +Generating RTLIL representation for module `\RAM64X1D_1'. +Generating RTLIL representation for module `\RAM128X1D'. +Generating RTLIL representation for module `\RAM256X1D'. +Generating RTLIL representation for module `\RAM32M'. +Generating RTLIL representation for module `\RAM32M16'. +Generating RTLIL representation for module `\RAM64M'. +Generating RTLIL representation for module `\RAM64M8'. +Generating RTLIL representation for module `\ROM16X1'. +Generating RTLIL representation for module `\ROM32X1'. +Generating RTLIL representation for module `\ROM64X1'. +Generating RTLIL representation for module `\ROM128X1'. +Generating RTLIL representation for module `\ROM256X1'. +Generating RTLIL representation for module `\SRL16E'. +Generating RTLIL representation for module `\SRLC16E'. +Generating RTLIL representation for module `\SRLC32E'. +Generating RTLIL representation for module `\MULT18X18'. +Generating RTLIL representation for module `\MULT18X18S'. +Generating RTLIL representation for module `\MULT18X18SIO'. +Generating RTLIL representation for module `\DSP48A'. +Generating RTLIL representation for module `\DSP48A1'. +Generating RTLIL representation for module `\DSP48E1'. +Successfully finished Verilog frontend. + +3.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v' to AST representation. +Generating RTLIL representation for module `\FDCPE'. +Generating RTLIL representation for module `\FDRSE'. +Generating RTLIL representation for module `\LDCPE'. +Generating RTLIL representation for module `\AND2B1L'. +Generating RTLIL representation for module `\OR2L'. +Generating RTLIL representation for module `\MUXF5'. +Generating RTLIL representation for module `\MUXF6'. +Generating RTLIL representation for module `\MUXF9'. +Generating RTLIL representation for module `\CARRY8'. +Generating RTLIL representation for module `\ORCY'. +Generating RTLIL representation for module `\MULT_AND'. +Generating RTLIL representation for module `\SRL16'. +Generating RTLIL representation for module `\SRLC16'. +Generating RTLIL representation for module `\CFGLUT5'. +Generating RTLIL representation for module `\RAMB16_S1'. +Generating RTLIL representation for module `\RAMB16_S2'. +Generating RTLIL representation for module `\RAMB16_S4'. +Generating RTLIL representation for module `\RAMB16_S9'. +Generating RTLIL representation for module `\RAMB16_S18'. +Generating RTLIL representation for module `\RAMB16_S36'. +Generating RTLIL representation for module `\RAMB16_S1_S1'. +Generating RTLIL representation for module `\RAMB16_S1_S2'. +Generating RTLIL representation for module `\RAMB16_S1_S4'. +Generating RTLIL representation for module `\RAMB16_S1_S9'. +Generating RTLIL representation for module `\RAMB16_S1_S18'. +Generating RTLIL representation for module `\RAMB16_S1_S36'. +Generating RTLIL representation for module `\RAMB16_S2_S2'. +Generating RTLIL representation for module `\RAMB16_S2_S4'. +Generating RTLIL representation for module `\RAMB16_S2_S9'. +Generating RTLIL representation for module `\RAMB16_S2_S18'. +Generating RTLIL representation for module `\RAMB16_S2_S36'. +Generating RTLIL representation for module `\RAMB16_S4_S4'. +Generating RTLIL representation for module `\RAMB16_S4_S9'. +Generating RTLIL representation for module `\RAMB16_S4_S18'. +Generating RTLIL representation for module `\RAMB16_S4_S36'. +Generating RTLIL representation for module `\RAMB16_S9_S9'. +Generating RTLIL representation for module `\RAMB16_S9_S18'. +Generating RTLIL representation for module `\RAMB16_S9_S36'. +Generating RTLIL representation for module `\RAMB16_S18_S18'. +Generating RTLIL representation for module `\RAMB16_S18_S36'. +Generating RTLIL representation for module `\RAMB16_S36_S36'. +Generating RTLIL representation for module `\RAMB16BWE_S18'. +Generating RTLIL representation for module `\RAMB16BWE_S36'. +Generating RTLIL representation for module `\RAMB16BWE_S18_S9'. +Generating RTLIL representation for module `\RAMB16BWE_S18_S18'. +Generating RTLIL representation for module `\RAMB16BWE_S36_S9'. +Generating RTLIL representation for module `\RAMB16BWE_S36_S18'. +Generating RTLIL representation for module `\RAMB16BWE_S36_S36'. +Generating RTLIL representation for module `\RAMB16BWER'. +Generating RTLIL representation for module `\RAMB8BWER'. +Generating RTLIL representation for module `\FIFO16'. +Generating RTLIL representation for module `\RAMB16'. +Generating RTLIL representation for module `\RAMB32_S64_ECC'. +Generating RTLIL representation for module `\FIFO18'. +Generating RTLIL representation for module `\FIFO18_36'. +Generating RTLIL representation for module `\FIFO36'. +Generating RTLIL representation for module `\FIFO36_72'. +Generating RTLIL representation for module `\RAMB18'. +Generating RTLIL representation for module `\RAMB36'. +Generating RTLIL representation for module `\RAMB18SDP'. +Generating RTLIL representation for module `\RAMB36SDP'. +Generating RTLIL representation for module `\FIFO18E1'. +Generating RTLIL representation for module `\FIFO36E1'. +Generating RTLIL representation for module `\RAMB18E1'. +Generating RTLIL representation for module `\RAMB36E1'. +Generating RTLIL representation for module `\FIFO18E2'. +Generating RTLIL representation for module `\FIFO36E2'. +Generating RTLIL representation for module `\RAMB18E2'. +Generating RTLIL representation for module `\RAMB36E2'. +Generating RTLIL representation for module `\URAM288'. +Generating RTLIL representation for module `\URAM288_BASE'. +Generating RTLIL representation for module `\DSP48'. +Generating RTLIL representation for module `\DSP48E'. +Generating RTLIL representation for module `\DSP48E2'. +Generating RTLIL representation for module `\IFDDRCPE'. +Generating RTLIL representation for module `\IFDDRRSE'. +Generating RTLIL representation for module `\OFDDRCPE'. +Generating RTLIL representation for module `\OFDDRRSE'. +Generating RTLIL representation for module `\OFDDRTCPE'. +Generating RTLIL representation for module `\OFDDRTRSE'. +Generating RTLIL representation for module `\IDDR2'. +Generating RTLIL representation for module `\ODDR2'. +Generating RTLIL representation for module `\IDDR'. +Generating RTLIL representation for module `\IDDR_2CLK'. +Generating RTLIL representation for module `\ODDR'. +Generating RTLIL representation for module `\IDELAYCTRL'. +Generating RTLIL representation for module `\IDELAY'. +Generating RTLIL representation for module `\ISERDES'. +Generating RTLIL representation for module `\OSERDES'. +Generating RTLIL representation for module `\IODELAY'. +Generating RTLIL representation for module `\ISERDES_NODELAY'. +Generating RTLIL representation for module `\IODELAYE1'. +Generating RTLIL representation for module `\ISERDESE1'. +Generating RTLIL representation for module `\OSERDESE1'. +Generating RTLIL representation for module `\IDELAYE2'. +Generating RTLIL representation for module `\ODELAYE2'. +Generating RTLIL representation for module `\ISERDESE2'. +Generating RTLIL representation for module `\OSERDESE2'. +Generating RTLIL representation for module `\PHASER_IN'. +Generating RTLIL representation for module `\PHASER_IN_PHY'. +Generating RTLIL representation for module `\PHASER_OUT'. +Generating RTLIL representation for module `\PHASER_OUT_PHY'. +Generating RTLIL representation for module `\PHASER_REF'. +Generating RTLIL representation for module `\PHY_CONTROL'. +Generating RTLIL representation for module `\IDDRE1'. +Generating RTLIL representation for module `\ODDRE1'. +Generating RTLIL representation for module `\IDELAYE3'. +Generating RTLIL representation for module `\ODELAYE3'. +Generating RTLIL representation for module `\ISERDESE3'. +Generating RTLIL representation for module `\OSERDESE3'. +Generating RTLIL representation for module `\BITSLICE_CONTROL'. +Generating RTLIL representation for module `\RIU_OR'. +Generating RTLIL representation for module `\RX_BITSLICE'. +Generating RTLIL representation for module `\RXTX_BITSLICE'. +Generating RTLIL representation for module `\TX_BITSLICE'. +Generating RTLIL representation for module `\TX_BITSLICE_TRI'. +Generating RTLIL representation for module `\IODELAY2'. +Generating RTLIL representation for module `\IODRP2'. +Generating RTLIL representation for module `\IODRP2_MCB'. +Generating RTLIL representation for module `\ISERDES2'. +Generating RTLIL representation for module `\OSERDES2'. +Generating RTLIL representation for module `\IBUF_DLY_ADJ'. +Generating RTLIL representation for module `\IBUF_IBUFDISABLE'. +Generating RTLIL representation for module `\IBUF_INTERMDISABLE'. +Generating RTLIL representation for module `\IBUF_ANALOG'. +Generating RTLIL representation for module `\IBUFE3'. +Generating RTLIL representation for module `\IBUFDS'. +Generating RTLIL representation for module `\IBUFDS_DLY_ADJ'. +Generating RTLIL representation for module `\IBUFDS_IBUFDISABLE'. +Generating RTLIL representation for module `\IBUFDS_INTERMDISABLE'. +Generating RTLIL representation for module `\IBUFDS_DIFF_OUT'. +Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_IBUFDISABLE'. +Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_INTERMDISABLE'. +Generating RTLIL representation for module `\IBUFDSE3'. +Generating RTLIL representation for module `\IBUFDS_DPHY'. +Generating RTLIL representation for module `\IBUFGDS'. +Generating RTLIL representation for module `\IBUFGDS_DIFF_OUT'. +Generating RTLIL representation for module `\IOBUF_DCIEN'. +Generating RTLIL representation for module `\IOBUF_INTERMDISABLE'. +Generating RTLIL representation for module `\IOBUFE3'. +Generating RTLIL representation for module `\IOBUFDS'. +Generating RTLIL representation for module `\IOBUFDS_DCIEN'. +Generating RTLIL representation for module `\IOBUFDS_INTERMDISABLE'. +Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT'. +Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_DCIEN'. +Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_INTERMDISABLE'. +Generating RTLIL representation for module `\IOBUFDSE3'. +Generating RTLIL representation for module `\OBUFDS'. +Generating RTLIL representation for module `\OBUFDS_DPHY'. +Generating RTLIL representation for module `\OBUFTDS'. +Generating RTLIL representation for module `\KEEPER'. +Generating RTLIL representation for module `\PULLDOWN'. +Generating RTLIL representation for module `\PULLUP'. +Generating RTLIL representation for module `\DCIRESET'. +Generating RTLIL representation for module `\HPIO_VREF'. +Generating RTLIL representation for module `\BUFGCE'. +Generating RTLIL representation for module `\BUFGCE_1'. +Generating RTLIL representation for module `\BUFGMUX'. +Generating RTLIL representation for module `\BUFGMUX_1'. +Generating RTLIL representation for module `\BUFGMUX_CTRL'. +Generating RTLIL representation for module `\BUFGMUX_VIRTEX4'. +Generating RTLIL representation for module `\BUFG_GT'. +Generating RTLIL representation for module `\BUFG_GT_SYNC'. +Generating RTLIL representation for module `\BUFG_PS'. +Generating RTLIL representation for module `\BUFGCE_DIV'. +Generating RTLIL representation for module `\BUFH'. +Generating RTLIL representation for module `\BUFIO2'. +Generating RTLIL representation for module `\BUFIO2_2CLK'. +Generating RTLIL representation for module `\BUFIO2FB'. +Generating RTLIL representation for module `\BUFPLL'. +Generating RTLIL representation for module `\BUFPLL_MCB'. +Generating RTLIL representation for module `\BUFIO'. +Generating RTLIL representation for module `\BUFIODQS'. +Generating RTLIL representation for module `\BUFR'. +Generating RTLIL representation for module `\BUFMR'. +Generating RTLIL representation for module `\BUFMRCE'. +Generating RTLIL representation for module `\DCM'. +Generating RTLIL representation for module `\DCM_SP'. +Generating RTLIL representation for module `\DCM_CLKGEN'. +Generating RTLIL representation for module `\DCM_ADV'. +Generating RTLIL representation for module `\DCM_BASE'. +Generating RTLIL representation for module `\DCM_PS'. +Generating RTLIL representation for module `\PMCD'. +Generating RTLIL representation for module `\PLL_ADV'. +Generating RTLIL representation for module `\PLL_BASE'. +Generating RTLIL representation for module `\MMCM_ADV'. +Generating RTLIL representation for module `\MMCM_BASE'. +Generating RTLIL representation for module `\MMCME2_ADV'. +Generating RTLIL representation for module `\MMCME2_BASE'. +Generating RTLIL representation for module `\PLLE2_ADV'. +Generating RTLIL representation for module `\PLLE2_BASE'. +Generating RTLIL representation for module `\MMCME3_ADV'. +Generating RTLIL representation for module `\MMCME3_BASE'. +Generating RTLIL representation for module `\PLLE3_ADV'. +Generating RTLIL representation for module `\PLLE3_BASE'. +Generating RTLIL representation for module `\MMCME4_ADV'. +Generating RTLIL representation for module `\MMCME4_BASE'. +Generating RTLIL representation for module `\PLLE4_ADV'. +Generating RTLIL representation for module `\PLLE4_BASE'. +Generating RTLIL representation for module `\BUFT'. +Generating RTLIL representation for module `\IN_FIFO'. +Generating RTLIL representation for module `\OUT_FIFO'. +Generating RTLIL representation for module `\HARD_SYNC'. +Generating RTLIL representation for module `\STARTUP_SPARTAN3'. +Generating RTLIL representation for module `\STARTUP_SPARTAN3E'. +Generating RTLIL representation for module `\STARTUP_SPARTAN3A'. +Generating RTLIL representation for module `\STARTUP_SPARTAN6'. +Generating RTLIL representation for module `\STARTUP_VIRTEX4'. +Generating RTLIL representation for module `\STARTUP_VIRTEX5'. +Generating RTLIL representation for module `\STARTUP_VIRTEX6'. +Generating RTLIL representation for module `\STARTUPE2'. +Generating RTLIL representation for module `\STARTUPE3'. +Generating RTLIL representation for module `\CAPTURE_SPARTAN3'. +Generating RTLIL representation for module `\CAPTURE_SPARTAN3A'. +Generating RTLIL representation for module `\CAPTURE_VIRTEX4'. +Generating RTLIL representation for module `\CAPTURE_VIRTEX5'. +Generating RTLIL representation for module `\CAPTURE_VIRTEX6'. +Generating RTLIL representation for module `\CAPTUREE2'. +Generating RTLIL representation for module `\ICAP_SPARTAN3A'. +Generating RTLIL representation for module `\ICAP_SPARTAN6'. +Generating RTLIL representation for module `\ICAP_VIRTEX4'. +Generating RTLIL representation for module `\ICAP_VIRTEX5'. +Generating RTLIL representation for module `\ICAP_VIRTEX6'. +Generating RTLIL representation for module `\ICAPE2'. +Generating RTLIL representation for module `\ICAPE3'. +Generating RTLIL representation for module `\BSCAN_SPARTAN3'. +Generating RTLIL representation for module `\BSCAN_SPARTAN3A'. +Generating RTLIL representation for module `\BSCAN_SPARTAN6'. +Generating RTLIL representation for module `\BSCAN_VIRTEX4'. +Generating RTLIL representation for module `\BSCAN_VIRTEX5'. +Generating RTLIL representation for module `\BSCAN_VIRTEX6'. +Generating RTLIL representation for module `\BSCANE2'. +Generating RTLIL representation for module `\DNA_PORT'. +Generating RTLIL representation for module `\DNA_PORTE2'. +Generating RTLIL representation for module `\FRAME_ECC_VIRTEX4'. +Generating RTLIL representation for module `\FRAME_ECC_VIRTEX5'. +Generating RTLIL representation for module `\FRAME_ECC_VIRTEX6'. +Generating RTLIL representation for module `\FRAME_ECCE2'. +Generating RTLIL representation for module `\FRAME_ECCE3'. +Generating RTLIL representation for module `\USR_ACCESS_VIRTEX4'. +Generating RTLIL representation for module `\USR_ACCESS_VIRTEX5'. +Generating RTLIL representation for module `\USR_ACCESS_VIRTEX6'. +Generating RTLIL representation for module `\USR_ACCESSE2'. +Generating RTLIL representation for module `\POST_CRC_INTERNAL'. +Generating RTLIL representation for module `\SUSPEND_SYNC'. +Generating RTLIL representation for module `\KEY_CLEAR'. +Generating RTLIL representation for module `\MASTER_JTAG'. +Generating RTLIL representation for module `\SPI_ACCESS'. +Generating RTLIL representation for module `\EFUSE_USR'. +Generating RTLIL representation for module `\SYSMON'. +Generating RTLIL representation for module `\XADC'. +Generating RTLIL representation for module `\SYSMONE1'. +Generating RTLIL representation for module `\SYSMONE4'. +Generating RTLIL representation for module `\GTPA1_DUAL'. +Generating RTLIL representation for module `\GT11_CUSTOM'. +Generating RTLIL representation for module `\GT11_DUAL'. +Generating RTLIL representation for module `\GT11CLK'. +Generating RTLIL representation for module `\GT11CLK_MGT'. +Generating RTLIL representation for module `\GTP_DUAL'. +Generating RTLIL representation for module `\GTX_DUAL'. +Generating RTLIL representation for module `\CRC32'. +Generating RTLIL representation for module `\CRC64'. +Generating RTLIL representation for module `\GTHE1_QUAD'. +Generating RTLIL representation for module `\GTXE1'. +Generating RTLIL representation for module `\IBUFDS_GTXE1'. +Generating RTLIL representation for module `\IBUFDS_GTHE1'. +Generating RTLIL representation for module `\GTHE2_CHANNEL'. +Generating RTLIL representation for module `\GTHE2_COMMON'. +Generating RTLIL representation for module `\GTPE2_CHANNEL'. +Generating RTLIL representation for module `\GTPE2_COMMON'. +Generating RTLIL representation for module `\GTXE2_CHANNEL'. +Generating RTLIL representation for module `\GTXE2_COMMON'. +Generating RTLIL representation for module `\IBUFDS_GTE2'. +Generating RTLIL representation for module `\GTHE3_CHANNEL'. +Generating RTLIL representation for module `\GTHE3_COMMON'. +Generating RTLIL representation for module `\GTHE4_CHANNEL'. +Generating RTLIL representation for module `\GTHE4_COMMON'. +Generating RTLIL representation for module `\GTYE3_CHANNEL'. +Generating RTLIL representation for module `\GTYE3_COMMON'. +Generating RTLIL representation for module `\GTYE4_CHANNEL'. +Generating RTLIL representation for module `\GTYE4_COMMON'. +Generating RTLIL representation for module `\IBUFDS_GTE3'. +Generating RTLIL representation for module `\IBUFDS_GTE4'. +Generating RTLIL representation for module `\OBUFDS_GTE3'. +Generating RTLIL representation for module `\OBUFDS_GTE3_ADV'. +Generating RTLIL representation for module `\OBUFDS_GTE4'. +Generating RTLIL representation for module `\OBUFDS_GTE4_ADV'. +Generating RTLIL representation for module `\PCIE_A1'. +Generating RTLIL representation for module `\PCIE_EP'. +Generating RTLIL representation for module `\PCIE_2_0'. +Generating RTLIL representation for module `\PCIE_2_1'. +Generating RTLIL representation for module `\PCIE_3_0'. +Generating RTLIL representation for module `\PCIE_3_1'. +Generating RTLIL representation for module `\PCIE40E4'. +Generating RTLIL representation for module `\EMAC'. +Generating RTLIL representation for module `\TEMAC'. +Generating RTLIL representation for module `\TEMAC_SINGLE'. +Generating RTLIL representation for module `\CMAC'. +Generating RTLIL representation for module `\CMACE4'. +Generating RTLIL representation for module `\PPC405_ADV'. +Generating RTLIL representation for module `\PPC440'. +Generating RTLIL representation for module `\MCB'. +Generating RTLIL representation for module `\PS7'. +Generating RTLIL representation for module `\PS8'. +Generating RTLIL representation for module `\ILKN'. +Generating RTLIL representation for module `\ILKNE4'. +Successfully finished Verilog frontend. + +3.3. Executing HIERARCHY pass (managing design hierarchy). + +3.3.1. Analyzing design hierarchy.. +Top module: \block_ram + +3.3.2. Analyzing design hierarchy.. +Top module: \block_ram +Removed 0 unused modules. + +3.4. Executing PROC pass (convert processes to netlists). + +3.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +3.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +3.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 1 assignment to connection. + +3.4.4. Executing PROC_INIT pass (extract init attributes). + +3.4.5. Executing PROC_ARST pass (detect async resets in processes). + +3.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\block_ram.$proc$attributes_test.v:14$2'. + 1/3: $0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 + 2/3: $0$memwr$\memory$attributes_test.v:16$1_DATA[3:0]$4 + 3/3: $0$memwr$\memory$attributes_test.v:16$1_ADDR[9:0]$3 + +3.4.7. Executing PROC_DLATCH pass (convert process syncs to latches). + +3.4.8. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\block_ram.\data_out_r' using process `\block_ram.$proc$attributes_test.v:14$2'. + created $dff cell `$procdff$48' with positive edge clock. +Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$1_ADDR' using process `\block_ram.$proc$attributes_test.v:14$2'. + created $dff cell `$procdff$49' with positive edge clock. +Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$1_DATA' using process `\block_ram.$proc$attributes_test.v:14$2'. + created $dff cell `$procdff$50' with positive edge clock. +Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$1_EN' using process `\block_ram.$proc$attributes_test.v:14$2'. + created $dff cell `$procdff$51' with positive edge clock. + +3.4.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\block_ram.$proc$attributes_test.v:14$2'. +Removing empty process `block_ram.$proc$attributes_test.v:14$2'. +Cleaned up 1 empty switch. + +3.5. Executing TRIBUF pass. + +3.6. Executing DEMINOUT pass (demote inout ports to input or output). + +3.7. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. +Removed 0 unused cells and 7 unused wires. + + +3.9. Executing CHECK pass (checking for obvious problems). +checking module block_ram.. +found and reported 0 problems. + +3.10. Executing OPT pass (performing simple optimizations). + +3.10.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.10.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +3.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \block_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \block_ram. + Consolidated identical input bits for $mux cell $procmux$42: + Old ports: A=4'0000, B=4'1111, Y=$0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 + New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 [0] + New connections: $0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 [3:1] = { $0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 [0] $0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 [0] $0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 [0] } + Optimizing cells in module \block_ram. +Performed a total of 1 changes. + +3.10.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +3.10.6. Executing OPT_RMDFF pass (remove dff with constant values). + +3.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +3.10.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.10.9. Rerunning OPT passes. (Maybe there is more to do..) + +3.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \block_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \block_ram. +Performed a total of 0 changes. + +3.10.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +3.10.13. Executing OPT_RMDFF pass (remove dff with constant values). + +3.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +3.10.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.10.16. Finished OPT passes. (There is nothing left to do.) + +3.11. Executing WREDUCE pass (reducing word size of cells). +Removed cell block_ram.$procmux$44 ($mux). +Removed cell block_ram.$procmux$46 ($mux). +Removed top 3 bits (of 4) from FF cell block_ram.$procdff$51 ($dff). + +3.12. Executing PEEPOPT pass (run peephole optimizers). + +3.13. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. +Removed 0 unused cells and 2 unused wires. + + +3.14. Executing PMUX2SHIFTX pass. + +3.15. Executing TECHMAP pass (map to technology primitives). + +3.15.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +3.15.2. Continuing TECHMAP pass. +No more expansions possible. + +3.16. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). +Checking cell `$memwr$\memory$attributes_test.v:16$7' in module `\block_ram': merged $dff to cell. +Checking cell `$memrd$\memory$attributes_test.v:17$6' in module `\block_ram': merged data $dff to cell. + +3.17. Executing TECHMAP pass (map to technology primitives). + +3.17.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +3.17.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v' to AST representation. +Generating RTLIL representation for module `\$__MUL25X18'. +Successfully finished Verilog frontend. + +3.17.3. Continuing TECHMAP pass. +No more expansions possible. + +3.18. Executing OPT_EXPR pass (perform const folding). + +3.19. Executing WREDUCE pass (reducing word size of cells). + +3.20. Executing XILINX_DSP pass (pack resources into DSPs). + +3.21. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module block_ram: + created 0 $alu and 0 $macc cells. + +3.22. Executing SHARE pass (SAT-based resource sharing). + +3.23. Executing OPT pass (performing simple optimizations). + +3.23.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.23.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +3.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \block_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \block_ram. +Performed a total of 0 changes. + +3.23.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +3.23.6. Executing OPT_RMDFF pass (remove dff with constant values). + +3.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. +Removed 4 unused cells and 5 unused wires. + + +3.23.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.23.9. Rerunning OPT passes. (Maybe there is more to do..) + +3.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \block_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +3.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \block_ram. +Performed a total of 0 changes. + +3.23.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +3.23.13. Executing OPT_RMDFF pass (remove dff with constant values). + +3.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +3.23.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.23.16. Finished OPT passes. (There is nothing left to do.) + +3.24. Executing FSM pass (extract and optimize FSM). + +3.24.1. Executing FSM_DETECT pass (finding FSMs in design). + +3.24.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +3.24.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +3.24.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +3.24.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +3.24.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +3.24.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +3.24.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +3.25. Executing OPT pass (performing simple optimizations). + +3.25.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.25.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +3.25.3. Executing OPT_RMDFF pass (remove dff with constant values). + +3.25.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +3.25.5. Finished fast OPT passes. + +3.26. Executing MEMORY pass. + +3.26.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +3.26.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). + +3.26.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +3.26.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +3.26.5. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +3.26.6. Executing MEMORY_COLLECT pass (generating $mem cells). +Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\block_ram': + $memwr$\memory$attributes_test.v:16$7 ($memwr) + $memrd$\memory$attributes_test.v:17$6 ($memrd) + +3.27. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +3.28. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). +Processing block_ram.memory: + Properties: ports=2 bits=4096 rports=1 wports=1 dbits=4 abits=10 words=1024 + Checking rule #1 for bram type $__XILINX_RAMB36_SDP (variant 1): + Bram geometry: abits=9 dbits=72 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_SDP: awaste=0 dwaste=68 bwaste=34816 waste=34816 efficiency=5 + Rule #1 for bram type $__XILINX_RAMB36_SDP (variant 1) accepted. + Mapping to bram type $__XILINX_RAMB36_SDP (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=34816 efficiency=5 + Storing for later selection. + Checking rule #2 for bram type $__XILINX_RAMB18_SDP (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_SDP: awaste=0 dwaste=32 bwaste=16384 waste=16384 efficiency=11 + Rule #2 for bram type $__XILINX_RAMB18_SDP (variant 1) accepted. + Mapping to bram type $__XILINX_RAMB18_SDP (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=16384 efficiency=11 + Storing for later selection. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 1): + Bram geometry: abits=10 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=0 dwaste=32 bwaste=32768 waste=32768 efficiency=11 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 1) accepted. + Mapping to bram type $__XILINX_RAMB36_TDP (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=32768 efficiency=11 + Storing for later selection. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 2): + Bram geometry: abits=11 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=1024 dwaste=14 bwaste=32768 waste=32768 efficiency=11 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 2) accepted. + Mapping to bram type $__XILINX_RAMB36_TDP (variant 2): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=32768 efficiency=11 + Storing for later selection. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 3): + Bram geometry: abits=12 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=3072 dwaste=5 bwaste=32768 waste=32768 efficiency=11 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 3) accepted. + Mapping to bram type $__XILINX_RAMB36_TDP (variant 3): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=32768 efficiency=11 + Storing for later selection. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 4): + Bram geometry: abits=13 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=7168 dwaste=0 bwaste=28672 waste=28672 efficiency=12 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 4) accepted. + Mapping to bram type $__XILINX_RAMB36_TDP (variant 4): + Shuffle bit order to accommodate enable buckets of size 4.. + Results of bit order shuffling: 0 1 2 3 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=28672 efficiency=12 + Storing for later selection. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 5): + Bram geometry: abits=14 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=15360 dwaste=0 bwaste=30720 waste=30720 efficiency=6 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 5) accepted. + Mapping to bram type $__XILINX_RAMB36_TDP (variant 5): + Shuffle bit order to accommodate enable buckets of size 2.. + Results of bit order shuffling: 0 1 2 3 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=30720 efficiency=6 + Storing for later selection. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 6): + Bram geometry: abits=15 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=31744 dwaste=0 bwaste=31744 waste=31744 efficiency=3 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 6) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_TDP: awaste=0 dwaste=14 bwaste=14336 waste=14336 efficiency=22 + Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 1) accepted. + Mapping to bram type $__XILINX_RAMB18_TDP (variant 1): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=14336 efficiency=22 + Storing for later selection. + Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_TDP: awaste=1024 dwaste=5 bwaste=14336 waste=14336 efficiency=22 + Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 2) accepted. + Mapping to bram type $__XILINX_RAMB18_TDP (variant 2): + Shuffle bit order to accommodate enable buckets of size 9.. + Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=14336 efficiency=22 + Storing for later selection. + Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_TDP: awaste=3072 dwaste=0 bwaste=12288 waste=12288 efficiency=25 + Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 3) accepted. + Mapping to bram type $__XILINX_RAMB18_TDP (variant 3): + Shuffle bit order to accommodate enable buckets of size 4.. + Results of bit order shuffling: 0 1 2 3 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=12288 efficiency=25 + Storing for later selection. + Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_TDP: awaste=7168 dwaste=0 bwaste=14336 waste=14336 efficiency=12 + Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 4) accepted. + Mapping to bram type $__XILINX_RAMB18_TDP (variant 4): + Shuffle bit order to accommodate enable buckets of size 2.. + Results of bit order shuffling: 0 1 2 3 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=14336 efficiency=12 + Storing for later selection. + Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_TDP: awaste=15360 dwaste=0 bwaste=15360 waste=15360 efficiency=6 + Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 5) accepted. + Mapping to bram type $__XILINX_RAMB18_TDP (variant 5): + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=15360 efficiency=6 + Storing for later selection. + Selecting best of 12 rules: + Efficiency for rule 4.5: efficiency=6, cells=4, acells=1 + Efficiency for rule 4.4: efficiency=12, cells=2, acells=1 + Efficiency for rule 4.3: efficiency=25, cells=1, acells=1 + Efficiency for rule 4.2: efficiency=22, cells=1, acells=1 + Efficiency for rule 4.1: efficiency=22, cells=1, acells=1 + Efficiency for rule 3.5: efficiency=6, cells=2, acells=1 + Efficiency for rule 3.4: efficiency=12, cells=1, acells=1 + Efficiency for rule 3.3: efficiency=11, cells=1, acells=1 + Efficiency for rule 3.2: efficiency=11, cells=1, acells=1 + Efficiency for rule 3.1: efficiency=11, cells=1, acells=1 + Efficiency for rule 2.1: efficiency=11, cells=2, acells=2 + Efficiency for rule 1.1: efficiency=5, cells=2, acells=2 + Selected rule 4.3 with efficiency 25. + Mapping to bram type $__XILINX_RAMB18_TDP (variant 3): + Shuffle bit order to accommodate enable buckets of size 4.. + Results of bit order shuffling: 0 1 2 3 + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Creating $__XILINX_RAMB18_TDP cell at grid position <0 0 0>: memory.0.0.0 + +3.29. Executing TECHMAP pass (map to technology primitives). + +3.29.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_brams_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_brams_map.v' to AST representation. +Generating RTLIL representation for module `\$__XILINX_RAMB36_SDP'. +Generating RTLIL representation for module `\$__XILINX_RAMB18_SDP'. +Generating RTLIL representation for module `\$__XILINX_RAMB36_TDP'. +Generating RTLIL representation for module `\$__XILINX_RAMB18_TDP'. +Successfully finished Verilog frontend. + +3.29.2. Continuing TECHMAP pass. +Using template $paramod\$__XILINX_RAMB18_TDP\CFG_ABITS=12\CFG_DBITS=4\CFG_ENABLE_B=1\CLKPOL2=1\CLKPOL3=1 for cells of type $__XILINX_RAMB18_TDP. +No more expansions possible. + + +3.30. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). + +3.31. Executing TECHMAP pass (map to technology primitives). + +3.31.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lutrams_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lutrams_map.v' to AST representation. +Generating RTLIL representation for module `\$__XILINX_RAM32X1D'. +Generating RTLIL representation for module `\$__XILINX_RAM64X1D'. +Generating RTLIL representation for module `\$__XILINX_RAM128X1D'. +Successfully finished Verilog frontend. + +3.31.2. Continuing TECHMAP pass. +No more expansions possible. + +3.32. Executing OPT pass (performing simple optimizations). + +3.32.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + + +3.32.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +3.32.3. Executing OPT_RMDFF pass (remove dff with constant values). + +3.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. +Removed 0 unused cells and 17 unused wires. + + +3.32.5. Finished fast OPT passes. + +3.33. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). + +3.34. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs). + +3.35. Executing DFF2DFFE pass (transform $dff to $dffe where applicable). +Transforming FF to FF+Enable cells in module block_ram: + +3.36. Executing OPT pass (performing simple optimizations). + +3.36.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.36.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +3.36.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \block_ram.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +3.36.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \block_ram. +Performed a total of 0 changes. + +3.36.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +3.36.6. Executing OPT_SHARE pass. + +3.36.7. Executing OPT_RMDFF pass (remove dff with constant values). + +3.36.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +3.36.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.36.10. Finished OPT passes. (There is nothing left to do.) + +3.37. Executing XILINX_SRL pass (Xilinx shift register extraction). + +3.38. Executing TECHMAP pass (map to technology primitives). + +3.38.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +3.38.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/arith_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/arith_map.v' to AST representation. +Generating RTLIL representation for module `\_80_xilinx_lcu'. +Generating RTLIL representation for module `\_80_xilinx_alu'. +Successfully finished Verilog frontend. + +3.38.3. Continuing TECHMAP pass. +No more expansions possible. + +3.39. Executing OPT pass (performing simple optimizations). + +3.39.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.39.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +3.39.3. Executing OPT_RMDFF pass (remove dff with constant values). + +3.39.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +3.39.5. Finished fast OPT passes. + +3.40. Executing TECHMAP pass (map to technology primitives). + +3.40.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +3.40.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v' to AST representation. +Generating RTLIL representation for module `\_90_dff_nn0_to_np0'. +Generating RTLIL representation for module `\_90_dff_pn0_to_pp0'. +Generating RTLIL representation for module `\_90_dff_nn1_to_np1'. +Generating RTLIL representation for module `\_90_dff_pn1_to_pp1'. +Generating RTLIL representation for module `\$__SHREG_'. +Generating RTLIL representation for module `\$__XILINX_SHREG_'. +Generating RTLIL representation for module `\$__XILINX_MUXF78'. +Generating RTLIL representation for module `\$__XILINX_TINOUTPAD'. +Generating RTLIL representation for module `\$__XILINX_TOUTPAD'. +Successfully finished Verilog frontend. + +3.40.3. Continuing TECHMAP pass. +No more expansions possible. + +3.41. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +3.42. Executing ABC pass (technology mapping using ABC). + +3.42.1. Extracting gate netlist of module `\block_ram' to `/input.blif'.. +Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. +Don't call ABC as there is nothing to map. +Removing temp directory. + +3.43. Executing XILINX_SRL pass (Xilinx shift register extraction). + +3.44. Executing TECHMAP pass (map to technology primitives). + +3.44.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lut_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lut_map.v' to AST representation. +Generating RTLIL representation for module `\$lut'. +Successfully finished Verilog frontend. + +3.44.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v' to AST representation. +Generating RTLIL representation for module `\_90_dff_nn0_to_np0'. +Generating RTLIL representation for module `\_90_dff_pn0_to_pp0'. +Generating RTLIL representation for module `\_90_dff_nn1_to_np1'. +Generating RTLIL representation for module `\_90_dff_pn1_to_pp1'. +Generating RTLIL representation for module `\$__SHREG_'. +Generating RTLIL representation for module `\$__XILINX_SHREG_'. +Generating RTLIL representation for module `\$__XILINX_MUXF78'. +Generating RTLIL representation for module `\$__XILINX_TINOUTPAD'. +Generating RTLIL representation for module `\$__XILINX_TOUTPAD'. +Successfully finished Verilog frontend. + +3.44.3. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_ff_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_ff_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFF_NN0_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_PN0_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_NN1_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_PN1_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_DLATCH_N_'. +Generating RTLIL representation for module `\$_DLATCH_P_'. +Successfully finished Verilog frontend. + +3.44.4. Continuing TECHMAP pass. +No more expansions possible. + +3.45. Executing CLKBUFMAP pass (inserting global clock buffers). +Inserting BUFG on block_ram.clk[0]. + +3.46. Executing HIERARCHY pass (managing design hierarchy). + +3.46.1. Analyzing design hierarchy.. +Top module: \block_ram + +3.46.2. Analyzing design hierarchy.. +Top module: \block_ram +Removed 0 unused modules. + +3.47. Printing statistics. + +=== block_ram === + + Number of wires: 12 + Number of wire bits: 62 + Number of public wires: 6 + Number of public wire bits: 24 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2 + BUFG 1 + RAMB18E1 1 + + Estimated number of LCs: 0 + +3.48. Executing CHECK pass (checking for obvious problems). +checking module block_ram.. +found and reported 0 problems. + +4. Executing Verilog-2005 frontend: attributes_test.v +Parsing Verilog input from `attributes_test.v' to AST representation. +Generating RTLIL representation for module `\block_ram'. +Generating RTLIL representation for module `\distributed_ram'. +Generating RTLIL representation for module `\distributed_ram_manual'. +Generating RTLIL representation for module `\distributed_ram_manual_syn'. +Successfully finished Verilog frontend. + +5. Executing HIERARCHY pass (managing design hierarchy). + +5.1. Analyzing design hierarchy.. +Top module: \distributed_ram + +5.2. Analyzing design hierarchy.. +Top module: \distributed_ram +Removing unused module `\distributed_ram_manual_syn'. +Removing unused module `\distributed_ram_manual'. +Removing unused module `\block_ram'. +Removed 3 unused modules. + +6. Executing SYNTH_XILINX pass. + +6.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v' to AST representation. +Generating RTLIL representation for module `\VCC'. +Generating RTLIL representation for module `\GND'. +Generating RTLIL representation for module `\IBUF'. +Generating RTLIL representation for module `\IBUFG'. +Generating RTLIL representation for module `\OBUF'. +Generating RTLIL representation for module `\IOBUF'. +Generating RTLIL representation for module `\OBUFT'. +Generating RTLIL representation for module `\BUFG'. +Generating RTLIL representation for module `\BUFGCTRL'. +Generating RTLIL representation for module `\BUFHCE'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\LUT1'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\LUT3'. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\LUT5'. +Generating RTLIL representation for module `\LUT6'. +Generating RTLIL representation for module `\LUT6_2'. +Generating RTLIL representation for module `\MUXCY'. +Generating RTLIL representation for module `\MUXF7'. +Generating RTLIL representation for module `\MUXF8'. +Generating RTLIL representation for module `\XORCY'. +Generating RTLIL representation for module `\CARRY4'. +Generating RTLIL representation for module `\FDRE'. +Generating RTLIL representation for module `\FDSE'. +Generating RTLIL representation for module `\FDCE'. +Generating RTLIL representation for module `\FDPE'. +Generating RTLIL representation for module `\FDRE_1'. +Generating RTLIL representation for module `\FDSE_1'. +Generating RTLIL representation for module `\FDCE_1'. +Generating RTLIL representation for module `\FDPE_1'. +Generating RTLIL representation for module `\LDCE'. +Generating RTLIL representation for module `\LDPE'. +Generating RTLIL representation for module `\RAM16X1S'. +Generating RTLIL representation for module `\RAM16X1S_1'. +Generating RTLIL representation for module `\RAM32X1S'. +Generating RTLIL representation for module `\RAM32X1S_1'. +Generating RTLIL representation for module `\RAM64X1S'. +Generating RTLIL representation for module `\RAM64X1S_1'. +Generating RTLIL representation for module `\RAM128X1S'. +Generating RTLIL representation for module `\RAM128X1S_1'. +Generating RTLIL representation for module `\RAM256X1S'. +Generating RTLIL representation for module `\RAM512X1S'. +Generating RTLIL representation for module `\RAM16X2S'. +Generating RTLIL representation for module `\RAM32X2S'. +Generating RTLIL representation for module `\RAM64X2S'. +Generating RTLIL representation for module `\RAM16X4S'. +Generating RTLIL representation for module `\RAM32X4S'. +Generating RTLIL representation for module `\RAM16X8S'. +Generating RTLIL representation for module `\RAM32X8S'. +Generating RTLIL representation for module `\RAM16X1D'. +Generating RTLIL representation for module `\RAM16X1D_1'. +Generating RTLIL representation for module `\RAM32X1D'. +Generating RTLIL representation for module `\RAM32X1D_1'. +Generating RTLIL representation for module `\RAM64X1D'. +Generating RTLIL representation for module `\RAM64X1D_1'. +Generating RTLIL representation for module `\RAM128X1D'. +Generating RTLIL representation for module `\RAM256X1D'. +Generating RTLIL representation for module `\RAM32M'. +Generating RTLIL representation for module `\RAM32M16'. +Generating RTLIL representation for module `\RAM64M'. +Generating RTLIL representation for module `\RAM64M8'. +Generating RTLIL representation for module `\ROM16X1'. +Generating RTLIL representation for module `\ROM32X1'. +Generating RTLIL representation for module `\ROM64X1'. +Generating RTLIL representation for module `\ROM128X1'. +Generating RTLIL representation for module `\ROM256X1'. +Generating RTLIL representation for module `\SRL16E'. +Generating RTLIL representation for module `\SRLC16E'. +Generating RTLIL representation for module `\SRLC32E'. +Generating RTLIL representation for module `\MULT18X18'. +Generating RTLIL representation for module `\MULT18X18S'. +Generating RTLIL representation for module `\MULT18X18SIO'. +Generating RTLIL representation for module `\DSP48A'. +Generating RTLIL representation for module `\DSP48A1'. +Generating RTLIL representation for module `\DSP48E1'. +Successfully finished Verilog frontend. + +6.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v' to AST representation. +Generating RTLIL representation for module `\FDCPE'. +Generating RTLIL representation for module `\FDRSE'. +Generating RTLIL representation for module `\LDCPE'. +Generating RTLIL representation for module `\AND2B1L'. +Generating RTLIL representation for module `\OR2L'. +Generating RTLIL representation for module `\MUXF5'. +Generating RTLIL representation for module `\MUXF6'. +Generating RTLIL representation for module `\MUXF9'. +Generating RTLIL representation for module `\CARRY8'. +Generating RTLIL representation for module `\ORCY'. +Generating RTLIL representation for module `\MULT_AND'. +Generating RTLIL representation for module `\SRL16'. +Generating RTLIL representation for module `\SRLC16'. +Generating RTLIL representation for module `\CFGLUT5'. +Generating RTLIL representation for module `\RAMB16_S1'. +Generating RTLIL representation for module `\RAMB16_S2'. +Generating RTLIL representation for module `\RAMB16_S4'. +Generating RTLIL representation for module `\RAMB16_S9'. +Generating RTLIL representation for module `\RAMB16_S18'. +Generating RTLIL representation for module `\RAMB16_S36'. +Generating RTLIL representation for module `\RAMB16_S1_S1'. +Generating RTLIL representation for module `\RAMB16_S1_S2'. +Generating RTLIL representation for module `\RAMB16_S1_S4'. +Generating RTLIL representation for module `\RAMB16_S1_S9'. +Generating RTLIL representation for module `\RAMB16_S1_S18'. +Generating RTLIL representation for module `\RAMB16_S1_S36'. +Generating RTLIL representation for module `\RAMB16_S2_S2'. +Generating RTLIL representation for module `\RAMB16_S2_S4'. +Generating RTLIL representation for module `\RAMB16_S2_S9'. +Generating RTLIL representation for module `\RAMB16_S2_S18'. +Generating RTLIL representation for module `\RAMB16_S2_S36'. +Generating RTLIL representation for module `\RAMB16_S4_S4'. +Generating RTLIL representation for module `\RAMB16_S4_S9'. +Generating RTLIL representation for module `\RAMB16_S4_S18'. +Generating RTLIL representation for module `\RAMB16_S4_S36'. +Generating RTLIL representation for module `\RAMB16_S9_S9'. +Generating RTLIL representation for module `\RAMB16_S9_S18'. +Generating RTLIL representation for module `\RAMB16_S9_S36'. +Generating RTLIL representation for module `\RAMB16_S18_S18'. +Generating RTLIL representation for module `\RAMB16_S18_S36'. +Generating RTLIL representation for module `\RAMB16_S36_S36'. +Generating RTLIL representation for module `\RAMB16BWE_S18'. +Generating RTLIL representation for module `\RAMB16BWE_S36'. +Generating RTLIL representation for module `\RAMB16BWE_S18_S9'. +Generating RTLIL representation for module `\RAMB16BWE_S18_S18'. +Generating RTLIL representation for module `\RAMB16BWE_S36_S9'. +Generating RTLIL representation for module `\RAMB16BWE_S36_S18'. +Generating RTLIL representation for module `\RAMB16BWE_S36_S36'. +Generating RTLIL representation for module `\RAMB16BWER'. +Generating RTLIL representation for module `\RAMB8BWER'. +Generating RTLIL representation for module `\FIFO16'. +Generating RTLIL representation for module `\RAMB16'. +Generating RTLIL representation for module `\RAMB32_S64_ECC'. +Generating RTLIL representation for module `\FIFO18'. +Generating RTLIL representation for module `\FIFO18_36'. +Generating RTLIL representation for module `\FIFO36'. +Generating RTLIL representation for module `\FIFO36_72'. +Generating RTLIL representation for module `\RAMB18'. +Generating RTLIL representation for module `\RAMB36'. +Generating RTLIL representation for module `\RAMB18SDP'. +Generating RTLIL representation for module `\RAMB36SDP'. +Generating RTLIL representation for module `\FIFO18E1'. +Generating RTLIL representation for module `\FIFO36E1'. +Generating RTLIL representation for module `\RAMB18E1'. +Generating RTLIL representation for module `\RAMB36E1'. +Generating RTLIL representation for module `\FIFO18E2'. +Generating RTLIL representation for module `\FIFO36E2'. +Generating RTLIL representation for module `\RAMB18E2'. +Generating RTLIL representation for module `\RAMB36E2'. +Generating RTLIL representation for module `\URAM288'. +Generating RTLIL representation for module `\URAM288_BASE'. +Generating RTLIL representation for module `\DSP48'. +Generating RTLIL representation for module `\DSP48E'. +Generating RTLIL representation for module `\DSP48E2'. +Generating RTLIL representation for module `\IFDDRCPE'. +Generating RTLIL representation for module `\IFDDRRSE'. +Generating RTLIL representation for module `\OFDDRCPE'. +Generating RTLIL representation for module `\OFDDRRSE'. +Generating RTLIL representation for module `\OFDDRTCPE'. +Generating RTLIL representation for module `\OFDDRTRSE'. +Generating RTLIL representation for module `\IDDR2'. +Generating RTLIL representation for module `\ODDR2'. +Generating RTLIL representation for module `\IDDR'. +Generating RTLIL representation for module `\IDDR_2CLK'. +Generating RTLIL representation for module `\ODDR'. +Generating RTLIL representation for module `\IDELAYCTRL'. +Generating RTLIL representation for module `\IDELAY'. +Generating RTLIL representation for module `\ISERDES'. +Generating RTLIL representation for module `\OSERDES'. +Generating RTLIL representation for module `\IODELAY'. +Generating RTLIL representation for module `\ISERDES_NODELAY'. +Generating RTLIL representation for module `\IODELAYE1'. +Generating RTLIL representation for module `\ISERDESE1'. +Generating RTLIL representation for module `\OSERDESE1'. +Generating RTLIL representation for module `\IDELAYE2'. +Generating RTLIL representation for module `\ODELAYE2'. +Generating RTLIL representation for module `\ISERDESE2'. +Generating RTLIL representation for module `\OSERDESE2'. +Generating RTLIL representation for module `\PHASER_IN'. +Generating RTLIL representation for module `\PHASER_IN_PHY'. +Generating RTLIL representation for module `\PHASER_OUT'. +Generating RTLIL representation for module `\PHASER_OUT_PHY'. +Generating RTLIL representation for module `\PHASER_REF'. +Generating RTLIL representation for module `\PHY_CONTROL'. +Generating RTLIL representation for module `\IDDRE1'. +Generating RTLIL representation for module `\ODDRE1'. +Generating RTLIL representation for module `\IDELAYE3'. +Generating RTLIL representation for module `\ODELAYE3'. +Generating RTLIL representation for module `\ISERDESE3'. +Generating RTLIL representation for module `\OSERDESE3'. +Generating RTLIL representation for module `\BITSLICE_CONTROL'. +Generating RTLIL representation for module `\RIU_OR'. +Generating RTLIL representation for module `\RX_BITSLICE'. +Generating RTLIL representation for module `\RXTX_BITSLICE'. +Generating RTLIL representation for module `\TX_BITSLICE'. +Generating RTLIL representation for module `\TX_BITSLICE_TRI'. +Generating RTLIL representation for module `\IODELAY2'. +Generating RTLIL representation for module `\IODRP2'. +Generating RTLIL representation for module `\IODRP2_MCB'. +Generating RTLIL representation for module `\ISERDES2'. +Generating RTLIL representation for module `\OSERDES2'. +Generating RTLIL representation for module `\IBUF_DLY_ADJ'. +Generating RTLIL representation for module `\IBUF_IBUFDISABLE'. +Generating RTLIL representation for module `\IBUF_INTERMDISABLE'. +Generating RTLIL representation for module `\IBUF_ANALOG'. +Generating RTLIL representation for module `\IBUFE3'. +Generating RTLIL representation for module `\IBUFDS'. +Generating RTLIL representation for module `\IBUFDS_DLY_ADJ'. +Generating RTLIL representation for module `\IBUFDS_IBUFDISABLE'. +Generating RTLIL representation for module `\IBUFDS_INTERMDISABLE'. +Generating RTLIL representation for module `\IBUFDS_DIFF_OUT'. +Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_IBUFDISABLE'. +Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_INTERMDISABLE'. +Generating RTLIL representation for module `\IBUFDSE3'. +Generating RTLIL representation for module `\IBUFDS_DPHY'. +Generating RTLIL representation for module `\IBUFGDS'. +Generating RTLIL representation for module `\IBUFGDS_DIFF_OUT'. +Generating RTLIL representation for module `\IOBUF_DCIEN'. +Generating RTLIL representation for module `\IOBUF_INTERMDISABLE'. +Generating RTLIL representation for module `\IOBUFE3'. +Generating RTLIL representation for module `\IOBUFDS'. +Generating RTLIL representation for module `\IOBUFDS_DCIEN'. +Generating RTLIL representation for module `\IOBUFDS_INTERMDISABLE'. +Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT'. +Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_DCIEN'. +Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_INTERMDISABLE'. +Generating RTLIL representation for module `\IOBUFDSE3'. +Generating RTLIL representation for module `\OBUFDS'. +Generating RTLIL representation for module `\OBUFDS_DPHY'. +Generating RTLIL representation for module `\OBUFTDS'. +Generating RTLIL representation for module `\KEEPER'. +Generating RTLIL representation for module `\PULLDOWN'. +Generating RTLIL representation for module `\PULLUP'. +Generating RTLIL representation for module `\DCIRESET'. +Generating RTLIL representation for module `\HPIO_VREF'. +Generating RTLIL representation for module `\BUFGCE'. +Generating RTLIL representation for module `\BUFGCE_1'. +Generating RTLIL representation for module `\BUFGMUX'. +Generating RTLIL representation for module `\BUFGMUX_1'. +Generating RTLIL representation for module `\BUFGMUX_CTRL'. +Generating RTLIL representation for module `\BUFGMUX_VIRTEX4'. +Generating RTLIL representation for module `\BUFG_GT'. +Generating RTLIL representation for module `\BUFG_GT_SYNC'. +Generating RTLIL representation for module `\BUFG_PS'. +Generating RTLIL representation for module `\BUFGCE_DIV'. +Generating RTLIL representation for module `\BUFH'. +Generating RTLIL representation for module `\BUFIO2'. +Generating RTLIL representation for module `\BUFIO2_2CLK'. +Generating RTLIL representation for module `\BUFIO2FB'. +Generating RTLIL representation for module `\BUFPLL'. +Generating RTLIL representation for module `\BUFPLL_MCB'. +Generating RTLIL representation for module `\BUFIO'. +Generating RTLIL representation for module `\BUFIODQS'. +Generating RTLIL representation for module `\BUFR'. +Generating RTLIL representation for module `\BUFMR'. +Generating RTLIL representation for module `\BUFMRCE'. +Generating RTLIL representation for module `\DCM'. +Generating RTLIL representation for module `\DCM_SP'. +Generating RTLIL representation for module `\DCM_CLKGEN'. +Generating RTLIL representation for module `\DCM_ADV'. +Generating RTLIL representation for module `\DCM_BASE'. +Generating RTLIL representation for module `\DCM_PS'. +Generating RTLIL representation for module `\PMCD'. +Generating RTLIL representation for module `\PLL_ADV'. +Generating RTLIL representation for module `\PLL_BASE'. +Generating RTLIL representation for module `\MMCM_ADV'. +Generating RTLIL representation for module `\MMCM_BASE'. +Generating RTLIL representation for module `\MMCME2_ADV'. +Generating RTLIL representation for module `\MMCME2_BASE'. +Generating RTLIL representation for module `\PLLE2_ADV'. +Generating RTLIL representation for module `\PLLE2_BASE'. +Generating RTLIL representation for module `\MMCME3_ADV'. +Generating RTLIL representation for module `\MMCME3_BASE'. +Generating RTLIL representation for module `\PLLE3_ADV'. +Generating RTLIL representation for module `\PLLE3_BASE'. +Generating RTLIL representation for module `\MMCME4_ADV'. +Generating RTLIL representation for module `\MMCME4_BASE'. +Generating RTLIL representation for module `\PLLE4_ADV'. +Generating RTLIL representation for module `\PLLE4_BASE'. +Generating RTLIL representation for module `\BUFT'. +Generating RTLIL representation for module `\IN_FIFO'. +Generating RTLIL representation for module `\OUT_FIFO'. +Generating RTLIL representation for module `\HARD_SYNC'. +Generating RTLIL representation for module `\STARTUP_SPARTAN3'. +Generating RTLIL representation for module `\STARTUP_SPARTAN3E'. +Generating RTLIL representation for module `\STARTUP_SPARTAN3A'. +Generating RTLIL representation for module `\STARTUP_SPARTAN6'. +Generating RTLIL representation for module `\STARTUP_VIRTEX4'. +Generating RTLIL representation for module `\STARTUP_VIRTEX5'. +Generating RTLIL representation for module `\STARTUP_VIRTEX6'. +Generating RTLIL representation for module `\STARTUPE2'. +Generating RTLIL representation for module `\STARTUPE3'. +Generating RTLIL representation for module `\CAPTURE_SPARTAN3'. +Generating RTLIL representation for module `\CAPTURE_SPARTAN3A'. +Generating RTLIL representation for module `\CAPTURE_VIRTEX4'. +Generating RTLIL representation for module `\CAPTURE_VIRTEX5'. +Generating RTLIL representation for module `\CAPTURE_VIRTEX6'. +Generating RTLIL representation for module `\CAPTUREE2'. +Generating RTLIL representation for module `\ICAP_SPARTAN3A'. +Generating RTLIL representation for module `\ICAP_SPARTAN6'. +Generating RTLIL representation for module `\ICAP_VIRTEX4'. +Generating RTLIL representation for module `\ICAP_VIRTEX5'. +Generating RTLIL representation for module `\ICAP_VIRTEX6'. +Generating RTLIL representation for module `\ICAPE2'. +Generating RTLIL representation for module `\ICAPE3'. +Generating RTLIL representation for module `\BSCAN_SPARTAN3'. +Generating RTLIL representation for module `\BSCAN_SPARTAN3A'. +Generating RTLIL representation for module `\BSCAN_SPARTAN6'. +Generating RTLIL representation for module `\BSCAN_VIRTEX4'. +Generating RTLIL representation for module `\BSCAN_VIRTEX5'. +Generating RTLIL representation for module `\BSCAN_VIRTEX6'. +Generating RTLIL representation for module `\BSCANE2'. +Generating RTLIL representation for module `\DNA_PORT'. +Generating RTLIL representation for module `\DNA_PORTE2'. +Generating RTLIL representation for module `\FRAME_ECC_VIRTEX4'. +Generating RTLIL representation for module `\FRAME_ECC_VIRTEX5'. +Generating RTLIL representation for module `\FRAME_ECC_VIRTEX6'. +Generating RTLIL representation for module `\FRAME_ECCE2'. +Generating RTLIL representation for module `\FRAME_ECCE3'. +Generating RTLIL representation for module `\USR_ACCESS_VIRTEX4'. +Generating RTLIL representation for module `\USR_ACCESS_VIRTEX5'. +Generating RTLIL representation for module `\USR_ACCESS_VIRTEX6'. +Generating RTLIL representation for module `\USR_ACCESSE2'. +Generating RTLIL representation for module `\POST_CRC_INTERNAL'. +Generating RTLIL representation for module `\SUSPEND_SYNC'. +Generating RTLIL representation for module `\KEY_CLEAR'. +Generating RTLIL representation for module `\MASTER_JTAG'. +Generating RTLIL representation for module `\SPI_ACCESS'. +Generating RTLIL representation for module `\EFUSE_USR'. +Generating RTLIL representation for module `\SYSMON'. +Generating RTLIL representation for module `\XADC'. +Generating RTLIL representation for module `\SYSMONE1'. +Generating RTLIL representation for module `\SYSMONE4'. +Generating RTLIL representation for module `\GTPA1_DUAL'. +Generating RTLIL representation for module `\GT11_CUSTOM'. +Generating RTLIL representation for module `\GT11_DUAL'. +Generating RTLIL representation for module `\GT11CLK'. +Generating RTLIL representation for module `\GT11CLK_MGT'. +Generating RTLIL representation for module `\GTP_DUAL'. +Generating RTLIL representation for module `\GTX_DUAL'. +Generating RTLIL representation for module `\CRC32'. +Generating RTLIL representation for module `\CRC64'. +Generating RTLIL representation for module `\GTHE1_QUAD'. +Generating RTLIL representation for module `\GTXE1'. +Generating RTLIL representation for module `\IBUFDS_GTXE1'. +Generating RTLIL representation for module `\IBUFDS_GTHE1'. +Generating RTLIL representation for module `\GTHE2_CHANNEL'. +Generating RTLIL representation for module `\GTHE2_COMMON'. +Generating RTLIL representation for module `\GTPE2_CHANNEL'. +Generating RTLIL representation for module `\GTPE2_COMMON'. +Generating RTLIL representation for module `\GTXE2_CHANNEL'. +Generating RTLIL representation for module `\GTXE2_COMMON'. +Generating RTLIL representation for module `\IBUFDS_GTE2'. +Generating RTLIL representation for module `\GTHE3_CHANNEL'. +Generating RTLIL representation for module `\GTHE3_COMMON'. +Generating RTLIL representation for module `\GTHE4_CHANNEL'. +Generating RTLIL representation for module `\GTHE4_COMMON'. +Generating RTLIL representation for module `\GTYE3_CHANNEL'. +Generating RTLIL representation for module `\GTYE3_COMMON'. +Generating RTLIL representation for module `\GTYE4_CHANNEL'. +Generating RTLIL representation for module `\GTYE4_COMMON'. +Generating RTLIL representation for module `\IBUFDS_GTE3'. +Generating RTLIL representation for module `\IBUFDS_GTE4'. +Generating RTLIL representation for module `\OBUFDS_GTE3'. +Generating RTLIL representation for module `\OBUFDS_GTE3_ADV'. +Generating RTLIL representation for module `\OBUFDS_GTE4'. +Generating RTLIL representation for module `\OBUFDS_GTE4_ADV'. +Generating RTLIL representation for module `\PCIE_A1'. +Generating RTLIL representation for module `\PCIE_EP'. +Generating RTLIL representation for module `\PCIE_2_0'. +Generating RTLIL representation for module `\PCIE_2_1'. +Generating RTLIL representation for module `\PCIE_3_0'. +Generating RTLIL representation for module `\PCIE_3_1'. +Generating RTLIL representation for module `\PCIE40E4'. +Generating RTLIL representation for module `\EMAC'. +Generating RTLIL representation for module `\TEMAC'. +Generating RTLIL representation for module `\TEMAC_SINGLE'. +Generating RTLIL representation for module `\CMAC'. +Generating RTLIL representation for module `\CMACE4'. +Generating RTLIL representation for module `\PPC405_ADV'. +Generating RTLIL representation for module `\PPC440'. +Generating RTLIL representation for module `\MCB'. +Generating RTLIL representation for module `\PS7'. +Generating RTLIL representation for module `\PS8'. +Generating RTLIL representation for module `\ILKN'. +Generating RTLIL representation for module `\ILKNE4'. +Successfully finished Verilog frontend. + +6.3. Executing HIERARCHY pass (managing design hierarchy). + +6.3.1. Analyzing design hierarchy.. +Top module: \distributed_ram + +6.3.2. Analyzing design hierarchy.. +Top module: \distributed_ram +Removed 0 unused modules. + +6.4. Executing PROC pass (convert processes to netlists). + +6.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +6.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +6.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 1 assignment to connection. + +6.4.4. Executing PROC_INIT pass (extract init attributes). + +6.4.5. Executing PROC_ARST pass (detect async resets in processes). + +6.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\distributed_ram.$proc$attributes_test.v:36$188'. + 1/3: $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 + 2/3: $0$memwr$\memory$attributes_test.v:38$187_DATA[7:0]$190 + 3/3: $0$memwr$\memory$attributes_test.v:38$187_ADDR[3:0]$189 + +6.4.7. Executing PROC_DLATCH pass (convert process syncs to latches). + +6.4.8. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\distributed_ram.\data_out_r' using process `\distributed_ram.$proc$attributes_test.v:36$188'. + created $dff cell `$procdff$227' with positive edge clock. +Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$187_ADDR' using process `\distributed_ram.$proc$attributes_test.v:36$188'. + created $dff cell `$procdff$228' with positive edge clock. +Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$187_DATA' using process `\distributed_ram.$proc$attributes_test.v:36$188'. + created $dff cell `$procdff$229' with positive edge clock. +Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$187_EN' using process `\distributed_ram.$proc$attributes_test.v:36$188'. + created $dff cell `$procdff$230' with positive edge clock. + +6.4.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\distributed_ram.$proc$attributes_test.v:36$188'. +Removing empty process `distributed_ram.$proc$attributes_test.v:36$188'. +Cleaned up 1 empty switch. + +6.5. Executing TRIBUF pass. + +6.6. Executing DEMINOUT pass (demote inout ports to input or output). + +6.7. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. +Removed 0 unused cells and 7 unused wires. + + +6.9. Executing CHECK pass (checking for obvious problems). +checking module distributed_ram.. +found and reported 0 problems. + +6.10. Executing OPT pass (performing simple optimizations). + +6.10.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.10.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\distributed_ram'. +Removed a total of 0 cells. + +6.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \distributed_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +6.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \distributed_ram. + Consolidated identical input bits for $mux cell $procmux$221: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 + New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] + New connections: $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [7:1] = { $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] } + Optimizing cells in module \distributed_ram. +Performed a total of 1 changes. + +6.10.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\distributed_ram'. +Removed a total of 0 cells. + +6.10.6. Executing OPT_RMDFF pass (remove dff with constant values). + +6.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. + +6.10.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.10.9. Rerunning OPT passes. (Maybe there is more to do..) + +6.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \distributed_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +6.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \distributed_ram. +Performed a total of 0 changes. + +6.10.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\distributed_ram'. +Removed a total of 0 cells. + +6.10.13. Executing OPT_RMDFF pass (remove dff with constant values). + +6.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. + +6.10.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.10.16. Finished OPT passes. (There is nothing left to do.) + +6.11. Executing WREDUCE pass (reducing word size of cells). +Removed cell distributed_ram.$procmux$223 ($mux). +Removed cell distributed_ram.$procmux$225 ($mux). +Removed top 7 bits (of 8) from FF cell distributed_ram.$procdff$230 ($dff). + +6.12. Executing PEEPOPT pass (run peephole optimizers). + +6.13. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. +Removed 0 unused cells and 2 unused wires. + + +6.14. Executing PMUX2SHIFTX pass. + +6.15. Executing TECHMAP pass (map to technology primitives). + +6.15.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +6.15.2. Continuing TECHMAP pass. +No more expansions possible. + +6.16. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). +Checking cell `$memwr$\memory$attributes_test.v:38$193' in module `\distributed_ram': merged $dff to cell. +Checking cell `$memrd$\memory$attributes_test.v:39$192' in module `\distributed_ram': merged data $dff to cell. + +6.17. Executing TECHMAP pass (map to technology primitives). + +6.17.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +6.17.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v' to AST representation. +Generating RTLIL representation for module `\$__MUL25X18'. +Successfully finished Verilog frontend. + +6.17.3. Continuing TECHMAP pass. +No more expansions possible. + +6.18. Executing OPT_EXPR pass (perform const folding). + +6.19. Executing WREDUCE pass (reducing word size of cells). + +6.20. Executing XILINX_DSP pass (pack resources into DSPs). + +6.21. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module distributed_ram: + created 0 $alu and 0 $macc cells. + +6.22. Executing SHARE pass (SAT-based resource sharing). + +6.23. Executing OPT pass (performing simple optimizations). + +6.23.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.23.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\distributed_ram'. +Removed a total of 0 cells. + +6.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \distributed_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +6.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \distributed_ram. +Performed a total of 0 changes. + +6.23.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\distributed_ram'. +Removed a total of 0 cells. + +6.23.6. Executing OPT_RMDFF pass (remove dff with constant values). + +6.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. +Removed 4 unused cells and 5 unused wires. + + +6.23.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.23.9. Rerunning OPT passes. (Maybe there is more to do..) + +6.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \distributed_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +6.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \distributed_ram. +Performed a total of 0 changes. + +6.23.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\distributed_ram'. +Removed a total of 0 cells. + +6.23.13. Executing OPT_RMDFF pass (remove dff with constant values). + +6.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. + +6.23.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.23.16. Finished OPT passes. (There is nothing left to do.) + +6.24. Executing FSM pass (extract and optimize FSM). + +6.24.1. Executing FSM_DETECT pass (finding FSMs in design). + +6.24.2. Executing FSM_EXTRACT pass (extracting FSM from design). + +6.24.3. Executing FSM_OPT pass (simple optimizations of FSMs). + +6.24.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. + +6.24.5. Executing FSM_OPT pass (simple optimizations of FSMs). + +6.24.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). + +6.24.7. Executing FSM_INFO pass (dumping all available information on FSM cells). + +6.24.8. Executing FSM_MAP pass (mapping FSMs to basic logic). + +6.25. Executing OPT pass (performing simple optimizations). + +6.25.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.25.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\distributed_ram'. +Removed a total of 0 cells. + +6.25.3. Executing OPT_RMDFF pass (remove dff with constant values). + +6.25.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. + +6.25.5. Finished fast OPT passes. + +6.26. Executing MEMORY pass. + +6.26.1. Executing OPT_MEM pass (optimize memories). +Performed a total of 0 transformations. + +6.26.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). + +6.26.3. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. + +6.26.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). + +6.26.5. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. + +6.26.6. Executing MEMORY_COLLECT pass (generating $mem cells). +Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\distributed_ram': + $memwr$\memory$attributes_test.v:38$193 ($memwr) + $memrd$\memory$attributes_test.v:39$192 ($memrd) + +6.27. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. + +6.28. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). +Processing distributed_ram.memory: + Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16 + Checking rule #1 for bram type $__XILINX_RAMB36_SDP (variant 1): + Bram geometry: abits=9 dbits=72 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_SDP: awaste=496 dwaste=64 bwaste=36736 waste=36736 efficiency=0 + Rule #1 for bram type $__XILINX_RAMB36_SDP (variant 1) rejected: requirement 'min efficiency 5' not met. + Checking rule #2 for bram type $__XILINX_RAMB18_SDP (variant 1): + Bram geometry: abits=9 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_SDP: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0 + Rule #2 for bram type $__XILINX_RAMB18_SDP (variant 1) rejected: requirement 'min efficiency 5' not met. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 1): + Bram geometry: abits=10 dbits=36 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=1008 dwaste=28 bwaste=36736 waste=36736 efficiency=0 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 1) rejected: requirement 'min efficiency 5' not met. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 2): + Bram geometry: abits=11 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=2032 dwaste=10 bwaste=36736 waste=36736 efficiency=0 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 2) rejected: requirement 'min efficiency 5' not met. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 3): + Bram geometry: abits=12 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=4080 dwaste=1 bwaste=36736 waste=36736 efficiency=0 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 3) rejected: requirement 'min efficiency 5' not met. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 4): + Bram geometry: abits=13 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=8176 dwaste=0 bwaste=32704 waste=32704 efficiency=0 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 4) rejected: requirement 'min efficiency 5' not met. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 5): + Bram geometry: abits=14 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=16368 dwaste=0 bwaste=32736 waste=32736 efficiency=0 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 5) rejected: requirement 'min efficiency 5' not met. + Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 6): + Bram geometry: abits=15 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB36_TDP: awaste=32752 dwaste=0 bwaste=32752 waste=32752 efficiency=0 + Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 6) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 1): + Bram geometry: abits=10 dbits=18 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_TDP: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0 + Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 1) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 2): + Bram geometry: abits=11 dbits=9 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_TDP: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0 + Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 2) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 3): + Bram geometry: abits=12 dbits=4 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_TDP: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0 + Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 3) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 4): + Bram geometry: abits=13 dbits=2 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_TDP: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0 + Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 4) rejected: requirement 'min efficiency 5' not met. + Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 5): + Bram geometry: abits=14 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAMB18_TDP: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0 + Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 5) rejected: requirement 'min efficiency 5' not met. + No acceptable bram resources found. + +6.29. Executing TECHMAP pass (map to technology primitives). + +6.29.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_brams_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_brams_map.v' to AST representation. +Generating RTLIL representation for module `\$__XILINX_RAMB36_SDP'. +Generating RTLIL representation for module `\$__XILINX_RAMB18_SDP'. +Generating RTLIL representation for module `\$__XILINX_RAMB36_TDP'. +Generating RTLIL representation for module `\$__XILINX_RAMB18_TDP'. +Successfully finished Verilog frontend. + +6.29.2. Continuing TECHMAP pass. +No more expansions possible. + +6.30. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). +Processing distributed_ram.memory: + Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16 + Checking rule #1 for bram type $__XILINX_RAM32X1D (variant 1): + Bram geometry: abits=5 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAM32X1D: awaste=16 dwaste=0 bwaste=16 waste=16 efficiency=50 + Rule #1 for bram type $__XILINX_RAM32X1D (variant 1) accepted. + Mapping to bram type $__XILINX_RAM32X1D (variant 1): + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=16 efficiency=50 + Storing for later selection. + Checking rule #2 for bram type $__XILINX_RAM64X1D (variant 1): + Bram geometry: abits=6 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAM64X1D: awaste=48 dwaste=0 bwaste=48 waste=48 efficiency=25 + Rule #2 for bram type $__XILINX_RAM64X1D (variant 1) accepted. + Mapping to bram type $__XILINX_RAM64X1D (variant 1): + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=48 efficiency=25 + Storing for later selection. + Checking rule #3 for bram type $__XILINX_RAM128X1D (variant 1): + Bram geometry: abits=7 dbits=1 wports=0 rports=0 + Estimated number of duplicates for more read ports: dups=1 + Metrics for $__XILINX_RAM128X1D: awaste=112 dwaste=0 bwaste=112 waste=112 efficiency=12 + Rule #3 for bram type $__XILINX_RAM128X1D (variant 1) accepted. + Mapping to bram type $__XILINX_RAM128X1D (variant 1): + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Updated properties: dups=1 waste=112 efficiency=12 + Storing for later selection. + Selecting best of 3 rules: + Efficiency for rule 3.1: efficiency=12, cells=8, acells=1 + Efficiency for rule 2.1: efficiency=25, cells=8, acells=1 + Efficiency for rule 1.1: efficiency=50, cells=8, acells=1 + Selected rule 1.1 with efficiency 50. + Mapping to bram type $__XILINX_RAM32X1D (variant 1): + Write port #0 is in clock domain \clk. + Mapped to bram port B1. + Read port #0 is in clock domain \clk. + Mapped to bram port A1.1. + Creating $__XILINX_RAM32X1D cell at grid position <0 0 0>: memory.0.0.0 + Creating $__XILINX_RAM32X1D cell at grid position <1 0 0>: memory.1.0.0 + Creating $__XILINX_RAM32X1D cell at grid position <2 0 0>: memory.2.0.0 + Creating $__XILINX_RAM32X1D cell at grid position <3 0 0>: memory.3.0.0 + Creating $__XILINX_RAM32X1D cell at grid position <4 0 0>: memory.4.0.0 + Creating $__XILINX_RAM32X1D cell at grid position <5 0 0>: memory.5.0.0 + Creating $__XILINX_RAM32X1D cell at grid position <6 0 0>: memory.6.0.0 + Creating $__XILINX_RAM32X1D cell at grid position <7 0 0>: memory.7.0.0 + +6.31. Executing TECHMAP pass (map to technology primitives). + +6.31.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lutrams_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lutrams_map.v' to AST representation. +Generating RTLIL representation for module `\$__XILINX_RAM32X1D'. +Generating RTLIL representation for module `\$__XILINX_RAM64X1D'. +Generating RTLIL representation for module `\$__XILINX_RAM128X1D'. +Successfully finished Verilog frontend. + +6.31.2. Continuing TECHMAP pass. +Using template $paramod\$__XILINX_RAM32X1D\CLKPOL2=1 for cells of type $__XILINX_RAM32X1D. +No more expansions possible. + + +6.32. Executing OPT pass (performing simple optimizations). + +6.32.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + + +6.32.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\distributed_ram'. +Removed a total of 0 cells. + +6.32.3. Executing OPT_RMDFF pass (remove dff with constant values). + +6.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. +Removed 0 unused cells and 65 unused wires. + + +6.32.5. Finished fast OPT passes. + +6.33. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). + +6.34. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs). + +6.35. Executing DFF2DFFE pass (transform $dff to $dffe where applicable). +Transforming FF to FF+Enable cells in module distributed_ram: + +6.36. Executing OPT pass (performing simple optimizations). + +6.36.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.36.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\distributed_ram'. +Removed a total of 0 cells. + +6.36.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \distributed_ram.. + Creating internal representation of mux trees. + No muxes found in this module. +Removed 0 multiplexer ports. + +6.36.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \distributed_ram. +Performed a total of 0 changes. + +6.36.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\distributed_ram'. +Removed a total of 0 cells. + +6.36.6. Executing OPT_SHARE pass. + +6.36.7. Executing OPT_RMDFF pass (remove dff with constant values). + +6.36.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. + +6.36.9. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.36.10. Finished OPT passes. (There is nothing left to do.) + +6.37. Executing XILINX_SRL pass (Xilinx shift register extraction). + +6.38. Executing TECHMAP pass (map to technology primitives). + +6.38.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +6.38.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/arith_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/arith_map.v' to AST representation. +Generating RTLIL representation for module `\_80_xilinx_lcu'. +Generating RTLIL representation for module `\_80_xilinx_alu'. +Successfully finished Verilog frontend. + +6.38.3. Continuing TECHMAP pass. +Using extmapper simplemap for cells of type $dff. +No more expansions possible. + + +6.39. Executing OPT pass (performing simple optimizations). + +6.39.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.39.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\distributed_ram'. +Removed a total of 0 cells. + +6.39.3. Executing OPT_RMDFF pass (remove dff with constant values). + +6.39.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram.. + +6.39.5. Finished fast OPT passes. + +6.40. Executing TECHMAP pass (map to technology primitives). + +6.40.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v' to AST representation. +Generating RTLIL representation for module `\_90_simplemap_bool_ops'. +Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. +Generating RTLIL representation for module `\_90_simplemap_logic_ops'. +Generating RTLIL representation for module `\_90_simplemap_compare_ops'. +Generating RTLIL representation for module `\_90_simplemap_various'. +Generating RTLIL representation for module `\_90_simplemap_registers'. +Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. +Generating RTLIL representation for module `\_90_shift_shiftx'. +Generating RTLIL representation for module `\_90_fa'. +Generating RTLIL representation for module `\_90_lcu'. +Generating RTLIL representation for module `\_90_alu'. +Generating RTLIL representation for module `\_90_macc'. +Generating RTLIL representation for module `\_90_alumacc'. +Generating RTLIL representation for module `\$__div_mod_u'. +Generating RTLIL representation for module `\$__div_mod'. +Generating RTLIL representation for module `\_90_div'. +Generating RTLIL representation for module `\_90_mod'. +Generating RTLIL representation for module `\_90_pow'. +Generating RTLIL representation for module `\_90_pmux'. +Generating RTLIL representation for module `\_90_lut'. +Successfully finished Verilog frontend. + +6.40.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v' to AST representation. +Generating RTLIL representation for module `\_90_dff_nn0_to_np0'. +Generating RTLIL representation for module `\_90_dff_pn0_to_pp0'. +Generating RTLIL representation for module `\_90_dff_nn1_to_np1'. +Generating RTLIL representation for module `\_90_dff_pn1_to_pp1'. +Generating RTLIL representation for module `\$__SHREG_'. +Generating RTLIL representation for module `\$__XILINX_SHREG_'. +Generating RTLIL representation for module `\$__XILINX_MUXF78'. +Generating RTLIL representation for module `\$__XILINX_TINOUTPAD'. +Generating RTLIL representation for module `\$__XILINX_TOUTPAD'. +Successfully finished Verilog frontend. + +6.40.3. Continuing TECHMAP pass. +No more expansions possible. + +6.41. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram. + +6.42. Executing ABC pass (technology mapping using ABC). + +6.42.1. Extracting gate netlist of module `\distributed_ram' to `/input.blif'.. +Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. +Don't call ABC as there is nothing to map. +Removing temp directory. + +6.43. Executing XILINX_SRL pass (Xilinx shift register extraction). + +6.44. Executing TECHMAP pass (map to technology primitives). + +6.44.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lut_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lut_map.v' to AST representation. +Generating RTLIL representation for module `\$lut'. +Successfully finished Verilog frontend. + +6.44.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v' to AST representation. +Generating RTLIL representation for module `\_90_dff_nn0_to_np0'. +Generating RTLIL representation for module `\_90_dff_pn0_to_pp0'. +Generating RTLIL representation for module `\_90_dff_nn1_to_np1'. +Generating RTLIL representation for module `\_90_dff_pn1_to_pp1'. +Generating RTLIL representation for module `\$__SHREG_'. +Generating RTLIL representation for module `\$__XILINX_SHREG_'. +Generating RTLIL representation for module `\$__XILINX_MUXF78'. +Generating RTLIL representation for module `\$__XILINX_TINOUTPAD'. +Generating RTLIL representation for module `\$__XILINX_TOUTPAD'. +Successfully finished Verilog frontend. + +6.44.3. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_ff_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_ff_map.v' to AST representation. +Generating RTLIL representation for module `\$_DFF_N_'. +Generating RTLIL representation for module `\$_DFF_P_'. +Generating RTLIL representation for module `\$_DFFE_NP_'. +Generating RTLIL representation for module `\$_DFFE_PP_'. +Generating RTLIL representation for module `\$_DFF_NN0_'. +Generating RTLIL representation for module `\$_DFF_NP0_'. +Generating RTLIL representation for module `\$_DFF_PN0_'. +Generating RTLIL representation for module `\$_DFF_PP0_'. +Generating RTLIL representation for module `\$_DFF_NN1_'. +Generating RTLIL representation for module `\$_DFF_NP1_'. +Generating RTLIL representation for module `\$_DFF_PN1_'. +Generating RTLIL representation for module `\$_DFF_PP1_'. +Generating RTLIL representation for module `\$_DLATCH_N_'. +Generating RTLIL representation for module `\$_DLATCH_P_'. +Successfully finished Verilog frontend. + +6.44.4. Continuing TECHMAP pass. +Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. +No more expansions possible. + +Removed 0 unused cells and 32 unused wires. + +6.45. Executing CLKBUFMAP pass (inserting global clock buffers). +Inserting BUFG on distributed_ram.clk[0]. + +6.46. Executing HIERARCHY pass (managing design hierarchy). + +6.46.1. Analyzing design hierarchy.. +Top module: \distributed_ram + +6.46.2. Analyzing design hierarchy.. +Top module: \distributed_ram +Removed 0 unused modules. + +6.47. Printing statistics. + +=== distributed_ram === + + Number of wires: 16 + Number of wire bits: 40 + Number of public wires: 6 + Number of public wire bits: 30 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 17 + BUFG 1 + FDRE 8 + RAM32X1D 8 + + Estimated number of LCs: 0 + +6.48. Executing CHECK pass (checking for obvious problems). +checking module distributed_ram.. +found and reported 0 problems. + +7. Executing Verilog-2005 frontend: attributes_test.v +Parsing Verilog input from `attributes_test.v' to AST representation. +Generating RTLIL representation for module `\block_ram'. +Generating RTLIL representation for module `\distributed_ram'. +Generating RTLIL representation for module `\distributed_ram_manual'. +Generating RTLIL representation for module `\distributed_ram_manual_syn'. +Successfully finished Verilog frontend. + +8. Executing PREP pass. + +8.1. Executing HIERARCHY pass (managing design hierarchy). + +8.2. Executing PROC pass (convert processes to netlists). + +8.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +8.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +8.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 4 assignments to connections. + +8.2.4. Executing PROC_INIT pass (extract init attributes). + +8.2.5. Executing PROC_ARST pass (detect async resets in processes). + +8.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers). +Creating decoders for process `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. + 1/3: $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 + 2/3: $0$memwr$\memory$attributes_test.v:82$440_DATA[7:0]$444 + 3/3: $0$memwr$\memory$attributes_test.v:82$440_ADDR[3:0]$442 +Creating decoders for process `\distributed_ram_manual.$proc$attributes_test.v:58$434'. + 1/3: $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 + 2/3: $0$memwr$\memory$attributes_test.v:60$433_DATA[7:0]$437 + 3/3: $0$memwr$\memory$attributes_test.v:60$433_ADDR[3:0]$436 +Creating decoders for process `\distributed_ram.$proc$attributes_test.v:36$427'. + 1/3: $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 + 2/3: $0$memwr$\memory$attributes_test.v:38$426_DATA[7:0]$429 + 3/3: $0$memwr$\memory$attributes_test.v:38$426_ADDR[3:0]$428 +Creating decoders for process `\block_ram.$proc$attributes_test.v:14$420'. + 1/3: $0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 + 2/3: $0$memwr$\memory$attributes_test.v:16$419_DATA[3:0]$422 + 3/3: $0$memwr$\memory$attributes_test.v:16$419_ADDR[9:0]$421 + +8.2.7. Executing PROC_DLATCH pass (convert process syncs to latches). + +8.2.8. Executing PROC_DFF pass (convert process syncs to FFs). +Creating register for signal `\distributed_ram_manual_syn.$memwr$\memory$attributes_test.v:82$440_ADDR' using process `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. + created $dff cell `$procdff$471' with positive edge clock. +Creating register for signal `\distributed_ram_manual_syn.\data_out_r' using process `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. + created $dff cell `$procdff$472' with positive edge clock. +Creating register for signal `\distributed_ram_manual_syn.$memwr$\memory$attributes_test.v:82$440_EN' using process `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. + created $dff cell `$procdff$473' with positive edge clock. +Creating register for signal `\distributed_ram_manual_syn.$memwr$\memory$attributes_test.v:82$440_DATA' using process `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. + created $dff cell `$procdff$474' with positive edge clock. +Creating register for signal `\distributed_ram_manual.$memwr$\memory$attributes_test.v:60$433_EN' using process `\distributed_ram_manual.$proc$attributes_test.v:58$434'. + created $dff cell `$procdff$475' with positive edge clock. +Creating register for signal `\distributed_ram_manual.$memwr$\memory$attributes_test.v:60$433_ADDR' using process `\distributed_ram_manual.$proc$attributes_test.v:58$434'. + created $dff cell `$procdff$476' with positive edge clock. +Creating register for signal `\distributed_ram_manual.$memwr$\memory$attributes_test.v:60$433_DATA' using process `\distributed_ram_manual.$proc$attributes_test.v:58$434'. + created $dff cell `$procdff$477' with positive edge clock. +Creating register for signal `\distributed_ram_manual.\data_out_r' using process `\distributed_ram_manual.$proc$attributes_test.v:58$434'. + created $dff cell `$procdff$478' with positive edge clock. +Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$426_ADDR' using process `\distributed_ram.$proc$attributes_test.v:36$427'. + created $dff cell `$procdff$479' with positive edge clock. +Creating register for signal `\distributed_ram.\data_out_r' using process `\distributed_ram.$proc$attributes_test.v:36$427'. + created $dff cell `$procdff$480' with positive edge clock. +Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$426_DATA' using process `\distributed_ram.$proc$attributes_test.v:36$427'. + created $dff cell `$procdff$481' with positive edge clock. +Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$426_EN' using process `\distributed_ram.$proc$attributes_test.v:36$427'. + created $dff cell `$procdff$482' with positive edge clock. +Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$419_ADDR' using process `\block_ram.$proc$attributes_test.v:14$420'. + created $dff cell `$procdff$483' with positive edge clock. +Creating register for signal `\block_ram.\data_out_r' using process `\block_ram.$proc$attributes_test.v:14$420'. + created $dff cell `$procdff$484' with positive edge clock. +Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$419_DATA' using process `\block_ram.$proc$attributes_test.v:14$420'. + created $dff cell `$procdff$485' with positive edge clock. +Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$419_EN' using process `\block_ram.$proc$attributes_test.v:14$420'. + created $dff cell `$procdff$486' with positive edge clock. + +8.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Found and cleaned up 1 empty switch in `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. +Removing empty process `distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. +Found and cleaned up 1 empty switch in `\distributed_ram_manual.$proc$attributes_test.v:58$434'. +Removing empty process `distributed_ram_manual.$proc$attributes_test.v:58$434'. +Found and cleaned up 1 empty switch in `\distributed_ram.$proc$attributes_test.v:36$427'. +Removing empty process `distributed_ram.$proc$attributes_test.v:36$427'. +Found and cleaned up 1 empty switch in `\block_ram.$proc$attributes_test.v:14$420'. +Removing empty process `block_ram.$proc$attributes_test.v:14$420'. +Cleaned up 4 empty switches. + +8.3. Executing OPT_EXPR pass (perform const folding). +Optimizing module distributed_ram_manual_syn. +Optimizing module distributed_ram_manual. +Optimizing module distributed_ram. +Optimizing module block_ram. + +8.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \distributed_ram_manual_syn.. +Finding unused cells or wires in module \distributed_ram_manual.. +Finding unused cells or wires in module \distributed_ram.. +Finding unused cells or wires in module \block_ram.. +Removed 0 unused cells and 28 unused wires. + + +8.5. Executing CHECK pass (checking for obvious problems). +checking module block_ram.. +checking module distributed_ram.. +checking module distributed_ram_manual.. +checking module distributed_ram_manual_syn.. +found and reported 0 problems. + +8.6. Executing OPT pass (performing simple optimizations). + +8.6.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. +Optimizing module distributed_ram. +Optimizing module distributed_ram_manual. +Optimizing module distributed_ram_manual_syn. + +8.6.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Finding identical cells in module `\distributed_ram'. +Finding identical cells in module `\distributed_ram_manual'. +Finding identical cells in module `\distributed_ram_manual_syn'. +Removed a total of 0 cells. + +8.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \block_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \distributed_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \distributed_ram_manual.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \distributed_ram_manual_syn.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +8.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \block_ram. + Consolidated identical input bits for $mux cell $procmux$465: + Old ports: A=4'0000, B=4'1111, Y=$0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 + New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 [0] + New connections: $0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 [3:1] = { $0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 [0] $0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 [0] $0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 [0] } + Optimizing cells in module \block_ram. + Optimizing cells in module \distributed_ram. + Consolidated identical input bits for $mux cell $procmux$459: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 + New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] + New connections: $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [7:1] = { $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] } + Optimizing cells in module \distributed_ram. + Optimizing cells in module \distributed_ram_manual. + Consolidated identical input bits for $mux cell $procmux$453: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 + New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] + New connections: $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [7:1] = { $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] } + Optimizing cells in module \distributed_ram_manual. + Optimizing cells in module \distributed_ram_manual_syn. + Consolidated identical input bits for $mux cell $procmux$447: + Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 + New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] + New connections: $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [7:1] = { $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] } + Optimizing cells in module \distributed_ram_manual_syn. +Performed a total of 4 changes. + +8.6.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Finding identical cells in module `\distributed_ram'. +Finding identical cells in module `\distributed_ram_manual'. +Finding identical cells in module `\distributed_ram_manual_syn'. +Removed a total of 0 cells. + +8.6.6. Executing OPT_RMDFF pass (remove dff with constant values). + +8.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. +Finding unused cells or wires in module \distributed_ram.. +Finding unused cells or wires in module \distributed_ram_manual.. +Finding unused cells or wires in module \distributed_ram_manual_syn.. + +8.6.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. +Optimizing module distributed_ram. +Optimizing module distributed_ram_manual. +Optimizing module distributed_ram_manual_syn. + +8.6.9. Rerunning OPT passes. (Maybe there is more to do..) + +8.6.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \block_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \distributed_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \distributed_ram_manual.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Running muxtree optimizer on module \distributed_ram_manual_syn.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +8.6.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \block_ram. + Optimizing cells in module \distributed_ram. + Optimizing cells in module \distributed_ram_manual. + Optimizing cells in module \distributed_ram_manual_syn. +Performed a total of 0 changes. + +8.6.12. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Finding identical cells in module `\distributed_ram'. +Finding identical cells in module `\distributed_ram_manual'. +Finding identical cells in module `\distributed_ram_manual_syn'. +Removed a total of 0 cells. + +8.6.13. Executing OPT_RMDFF pass (remove dff with constant values). + +8.6.14. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. +Finding unused cells or wires in module \distributed_ram.. +Finding unused cells or wires in module \distributed_ram_manual.. +Finding unused cells or wires in module \distributed_ram_manual_syn.. + +8.6.15. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. +Optimizing module distributed_ram. +Optimizing module distributed_ram_manual. +Optimizing module distributed_ram_manual_syn. + +8.6.16. Finished OPT passes. (There is nothing left to do.) + +8.7. Executing WREDUCE pass (reducing word size of cells). +Removed top 3 bits (of 4) from FF cell block_ram.$procdff$486 ($dff). +Removed top 7 bits (of 8) from FF cell distributed_ram.$procdff$482 ($dff). +Removed top 7 bits (of 8) from FF cell distributed_ram_manual.$procdff$475 ($dff). +Removed top 7 bits (of 8) from FF cell distributed_ram_manual_syn.$procdff$473 ($dff). + +8.8. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). +Checking cell `$memwr$\memory$attributes_test.v:16$425' in module `\block_ram': merged $dff to cell. +Checking cell `$memwr$\memory$attributes_test.v:38$432' in module `\distributed_ram': merged $dff to cell. +Checking cell `$memwr$\memory$attributes_test.v:60$439' in module `\distributed_ram_manual': merged $dff to cell. +Checking cell `$memwr$\memory$attributes_test.v:82$446' in module `\distributed_ram_manual_syn': merged $dff to cell. + +8.9. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. +Finding unused cells or wires in module \distributed_ram.. +Finding unused cells or wires in module \distributed_ram_manual.. +Finding unused cells or wires in module \distributed_ram_manual_syn.. +Removed 12 unused cells and 12 unused wires. + + +8.10. Executing MEMORY_COLLECT pass (generating $mem cells). +Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\block_ram': + $memwr$\memory$attributes_test.v:16$425 ($memwr) + $memrd$\memory$attributes_test.v:17$424 ($memrd) +Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\distributed_ram': + $memwr$\memory$attributes_test.v:38$432 ($memwr) + $memrd$\memory$attributes_test.v:39$431 ($memrd) +Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\distributed_ram_manual': + $memwr$\memory$attributes_test.v:60$439 ($memwr) + $memrd$\memory$attributes_test.v:61$438 ($memrd) +Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\distributed_ram_manual_syn': + $memwr$\memory$attributes_test.v:82$446 ($memwr) + $memrd$\memory$attributes_test.v:83$445 ($memrd) + +8.11. Executing OPT pass (performing simple optimizations). + +8.11.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. +Optimizing module distributed_ram. +Optimizing module distributed_ram_manual. +Optimizing module distributed_ram_manual_syn. + +8.11.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Finding identical cells in module `\distributed_ram'. +Finding identical cells in module `\distributed_ram_manual'. +Finding identical cells in module `\distributed_ram_manual_syn'. +Removed a total of 0 cells. + +8.11.3. Executing OPT_RMDFF pass (remove dff with constant values). + +8.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. +Finding unused cells or wires in module \distributed_ram.. +Finding unused cells or wires in module \distributed_ram_manual.. +Finding unused cells or wires in module \distributed_ram_manual_syn.. + +8.11.5. Finished fast OPT passes. + +8.12. Printing statistics. + +=== block_ram === + + Number of wires: 10 + Number of wire bits: 46 + Number of public wires: 6 + Number of public wire bits: 24 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + $dff 1 + $mem 1 + $mux 3 + +=== distributed_ram === + + Number of wires: 10 + Number of wire bits: 58 + Number of public wires: 6 + Number of public wire bits: 30 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + $dff 1 + $mem 1 + $mux 3 + +=== distributed_ram_manual === + + Number of wires: 10 + Number of wire bits: 58 + Number of public wires: 6 + Number of public wire bits: 30 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + $dff 1 + $mem 1 + $mux 3 + +=== distributed_ram_manual_syn === + + Number of wires: 10 + Number of wire bits: 58 + Number of public wires: 6 + Number of public wire bits: 30 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 5 + $dff 1 + $mem 1 + $mux 3 + +8.13. Executing CHECK pass (checking for obvious problems). +checking module block_ram.. +checking module distributed_ram.. +checking module distributed_ram_manual.. +checking module distributed_ram_manual_syn.. +found and reported 0 problems. + +9. Executing SYNTH_XILINX pass. + +9.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v' to AST representation. +Generating RTLIL representation for module `\VCC'. +Generating RTLIL representation for module `\GND'. +Generating RTLIL representation for module `\IBUF'. +Generating RTLIL representation for module `\IBUFG'. +Generating RTLIL representation for module `\OBUF'. +Generating RTLIL representation for module `\IOBUF'. +Generating RTLIL representation for module `\OBUFT'. +Generating RTLIL representation for module `\BUFG'. +Generating RTLIL representation for module `\BUFGCTRL'. +Generating RTLIL representation for module `\BUFHCE'. +Generating RTLIL representation for module `\INV'. +Generating RTLIL representation for module `\LUT1'. +Generating RTLIL representation for module `\LUT2'. +Generating RTLIL representation for module `\LUT3'. +Generating RTLIL representation for module `\LUT4'. +Generating RTLIL representation for module `\LUT5'. +Generating RTLIL representation for module `\LUT6'. +Generating RTLIL representation for module `\LUT6_2'. +Generating RTLIL representation for module `\MUXCY'. +Generating RTLIL representation for module `\MUXF7'. +Generating RTLIL representation for module `\MUXF8'. +Generating RTLIL representation for module `\XORCY'. +Generating RTLIL representation for module `\CARRY4'. +Generating RTLIL representation for module `\FDRE'. +Generating RTLIL representation for module `\FDSE'. +Generating RTLIL representation for module `\FDCE'. +Generating RTLIL representation for module `\FDPE'. +Generating RTLIL representation for module `\FDRE_1'. +Generating RTLIL representation for module `\FDSE_1'. +Generating RTLIL representation for module `\FDCE_1'. +Generating RTLIL representation for module `\FDPE_1'. +Generating RTLIL representation for module `\LDCE'. +Generating RTLIL representation for module `\LDPE'. +Generating RTLIL representation for module `\RAM16X1S'. +Generating RTLIL representation for module `\RAM16X1S_1'. +Generating RTLIL representation for module `\RAM32X1S'. +Generating RTLIL representation for module `\RAM32X1S_1'. +Generating RTLIL representation for module `\RAM64X1S'. +Generating RTLIL representation for module `\RAM64X1S_1'. +Generating RTLIL representation for module `\RAM128X1S'. +Generating RTLIL representation for module `\RAM128X1S_1'. +Generating RTLIL representation for module `\RAM256X1S'. +Generating RTLIL representation for module `\RAM512X1S'. +Generating RTLIL representation for module `\RAM16X2S'. +Generating RTLIL representation for module `\RAM32X2S'. +Generating RTLIL representation for module `\RAM64X2S'. +Generating RTLIL representation for module `\RAM16X4S'. +Generating RTLIL representation for module `\RAM32X4S'. +Generating RTLIL representation for module `\RAM16X8S'. +Generating RTLIL representation for module `\RAM32X8S'. +Generating RTLIL representation for module `\RAM16X1D'. +Generating RTLIL representation for module `\RAM16X1D_1'. +Generating RTLIL representation for module `\RAM32X1D'. +Generating RTLIL representation for module `\RAM32X1D_1'. +Generating RTLIL representation for module `\RAM64X1D'. +Generating RTLIL representation for module `\RAM64X1D_1'. +Generating RTLIL representation for module `\RAM128X1D'. +Generating RTLIL representation for module `\RAM256X1D'. +Generating RTLIL representation for module `\RAM32M'. +Generating RTLIL representation for module `\RAM32M16'. +Generating RTLIL representation for module `\RAM64M'. +Generating RTLIL representation for module `\RAM64M8'. +Generating RTLIL representation for module `\ROM16X1'. +Generating RTLIL representation for module `\ROM32X1'. +Generating RTLIL representation for module `\ROM64X1'. +Generating RTLIL representation for module `\ROM128X1'. +Generating RTLIL representation for module `\ROM256X1'. +Generating RTLIL representation for module `\SRL16E'. +Generating RTLIL representation for module `\SRLC16E'. +Generating RTLIL representation for module `\SRLC32E'. +Generating RTLIL representation for module `\MULT18X18'. +Generating RTLIL representation for module `\MULT18X18S'. +Generating RTLIL representation for module `\MULT18X18SIO'. +Generating RTLIL representation for module `\DSP48A'. +Generating RTLIL representation for module `\DSP48A1'. +Generating RTLIL representation for module `\DSP48E1'. +Successfully finished Verilog frontend. + +9.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v' to AST representation. +Generating RTLIL representation for module `\FDCPE'. +Generating RTLIL representation for module `\FDRSE'. +Generating RTLIL representation for module `\LDCPE'. +Generating RTLIL representation for module `\AND2B1L'. +Generating RTLIL representation for module `\OR2L'. +Generating RTLIL representation for module `\MUXF5'. +Generating RTLIL representation for module `\MUXF6'. +Generating RTLIL representation for module `\MUXF9'. +Generating RTLIL representation for module `\CARRY8'. +Generating RTLIL representation for module `\ORCY'. +Generating RTLIL representation for module `\MULT_AND'. +Generating RTLIL representation for module `\SRL16'. +Generating RTLIL representation for module `\SRLC16'. +Generating RTLIL representation for module `\CFGLUT5'. +Generating RTLIL representation for module `\RAMB16_S1'. +Generating RTLIL representation for module `\RAMB16_S2'. +Generating RTLIL representation for module `\RAMB16_S4'. +Generating RTLIL representation for module `\RAMB16_S9'. +Generating RTLIL representation for module `\RAMB16_S18'. +Generating RTLIL representation for module `\RAMB16_S36'. +Generating RTLIL representation for module `\RAMB16_S1_S1'. +Generating RTLIL representation for module `\RAMB16_S1_S2'. +Generating RTLIL representation for module `\RAMB16_S1_S4'. +Generating RTLIL representation for module `\RAMB16_S1_S9'. +Generating RTLIL representation for module `\RAMB16_S1_S18'. +Generating RTLIL representation for module `\RAMB16_S1_S36'. +Generating RTLIL representation for module `\RAMB16_S2_S2'. +Generating RTLIL representation for module `\RAMB16_S2_S4'. +Generating RTLIL representation for module `\RAMB16_S2_S9'. +Generating RTLIL representation for module `\RAMB16_S2_S18'. +Generating RTLIL representation for module `\RAMB16_S2_S36'. +Generating RTLIL representation for module `\RAMB16_S4_S4'. +Generating RTLIL representation for module `\RAMB16_S4_S9'. +Generating RTLIL representation for module `\RAMB16_S4_S18'. +Generating RTLIL representation for module `\RAMB16_S4_S36'. +Generating RTLIL representation for module `\RAMB16_S9_S9'. +Generating RTLIL representation for module `\RAMB16_S9_S18'. +Generating RTLIL representation for module `\RAMB16_S9_S36'. +Generating RTLIL representation for module `\RAMB16_S18_S18'. +Generating RTLIL representation for module `\RAMB16_S18_S36'. +Generating RTLIL representation for module `\RAMB16_S36_S36'. +Generating RTLIL representation for module `\RAMB16BWE_S18'. +Generating RTLIL representation for module `\RAMB16BWE_S36'. +Generating RTLIL representation for module `\RAMB16BWE_S18_S9'. +Generating RTLIL representation for module `\RAMB16BWE_S18_S18'. +Generating RTLIL representation for module `\RAMB16BWE_S36_S9'. +Generating RTLIL representation for module `\RAMB16BWE_S36_S18'. +Generating RTLIL representation for module `\RAMB16BWE_S36_S36'. +Generating RTLIL representation for module `\RAMB16BWER'. +Generating RTLIL representation for module `\RAMB8BWER'. +Generating RTLIL representation for module `\FIFO16'. +Generating RTLIL representation for module `\RAMB16'. +Generating RTLIL representation for module `\RAMB32_S64_ECC'. +Generating RTLIL representation for module `\FIFO18'. +Generating RTLIL representation for module `\FIFO18_36'. +Generating RTLIL representation for module `\FIFO36'. +Generating RTLIL representation for module `\FIFO36_72'. +Generating RTLIL representation for module `\RAMB18'. +Generating RTLIL representation for module `\RAMB36'. +Generating RTLIL representation for module `\RAMB18SDP'. +Generating RTLIL representation for module `\RAMB36SDP'. +Generating RTLIL representation for module `\FIFO18E1'. +Generating RTLIL representation for module `\FIFO36E1'. +Generating RTLIL representation for module `\RAMB18E1'. +Generating RTLIL representation for module `\RAMB36E1'. +Generating RTLIL representation for module `\FIFO18E2'. +Generating RTLIL representation for module `\FIFO36E2'. +Generating RTLIL representation for module `\RAMB18E2'. +Generating RTLIL representation for module `\RAMB36E2'. +Generating RTLIL representation for module `\URAM288'. +Generating RTLIL representation for module `\URAM288_BASE'. +Generating RTLIL representation for module `\DSP48'. +Generating RTLIL representation for module `\DSP48E'. +Generating RTLIL representation for module `\DSP48E2'. +Generating RTLIL representation for module `\IFDDRCPE'. +Generating RTLIL representation for module `\IFDDRRSE'. +Generating RTLIL representation for module `\OFDDRCPE'. +Generating RTLIL representation for module `\OFDDRRSE'. +Generating RTLIL representation for module `\OFDDRTCPE'. +Generating RTLIL representation for module `\OFDDRTRSE'. +Generating RTLIL representation for module `\IDDR2'. +Generating RTLIL representation for module `\ODDR2'. +Generating RTLIL representation for module `\IDDR'. +Generating RTLIL representation for module `\IDDR_2CLK'. +Generating RTLIL representation for module `\ODDR'. +Generating RTLIL representation for module `\IDELAYCTRL'. +Generating RTLIL representation for module `\IDELAY'. +Generating RTLIL representation for module `\ISERDES'. +Generating RTLIL representation for module `\OSERDES'. +Generating RTLIL representation for module `\IODELAY'. +Generating RTLIL representation for module `\ISERDES_NODELAY'. +Generating RTLIL representation for module `\IODELAYE1'. +Generating RTLIL representation for module `\ISERDESE1'. +Generating RTLIL representation for module `\OSERDESE1'. +Generating RTLIL representation for module `\IDELAYE2'. +Generating RTLIL representation for module `\ODELAYE2'. +Generating RTLIL representation for module `\ISERDESE2'. +Generating RTLIL representation for module `\OSERDESE2'. +Generating RTLIL representation for module `\PHASER_IN'. +Generating RTLIL representation for module `\PHASER_IN_PHY'. +Generating RTLIL representation for module `\PHASER_OUT'. +Generating RTLIL representation for module `\PHASER_OUT_PHY'. +Generating RTLIL representation for module `\PHASER_REF'. +Generating RTLIL representation for module `\PHY_CONTROL'. +Generating RTLIL representation for module `\IDDRE1'. +Generating RTLIL representation for module `\ODDRE1'. +Generating RTLIL representation for module `\IDELAYE3'. +Generating RTLIL representation for module `\ODELAYE3'. +Generating RTLIL representation for module `\ISERDESE3'. +Generating RTLIL representation for module `\OSERDESE3'. +Generating RTLIL representation for module `\BITSLICE_CONTROL'. +Generating RTLIL representation for module `\RIU_OR'. +Generating RTLIL representation for module `\RX_BITSLICE'. +Generating RTLIL representation for module `\RXTX_BITSLICE'. +Generating RTLIL representation for module `\TX_BITSLICE'. +Generating RTLIL representation for module `\TX_BITSLICE_TRI'. +Generating RTLIL representation for module `\IODELAY2'. +Generating RTLIL representation for module `\IODRP2'. +Generating RTLIL representation for module `\IODRP2_MCB'. +Generating RTLIL representation for module `\ISERDES2'. +Generating RTLIL representation for module `\OSERDES2'. +Generating RTLIL representation for module `\IBUF_DLY_ADJ'. +Generating RTLIL representation for module `\IBUF_IBUFDISABLE'. +Generating RTLIL representation for module `\IBUF_INTERMDISABLE'. +Generating RTLIL representation for module `\IBUF_ANALOG'. +Generating RTLIL representation for module `\IBUFE3'. +Generating RTLIL representation for module `\IBUFDS'. +Generating RTLIL representation for module `\IBUFDS_DLY_ADJ'. +Generating RTLIL representation for module `\IBUFDS_IBUFDISABLE'. +Generating RTLIL representation for module `\IBUFDS_INTERMDISABLE'. +Generating RTLIL representation for module `\IBUFDS_DIFF_OUT'. +Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_IBUFDISABLE'. +Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_INTERMDISABLE'. +Generating RTLIL representation for module `\IBUFDSE3'. +Generating RTLIL representation for module `\IBUFDS_DPHY'. +Generating RTLIL representation for module `\IBUFGDS'. +Generating RTLIL representation for module `\IBUFGDS_DIFF_OUT'. +Generating RTLIL representation for module `\IOBUF_DCIEN'. +Generating RTLIL representation for module `\IOBUF_INTERMDISABLE'. +Generating RTLIL representation for module `\IOBUFE3'. +Generating RTLIL representation for module `\IOBUFDS'. +Generating RTLIL representation for module `\IOBUFDS_DCIEN'. +Generating RTLIL representation for module `\IOBUFDS_INTERMDISABLE'. +Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT'. +Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_DCIEN'. +Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_INTERMDISABLE'. +Generating RTLIL representation for module `\IOBUFDSE3'. +Generating RTLIL representation for module `\OBUFDS'. +Generating RTLIL representation for module `\OBUFDS_DPHY'. +Generating RTLIL representation for module `\OBUFTDS'. +Generating RTLIL representation for module `\KEEPER'. +Generating RTLIL representation for module `\PULLDOWN'. +Generating RTLIL representation for module `\PULLUP'. +Generating RTLIL representation for module `\DCIRESET'. +Generating RTLIL representation for module `\HPIO_VREF'. +Generating RTLIL representation for module `\BUFGCE'. +Generating RTLIL representation for module `\BUFGCE_1'. +Generating RTLIL representation for module `\BUFGMUX'. +Generating RTLIL representation for module `\BUFGMUX_1'. +Generating RTLIL representation for module `\BUFGMUX_CTRL'. +Generating RTLIL representation for module `\BUFGMUX_VIRTEX4'. +Generating RTLIL representation for module `\BUFG_GT'. +Generating RTLIL representation for module `\BUFG_GT_SYNC'. +Generating RTLIL representation for module `\BUFG_PS'. +Generating RTLIL representation for module `\BUFGCE_DIV'. +Generating RTLIL representation for module `\BUFH'. +Generating RTLIL representation for module `\BUFIO2'. +Generating RTLIL representation for module `\BUFIO2_2CLK'. +Generating RTLIL representation for module `\BUFIO2FB'. +Generating RTLIL representation for module `\BUFPLL'. +Generating RTLIL representation for module `\BUFPLL_MCB'. +Generating RTLIL representation for module `\BUFIO'. +Generating RTLIL representation for module `\BUFIODQS'. +Generating RTLIL representation for module `\BUFR'. +Generating RTLIL representation for module `\BUFMR'. +Generating RTLIL representation for module `\BUFMRCE'. +Generating RTLIL representation for module `\DCM'. +Generating RTLIL representation for module `\DCM_SP'. +Generating RTLIL representation for module `\DCM_CLKGEN'. +Generating RTLIL representation for module `\DCM_ADV'. +Generating RTLIL representation for module `\DCM_BASE'. +Generating RTLIL representation for module `\DCM_PS'. +Generating RTLIL representation for module `\PMCD'. +Generating RTLIL representation for module `\PLL_ADV'. +Generating RTLIL representation for module `\PLL_BASE'. +Generating RTLIL representation for module `\MMCM_ADV'. +Generating RTLIL representation for module `\MMCM_BASE'. +Generating RTLIL representation for module `\MMCME2_ADV'. +Generating RTLIL representation for module `\MMCME2_BASE'. +Generating RTLIL representation for module `\PLLE2_ADV'. +Generating RTLIL representation for module `\PLLE2_BASE'. +Generating RTLIL representation for module `\MMCME3_ADV'. +Generating RTLIL representation for module `\MMCME3_BASE'. +Generating RTLIL representation for module `\PLLE3_ADV'. +Generating RTLIL representation for module `\PLLE3_BASE'. +Generating RTLIL representation for module `\MMCME4_ADV'. +Generating RTLIL representation for module `\MMCME4_BASE'. +Generating RTLIL representation for module `\PLLE4_ADV'. +Generating RTLIL representation for module `\PLLE4_BASE'. +Generating RTLIL representation for module `\BUFT'. +Generating RTLIL representation for module `\IN_FIFO'. +Generating RTLIL representation for module `\OUT_FIFO'. +Generating RTLIL representation for module `\HARD_SYNC'. +Generating RTLIL representation for module `\STARTUP_SPARTAN3'. +Generating RTLIL representation for module `\STARTUP_SPARTAN3E'. +Generating RTLIL representation for module `\STARTUP_SPARTAN3A'. +Generating RTLIL representation for module `\STARTUP_SPARTAN6'. +Generating RTLIL representation for module `\STARTUP_VIRTEX4'. +Generating RTLIL representation for module `\STARTUP_VIRTEX5'. +Generating RTLIL representation for module `\STARTUP_VIRTEX6'. +Generating RTLIL representation for module `\STARTUPE2'. +Generating RTLIL representation for module `\STARTUPE3'. +Generating RTLIL representation for module `\CAPTURE_SPARTAN3'. +Generating RTLIL representation for module `\CAPTURE_SPARTAN3A'. +Generating RTLIL representation for module `\CAPTURE_VIRTEX4'. +Generating RTLIL representation for module `\CAPTURE_VIRTEX5'. +Generating RTLIL representation for module `\CAPTURE_VIRTEX6'. +Generating RTLIL representation for module `\CAPTUREE2'. +Generating RTLIL representation for module `\ICAP_SPARTAN3A'. +Generating RTLIL representation for module `\ICAP_SPARTAN6'. +Generating RTLIL representation for module `\ICAP_VIRTEX4'. +Generating RTLIL representation for module `\ICAP_VIRTEX5'. +Generating RTLIL representation for module `\ICAP_VIRTEX6'. +Generating RTLIL representation for module `\ICAPE2'. +Generating RTLIL representation for module `\ICAPE3'. +Generating RTLIL representation for module `\BSCAN_SPARTAN3'. +Generating RTLIL representation for module `\BSCAN_SPARTAN3A'. +Generating RTLIL representation for module `\BSCAN_SPARTAN6'. +Generating RTLIL representation for module `\BSCAN_VIRTEX4'. +Generating RTLIL representation for module `\BSCAN_VIRTEX5'. +Generating RTLIL representation for module `\BSCAN_VIRTEX6'. +Generating RTLIL representation for module `\BSCANE2'. +Generating RTLIL representation for module `\DNA_PORT'. +Generating RTLIL representation for module `\DNA_PORTE2'. +Generating RTLIL representation for module `\FRAME_ECC_VIRTEX4'. +Generating RTLIL representation for module `\FRAME_ECC_VIRTEX5'. +Generating RTLIL representation for module `\FRAME_ECC_VIRTEX6'. +Generating RTLIL representation for module `\FRAME_ECCE2'. +Generating RTLIL representation for module `\FRAME_ECCE3'. +Generating RTLIL representation for module `\USR_ACCESS_VIRTEX4'. +Generating RTLIL representation for module `\USR_ACCESS_VIRTEX5'. +Generating RTLIL representation for module `\USR_ACCESS_VIRTEX6'. +Generating RTLIL representation for module `\USR_ACCESSE2'. +Generating RTLIL representation for module `\POST_CRC_INTERNAL'. +Generating RTLIL representation for module `\SUSPEND_SYNC'. +Generating RTLIL representation for module `\KEY_CLEAR'. +Generating RTLIL representation for module `\MASTER_JTAG'. +Generating RTLIL representation for module `\SPI_ACCESS'. +Generating RTLIL representation for module `\EFUSE_USR'. +Generating RTLIL representation for module `\SYSMON'. +Generating RTLIL representation for module `\XADC'. +Generating RTLIL representation for module `\SYSMONE1'. +Generating RTLIL representation for module `\SYSMONE4'. +Generating RTLIL representation for module `\GTPA1_DUAL'. +Generating RTLIL representation for module `\GT11_CUSTOM'. +Generating RTLIL representation for module `\GT11_DUAL'. +Generating RTLIL representation for module `\GT11CLK'. +Generating RTLIL representation for module `\GT11CLK_MGT'. +Generating RTLIL representation for module `\GTP_DUAL'. +Generating RTLIL representation for module `\GTX_DUAL'. +Generating RTLIL representation for module `\CRC32'. +Generating RTLIL representation for module `\CRC64'. +Generating RTLIL representation for module `\GTHE1_QUAD'. +Generating RTLIL representation for module `\GTXE1'. +Generating RTLIL representation for module `\IBUFDS_GTXE1'. +Generating RTLIL representation for module `\IBUFDS_GTHE1'. +Generating RTLIL representation for module `\GTHE2_CHANNEL'. +Generating RTLIL representation for module `\GTHE2_COMMON'. +Generating RTLIL representation for module `\GTPE2_CHANNEL'. +Generating RTLIL representation for module `\GTPE2_COMMON'. +Generating RTLIL representation for module `\GTXE2_CHANNEL'. +Generating RTLIL representation for module `\GTXE2_COMMON'. +Generating RTLIL representation for module `\IBUFDS_GTE2'. +Generating RTLIL representation for module `\GTHE3_CHANNEL'. +Generating RTLIL representation for module `\GTHE3_COMMON'. +Generating RTLIL representation for module `\GTHE4_CHANNEL'. +Generating RTLIL representation for module `\GTHE4_COMMON'. +Generating RTLIL representation for module `\GTYE3_CHANNEL'. +Generating RTLIL representation for module `\GTYE3_COMMON'. +Generating RTLIL representation for module `\GTYE4_CHANNEL'. +Generating RTLIL representation for module `\GTYE4_COMMON'. +Generating RTLIL representation for module `\IBUFDS_GTE3'. +Generating RTLIL representation for module `\IBUFDS_GTE4'. +Generating RTLIL representation for module `\OBUFDS_GTE3'. +Generating RTLIL representation for module `\OBUFDS_GTE3_ADV'. +Generating RTLIL representation for module `\OBUFDS_GTE4'. +Generating RTLIL representation for module `\OBUFDS_GTE4_ADV'. +Generating RTLIL representation for module `\PCIE_A1'. +Generating RTLIL representation for module `\PCIE_EP'. +Generating RTLIL representation for module `\PCIE_2_0'. +Generating RTLIL representation for module `\PCIE_2_1'. +Generating RTLIL representation for module `\PCIE_3_0'. +Generating RTLIL representation for module `\PCIE_3_1'. +Generating RTLIL representation for module `\PCIE40E4'. +Generating RTLIL representation for module `\EMAC'. +Generating RTLIL representation for module `\TEMAC'. +Generating RTLIL representation for module `\TEMAC_SINGLE'. +Generating RTLIL representation for module `\CMAC'. +Generating RTLIL representation for module `\CMACE4'. +Generating RTLIL representation for module `\PPC405_ADV'. +Generating RTLIL representation for module `\PPC440'. +Generating RTLIL representation for module `\MCB'. +Generating RTLIL representation for module `\PS7'. +Generating RTLIL representation for module `\PS8'. +Generating RTLIL representation for module `\ILKN'. +Generating RTLIL representation for module `\ILKNE4'. +Successfully finished Verilog frontend. + +9.3. Executing HIERARCHY pass (managing design hierarchy). + +9.3.1. Analyzing design hierarchy.. +Top module: \block_ram + +9.3.2. Analyzing design hierarchy.. +Top module: \block_ram +Removing unused module `\distributed_ram'. +Removing unused module `\distributed_ram_manual'. +Removing unused module `\distributed_ram_manual_syn'. +Removed 3 unused modules. + +9.4. Executing PROC pass (convert processes to netlists). + +9.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +9.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). +Removed a total of 0 dead cases. + +9.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). +Removed 0 redundant assignments. +Promoted 0 assignments to connections. + +9.4.4. Executing PROC_INIT pass (extract init attributes). + +9.4.5. Executing PROC_ARST pass (detect async resets in processes). + +9.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers). + +9.4.7. Executing PROC_DLATCH pass (convert process syncs to latches). + +9.4.8. Executing PROC_DFF pass (convert process syncs to FFs). + +9.4.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). +Cleaned up 0 empty switches. + +9.5. Executing TRIBUF pass. + +9.6. Executing DEMINOUT pass (demote inout ports to input or output). + +9.7. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +9.8. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +9.9. Executing CHECK pass (checking for obvious problems). +checking module block_ram.. +found and reported 0 problems. + +9.10. Executing OPT pass (performing simple optimizations). + +9.10.1. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +9.10.2. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +9.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). +Running muxtree optimizer on module \block_ram.. + Creating internal representation of mux trees. + Evaluating internal representation of mux trees. + Analyzing evaluation results. +Removed 0 multiplexer ports. + + +9.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). + Optimizing cells in module \block_ram. +Performed a total of 0 changes. + +9.10.5. Executing OPT_MERGE pass (detect identical cells). +Finding identical cells in module `\block_ram'. +Removed a total of 0 cells. + +9.10.6. Executing OPT_RMDFF pass (remove dff with constant values). + +9.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. + +9.10.8. Executing OPT_EXPR pass (perform const folding). +Optimizing module block_ram. + +9.10.9. Finished OPT passes. (There is nothing left to do.) + +9.11. Executing WREDUCE pass (reducing word size of cells). +Removed cell block_ram.$procmux$469 ($mux). +Removed cell block_ram.$procmux$467 ($mux). + +9.12. Executing PEEPOPT pass (run peephole optimizers). + +9.13. Executing OPT_CLEAN pass (remove unused cells and wires). +Finding unused cells or wires in module \block_ram.. +Removed 0 unused cells and 2 unused wires. + + +9.14. Executing PMUX2SHIFTX pass. + +9.15. Executing TECHMAP pass (map to technology primitives). + +9.15.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v' to AST representation. +Generating RTLIL representation for module `\_90_lut_cmp_'. +Successfully finished Verilog frontend. + +9.15.2. Continuing TECHMAP pass. +No more expansions possible. + +9.16. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). + +9.17. Executing TECHMAP pass (map to technology primitives). + +9.17.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v' to AST representation. +Generating RTLIL representation for module `\_80_mul'. +Generating RTLIL representation for module `\_90_soft_mul'. +Successfully finished Verilog frontend. + +9.17.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v +Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v' to AST representation. +Generating RTLIL representation for module `\$__MUL25X18'. +Successfully finished Verilog frontend. + +9.17.3. Continuing TECHMAP pass. +No more expansions possible. + +9.18. Executing OPT_EXPR pass (perform const folding). + +9.19. Executing WREDUCE pass (reducing word size of cells). + +9.20. Executing XILINX_DSP pass (pack resources into DSPs). + +9.21. Executing ALUMACC pass (create $alu and $macc cells). +Extracting $alu and $macc cells in module block_ram: + created 0 $alu and 0 $macc cells. + +9.22. Executing SHARE pass (SAT-based resource sharing). -- cgit v1.2.3 From f3f59910eb06bf74a2a4b8157797a327dd097451 Mon Sep 17 00:00:00 2001 From: Diego H Date: Sun, 15 Dec 2019 23:51:58 -0600 Subject: Removing fixed attribute value to !ramstyle rules --- tests/arch/common/memory_attributes/log | 3238 ------------------------------- 1 file changed, 3238 deletions(-) delete mode 100644 tests/arch/common/memory_attributes/log (limited to 'tests') diff --git a/tests/arch/common/memory_attributes/log b/tests/arch/common/memory_attributes/log deleted file mode 100644 index 5d526e661..000000000 --- a/tests/arch/common/memory_attributes/log +++ /dev/null @@ -1,3238 +0,0 @@ - - /----------------------------------------------------------------------------\ - | | - | yosys -- Yosys Open SYnthesis Suite | - | | - | Copyright (C) 2012 - 2019 Clifford Wolf | - | | - | Permission to use, copy, modify, and/or distribute this software for any | - | purpose with or without fee is hereby granted, provided that the above | - | copyright notice and this permission notice appear in all copies. | - | | - | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | - | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | - | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | - | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | - | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | - | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | - | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | - | | - \----------------------------------------------------------------------------/ - - Yosys 0.9+932 (git sha1 26699340, clang 6.0.0-1ubuntu2 -fPIC -Os) - - --- Executing script file `attributes_test.ys' -- - -1. Executing Verilog-2005 frontend: attributes_test.v -Parsing Verilog input from `attributes_test.v' to AST representation. -Generating RTLIL representation for module `\block_ram'. -Generating RTLIL representation for module `\distributed_ram'. -Generating RTLIL representation for module `\distributed_ram_manual'. -Generating RTLIL representation for module `\distributed_ram_manual_syn'. -Successfully finished Verilog frontend. - -2. Executing HIERARCHY pass (managing design hierarchy). - -2.1. Analyzing design hierarchy.. -Top module: \block_ram - -2.2. Analyzing design hierarchy.. -Top module: \block_ram -Removing unused module `\distributed_ram_manual_syn'. -Removing unused module `\distributed_ram_manual'. -Removing unused module `\distributed_ram'. -Removed 3 unused modules. - -3. Executing SYNTH_XILINX pass. - -3.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v' to AST representation. -Generating RTLIL representation for module `\VCC'. -Generating RTLIL representation for module `\GND'. -Generating RTLIL representation for module `\IBUF'. -Generating RTLIL representation for module `\IBUFG'. -Generating RTLIL representation for module `\OBUF'. -Generating RTLIL representation for module `\IOBUF'. -Generating RTLIL representation for module `\OBUFT'. -Generating RTLIL representation for module `\BUFG'. -Generating RTLIL representation for module `\BUFGCTRL'. -Generating RTLIL representation for module `\BUFHCE'. -Generating RTLIL representation for module `\INV'. -Generating RTLIL representation for module `\LUT1'. -Generating RTLIL representation for module `\LUT2'. -Generating RTLIL representation for module `\LUT3'. -Generating RTLIL representation for module `\LUT4'. -Generating RTLIL representation for module `\LUT5'. -Generating RTLIL representation for module `\LUT6'. -Generating RTLIL representation for module `\LUT6_2'. -Generating RTLIL representation for module `\MUXCY'. -Generating RTLIL representation for module `\MUXF7'. -Generating RTLIL representation for module `\MUXF8'. -Generating RTLIL representation for module `\XORCY'. -Generating RTLIL representation for module `\CARRY4'. -Generating RTLIL representation for module `\FDRE'. -Generating RTLIL representation for module `\FDSE'. -Generating RTLIL representation for module `\FDCE'. -Generating RTLIL representation for module `\FDPE'. -Generating RTLIL representation for module `\FDRE_1'. -Generating RTLIL representation for module `\FDSE_1'. -Generating RTLIL representation for module `\FDCE_1'. -Generating RTLIL representation for module `\FDPE_1'. -Generating RTLIL representation for module `\LDCE'. -Generating RTLIL representation for module `\LDPE'. -Generating RTLIL representation for module `\RAM16X1S'. -Generating RTLIL representation for module `\RAM16X1S_1'. -Generating RTLIL representation for module `\RAM32X1S'. -Generating RTLIL representation for module `\RAM32X1S_1'. -Generating RTLIL representation for module `\RAM64X1S'. -Generating RTLIL representation for module `\RAM64X1S_1'. -Generating RTLIL representation for module `\RAM128X1S'. -Generating RTLIL representation for module `\RAM128X1S_1'. -Generating RTLIL representation for module `\RAM256X1S'. -Generating RTLIL representation for module `\RAM512X1S'. -Generating RTLIL representation for module `\RAM16X2S'. -Generating RTLIL representation for module `\RAM32X2S'. -Generating RTLIL representation for module `\RAM64X2S'. -Generating RTLIL representation for module `\RAM16X4S'. -Generating RTLIL representation for module `\RAM32X4S'. -Generating RTLIL representation for module `\RAM16X8S'. -Generating RTLIL representation for module `\RAM32X8S'. -Generating RTLIL representation for module `\RAM16X1D'. -Generating RTLIL representation for module `\RAM16X1D_1'. -Generating RTLIL representation for module `\RAM32X1D'. -Generating RTLIL representation for module `\RAM32X1D_1'. -Generating RTLIL representation for module `\RAM64X1D'. -Generating RTLIL representation for module `\RAM64X1D_1'. -Generating RTLIL representation for module `\RAM128X1D'. -Generating RTLIL representation for module `\RAM256X1D'. -Generating RTLIL representation for module `\RAM32M'. -Generating RTLIL representation for module `\RAM32M16'. -Generating RTLIL representation for module `\RAM64M'. -Generating RTLIL representation for module `\RAM64M8'. -Generating RTLIL representation for module `\ROM16X1'. -Generating RTLIL representation for module `\ROM32X1'. -Generating RTLIL representation for module `\ROM64X1'. -Generating RTLIL representation for module `\ROM128X1'. -Generating RTLIL representation for module `\ROM256X1'. -Generating RTLIL representation for module `\SRL16E'. -Generating RTLIL representation for module `\SRLC16E'. -Generating RTLIL representation for module `\SRLC32E'. -Generating RTLIL representation for module `\MULT18X18'. -Generating RTLIL representation for module `\MULT18X18S'. -Generating RTLIL representation for module `\MULT18X18SIO'. -Generating RTLIL representation for module `\DSP48A'. -Generating RTLIL representation for module `\DSP48A1'. -Generating RTLIL representation for module `\DSP48E1'. -Successfully finished Verilog frontend. - -3.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v' to AST representation. -Generating RTLIL representation for module `\FDCPE'. -Generating RTLIL representation for module `\FDRSE'. -Generating RTLIL representation for module `\LDCPE'. -Generating RTLIL representation for module `\AND2B1L'. -Generating RTLIL representation for module `\OR2L'. -Generating RTLIL representation for module `\MUXF5'. -Generating RTLIL representation for module `\MUXF6'. -Generating RTLIL representation for module `\MUXF9'. -Generating RTLIL representation for module `\CARRY8'. -Generating RTLIL representation for module `\ORCY'. -Generating RTLIL representation for module `\MULT_AND'. -Generating RTLIL representation for module `\SRL16'. -Generating RTLIL representation for module `\SRLC16'. -Generating RTLIL representation for module `\CFGLUT5'. -Generating RTLIL representation for module `\RAMB16_S1'. -Generating RTLIL representation for module `\RAMB16_S2'. -Generating RTLIL representation for module `\RAMB16_S4'. -Generating RTLIL representation for module `\RAMB16_S9'. -Generating RTLIL representation for module `\RAMB16_S18'. -Generating RTLIL representation for module `\RAMB16_S36'. -Generating RTLIL representation for module `\RAMB16_S1_S1'. -Generating RTLIL representation for module `\RAMB16_S1_S2'. -Generating RTLIL representation for module `\RAMB16_S1_S4'. -Generating RTLIL representation for module `\RAMB16_S1_S9'. -Generating RTLIL representation for module `\RAMB16_S1_S18'. -Generating RTLIL representation for module `\RAMB16_S1_S36'. -Generating RTLIL representation for module `\RAMB16_S2_S2'. -Generating RTLIL representation for module `\RAMB16_S2_S4'. -Generating RTLIL representation for module `\RAMB16_S2_S9'. -Generating RTLIL representation for module `\RAMB16_S2_S18'. -Generating RTLIL representation for module `\RAMB16_S2_S36'. -Generating RTLIL representation for module `\RAMB16_S4_S4'. -Generating RTLIL representation for module `\RAMB16_S4_S9'. -Generating RTLIL representation for module `\RAMB16_S4_S18'. -Generating RTLIL representation for module `\RAMB16_S4_S36'. -Generating RTLIL representation for module `\RAMB16_S9_S9'. -Generating RTLIL representation for module `\RAMB16_S9_S18'. -Generating RTLIL representation for module `\RAMB16_S9_S36'. -Generating RTLIL representation for module `\RAMB16_S18_S18'. -Generating RTLIL representation for module `\RAMB16_S18_S36'. -Generating RTLIL representation for module `\RAMB16_S36_S36'. -Generating RTLIL representation for module `\RAMB16BWE_S18'. -Generating RTLIL representation for module `\RAMB16BWE_S36'. -Generating RTLIL representation for module `\RAMB16BWE_S18_S9'. -Generating RTLIL representation for module `\RAMB16BWE_S18_S18'. -Generating RTLIL representation for module `\RAMB16BWE_S36_S9'. -Generating RTLIL representation for module `\RAMB16BWE_S36_S18'. -Generating RTLIL representation for module `\RAMB16BWE_S36_S36'. -Generating RTLIL representation for module `\RAMB16BWER'. -Generating RTLIL representation for module `\RAMB8BWER'. -Generating RTLIL representation for module `\FIFO16'. -Generating RTLIL representation for module `\RAMB16'. -Generating RTLIL representation for module `\RAMB32_S64_ECC'. -Generating RTLIL representation for module `\FIFO18'. -Generating RTLIL representation for module `\FIFO18_36'. -Generating RTLIL representation for module `\FIFO36'. -Generating RTLIL representation for module `\FIFO36_72'. -Generating RTLIL representation for module `\RAMB18'. -Generating RTLIL representation for module `\RAMB36'. -Generating RTLIL representation for module `\RAMB18SDP'. -Generating RTLIL representation for module `\RAMB36SDP'. -Generating RTLIL representation for module `\FIFO18E1'. -Generating RTLIL representation for module `\FIFO36E1'. -Generating RTLIL representation for module `\RAMB18E1'. -Generating RTLIL representation for module `\RAMB36E1'. -Generating RTLIL representation for module `\FIFO18E2'. -Generating RTLIL representation for module `\FIFO36E2'. -Generating RTLIL representation for module `\RAMB18E2'. -Generating RTLIL representation for module `\RAMB36E2'. -Generating RTLIL representation for module `\URAM288'. -Generating RTLIL representation for module `\URAM288_BASE'. -Generating RTLIL representation for module `\DSP48'. -Generating RTLIL representation for module `\DSP48E'. -Generating RTLIL representation for module `\DSP48E2'. -Generating RTLIL representation for module `\IFDDRCPE'. -Generating RTLIL representation for module `\IFDDRRSE'. -Generating RTLIL representation for module `\OFDDRCPE'. -Generating RTLIL representation for module `\OFDDRRSE'. -Generating RTLIL representation for module `\OFDDRTCPE'. -Generating RTLIL representation for module `\OFDDRTRSE'. -Generating RTLIL representation for module `\IDDR2'. -Generating RTLIL representation for module `\ODDR2'. -Generating RTLIL representation for module `\IDDR'. -Generating RTLIL representation for module `\IDDR_2CLK'. -Generating RTLIL representation for module `\ODDR'. -Generating RTLIL representation for module `\IDELAYCTRL'. -Generating RTLIL representation for module `\IDELAY'. -Generating RTLIL representation for module `\ISERDES'. -Generating RTLIL representation for module `\OSERDES'. -Generating RTLIL representation for module `\IODELAY'. -Generating RTLIL representation for module `\ISERDES_NODELAY'. -Generating RTLIL representation for module `\IODELAYE1'. -Generating RTLIL representation for module `\ISERDESE1'. -Generating RTLIL representation for module `\OSERDESE1'. -Generating RTLIL representation for module `\IDELAYE2'. -Generating RTLIL representation for module `\ODELAYE2'. -Generating RTLIL representation for module `\ISERDESE2'. -Generating RTLIL representation for module `\OSERDESE2'. -Generating RTLIL representation for module `\PHASER_IN'. -Generating RTLIL representation for module `\PHASER_IN_PHY'. -Generating RTLIL representation for module `\PHASER_OUT'. -Generating RTLIL representation for module `\PHASER_OUT_PHY'. -Generating RTLIL representation for module `\PHASER_REF'. -Generating RTLIL representation for module `\PHY_CONTROL'. -Generating RTLIL representation for module `\IDDRE1'. -Generating RTLIL representation for module `\ODDRE1'. -Generating RTLIL representation for module `\IDELAYE3'. -Generating RTLIL representation for module `\ODELAYE3'. -Generating RTLIL representation for module `\ISERDESE3'. -Generating RTLIL representation for module `\OSERDESE3'. -Generating RTLIL representation for module `\BITSLICE_CONTROL'. -Generating RTLIL representation for module `\RIU_OR'. -Generating RTLIL representation for module `\RX_BITSLICE'. -Generating RTLIL representation for module `\RXTX_BITSLICE'. -Generating RTLIL representation for module `\TX_BITSLICE'. -Generating RTLIL representation for module `\TX_BITSLICE_TRI'. -Generating RTLIL representation for module `\IODELAY2'. -Generating RTLIL representation for module `\IODRP2'. -Generating RTLIL representation for module `\IODRP2_MCB'. -Generating RTLIL representation for module `\ISERDES2'. -Generating RTLIL representation for module `\OSERDES2'. -Generating RTLIL representation for module `\IBUF_DLY_ADJ'. -Generating RTLIL representation for module `\IBUF_IBUFDISABLE'. -Generating RTLIL representation for module `\IBUF_INTERMDISABLE'. -Generating RTLIL representation for module `\IBUF_ANALOG'. -Generating RTLIL representation for module `\IBUFE3'. -Generating RTLIL representation for module `\IBUFDS'. -Generating RTLIL representation for module `\IBUFDS_DLY_ADJ'. -Generating RTLIL representation for module `\IBUFDS_IBUFDISABLE'. -Generating RTLIL representation for module `\IBUFDS_INTERMDISABLE'. -Generating RTLIL representation for module `\IBUFDS_DIFF_OUT'. -Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_IBUFDISABLE'. -Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_INTERMDISABLE'. -Generating RTLIL representation for module `\IBUFDSE3'. -Generating RTLIL representation for module `\IBUFDS_DPHY'. -Generating RTLIL representation for module `\IBUFGDS'. -Generating RTLIL representation for module `\IBUFGDS_DIFF_OUT'. -Generating RTLIL representation for module `\IOBUF_DCIEN'. -Generating RTLIL representation for module `\IOBUF_INTERMDISABLE'. -Generating RTLIL representation for module `\IOBUFE3'. -Generating RTLIL representation for module `\IOBUFDS'. -Generating RTLIL representation for module `\IOBUFDS_DCIEN'. -Generating RTLIL representation for module `\IOBUFDS_INTERMDISABLE'. -Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT'. -Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_DCIEN'. -Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_INTERMDISABLE'. -Generating RTLIL representation for module `\IOBUFDSE3'. -Generating RTLIL representation for module `\OBUFDS'. -Generating RTLIL representation for module `\OBUFDS_DPHY'. -Generating RTLIL representation for module `\OBUFTDS'. -Generating RTLIL representation for module `\KEEPER'. -Generating RTLIL representation for module `\PULLDOWN'. -Generating RTLIL representation for module `\PULLUP'. -Generating RTLIL representation for module `\DCIRESET'. -Generating RTLIL representation for module `\HPIO_VREF'. -Generating RTLIL representation for module `\BUFGCE'. -Generating RTLIL representation for module `\BUFGCE_1'. -Generating RTLIL representation for module `\BUFGMUX'. -Generating RTLIL representation for module `\BUFGMUX_1'. -Generating RTLIL representation for module `\BUFGMUX_CTRL'. -Generating RTLIL representation for module `\BUFGMUX_VIRTEX4'. -Generating RTLIL representation for module `\BUFG_GT'. -Generating RTLIL representation for module `\BUFG_GT_SYNC'. -Generating RTLIL representation for module `\BUFG_PS'. -Generating RTLIL representation for module `\BUFGCE_DIV'. -Generating RTLIL representation for module `\BUFH'. -Generating RTLIL representation for module `\BUFIO2'. -Generating RTLIL representation for module `\BUFIO2_2CLK'. -Generating RTLIL representation for module `\BUFIO2FB'. -Generating RTLIL representation for module `\BUFPLL'. -Generating RTLIL representation for module `\BUFPLL_MCB'. -Generating RTLIL representation for module `\BUFIO'. -Generating RTLIL representation for module `\BUFIODQS'. -Generating RTLIL representation for module `\BUFR'. -Generating RTLIL representation for module `\BUFMR'. -Generating RTLIL representation for module `\BUFMRCE'. -Generating RTLIL representation for module `\DCM'. -Generating RTLIL representation for module `\DCM_SP'. -Generating RTLIL representation for module `\DCM_CLKGEN'. -Generating RTLIL representation for module `\DCM_ADV'. -Generating RTLIL representation for module `\DCM_BASE'. -Generating RTLIL representation for module `\DCM_PS'. -Generating RTLIL representation for module `\PMCD'. -Generating RTLIL representation for module `\PLL_ADV'. -Generating RTLIL representation for module `\PLL_BASE'. -Generating RTLIL representation for module `\MMCM_ADV'. -Generating RTLIL representation for module `\MMCM_BASE'. -Generating RTLIL representation for module `\MMCME2_ADV'. -Generating RTLIL representation for module `\MMCME2_BASE'. -Generating RTLIL representation for module `\PLLE2_ADV'. -Generating RTLIL representation for module `\PLLE2_BASE'. -Generating RTLIL representation for module `\MMCME3_ADV'. -Generating RTLIL representation for module `\MMCME3_BASE'. -Generating RTLIL representation for module `\PLLE3_ADV'. -Generating RTLIL representation for module `\PLLE3_BASE'. -Generating RTLIL representation for module `\MMCME4_ADV'. -Generating RTLIL representation for module `\MMCME4_BASE'. -Generating RTLIL representation for module `\PLLE4_ADV'. -Generating RTLIL representation for module `\PLLE4_BASE'. -Generating RTLIL representation for module `\BUFT'. -Generating RTLIL representation for module `\IN_FIFO'. -Generating RTLIL representation for module `\OUT_FIFO'. -Generating RTLIL representation for module `\HARD_SYNC'. -Generating RTLIL representation for module `\STARTUP_SPARTAN3'. -Generating RTLIL representation for module `\STARTUP_SPARTAN3E'. -Generating RTLIL representation for module `\STARTUP_SPARTAN3A'. -Generating RTLIL representation for module `\STARTUP_SPARTAN6'. -Generating RTLIL representation for module `\STARTUP_VIRTEX4'. -Generating RTLIL representation for module `\STARTUP_VIRTEX5'. -Generating RTLIL representation for module `\STARTUP_VIRTEX6'. -Generating RTLIL representation for module `\STARTUPE2'. -Generating RTLIL representation for module `\STARTUPE3'. -Generating RTLIL representation for module `\CAPTURE_SPARTAN3'. -Generating RTLIL representation for module `\CAPTURE_SPARTAN3A'. -Generating RTLIL representation for module `\CAPTURE_VIRTEX4'. -Generating RTLIL representation for module `\CAPTURE_VIRTEX5'. -Generating RTLIL representation for module `\CAPTURE_VIRTEX6'. -Generating RTLIL representation for module `\CAPTUREE2'. -Generating RTLIL representation for module `\ICAP_SPARTAN3A'. -Generating RTLIL representation for module `\ICAP_SPARTAN6'. -Generating RTLIL representation for module `\ICAP_VIRTEX4'. -Generating RTLIL representation for module `\ICAP_VIRTEX5'. -Generating RTLIL representation for module `\ICAP_VIRTEX6'. -Generating RTLIL representation for module `\ICAPE2'. -Generating RTLIL representation for module `\ICAPE3'. -Generating RTLIL representation for module `\BSCAN_SPARTAN3'. -Generating RTLIL representation for module `\BSCAN_SPARTAN3A'. -Generating RTLIL representation for module `\BSCAN_SPARTAN6'. -Generating RTLIL representation for module `\BSCAN_VIRTEX4'. -Generating RTLIL representation for module `\BSCAN_VIRTEX5'. -Generating RTLIL representation for module `\BSCAN_VIRTEX6'. -Generating RTLIL representation for module `\BSCANE2'. -Generating RTLIL representation for module `\DNA_PORT'. -Generating RTLIL representation for module `\DNA_PORTE2'. -Generating RTLIL representation for module `\FRAME_ECC_VIRTEX4'. -Generating RTLIL representation for module `\FRAME_ECC_VIRTEX5'. -Generating RTLIL representation for module `\FRAME_ECC_VIRTEX6'. -Generating RTLIL representation for module `\FRAME_ECCE2'. -Generating RTLIL representation for module `\FRAME_ECCE3'. -Generating RTLIL representation for module `\USR_ACCESS_VIRTEX4'. -Generating RTLIL representation for module `\USR_ACCESS_VIRTEX5'. -Generating RTLIL representation for module `\USR_ACCESS_VIRTEX6'. -Generating RTLIL representation for module `\USR_ACCESSE2'. -Generating RTLIL representation for module `\POST_CRC_INTERNAL'. -Generating RTLIL representation for module `\SUSPEND_SYNC'. -Generating RTLIL representation for module `\KEY_CLEAR'. -Generating RTLIL representation for module `\MASTER_JTAG'. -Generating RTLIL representation for module `\SPI_ACCESS'. -Generating RTLIL representation for module `\EFUSE_USR'. -Generating RTLIL representation for module `\SYSMON'. -Generating RTLIL representation for module `\XADC'. -Generating RTLIL representation for module `\SYSMONE1'. -Generating RTLIL representation for module `\SYSMONE4'. -Generating RTLIL representation for module `\GTPA1_DUAL'. -Generating RTLIL representation for module `\GT11_CUSTOM'. -Generating RTLIL representation for module `\GT11_DUAL'. -Generating RTLIL representation for module `\GT11CLK'. -Generating RTLIL representation for module `\GT11CLK_MGT'. -Generating RTLIL representation for module `\GTP_DUAL'. -Generating RTLIL representation for module `\GTX_DUAL'. -Generating RTLIL representation for module `\CRC32'. -Generating RTLIL representation for module `\CRC64'. -Generating RTLIL representation for module `\GTHE1_QUAD'. -Generating RTLIL representation for module `\GTXE1'. -Generating RTLIL representation for module `\IBUFDS_GTXE1'. -Generating RTLIL representation for module `\IBUFDS_GTHE1'. -Generating RTLIL representation for module `\GTHE2_CHANNEL'. -Generating RTLIL representation for module `\GTHE2_COMMON'. -Generating RTLIL representation for module `\GTPE2_CHANNEL'. -Generating RTLIL representation for module `\GTPE2_COMMON'. -Generating RTLIL representation for module `\GTXE2_CHANNEL'. -Generating RTLIL representation for module `\GTXE2_COMMON'. -Generating RTLIL representation for module `\IBUFDS_GTE2'. -Generating RTLIL representation for module `\GTHE3_CHANNEL'. -Generating RTLIL representation for module `\GTHE3_COMMON'. -Generating RTLIL representation for module `\GTHE4_CHANNEL'. -Generating RTLIL representation for module `\GTHE4_COMMON'. -Generating RTLIL representation for module `\GTYE3_CHANNEL'. -Generating RTLIL representation for module `\GTYE3_COMMON'. -Generating RTLIL representation for module `\GTYE4_CHANNEL'. -Generating RTLIL representation for module `\GTYE4_COMMON'. -Generating RTLIL representation for module `\IBUFDS_GTE3'. -Generating RTLIL representation for module `\IBUFDS_GTE4'. -Generating RTLIL representation for module `\OBUFDS_GTE3'. -Generating RTLIL representation for module `\OBUFDS_GTE3_ADV'. -Generating RTLIL representation for module `\OBUFDS_GTE4'. -Generating RTLIL representation for module `\OBUFDS_GTE4_ADV'. -Generating RTLIL representation for module `\PCIE_A1'. -Generating RTLIL representation for module `\PCIE_EP'. -Generating RTLIL representation for module `\PCIE_2_0'. -Generating RTLIL representation for module `\PCIE_2_1'. -Generating RTLIL representation for module `\PCIE_3_0'. -Generating RTLIL representation for module `\PCIE_3_1'. -Generating RTLIL representation for module `\PCIE40E4'. -Generating RTLIL representation for module `\EMAC'. -Generating RTLIL representation for module `\TEMAC'. -Generating RTLIL representation for module `\TEMAC_SINGLE'. -Generating RTLIL representation for module `\CMAC'. -Generating RTLIL representation for module `\CMACE4'. -Generating RTLIL representation for module `\PPC405_ADV'. -Generating RTLIL representation for module `\PPC440'. -Generating RTLIL representation for module `\MCB'. -Generating RTLIL representation for module `\PS7'. -Generating RTLIL representation for module `\PS8'. -Generating RTLIL representation for module `\ILKN'. -Generating RTLIL representation for module `\ILKNE4'. -Successfully finished Verilog frontend. - -3.3. Executing HIERARCHY pass (managing design hierarchy). - -3.3.1. Analyzing design hierarchy.. -Top module: \block_ram - -3.3.2. Analyzing design hierarchy.. -Top module: \block_ram -Removed 0 unused modules. - -3.4. Executing PROC pass (convert processes to netlists). - -3.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. - -3.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Removed a total of 0 dead cases. - -3.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 0 redundant assignments. -Promoted 1 assignment to connection. - -3.4.4. Executing PROC_INIT pass (extract init attributes). - -3.4.5. Executing PROC_ARST pass (detect async resets in processes). - -3.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\block_ram.$proc$attributes_test.v:14$2'. - 1/3: $0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 - 2/3: $0$memwr$\memory$attributes_test.v:16$1_DATA[3:0]$4 - 3/3: $0$memwr$\memory$attributes_test.v:16$1_ADDR[9:0]$3 - -3.4.7. Executing PROC_DLATCH pass (convert process syncs to latches). - -3.4.8. Executing PROC_DFF pass (convert process syncs to FFs). -Creating register for signal `\block_ram.\data_out_r' using process `\block_ram.$proc$attributes_test.v:14$2'. - created $dff cell `$procdff$48' with positive edge clock. -Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$1_ADDR' using process `\block_ram.$proc$attributes_test.v:14$2'. - created $dff cell `$procdff$49' with positive edge clock. -Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$1_DATA' using process `\block_ram.$proc$attributes_test.v:14$2'. - created $dff cell `$procdff$50' with positive edge clock. -Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$1_EN' using process `\block_ram.$proc$attributes_test.v:14$2'. - created $dff cell `$procdff$51' with positive edge clock. - -3.4.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Found and cleaned up 1 empty switch in `\block_ram.$proc$attributes_test.v:14$2'. -Removing empty process `block_ram.$proc$attributes_test.v:14$2'. -Cleaned up 1 empty switch. - -3.5. Executing TRIBUF pass. - -3.6. Executing DEMINOUT pass (demote inout ports to input or output). - -3.7. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.8. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. -Removed 0 unused cells and 7 unused wires. - - -3.9. Executing CHECK pass (checking for obvious problems). -checking module block_ram.. -found and reported 0 problems. - -3.10. Executing OPT pass (performing simple optimizations). - -3.10.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.10.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -3.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \block_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -3.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \block_ram. - Consolidated identical input bits for $mux cell $procmux$42: - Old ports: A=4'0000, B=4'1111, Y=$0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 - New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 [0] - New connections: $0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 [3:1] = { $0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 [0] $0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 [0] $0$memwr$\memory$attributes_test.v:16$1_EN[3:0]$5 [0] } - Optimizing cells in module \block_ram. -Performed a total of 1 changes. - -3.10.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -3.10.6. Executing OPT_RMDFF pass (remove dff with constant values). - -3.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -3.10.8. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.10.9. Rerunning OPT passes. (Maybe there is more to do..) - -3.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \block_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -3.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \block_ram. -Performed a total of 0 changes. - -3.10.12. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -3.10.13. Executing OPT_RMDFF pass (remove dff with constant values). - -3.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -3.10.15. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.10.16. Finished OPT passes. (There is nothing left to do.) - -3.11. Executing WREDUCE pass (reducing word size of cells). -Removed cell block_ram.$procmux$44 ($mux). -Removed cell block_ram.$procmux$46 ($mux). -Removed top 3 bits (of 4) from FF cell block_ram.$procdff$51 ($dff). - -3.12. Executing PEEPOPT pass (run peephole optimizers). - -3.13. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. -Removed 0 unused cells and 2 unused wires. - - -3.14. Executing PMUX2SHIFTX pass. - -3.15. Executing TECHMAP pass (map to technology primitives). - -3.15.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v' to AST representation. -Generating RTLIL representation for module `\_90_lut_cmp_'. -Successfully finished Verilog frontend. - -3.15.2. Continuing TECHMAP pass. -No more expansions possible. - -3.16. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). -Checking cell `$memwr$\memory$attributes_test.v:16$7' in module `\block_ram': merged $dff to cell. -Checking cell `$memrd$\memory$attributes_test.v:17$6' in module `\block_ram': merged data $dff to cell. - -3.17. Executing TECHMAP pass (map to technology primitives). - -3.17.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v' to AST representation. -Generating RTLIL representation for module `\_80_mul'. -Generating RTLIL representation for module `\_90_soft_mul'. -Successfully finished Verilog frontend. - -3.17.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v' to AST representation. -Generating RTLIL representation for module `\$__MUL25X18'. -Successfully finished Verilog frontend. - -3.17.3. Continuing TECHMAP pass. -No more expansions possible. - -3.18. Executing OPT_EXPR pass (perform const folding). - -3.19. Executing WREDUCE pass (reducing word size of cells). - -3.20. Executing XILINX_DSP pass (pack resources into DSPs). - -3.21. Executing ALUMACC pass (create $alu and $macc cells). -Extracting $alu and $macc cells in module block_ram: - created 0 $alu and 0 $macc cells. - -3.22. Executing SHARE pass (SAT-based resource sharing). - -3.23. Executing OPT pass (performing simple optimizations). - -3.23.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.23.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -3.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \block_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -3.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \block_ram. -Performed a total of 0 changes. - -3.23.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -3.23.6. Executing OPT_RMDFF pass (remove dff with constant values). - -3.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. -Removed 4 unused cells and 5 unused wires. - - -3.23.8. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.23.9. Rerunning OPT passes. (Maybe there is more to do..) - -3.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \block_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -3.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \block_ram. -Performed a total of 0 changes. - -3.23.12. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -3.23.13. Executing OPT_RMDFF pass (remove dff with constant values). - -3.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -3.23.15. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.23.16. Finished OPT passes. (There is nothing left to do.) - -3.24. Executing FSM pass (extract and optimize FSM). - -3.24.1. Executing FSM_DETECT pass (finding FSMs in design). - -3.24.2. Executing FSM_EXTRACT pass (extracting FSM from design). - -3.24.3. Executing FSM_OPT pass (simple optimizations of FSMs). - -3.24.4. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -3.24.5. Executing FSM_OPT pass (simple optimizations of FSMs). - -3.24.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). - -3.24.7. Executing FSM_INFO pass (dumping all available information on FSM cells). - -3.24.8. Executing FSM_MAP pass (mapping FSMs to basic logic). - -3.25. Executing OPT pass (performing simple optimizations). - -3.25.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.25.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -3.25.3. Executing OPT_RMDFF pass (remove dff with constant values). - -3.25.4. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -3.25.5. Finished fast OPT passes. - -3.26. Executing MEMORY pass. - -3.26.1. Executing OPT_MEM pass (optimize memories). -Performed a total of 0 transformations. - -3.26.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). - -3.26.3. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -3.26.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). - -3.26.5. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -3.26.6. Executing MEMORY_COLLECT pass (generating $mem cells). -Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\block_ram': - $memwr$\memory$attributes_test.v:16$7 ($memwr) - $memrd$\memory$attributes_test.v:17$6 ($memrd) - -3.27. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -3.28. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). -Processing block_ram.memory: - Properties: ports=2 bits=4096 rports=1 wports=1 dbits=4 abits=10 words=1024 - Checking rule #1 for bram type $__XILINX_RAMB36_SDP (variant 1): - Bram geometry: abits=9 dbits=72 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_SDP: awaste=0 dwaste=68 bwaste=34816 waste=34816 efficiency=5 - Rule #1 for bram type $__XILINX_RAMB36_SDP (variant 1) accepted. - Mapping to bram type $__XILINX_RAMB36_SDP (variant 1): - Shuffle bit order to accommodate enable buckets of size 9.. - Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=34816 efficiency=5 - Storing for later selection. - Checking rule #2 for bram type $__XILINX_RAMB18_SDP (variant 1): - Bram geometry: abits=9 dbits=36 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_SDP: awaste=0 dwaste=32 bwaste=16384 waste=16384 efficiency=11 - Rule #2 for bram type $__XILINX_RAMB18_SDP (variant 1) accepted. - Mapping to bram type $__XILINX_RAMB18_SDP (variant 1): - Shuffle bit order to accommodate enable buckets of size 9.. - Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=16384 efficiency=11 - Storing for later selection. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 1): - Bram geometry: abits=10 dbits=36 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=0 dwaste=32 bwaste=32768 waste=32768 efficiency=11 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 1) accepted. - Mapping to bram type $__XILINX_RAMB36_TDP (variant 1): - Shuffle bit order to accommodate enable buckets of size 9.. - Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=32768 efficiency=11 - Storing for later selection. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 2): - Bram geometry: abits=11 dbits=18 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=1024 dwaste=14 bwaste=32768 waste=32768 efficiency=11 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 2) accepted. - Mapping to bram type $__XILINX_RAMB36_TDP (variant 2): - Shuffle bit order to accommodate enable buckets of size 9.. - Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=32768 efficiency=11 - Storing for later selection. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 3): - Bram geometry: abits=12 dbits=9 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=3072 dwaste=5 bwaste=32768 waste=32768 efficiency=11 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 3) accepted. - Mapping to bram type $__XILINX_RAMB36_TDP (variant 3): - Shuffle bit order to accommodate enable buckets of size 9.. - Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=32768 efficiency=11 - Storing for later selection. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 4): - Bram geometry: abits=13 dbits=4 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=7168 dwaste=0 bwaste=28672 waste=28672 efficiency=12 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 4) accepted. - Mapping to bram type $__XILINX_RAMB36_TDP (variant 4): - Shuffle bit order to accommodate enable buckets of size 4.. - Results of bit order shuffling: 0 1 2 3 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=28672 efficiency=12 - Storing for later selection. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 5): - Bram geometry: abits=14 dbits=2 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=15360 dwaste=0 bwaste=30720 waste=30720 efficiency=6 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 5) accepted. - Mapping to bram type $__XILINX_RAMB36_TDP (variant 5): - Shuffle bit order to accommodate enable buckets of size 2.. - Results of bit order shuffling: 0 1 2 3 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=30720 efficiency=6 - Storing for later selection. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 6): - Bram geometry: abits=15 dbits=1 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=31744 dwaste=0 bwaste=31744 waste=31744 efficiency=3 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 6) rejected: requirement 'min efficiency 5' not met. - Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 1): - Bram geometry: abits=10 dbits=18 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_TDP: awaste=0 dwaste=14 bwaste=14336 waste=14336 efficiency=22 - Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 1) accepted. - Mapping to bram type $__XILINX_RAMB18_TDP (variant 1): - Shuffle bit order to accommodate enable buckets of size 9.. - Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=14336 efficiency=22 - Storing for later selection. - Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 2): - Bram geometry: abits=11 dbits=9 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_TDP: awaste=1024 dwaste=5 bwaste=14336 waste=14336 efficiency=22 - Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 2) accepted. - Mapping to bram type $__XILINX_RAMB18_TDP (variant 2): - Shuffle bit order to accommodate enable buckets of size 9.. - Results of bit order shuffling: 0 1 2 3 -1 -1 -1 -1 -1 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=14336 efficiency=22 - Storing for later selection. - Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 3): - Bram geometry: abits=12 dbits=4 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_TDP: awaste=3072 dwaste=0 bwaste=12288 waste=12288 efficiency=25 - Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 3) accepted. - Mapping to bram type $__XILINX_RAMB18_TDP (variant 3): - Shuffle bit order to accommodate enable buckets of size 4.. - Results of bit order shuffling: 0 1 2 3 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=12288 efficiency=25 - Storing for later selection. - Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 4): - Bram geometry: abits=13 dbits=2 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_TDP: awaste=7168 dwaste=0 bwaste=14336 waste=14336 efficiency=12 - Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 4) accepted. - Mapping to bram type $__XILINX_RAMB18_TDP (variant 4): - Shuffle bit order to accommodate enable buckets of size 2.. - Results of bit order shuffling: 0 1 2 3 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=14336 efficiency=12 - Storing for later selection. - Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 5): - Bram geometry: abits=14 dbits=1 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_TDP: awaste=15360 dwaste=0 bwaste=15360 waste=15360 efficiency=6 - Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 5) accepted. - Mapping to bram type $__XILINX_RAMB18_TDP (variant 5): - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=15360 efficiency=6 - Storing for later selection. - Selecting best of 12 rules: - Efficiency for rule 4.5: efficiency=6, cells=4, acells=1 - Efficiency for rule 4.4: efficiency=12, cells=2, acells=1 - Efficiency for rule 4.3: efficiency=25, cells=1, acells=1 - Efficiency for rule 4.2: efficiency=22, cells=1, acells=1 - Efficiency for rule 4.1: efficiency=22, cells=1, acells=1 - Efficiency for rule 3.5: efficiency=6, cells=2, acells=1 - Efficiency for rule 3.4: efficiency=12, cells=1, acells=1 - Efficiency for rule 3.3: efficiency=11, cells=1, acells=1 - Efficiency for rule 3.2: efficiency=11, cells=1, acells=1 - Efficiency for rule 3.1: efficiency=11, cells=1, acells=1 - Efficiency for rule 2.1: efficiency=11, cells=2, acells=2 - Efficiency for rule 1.1: efficiency=5, cells=2, acells=2 - Selected rule 4.3 with efficiency 25. - Mapping to bram type $__XILINX_RAMB18_TDP (variant 3): - Shuffle bit order to accommodate enable buckets of size 4.. - Results of bit order shuffling: 0 1 2 3 - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Creating $__XILINX_RAMB18_TDP cell at grid position <0 0 0>: memory.0.0.0 - -3.29. Executing TECHMAP pass (map to technology primitives). - -3.29.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_brams_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_brams_map.v' to AST representation. -Generating RTLIL representation for module `\$__XILINX_RAMB36_SDP'. -Generating RTLIL representation for module `\$__XILINX_RAMB18_SDP'. -Generating RTLIL representation for module `\$__XILINX_RAMB36_TDP'. -Generating RTLIL representation for module `\$__XILINX_RAMB18_TDP'. -Successfully finished Verilog frontend. - -3.29.2. Continuing TECHMAP pass. -Using template $paramod\$__XILINX_RAMB18_TDP\CFG_ABITS=12\CFG_DBITS=4\CFG_ENABLE_B=1\CLKPOL2=1\CLKPOL3=1 for cells of type $__XILINX_RAMB18_TDP. -No more expansions possible. - - -3.30. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). - -3.31. Executing TECHMAP pass (map to technology primitives). - -3.31.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lutrams_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lutrams_map.v' to AST representation. -Generating RTLIL representation for module `\$__XILINX_RAM32X1D'. -Generating RTLIL representation for module `\$__XILINX_RAM64X1D'. -Generating RTLIL representation for module `\$__XILINX_RAM128X1D'. -Successfully finished Verilog frontend. - -3.31.2. Continuing TECHMAP pass. -No more expansions possible. - -3.32. Executing OPT pass (performing simple optimizations). - -3.32.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - - -3.32.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -3.32.3. Executing OPT_RMDFF pass (remove dff with constant values). - -3.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. -Removed 0 unused cells and 17 unused wires. - - -3.32.5. Finished fast OPT passes. - -3.33. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). - -3.34. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs). - -3.35. Executing DFF2DFFE pass (transform $dff to $dffe where applicable). -Transforming FF to FF+Enable cells in module block_ram: - -3.36. Executing OPT pass (performing simple optimizations). - -3.36.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.36.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -3.36.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \block_ram.. - Creating internal representation of mux trees. - No muxes found in this module. -Removed 0 multiplexer ports. - -3.36.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \block_ram. -Performed a total of 0 changes. - -3.36.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -3.36.6. Executing OPT_SHARE pass. - -3.36.7. Executing OPT_RMDFF pass (remove dff with constant values). - -3.36.8. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -3.36.9. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.36.10. Finished OPT passes. (There is nothing left to do.) - -3.37. Executing XILINX_SRL pass (Xilinx shift register extraction). - -3.38. Executing TECHMAP pass (map to technology primitives). - -3.38.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v' to AST representation. -Generating RTLIL representation for module `\_90_simplemap_bool_ops'. -Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. -Generating RTLIL representation for module `\_90_simplemap_logic_ops'. -Generating RTLIL representation for module `\_90_simplemap_compare_ops'. -Generating RTLIL representation for module `\_90_simplemap_various'. -Generating RTLIL representation for module `\_90_simplemap_registers'. -Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. -Generating RTLIL representation for module `\_90_shift_shiftx'. -Generating RTLIL representation for module `\_90_fa'. -Generating RTLIL representation for module `\_90_lcu'. -Generating RTLIL representation for module `\_90_alu'. -Generating RTLIL representation for module `\_90_macc'. -Generating RTLIL representation for module `\_90_alumacc'. -Generating RTLIL representation for module `\$__div_mod_u'. -Generating RTLIL representation for module `\$__div_mod'. -Generating RTLIL representation for module `\_90_div'. -Generating RTLIL representation for module `\_90_mod'. -Generating RTLIL representation for module `\_90_pow'. -Generating RTLIL representation for module `\_90_pmux'. -Generating RTLIL representation for module `\_90_lut'. -Successfully finished Verilog frontend. - -3.38.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/arith_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/arith_map.v' to AST representation. -Generating RTLIL representation for module `\_80_xilinx_lcu'. -Generating RTLIL representation for module `\_80_xilinx_alu'. -Successfully finished Verilog frontend. - -3.38.3. Continuing TECHMAP pass. -No more expansions possible. - -3.39. Executing OPT pass (performing simple optimizations). - -3.39.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.39.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -3.39.3. Executing OPT_RMDFF pass (remove dff with constant values). - -3.39.4. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -3.39.5. Finished fast OPT passes. - -3.40. Executing TECHMAP pass (map to technology primitives). - -3.40.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v' to AST representation. -Generating RTLIL representation for module `\_90_simplemap_bool_ops'. -Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. -Generating RTLIL representation for module `\_90_simplemap_logic_ops'. -Generating RTLIL representation for module `\_90_simplemap_compare_ops'. -Generating RTLIL representation for module `\_90_simplemap_various'. -Generating RTLIL representation for module `\_90_simplemap_registers'. -Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. -Generating RTLIL representation for module `\_90_shift_shiftx'. -Generating RTLIL representation for module `\_90_fa'. -Generating RTLIL representation for module `\_90_lcu'. -Generating RTLIL representation for module `\_90_alu'. -Generating RTLIL representation for module `\_90_macc'. -Generating RTLIL representation for module `\_90_alumacc'. -Generating RTLIL representation for module `\$__div_mod_u'. -Generating RTLIL representation for module `\$__div_mod'. -Generating RTLIL representation for module `\_90_div'. -Generating RTLIL representation for module `\_90_mod'. -Generating RTLIL representation for module `\_90_pow'. -Generating RTLIL representation for module `\_90_pmux'. -Generating RTLIL representation for module `\_90_lut'. -Successfully finished Verilog frontend. - -3.40.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v' to AST representation. -Generating RTLIL representation for module `\_90_dff_nn0_to_np0'. -Generating RTLIL representation for module `\_90_dff_pn0_to_pp0'. -Generating RTLIL representation for module `\_90_dff_nn1_to_np1'. -Generating RTLIL representation for module `\_90_dff_pn1_to_pp1'. -Generating RTLIL representation for module `\$__SHREG_'. -Generating RTLIL representation for module `\$__XILINX_SHREG_'. -Generating RTLIL representation for module `\$__XILINX_MUXF78'. -Generating RTLIL representation for module `\$__XILINX_TINOUTPAD'. -Generating RTLIL representation for module `\$__XILINX_TOUTPAD'. -Successfully finished Verilog frontend. - -3.40.3. Continuing TECHMAP pass. -No more expansions possible. - -3.41. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -3.42. Executing ABC pass (technology mapping using ABC). - -3.42.1. Extracting gate netlist of module `\block_ram' to `/input.blif'.. -Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. -Don't call ABC as there is nothing to map. -Removing temp directory. - -3.43. Executing XILINX_SRL pass (Xilinx shift register extraction). - -3.44. Executing TECHMAP pass (map to technology primitives). - -3.44.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lut_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lut_map.v' to AST representation. -Generating RTLIL representation for module `\$lut'. -Successfully finished Verilog frontend. - -3.44.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v' to AST representation. -Generating RTLIL representation for module `\_90_dff_nn0_to_np0'. -Generating RTLIL representation for module `\_90_dff_pn0_to_pp0'. -Generating RTLIL representation for module `\_90_dff_nn1_to_np1'. -Generating RTLIL representation for module `\_90_dff_pn1_to_pp1'. -Generating RTLIL representation for module `\$__SHREG_'. -Generating RTLIL representation for module `\$__XILINX_SHREG_'. -Generating RTLIL representation for module `\$__XILINX_MUXF78'. -Generating RTLIL representation for module `\$__XILINX_TINOUTPAD'. -Generating RTLIL representation for module `\$__XILINX_TOUTPAD'. -Successfully finished Verilog frontend. - -3.44.3. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_ff_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_ff_map.v' to AST representation. -Generating RTLIL representation for module `\$_DFF_N_'. -Generating RTLIL representation for module `\$_DFF_P_'. -Generating RTLIL representation for module `\$_DFFE_NP_'. -Generating RTLIL representation for module `\$_DFFE_PP_'. -Generating RTLIL representation for module `\$_DFF_NN0_'. -Generating RTLIL representation for module `\$_DFF_NP0_'. -Generating RTLIL representation for module `\$_DFF_PN0_'. -Generating RTLIL representation for module `\$_DFF_PP0_'. -Generating RTLIL representation for module `\$_DFF_NN1_'. -Generating RTLIL representation for module `\$_DFF_NP1_'. -Generating RTLIL representation for module `\$_DFF_PN1_'. -Generating RTLIL representation for module `\$_DFF_PP1_'. -Generating RTLIL representation for module `\$_DLATCH_N_'. -Generating RTLIL representation for module `\$_DLATCH_P_'. -Successfully finished Verilog frontend. - -3.44.4. Continuing TECHMAP pass. -No more expansions possible. - -3.45. Executing CLKBUFMAP pass (inserting global clock buffers). -Inserting BUFG on block_ram.clk[0]. - -3.46. Executing HIERARCHY pass (managing design hierarchy). - -3.46.1. Analyzing design hierarchy.. -Top module: \block_ram - -3.46.2. Analyzing design hierarchy.. -Top module: \block_ram -Removed 0 unused modules. - -3.47. Printing statistics. - -=== block_ram === - - Number of wires: 12 - Number of wire bits: 62 - Number of public wires: 6 - Number of public wire bits: 24 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 2 - BUFG 1 - RAMB18E1 1 - - Estimated number of LCs: 0 - -3.48. Executing CHECK pass (checking for obvious problems). -checking module block_ram.. -found and reported 0 problems. - -4. Executing Verilog-2005 frontend: attributes_test.v -Parsing Verilog input from `attributes_test.v' to AST representation. -Generating RTLIL representation for module `\block_ram'. -Generating RTLIL representation for module `\distributed_ram'. -Generating RTLIL representation for module `\distributed_ram_manual'. -Generating RTLIL representation for module `\distributed_ram_manual_syn'. -Successfully finished Verilog frontend. - -5. Executing HIERARCHY pass (managing design hierarchy). - -5.1. Analyzing design hierarchy.. -Top module: \distributed_ram - -5.2. Analyzing design hierarchy.. -Top module: \distributed_ram -Removing unused module `\distributed_ram_manual_syn'. -Removing unused module `\distributed_ram_manual'. -Removing unused module `\block_ram'. -Removed 3 unused modules. - -6. Executing SYNTH_XILINX pass. - -6.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v' to AST representation. -Generating RTLIL representation for module `\VCC'. -Generating RTLIL representation for module `\GND'. -Generating RTLIL representation for module `\IBUF'. -Generating RTLIL representation for module `\IBUFG'. -Generating RTLIL representation for module `\OBUF'. -Generating RTLIL representation for module `\IOBUF'. -Generating RTLIL representation for module `\OBUFT'. -Generating RTLIL representation for module `\BUFG'. -Generating RTLIL representation for module `\BUFGCTRL'. -Generating RTLIL representation for module `\BUFHCE'. -Generating RTLIL representation for module `\INV'. -Generating RTLIL representation for module `\LUT1'. -Generating RTLIL representation for module `\LUT2'. -Generating RTLIL representation for module `\LUT3'. -Generating RTLIL representation for module `\LUT4'. -Generating RTLIL representation for module `\LUT5'. -Generating RTLIL representation for module `\LUT6'. -Generating RTLIL representation for module `\LUT6_2'. -Generating RTLIL representation for module `\MUXCY'. -Generating RTLIL representation for module `\MUXF7'. -Generating RTLIL representation for module `\MUXF8'. -Generating RTLIL representation for module `\XORCY'. -Generating RTLIL representation for module `\CARRY4'. -Generating RTLIL representation for module `\FDRE'. -Generating RTLIL representation for module `\FDSE'. -Generating RTLIL representation for module `\FDCE'. -Generating RTLIL representation for module `\FDPE'. -Generating RTLIL representation for module `\FDRE_1'. -Generating RTLIL representation for module `\FDSE_1'. -Generating RTLIL representation for module `\FDCE_1'. -Generating RTLIL representation for module `\FDPE_1'. -Generating RTLIL representation for module `\LDCE'. -Generating RTLIL representation for module `\LDPE'. -Generating RTLIL representation for module `\RAM16X1S'. -Generating RTLIL representation for module `\RAM16X1S_1'. -Generating RTLIL representation for module `\RAM32X1S'. -Generating RTLIL representation for module `\RAM32X1S_1'. -Generating RTLIL representation for module `\RAM64X1S'. -Generating RTLIL representation for module `\RAM64X1S_1'. -Generating RTLIL representation for module `\RAM128X1S'. -Generating RTLIL representation for module `\RAM128X1S_1'. -Generating RTLIL representation for module `\RAM256X1S'. -Generating RTLIL representation for module `\RAM512X1S'. -Generating RTLIL representation for module `\RAM16X2S'. -Generating RTLIL representation for module `\RAM32X2S'. -Generating RTLIL representation for module `\RAM64X2S'. -Generating RTLIL representation for module `\RAM16X4S'. -Generating RTLIL representation for module `\RAM32X4S'. -Generating RTLIL representation for module `\RAM16X8S'. -Generating RTLIL representation for module `\RAM32X8S'. -Generating RTLIL representation for module `\RAM16X1D'. -Generating RTLIL representation for module `\RAM16X1D_1'. -Generating RTLIL representation for module `\RAM32X1D'. -Generating RTLIL representation for module `\RAM32X1D_1'. -Generating RTLIL representation for module `\RAM64X1D'. -Generating RTLIL representation for module `\RAM64X1D_1'. -Generating RTLIL representation for module `\RAM128X1D'. -Generating RTLIL representation for module `\RAM256X1D'. -Generating RTLIL representation for module `\RAM32M'. -Generating RTLIL representation for module `\RAM32M16'. -Generating RTLIL representation for module `\RAM64M'. -Generating RTLIL representation for module `\RAM64M8'. -Generating RTLIL representation for module `\ROM16X1'. -Generating RTLIL representation for module `\ROM32X1'. -Generating RTLIL representation for module `\ROM64X1'. -Generating RTLIL representation for module `\ROM128X1'. -Generating RTLIL representation for module `\ROM256X1'. -Generating RTLIL representation for module `\SRL16E'. -Generating RTLIL representation for module `\SRLC16E'. -Generating RTLIL representation for module `\SRLC32E'. -Generating RTLIL representation for module `\MULT18X18'. -Generating RTLIL representation for module `\MULT18X18S'. -Generating RTLIL representation for module `\MULT18X18SIO'. -Generating RTLIL representation for module `\DSP48A'. -Generating RTLIL representation for module `\DSP48A1'. -Generating RTLIL representation for module `\DSP48E1'. -Successfully finished Verilog frontend. - -6.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v' to AST representation. -Generating RTLIL representation for module `\FDCPE'. -Generating RTLIL representation for module `\FDRSE'. -Generating RTLIL representation for module `\LDCPE'. -Generating RTLIL representation for module `\AND2B1L'. -Generating RTLIL representation for module `\OR2L'. -Generating RTLIL representation for module `\MUXF5'. -Generating RTLIL representation for module `\MUXF6'. -Generating RTLIL representation for module `\MUXF9'. -Generating RTLIL representation for module `\CARRY8'. -Generating RTLIL representation for module `\ORCY'. -Generating RTLIL representation for module `\MULT_AND'. -Generating RTLIL representation for module `\SRL16'. -Generating RTLIL representation for module `\SRLC16'. -Generating RTLIL representation for module `\CFGLUT5'. -Generating RTLIL representation for module `\RAMB16_S1'. -Generating RTLIL representation for module `\RAMB16_S2'. -Generating RTLIL representation for module `\RAMB16_S4'. -Generating RTLIL representation for module `\RAMB16_S9'. -Generating RTLIL representation for module `\RAMB16_S18'. -Generating RTLIL representation for module `\RAMB16_S36'. -Generating RTLIL representation for module `\RAMB16_S1_S1'. -Generating RTLIL representation for module `\RAMB16_S1_S2'. -Generating RTLIL representation for module `\RAMB16_S1_S4'. -Generating RTLIL representation for module `\RAMB16_S1_S9'. -Generating RTLIL representation for module `\RAMB16_S1_S18'. -Generating RTLIL representation for module `\RAMB16_S1_S36'. -Generating RTLIL representation for module `\RAMB16_S2_S2'. -Generating RTLIL representation for module `\RAMB16_S2_S4'. -Generating RTLIL representation for module `\RAMB16_S2_S9'. -Generating RTLIL representation for module `\RAMB16_S2_S18'. -Generating RTLIL representation for module `\RAMB16_S2_S36'. -Generating RTLIL representation for module `\RAMB16_S4_S4'. -Generating RTLIL representation for module `\RAMB16_S4_S9'. -Generating RTLIL representation for module `\RAMB16_S4_S18'. -Generating RTLIL representation for module `\RAMB16_S4_S36'. -Generating RTLIL representation for module `\RAMB16_S9_S9'. -Generating RTLIL representation for module `\RAMB16_S9_S18'. -Generating RTLIL representation for module `\RAMB16_S9_S36'. -Generating RTLIL representation for module `\RAMB16_S18_S18'. -Generating RTLIL representation for module `\RAMB16_S18_S36'. -Generating RTLIL representation for module `\RAMB16_S36_S36'. -Generating RTLIL representation for module `\RAMB16BWE_S18'. -Generating RTLIL representation for module `\RAMB16BWE_S36'. -Generating RTLIL representation for module `\RAMB16BWE_S18_S9'. -Generating RTLIL representation for module `\RAMB16BWE_S18_S18'. -Generating RTLIL representation for module `\RAMB16BWE_S36_S9'. -Generating RTLIL representation for module `\RAMB16BWE_S36_S18'. -Generating RTLIL representation for module `\RAMB16BWE_S36_S36'. -Generating RTLIL representation for module `\RAMB16BWER'. -Generating RTLIL representation for module `\RAMB8BWER'. -Generating RTLIL representation for module `\FIFO16'. -Generating RTLIL representation for module `\RAMB16'. -Generating RTLIL representation for module `\RAMB32_S64_ECC'. -Generating RTLIL representation for module `\FIFO18'. -Generating RTLIL representation for module `\FIFO18_36'. -Generating RTLIL representation for module `\FIFO36'. -Generating RTLIL representation for module `\FIFO36_72'. -Generating RTLIL representation for module `\RAMB18'. -Generating RTLIL representation for module `\RAMB36'. -Generating RTLIL representation for module `\RAMB18SDP'. -Generating RTLIL representation for module `\RAMB36SDP'. -Generating RTLIL representation for module `\FIFO18E1'. -Generating RTLIL representation for module `\FIFO36E1'. -Generating RTLIL representation for module `\RAMB18E1'. -Generating RTLIL representation for module `\RAMB36E1'. -Generating RTLIL representation for module `\FIFO18E2'. -Generating RTLIL representation for module `\FIFO36E2'. -Generating RTLIL representation for module `\RAMB18E2'. -Generating RTLIL representation for module `\RAMB36E2'. -Generating RTLIL representation for module `\URAM288'. -Generating RTLIL representation for module `\URAM288_BASE'. -Generating RTLIL representation for module `\DSP48'. -Generating RTLIL representation for module `\DSP48E'. -Generating RTLIL representation for module `\DSP48E2'. -Generating RTLIL representation for module `\IFDDRCPE'. -Generating RTLIL representation for module `\IFDDRRSE'. -Generating RTLIL representation for module `\OFDDRCPE'. -Generating RTLIL representation for module `\OFDDRRSE'. -Generating RTLIL representation for module `\OFDDRTCPE'. -Generating RTLIL representation for module `\OFDDRTRSE'. -Generating RTLIL representation for module `\IDDR2'. -Generating RTLIL representation for module `\ODDR2'. -Generating RTLIL representation for module `\IDDR'. -Generating RTLIL representation for module `\IDDR_2CLK'. -Generating RTLIL representation for module `\ODDR'. -Generating RTLIL representation for module `\IDELAYCTRL'. -Generating RTLIL representation for module `\IDELAY'. -Generating RTLIL representation for module `\ISERDES'. -Generating RTLIL representation for module `\OSERDES'. -Generating RTLIL representation for module `\IODELAY'. -Generating RTLIL representation for module `\ISERDES_NODELAY'. -Generating RTLIL representation for module `\IODELAYE1'. -Generating RTLIL representation for module `\ISERDESE1'. -Generating RTLIL representation for module `\OSERDESE1'. -Generating RTLIL representation for module `\IDELAYE2'. -Generating RTLIL representation for module `\ODELAYE2'. -Generating RTLIL representation for module `\ISERDESE2'. -Generating RTLIL representation for module `\OSERDESE2'. -Generating RTLIL representation for module `\PHASER_IN'. -Generating RTLIL representation for module `\PHASER_IN_PHY'. -Generating RTLIL representation for module `\PHASER_OUT'. -Generating RTLIL representation for module `\PHASER_OUT_PHY'. -Generating RTLIL representation for module `\PHASER_REF'. -Generating RTLIL representation for module `\PHY_CONTROL'. -Generating RTLIL representation for module `\IDDRE1'. -Generating RTLIL representation for module `\ODDRE1'. -Generating RTLIL representation for module `\IDELAYE3'. -Generating RTLIL representation for module `\ODELAYE3'. -Generating RTLIL representation for module `\ISERDESE3'. -Generating RTLIL representation for module `\OSERDESE3'. -Generating RTLIL representation for module `\BITSLICE_CONTROL'. -Generating RTLIL representation for module `\RIU_OR'. -Generating RTLIL representation for module `\RX_BITSLICE'. -Generating RTLIL representation for module `\RXTX_BITSLICE'. -Generating RTLIL representation for module `\TX_BITSLICE'. -Generating RTLIL representation for module `\TX_BITSLICE_TRI'. -Generating RTLIL representation for module `\IODELAY2'. -Generating RTLIL representation for module `\IODRP2'. -Generating RTLIL representation for module `\IODRP2_MCB'. -Generating RTLIL representation for module `\ISERDES2'. -Generating RTLIL representation for module `\OSERDES2'. -Generating RTLIL representation for module `\IBUF_DLY_ADJ'. -Generating RTLIL representation for module `\IBUF_IBUFDISABLE'. -Generating RTLIL representation for module `\IBUF_INTERMDISABLE'. -Generating RTLIL representation for module `\IBUF_ANALOG'. -Generating RTLIL representation for module `\IBUFE3'. -Generating RTLIL representation for module `\IBUFDS'. -Generating RTLIL representation for module `\IBUFDS_DLY_ADJ'. -Generating RTLIL representation for module `\IBUFDS_IBUFDISABLE'. -Generating RTLIL representation for module `\IBUFDS_INTERMDISABLE'. -Generating RTLIL representation for module `\IBUFDS_DIFF_OUT'. -Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_IBUFDISABLE'. -Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_INTERMDISABLE'. -Generating RTLIL representation for module `\IBUFDSE3'. -Generating RTLIL representation for module `\IBUFDS_DPHY'. -Generating RTLIL representation for module `\IBUFGDS'. -Generating RTLIL representation for module `\IBUFGDS_DIFF_OUT'. -Generating RTLIL representation for module `\IOBUF_DCIEN'. -Generating RTLIL representation for module `\IOBUF_INTERMDISABLE'. -Generating RTLIL representation for module `\IOBUFE3'. -Generating RTLIL representation for module `\IOBUFDS'. -Generating RTLIL representation for module `\IOBUFDS_DCIEN'. -Generating RTLIL representation for module `\IOBUFDS_INTERMDISABLE'. -Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT'. -Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_DCIEN'. -Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_INTERMDISABLE'. -Generating RTLIL representation for module `\IOBUFDSE3'. -Generating RTLIL representation for module `\OBUFDS'. -Generating RTLIL representation for module `\OBUFDS_DPHY'. -Generating RTLIL representation for module `\OBUFTDS'. -Generating RTLIL representation for module `\KEEPER'. -Generating RTLIL representation for module `\PULLDOWN'. -Generating RTLIL representation for module `\PULLUP'. -Generating RTLIL representation for module `\DCIRESET'. -Generating RTLIL representation for module `\HPIO_VREF'. -Generating RTLIL representation for module `\BUFGCE'. -Generating RTLIL representation for module `\BUFGCE_1'. -Generating RTLIL representation for module `\BUFGMUX'. -Generating RTLIL representation for module `\BUFGMUX_1'. -Generating RTLIL representation for module `\BUFGMUX_CTRL'. -Generating RTLIL representation for module `\BUFGMUX_VIRTEX4'. -Generating RTLIL representation for module `\BUFG_GT'. -Generating RTLIL representation for module `\BUFG_GT_SYNC'. -Generating RTLIL representation for module `\BUFG_PS'. -Generating RTLIL representation for module `\BUFGCE_DIV'. -Generating RTLIL representation for module `\BUFH'. -Generating RTLIL representation for module `\BUFIO2'. -Generating RTLIL representation for module `\BUFIO2_2CLK'. -Generating RTLIL representation for module `\BUFIO2FB'. -Generating RTLIL representation for module `\BUFPLL'. -Generating RTLIL representation for module `\BUFPLL_MCB'. -Generating RTLIL representation for module `\BUFIO'. -Generating RTLIL representation for module `\BUFIODQS'. -Generating RTLIL representation for module `\BUFR'. -Generating RTLIL representation for module `\BUFMR'. -Generating RTLIL representation for module `\BUFMRCE'. -Generating RTLIL representation for module `\DCM'. -Generating RTLIL representation for module `\DCM_SP'. -Generating RTLIL representation for module `\DCM_CLKGEN'. -Generating RTLIL representation for module `\DCM_ADV'. -Generating RTLIL representation for module `\DCM_BASE'. -Generating RTLIL representation for module `\DCM_PS'. -Generating RTLIL representation for module `\PMCD'. -Generating RTLIL representation for module `\PLL_ADV'. -Generating RTLIL representation for module `\PLL_BASE'. -Generating RTLIL representation for module `\MMCM_ADV'. -Generating RTLIL representation for module `\MMCM_BASE'. -Generating RTLIL representation for module `\MMCME2_ADV'. -Generating RTLIL representation for module `\MMCME2_BASE'. -Generating RTLIL representation for module `\PLLE2_ADV'. -Generating RTLIL representation for module `\PLLE2_BASE'. -Generating RTLIL representation for module `\MMCME3_ADV'. -Generating RTLIL representation for module `\MMCME3_BASE'. -Generating RTLIL representation for module `\PLLE3_ADV'. -Generating RTLIL representation for module `\PLLE3_BASE'. -Generating RTLIL representation for module `\MMCME4_ADV'. -Generating RTLIL representation for module `\MMCME4_BASE'. -Generating RTLIL representation for module `\PLLE4_ADV'. -Generating RTLIL representation for module `\PLLE4_BASE'. -Generating RTLIL representation for module `\BUFT'. -Generating RTLIL representation for module `\IN_FIFO'. -Generating RTLIL representation for module `\OUT_FIFO'. -Generating RTLIL representation for module `\HARD_SYNC'. -Generating RTLIL representation for module `\STARTUP_SPARTAN3'. -Generating RTLIL representation for module `\STARTUP_SPARTAN3E'. -Generating RTLIL representation for module `\STARTUP_SPARTAN3A'. -Generating RTLIL representation for module `\STARTUP_SPARTAN6'. -Generating RTLIL representation for module `\STARTUP_VIRTEX4'. -Generating RTLIL representation for module `\STARTUP_VIRTEX5'. -Generating RTLIL representation for module `\STARTUP_VIRTEX6'. -Generating RTLIL representation for module `\STARTUPE2'. -Generating RTLIL representation for module `\STARTUPE3'. -Generating RTLIL representation for module `\CAPTURE_SPARTAN3'. -Generating RTLIL representation for module `\CAPTURE_SPARTAN3A'. -Generating RTLIL representation for module `\CAPTURE_VIRTEX4'. -Generating RTLIL representation for module `\CAPTURE_VIRTEX5'. -Generating RTLIL representation for module `\CAPTURE_VIRTEX6'. -Generating RTLIL representation for module `\CAPTUREE2'. -Generating RTLIL representation for module `\ICAP_SPARTAN3A'. -Generating RTLIL representation for module `\ICAP_SPARTAN6'. -Generating RTLIL representation for module `\ICAP_VIRTEX4'. -Generating RTLIL representation for module `\ICAP_VIRTEX5'. -Generating RTLIL representation for module `\ICAP_VIRTEX6'. -Generating RTLIL representation for module `\ICAPE2'. -Generating RTLIL representation for module `\ICAPE3'. -Generating RTLIL representation for module `\BSCAN_SPARTAN3'. -Generating RTLIL representation for module `\BSCAN_SPARTAN3A'. -Generating RTLIL representation for module `\BSCAN_SPARTAN6'. -Generating RTLIL representation for module `\BSCAN_VIRTEX4'. -Generating RTLIL representation for module `\BSCAN_VIRTEX5'. -Generating RTLIL representation for module `\BSCAN_VIRTEX6'. -Generating RTLIL representation for module `\BSCANE2'. -Generating RTLIL representation for module `\DNA_PORT'. -Generating RTLIL representation for module `\DNA_PORTE2'. -Generating RTLIL representation for module `\FRAME_ECC_VIRTEX4'. -Generating RTLIL representation for module `\FRAME_ECC_VIRTEX5'. -Generating RTLIL representation for module `\FRAME_ECC_VIRTEX6'. -Generating RTLIL representation for module `\FRAME_ECCE2'. -Generating RTLIL representation for module `\FRAME_ECCE3'. -Generating RTLIL representation for module `\USR_ACCESS_VIRTEX4'. -Generating RTLIL representation for module `\USR_ACCESS_VIRTEX5'. -Generating RTLIL representation for module `\USR_ACCESS_VIRTEX6'. -Generating RTLIL representation for module `\USR_ACCESSE2'. -Generating RTLIL representation for module `\POST_CRC_INTERNAL'. -Generating RTLIL representation for module `\SUSPEND_SYNC'. -Generating RTLIL representation for module `\KEY_CLEAR'. -Generating RTLIL representation for module `\MASTER_JTAG'. -Generating RTLIL representation for module `\SPI_ACCESS'. -Generating RTLIL representation for module `\EFUSE_USR'. -Generating RTLIL representation for module `\SYSMON'. -Generating RTLIL representation for module `\XADC'. -Generating RTLIL representation for module `\SYSMONE1'. -Generating RTLIL representation for module `\SYSMONE4'. -Generating RTLIL representation for module `\GTPA1_DUAL'. -Generating RTLIL representation for module `\GT11_CUSTOM'. -Generating RTLIL representation for module `\GT11_DUAL'. -Generating RTLIL representation for module `\GT11CLK'. -Generating RTLIL representation for module `\GT11CLK_MGT'. -Generating RTLIL representation for module `\GTP_DUAL'. -Generating RTLIL representation for module `\GTX_DUAL'. -Generating RTLIL representation for module `\CRC32'. -Generating RTLIL representation for module `\CRC64'. -Generating RTLIL representation for module `\GTHE1_QUAD'. -Generating RTLIL representation for module `\GTXE1'. -Generating RTLIL representation for module `\IBUFDS_GTXE1'. -Generating RTLIL representation for module `\IBUFDS_GTHE1'. -Generating RTLIL representation for module `\GTHE2_CHANNEL'. -Generating RTLIL representation for module `\GTHE2_COMMON'. -Generating RTLIL representation for module `\GTPE2_CHANNEL'. -Generating RTLIL representation for module `\GTPE2_COMMON'. -Generating RTLIL representation for module `\GTXE2_CHANNEL'. -Generating RTLIL representation for module `\GTXE2_COMMON'. -Generating RTLIL representation for module `\IBUFDS_GTE2'. -Generating RTLIL representation for module `\GTHE3_CHANNEL'. -Generating RTLIL representation for module `\GTHE3_COMMON'. -Generating RTLIL representation for module `\GTHE4_CHANNEL'. -Generating RTLIL representation for module `\GTHE4_COMMON'. -Generating RTLIL representation for module `\GTYE3_CHANNEL'. -Generating RTLIL representation for module `\GTYE3_COMMON'. -Generating RTLIL representation for module `\GTYE4_CHANNEL'. -Generating RTLIL representation for module `\GTYE4_COMMON'. -Generating RTLIL representation for module `\IBUFDS_GTE3'. -Generating RTLIL representation for module `\IBUFDS_GTE4'. -Generating RTLIL representation for module `\OBUFDS_GTE3'. -Generating RTLIL representation for module `\OBUFDS_GTE3_ADV'. -Generating RTLIL representation for module `\OBUFDS_GTE4'. -Generating RTLIL representation for module `\OBUFDS_GTE4_ADV'. -Generating RTLIL representation for module `\PCIE_A1'. -Generating RTLIL representation for module `\PCIE_EP'. -Generating RTLIL representation for module `\PCIE_2_0'. -Generating RTLIL representation for module `\PCIE_2_1'. -Generating RTLIL representation for module `\PCIE_3_0'. -Generating RTLIL representation for module `\PCIE_3_1'. -Generating RTLIL representation for module `\PCIE40E4'. -Generating RTLIL representation for module `\EMAC'. -Generating RTLIL representation for module `\TEMAC'. -Generating RTLIL representation for module `\TEMAC_SINGLE'. -Generating RTLIL representation for module `\CMAC'. -Generating RTLIL representation for module `\CMACE4'. -Generating RTLIL representation for module `\PPC405_ADV'. -Generating RTLIL representation for module `\PPC440'. -Generating RTLIL representation for module `\MCB'. -Generating RTLIL representation for module `\PS7'. -Generating RTLIL representation for module `\PS8'. -Generating RTLIL representation for module `\ILKN'. -Generating RTLIL representation for module `\ILKNE4'. -Successfully finished Verilog frontend. - -6.3. Executing HIERARCHY pass (managing design hierarchy). - -6.3.1. Analyzing design hierarchy.. -Top module: \distributed_ram - -6.3.2. Analyzing design hierarchy.. -Top module: \distributed_ram -Removed 0 unused modules. - -6.4. Executing PROC pass (convert processes to netlists). - -6.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. - -6.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Removed a total of 0 dead cases. - -6.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 0 redundant assignments. -Promoted 1 assignment to connection. - -6.4.4. Executing PROC_INIT pass (extract init attributes). - -6.4.5. Executing PROC_ARST pass (detect async resets in processes). - -6.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\distributed_ram.$proc$attributes_test.v:36$188'. - 1/3: $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 - 2/3: $0$memwr$\memory$attributes_test.v:38$187_DATA[7:0]$190 - 3/3: $0$memwr$\memory$attributes_test.v:38$187_ADDR[3:0]$189 - -6.4.7. Executing PROC_DLATCH pass (convert process syncs to latches). - -6.4.8. Executing PROC_DFF pass (convert process syncs to FFs). -Creating register for signal `\distributed_ram.\data_out_r' using process `\distributed_ram.$proc$attributes_test.v:36$188'. - created $dff cell `$procdff$227' with positive edge clock. -Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$187_ADDR' using process `\distributed_ram.$proc$attributes_test.v:36$188'. - created $dff cell `$procdff$228' with positive edge clock. -Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$187_DATA' using process `\distributed_ram.$proc$attributes_test.v:36$188'. - created $dff cell `$procdff$229' with positive edge clock. -Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$187_EN' using process `\distributed_ram.$proc$attributes_test.v:36$188'. - created $dff cell `$procdff$230' with positive edge clock. - -6.4.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Found and cleaned up 1 empty switch in `\distributed_ram.$proc$attributes_test.v:36$188'. -Removing empty process `distributed_ram.$proc$attributes_test.v:36$188'. -Cleaned up 1 empty switch. - -6.5. Executing TRIBUF pass. - -6.6. Executing DEMINOUT pass (demote inout ports to input or output). - -6.7. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.8. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. -Removed 0 unused cells and 7 unused wires. - - -6.9. Executing CHECK pass (checking for obvious problems). -checking module distributed_ram.. -found and reported 0 problems. - -6.10. Executing OPT pass (performing simple optimizations). - -6.10.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.10.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\distributed_ram'. -Removed a total of 0 cells. - -6.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \distributed_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -6.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \distributed_ram. - Consolidated identical input bits for $mux cell $procmux$221: - Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 - New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] - New connections: $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [7:1] = { $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] $0$memwr$\memory$attributes_test.v:38$187_EN[7:0]$191 [0] } - Optimizing cells in module \distributed_ram. -Performed a total of 1 changes. - -6.10.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\distributed_ram'. -Removed a total of 0 cells. - -6.10.6. Executing OPT_RMDFF pass (remove dff with constant values). - -6.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. - -6.10.8. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.10.9. Rerunning OPT passes. (Maybe there is more to do..) - -6.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \distributed_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -6.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \distributed_ram. -Performed a total of 0 changes. - -6.10.12. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\distributed_ram'. -Removed a total of 0 cells. - -6.10.13. Executing OPT_RMDFF pass (remove dff with constant values). - -6.10.14. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. - -6.10.15. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.10.16. Finished OPT passes. (There is nothing left to do.) - -6.11. Executing WREDUCE pass (reducing word size of cells). -Removed cell distributed_ram.$procmux$223 ($mux). -Removed cell distributed_ram.$procmux$225 ($mux). -Removed top 7 bits (of 8) from FF cell distributed_ram.$procdff$230 ($dff). - -6.12. Executing PEEPOPT pass (run peephole optimizers). - -6.13. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. -Removed 0 unused cells and 2 unused wires. - - -6.14. Executing PMUX2SHIFTX pass. - -6.15. Executing TECHMAP pass (map to technology primitives). - -6.15.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v' to AST representation. -Generating RTLIL representation for module `\_90_lut_cmp_'. -Successfully finished Verilog frontend. - -6.15.2. Continuing TECHMAP pass. -No more expansions possible. - -6.16. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). -Checking cell `$memwr$\memory$attributes_test.v:38$193' in module `\distributed_ram': merged $dff to cell. -Checking cell `$memrd$\memory$attributes_test.v:39$192' in module `\distributed_ram': merged data $dff to cell. - -6.17. Executing TECHMAP pass (map to technology primitives). - -6.17.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v' to AST representation. -Generating RTLIL representation for module `\_80_mul'. -Generating RTLIL representation for module `\_90_soft_mul'. -Successfully finished Verilog frontend. - -6.17.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v' to AST representation. -Generating RTLIL representation for module `\$__MUL25X18'. -Successfully finished Verilog frontend. - -6.17.3. Continuing TECHMAP pass. -No more expansions possible. - -6.18. Executing OPT_EXPR pass (perform const folding). - -6.19. Executing WREDUCE pass (reducing word size of cells). - -6.20. Executing XILINX_DSP pass (pack resources into DSPs). - -6.21. Executing ALUMACC pass (create $alu and $macc cells). -Extracting $alu and $macc cells in module distributed_ram: - created 0 $alu and 0 $macc cells. - -6.22. Executing SHARE pass (SAT-based resource sharing). - -6.23. Executing OPT pass (performing simple optimizations). - -6.23.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.23.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\distributed_ram'. -Removed a total of 0 cells. - -6.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \distributed_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -6.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \distributed_ram. -Performed a total of 0 changes. - -6.23.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\distributed_ram'. -Removed a total of 0 cells. - -6.23.6. Executing OPT_RMDFF pass (remove dff with constant values). - -6.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. -Removed 4 unused cells and 5 unused wires. - - -6.23.8. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.23.9. Rerunning OPT passes. (Maybe there is more to do..) - -6.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \distributed_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -6.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \distributed_ram. -Performed a total of 0 changes. - -6.23.12. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\distributed_ram'. -Removed a total of 0 cells. - -6.23.13. Executing OPT_RMDFF pass (remove dff with constant values). - -6.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. - -6.23.15. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.23.16. Finished OPT passes. (There is nothing left to do.) - -6.24. Executing FSM pass (extract and optimize FSM). - -6.24.1. Executing FSM_DETECT pass (finding FSMs in design). - -6.24.2. Executing FSM_EXTRACT pass (extracting FSM from design). - -6.24.3. Executing FSM_OPT pass (simple optimizations of FSMs). - -6.24.4. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. - -6.24.5. Executing FSM_OPT pass (simple optimizations of FSMs). - -6.24.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). - -6.24.7. Executing FSM_INFO pass (dumping all available information on FSM cells). - -6.24.8. Executing FSM_MAP pass (mapping FSMs to basic logic). - -6.25. Executing OPT pass (performing simple optimizations). - -6.25.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.25.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\distributed_ram'. -Removed a total of 0 cells. - -6.25.3. Executing OPT_RMDFF pass (remove dff with constant values). - -6.25.4. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. - -6.25.5. Finished fast OPT passes. - -6.26. Executing MEMORY pass. - -6.26.1. Executing OPT_MEM pass (optimize memories). -Performed a total of 0 transformations. - -6.26.2. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). - -6.26.3. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. - -6.26.4. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). - -6.26.5. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. - -6.26.6. Executing MEMORY_COLLECT pass (generating $mem cells). -Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\distributed_ram': - $memwr$\memory$attributes_test.v:38$193 ($memwr) - $memrd$\memory$attributes_test.v:39$192 ($memrd) - -6.27. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. - -6.28. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). -Processing distributed_ram.memory: - Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16 - Checking rule #1 for bram type $__XILINX_RAMB36_SDP (variant 1): - Bram geometry: abits=9 dbits=72 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_SDP: awaste=496 dwaste=64 bwaste=36736 waste=36736 efficiency=0 - Rule #1 for bram type $__XILINX_RAMB36_SDP (variant 1) rejected: requirement 'min efficiency 5' not met. - Checking rule #2 for bram type $__XILINX_RAMB18_SDP (variant 1): - Bram geometry: abits=9 dbits=36 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_SDP: awaste=496 dwaste=28 bwaste=18304 waste=18304 efficiency=0 - Rule #2 for bram type $__XILINX_RAMB18_SDP (variant 1) rejected: requirement 'min efficiency 5' not met. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 1): - Bram geometry: abits=10 dbits=36 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=1008 dwaste=28 bwaste=36736 waste=36736 efficiency=0 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 1) rejected: requirement 'min efficiency 5' not met. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 2): - Bram geometry: abits=11 dbits=18 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=2032 dwaste=10 bwaste=36736 waste=36736 efficiency=0 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 2) rejected: requirement 'min efficiency 5' not met. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 3): - Bram geometry: abits=12 dbits=9 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=4080 dwaste=1 bwaste=36736 waste=36736 efficiency=0 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 3) rejected: requirement 'min efficiency 5' not met. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 4): - Bram geometry: abits=13 dbits=4 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=8176 dwaste=0 bwaste=32704 waste=32704 efficiency=0 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 4) rejected: requirement 'min efficiency 5' not met. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 5): - Bram geometry: abits=14 dbits=2 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=16368 dwaste=0 bwaste=32736 waste=32736 efficiency=0 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 5) rejected: requirement 'min efficiency 5' not met. - Checking rule #3 for bram type $__XILINX_RAMB36_TDP (variant 6): - Bram geometry: abits=15 dbits=1 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB36_TDP: awaste=32752 dwaste=0 bwaste=32752 waste=32752 efficiency=0 - Rule #3 for bram type $__XILINX_RAMB36_TDP (variant 6) rejected: requirement 'min efficiency 5' not met. - Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 1): - Bram geometry: abits=10 dbits=18 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_TDP: awaste=1008 dwaste=10 bwaste=18304 waste=18304 efficiency=0 - Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 1) rejected: requirement 'min efficiency 5' not met. - Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 2): - Bram geometry: abits=11 dbits=9 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_TDP: awaste=2032 dwaste=1 bwaste=18304 waste=18304 efficiency=0 - Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 2) rejected: requirement 'min efficiency 5' not met. - Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 3): - Bram geometry: abits=12 dbits=4 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_TDP: awaste=4080 dwaste=0 bwaste=16320 waste=16320 efficiency=0 - Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 3) rejected: requirement 'min efficiency 5' not met. - Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 4): - Bram geometry: abits=13 dbits=2 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_TDP: awaste=8176 dwaste=0 bwaste=16352 waste=16352 efficiency=0 - Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 4) rejected: requirement 'min efficiency 5' not met. - Checking rule #4 for bram type $__XILINX_RAMB18_TDP (variant 5): - Bram geometry: abits=14 dbits=1 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAMB18_TDP: awaste=16368 dwaste=0 bwaste=16368 waste=16368 efficiency=0 - Rule #4 for bram type $__XILINX_RAMB18_TDP (variant 5) rejected: requirement 'min efficiency 5' not met. - No acceptable bram resources found. - -6.29. Executing TECHMAP pass (map to technology primitives). - -6.29.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_brams_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_brams_map.v' to AST representation. -Generating RTLIL representation for module `\$__XILINX_RAMB36_SDP'. -Generating RTLIL representation for module `\$__XILINX_RAMB18_SDP'. -Generating RTLIL representation for module `\$__XILINX_RAMB36_TDP'. -Generating RTLIL representation for module `\$__XILINX_RAMB18_TDP'. -Successfully finished Verilog frontend. - -6.29.2. Continuing TECHMAP pass. -No more expansions possible. - -6.30. Executing MEMORY_BRAM pass (mapping $mem cells to block memories). -Processing distributed_ram.memory: - Properties: ports=2 bits=128 rports=1 wports=1 dbits=8 abits=4 words=16 - Checking rule #1 for bram type $__XILINX_RAM32X1D (variant 1): - Bram geometry: abits=5 dbits=1 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAM32X1D: awaste=16 dwaste=0 bwaste=16 waste=16 efficiency=50 - Rule #1 for bram type $__XILINX_RAM32X1D (variant 1) accepted. - Mapping to bram type $__XILINX_RAM32X1D (variant 1): - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=16 efficiency=50 - Storing for later selection. - Checking rule #2 for bram type $__XILINX_RAM64X1D (variant 1): - Bram geometry: abits=6 dbits=1 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAM64X1D: awaste=48 dwaste=0 bwaste=48 waste=48 efficiency=25 - Rule #2 for bram type $__XILINX_RAM64X1D (variant 1) accepted. - Mapping to bram type $__XILINX_RAM64X1D (variant 1): - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=48 efficiency=25 - Storing for later selection. - Checking rule #3 for bram type $__XILINX_RAM128X1D (variant 1): - Bram geometry: abits=7 dbits=1 wports=0 rports=0 - Estimated number of duplicates for more read ports: dups=1 - Metrics for $__XILINX_RAM128X1D: awaste=112 dwaste=0 bwaste=112 waste=112 efficiency=12 - Rule #3 for bram type $__XILINX_RAM128X1D (variant 1) accepted. - Mapping to bram type $__XILINX_RAM128X1D (variant 1): - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Updated properties: dups=1 waste=112 efficiency=12 - Storing for later selection. - Selecting best of 3 rules: - Efficiency for rule 3.1: efficiency=12, cells=8, acells=1 - Efficiency for rule 2.1: efficiency=25, cells=8, acells=1 - Efficiency for rule 1.1: efficiency=50, cells=8, acells=1 - Selected rule 1.1 with efficiency 50. - Mapping to bram type $__XILINX_RAM32X1D (variant 1): - Write port #0 is in clock domain \clk. - Mapped to bram port B1. - Read port #0 is in clock domain \clk. - Mapped to bram port A1.1. - Creating $__XILINX_RAM32X1D cell at grid position <0 0 0>: memory.0.0.0 - Creating $__XILINX_RAM32X1D cell at grid position <1 0 0>: memory.1.0.0 - Creating $__XILINX_RAM32X1D cell at grid position <2 0 0>: memory.2.0.0 - Creating $__XILINX_RAM32X1D cell at grid position <3 0 0>: memory.3.0.0 - Creating $__XILINX_RAM32X1D cell at grid position <4 0 0>: memory.4.0.0 - Creating $__XILINX_RAM32X1D cell at grid position <5 0 0>: memory.5.0.0 - Creating $__XILINX_RAM32X1D cell at grid position <6 0 0>: memory.6.0.0 - Creating $__XILINX_RAM32X1D cell at grid position <7 0 0>: memory.7.0.0 - -6.31. Executing TECHMAP pass (map to technology primitives). - -6.31.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lutrams_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lutrams_map.v' to AST representation. -Generating RTLIL representation for module `\$__XILINX_RAM32X1D'. -Generating RTLIL representation for module `\$__XILINX_RAM64X1D'. -Generating RTLIL representation for module `\$__XILINX_RAM128X1D'. -Successfully finished Verilog frontend. - -6.31.2. Continuing TECHMAP pass. -Using template $paramod\$__XILINX_RAM32X1D\CLKPOL2=1 for cells of type $__XILINX_RAM32X1D. -No more expansions possible. - - -6.32. Executing OPT pass (performing simple optimizations). - -6.32.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - - -6.32.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\distributed_ram'. -Removed a total of 0 cells. - -6.32.3. Executing OPT_RMDFF pass (remove dff with constant values). - -6.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. -Removed 0 unused cells and 65 unused wires. - - -6.32.5. Finished fast OPT passes. - -6.33. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops). - -6.34. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs). - -6.35. Executing DFF2DFFE pass (transform $dff to $dffe where applicable). -Transforming FF to FF+Enable cells in module distributed_ram: - -6.36. Executing OPT pass (performing simple optimizations). - -6.36.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.36.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\distributed_ram'. -Removed a total of 0 cells. - -6.36.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \distributed_ram.. - Creating internal representation of mux trees. - No muxes found in this module. -Removed 0 multiplexer ports. - -6.36.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \distributed_ram. -Performed a total of 0 changes. - -6.36.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\distributed_ram'. -Removed a total of 0 cells. - -6.36.6. Executing OPT_SHARE pass. - -6.36.7. Executing OPT_RMDFF pass (remove dff with constant values). - -6.36.8. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. - -6.36.9. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.36.10. Finished OPT passes. (There is nothing left to do.) - -6.37. Executing XILINX_SRL pass (Xilinx shift register extraction). - -6.38. Executing TECHMAP pass (map to technology primitives). - -6.38.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v' to AST representation. -Generating RTLIL representation for module `\_90_simplemap_bool_ops'. -Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. -Generating RTLIL representation for module `\_90_simplemap_logic_ops'. -Generating RTLIL representation for module `\_90_simplemap_compare_ops'. -Generating RTLIL representation for module `\_90_simplemap_various'. -Generating RTLIL representation for module `\_90_simplemap_registers'. -Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. -Generating RTLIL representation for module `\_90_shift_shiftx'. -Generating RTLIL representation for module `\_90_fa'. -Generating RTLIL representation for module `\_90_lcu'. -Generating RTLIL representation for module `\_90_alu'. -Generating RTLIL representation for module `\_90_macc'. -Generating RTLIL representation for module `\_90_alumacc'. -Generating RTLIL representation for module `\$__div_mod_u'. -Generating RTLIL representation for module `\$__div_mod'. -Generating RTLIL representation for module `\_90_div'. -Generating RTLIL representation for module `\_90_mod'. -Generating RTLIL representation for module `\_90_pow'. -Generating RTLIL representation for module `\_90_pmux'. -Generating RTLIL representation for module `\_90_lut'. -Successfully finished Verilog frontend. - -6.38.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/arith_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/arith_map.v' to AST representation. -Generating RTLIL representation for module `\_80_xilinx_lcu'. -Generating RTLIL representation for module `\_80_xilinx_alu'. -Successfully finished Verilog frontend. - -6.38.3. Continuing TECHMAP pass. -Using extmapper simplemap for cells of type $dff. -No more expansions possible. - - -6.39. Executing OPT pass (performing simple optimizations). - -6.39.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.39.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\distributed_ram'. -Removed a total of 0 cells. - -6.39.3. Executing OPT_RMDFF pass (remove dff with constant values). - -6.39.4. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram.. - -6.39.5. Finished fast OPT passes. - -6.40. Executing TECHMAP pass (map to technology primitives). - -6.40.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/techmap.v' to AST representation. -Generating RTLIL representation for module `\_90_simplemap_bool_ops'. -Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. -Generating RTLIL representation for module `\_90_simplemap_logic_ops'. -Generating RTLIL representation for module `\_90_simplemap_compare_ops'. -Generating RTLIL representation for module `\_90_simplemap_various'. -Generating RTLIL representation for module `\_90_simplemap_registers'. -Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. -Generating RTLIL representation for module `\_90_shift_shiftx'. -Generating RTLIL representation for module `\_90_fa'. -Generating RTLIL representation for module `\_90_lcu'. -Generating RTLIL representation for module `\_90_alu'. -Generating RTLIL representation for module `\_90_macc'. -Generating RTLIL representation for module `\_90_alumacc'. -Generating RTLIL representation for module `\$__div_mod_u'. -Generating RTLIL representation for module `\$__div_mod'. -Generating RTLIL representation for module `\_90_div'. -Generating RTLIL representation for module `\_90_mod'. -Generating RTLIL representation for module `\_90_pow'. -Generating RTLIL representation for module `\_90_pmux'. -Generating RTLIL representation for module `\_90_lut'. -Successfully finished Verilog frontend. - -6.40.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v' to AST representation. -Generating RTLIL representation for module `\_90_dff_nn0_to_np0'. -Generating RTLIL representation for module `\_90_dff_pn0_to_pp0'. -Generating RTLIL representation for module `\_90_dff_nn1_to_np1'. -Generating RTLIL representation for module `\_90_dff_pn1_to_pp1'. -Generating RTLIL representation for module `\$__SHREG_'. -Generating RTLIL representation for module `\$__XILINX_SHREG_'. -Generating RTLIL representation for module `\$__XILINX_MUXF78'. -Generating RTLIL representation for module `\$__XILINX_TINOUTPAD'. -Generating RTLIL representation for module `\$__XILINX_TOUTPAD'. -Successfully finished Verilog frontend. - -6.40.3. Continuing TECHMAP pass. -No more expansions possible. - -6.41. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram. - -6.42. Executing ABC pass (technology mapping using ABC). - -6.42.1. Extracting gate netlist of module `\distributed_ram' to `/input.blif'.. -Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs. -Don't call ABC as there is nothing to map. -Removing temp directory. - -6.43. Executing XILINX_SRL pass (Xilinx shift register extraction). - -6.44. Executing TECHMAP pass (map to technology primitives). - -6.44.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lut_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/lut_map.v' to AST representation. -Generating RTLIL representation for module `\$lut'. -Successfully finished Verilog frontend. - -6.44.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_map.v' to AST representation. -Generating RTLIL representation for module `\_90_dff_nn0_to_np0'. -Generating RTLIL representation for module `\_90_dff_pn0_to_pp0'. -Generating RTLIL representation for module `\_90_dff_nn1_to_np1'. -Generating RTLIL representation for module `\_90_dff_pn1_to_pp1'. -Generating RTLIL representation for module `\$__SHREG_'. -Generating RTLIL representation for module `\$__XILINX_SHREG_'. -Generating RTLIL representation for module `\$__XILINX_MUXF78'. -Generating RTLIL representation for module `\$__XILINX_TINOUTPAD'. -Generating RTLIL representation for module `\$__XILINX_TOUTPAD'. -Successfully finished Verilog frontend. - -6.44.3. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_ff_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_ff_map.v' to AST representation. -Generating RTLIL representation for module `\$_DFF_N_'. -Generating RTLIL representation for module `\$_DFF_P_'. -Generating RTLIL representation for module `\$_DFFE_NP_'. -Generating RTLIL representation for module `\$_DFFE_PP_'. -Generating RTLIL representation for module `\$_DFF_NN0_'. -Generating RTLIL representation for module `\$_DFF_NP0_'. -Generating RTLIL representation for module `\$_DFF_PN0_'. -Generating RTLIL representation for module `\$_DFF_PP0_'. -Generating RTLIL representation for module `\$_DFF_NN1_'. -Generating RTLIL representation for module `\$_DFF_NP1_'. -Generating RTLIL representation for module `\$_DFF_PN1_'. -Generating RTLIL representation for module `\$_DFF_PP1_'. -Generating RTLIL representation for module `\$_DLATCH_N_'. -Generating RTLIL representation for module `\$_DLATCH_P_'. -Successfully finished Verilog frontend. - -6.44.4. Continuing TECHMAP pass. -Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. -No more expansions possible. - -Removed 0 unused cells and 32 unused wires. - -6.45. Executing CLKBUFMAP pass (inserting global clock buffers). -Inserting BUFG on distributed_ram.clk[0]. - -6.46. Executing HIERARCHY pass (managing design hierarchy). - -6.46.1. Analyzing design hierarchy.. -Top module: \distributed_ram - -6.46.2. Analyzing design hierarchy.. -Top module: \distributed_ram -Removed 0 unused modules. - -6.47. Printing statistics. - -=== distributed_ram === - - Number of wires: 16 - Number of wire bits: 40 - Number of public wires: 6 - Number of public wire bits: 30 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 17 - BUFG 1 - FDRE 8 - RAM32X1D 8 - - Estimated number of LCs: 0 - -6.48. Executing CHECK pass (checking for obvious problems). -checking module distributed_ram.. -found and reported 0 problems. - -7. Executing Verilog-2005 frontend: attributes_test.v -Parsing Verilog input from `attributes_test.v' to AST representation. -Generating RTLIL representation for module `\block_ram'. -Generating RTLIL representation for module `\distributed_ram'. -Generating RTLIL representation for module `\distributed_ram_manual'. -Generating RTLIL representation for module `\distributed_ram_manual_syn'. -Successfully finished Verilog frontend. - -8. Executing PREP pass. - -8.1. Executing HIERARCHY pass (managing design hierarchy). - -8.2. Executing PROC pass (convert processes to netlists). - -8.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. - -8.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Removed a total of 0 dead cases. - -8.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 0 redundant assignments. -Promoted 4 assignments to connections. - -8.2.4. Executing PROC_INIT pass (extract init attributes). - -8.2.5. Executing PROC_ARST pass (detect async resets in processes). - -8.2.6. Executing PROC_MUX pass (convert decision trees to multiplexers). -Creating decoders for process `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. - 1/3: $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 - 2/3: $0$memwr$\memory$attributes_test.v:82$440_DATA[7:0]$444 - 3/3: $0$memwr$\memory$attributes_test.v:82$440_ADDR[3:0]$442 -Creating decoders for process `\distributed_ram_manual.$proc$attributes_test.v:58$434'. - 1/3: $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 - 2/3: $0$memwr$\memory$attributes_test.v:60$433_DATA[7:0]$437 - 3/3: $0$memwr$\memory$attributes_test.v:60$433_ADDR[3:0]$436 -Creating decoders for process `\distributed_ram.$proc$attributes_test.v:36$427'. - 1/3: $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 - 2/3: $0$memwr$\memory$attributes_test.v:38$426_DATA[7:0]$429 - 3/3: $0$memwr$\memory$attributes_test.v:38$426_ADDR[3:0]$428 -Creating decoders for process `\block_ram.$proc$attributes_test.v:14$420'. - 1/3: $0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 - 2/3: $0$memwr$\memory$attributes_test.v:16$419_DATA[3:0]$422 - 3/3: $0$memwr$\memory$attributes_test.v:16$419_ADDR[9:0]$421 - -8.2.7. Executing PROC_DLATCH pass (convert process syncs to latches). - -8.2.8. Executing PROC_DFF pass (convert process syncs to FFs). -Creating register for signal `\distributed_ram_manual_syn.$memwr$\memory$attributes_test.v:82$440_ADDR' using process `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. - created $dff cell `$procdff$471' with positive edge clock. -Creating register for signal `\distributed_ram_manual_syn.\data_out_r' using process `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. - created $dff cell `$procdff$472' with positive edge clock. -Creating register for signal `\distributed_ram_manual_syn.$memwr$\memory$attributes_test.v:82$440_EN' using process `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. - created $dff cell `$procdff$473' with positive edge clock. -Creating register for signal `\distributed_ram_manual_syn.$memwr$\memory$attributes_test.v:82$440_DATA' using process `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. - created $dff cell `$procdff$474' with positive edge clock. -Creating register for signal `\distributed_ram_manual.$memwr$\memory$attributes_test.v:60$433_EN' using process `\distributed_ram_manual.$proc$attributes_test.v:58$434'. - created $dff cell `$procdff$475' with positive edge clock. -Creating register for signal `\distributed_ram_manual.$memwr$\memory$attributes_test.v:60$433_ADDR' using process `\distributed_ram_manual.$proc$attributes_test.v:58$434'. - created $dff cell `$procdff$476' with positive edge clock. -Creating register for signal `\distributed_ram_manual.$memwr$\memory$attributes_test.v:60$433_DATA' using process `\distributed_ram_manual.$proc$attributes_test.v:58$434'. - created $dff cell `$procdff$477' with positive edge clock. -Creating register for signal `\distributed_ram_manual.\data_out_r' using process `\distributed_ram_manual.$proc$attributes_test.v:58$434'. - created $dff cell `$procdff$478' with positive edge clock. -Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$426_ADDR' using process `\distributed_ram.$proc$attributes_test.v:36$427'. - created $dff cell `$procdff$479' with positive edge clock. -Creating register for signal `\distributed_ram.\data_out_r' using process `\distributed_ram.$proc$attributes_test.v:36$427'. - created $dff cell `$procdff$480' with positive edge clock. -Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$426_DATA' using process `\distributed_ram.$proc$attributes_test.v:36$427'. - created $dff cell `$procdff$481' with positive edge clock. -Creating register for signal `\distributed_ram.$memwr$\memory$attributes_test.v:38$426_EN' using process `\distributed_ram.$proc$attributes_test.v:36$427'. - created $dff cell `$procdff$482' with positive edge clock. -Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$419_ADDR' using process `\block_ram.$proc$attributes_test.v:14$420'. - created $dff cell `$procdff$483' with positive edge clock. -Creating register for signal `\block_ram.\data_out_r' using process `\block_ram.$proc$attributes_test.v:14$420'. - created $dff cell `$procdff$484' with positive edge clock. -Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$419_DATA' using process `\block_ram.$proc$attributes_test.v:14$420'. - created $dff cell `$procdff$485' with positive edge clock. -Creating register for signal `\block_ram.$memwr$\memory$attributes_test.v:16$419_EN' using process `\block_ram.$proc$attributes_test.v:14$420'. - created $dff cell `$procdff$486' with positive edge clock. - -8.2.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Found and cleaned up 1 empty switch in `\distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. -Removing empty process `distributed_ram_manual_syn.$proc$attributes_test.v:80$441'. -Found and cleaned up 1 empty switch in `\distributed_ram_manual.$proc$attributes_test.v:58$434'. -Removing empty process `distributed_ram_manual.$proc$attributes_test.v:58$434'. -Found and cleaned up 1 empty switch in `\distributed_ram.$proc$attributes_test.v:36$427'. -Removing empty process `distributed_ram.$proc$attributes_test.v:36$427'. -Found and cleaned up 1 empty switch in `\block_ram.$proc$attributes_test.v:14$420'. -Removing empty process `block_ram.$proc$attributes_test.v:14$420'. -Cleaned up 4 empty switches. - -8.3. Executing OPT_EXPR pass (perform const folding). -Optimizing module distributed_ram_manual_syn. -Optimizing module distributed_ram_manual. -Optimizing module distributed_ram. -Optimizing module block_ram. - -8.4. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \distributed_ram_manual_syn.. -Finding unused cells or wires in module \distributed_ram_manual.. -Finding unused cells or wires in module \distributed_ram.. -Finding unused cells or wires in module \block_ram.. -Removed 0 unused cells and 28 unused wires. - - -8.5. Executing CHECK pass (checking for obvious problems). -checking module block_ram.. -checking module distributed_ram.. -checking module distributed_ram_manual.. -checking module distributed_ram_manual_syn.. -found and reported 0 problems. - -8.6. Executing OPT pass (performing simple optimizations). - -8.6.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. -Optimizing module distributed_ram. -Optimizing module distributed_ram_manual. -Optimizing module distributed_ram_manual_syn. - -8.6.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Finding identical cells in module `\distributed_ram'. -Finding identical cells in module `\distributed_ram_manual'. -Finding identical cells in module `\distributed_ram_manual_syn'. -Removed a total of 0 cells. - -8.6.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \block_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Running muxtree optimizer on module \distributed_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Running muxtree optimizer on module \distributed_ram_manual.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Running muxtree optimizer on module \distributed_ram_manual_syn.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -8.6.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \block_ram. - Consolidated identical input bits for $mux cell $procmux$465: - Old ports: A=4'0000, B=4'1111, Y=$0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 - New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 [0] - New connections: $0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 [3:1] = { $0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 [0] $0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 [0] $0$memwr$\memory$attributes_test.v:16$419_EN[3:0]$423 [0] } - Optimizing cells in module \block_ram. - Optimizing cells in module \distributed_ram. - Consolidated identical input bits for $mux cell $procmux$459: - Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 - New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] - New connections: $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [7:1] = { $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] $0$memwr$\memory$attributes_test.v:38$426_EN[7:0]$430 [0] } - Optimizing cells in module \distributed_ram. - Optimizing cells in module \distributed_ram_manual. - Consolidated identical input bits for $mux cell $procmux$453: - Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 - New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] - New connections: $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [7:1] = { $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] $0$memwr$\memory$attributes_test.v:60$433_EN[7:0]$435 [0] } - Optimizing cells in module \distributed_ram_manual. - Optimizing cells in module \distributed_ram_manual_syn. - Consolidated identical input bits for $mux cell $procmux$447: - Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 - New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] - New connections: $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [7:1] = { $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] $0$memwr$\memory$attributes_test.v:82$440_EN[7:0]$443 [0] } - Optimizing cells in module \distributed_ram_manual_syn. -Performed a total of 4 changes. - -8.6.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Finding identical cells in module `\distributed_ram'. -Finding identical cells in module `\distributed_ram_manual'. -Finding identical cells in module `\distributed_ram_manual_syn'. -Removed a total of 0 cells. - -8.6.6. Executing OPT_RMDFF pass (remove dff with constant values). - -8.6.7. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. -Finding unused cells or wires in module \distributed_ram.. -Finding unused cells or wires in module \distributed_ram_manual.. -Finding unused cells or wires in module \distributed_ram_manual_syn.. - -8.6.8. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. -Optimizing module distributed_ram. -Optimizing module distributed_ram_manual. -Optimizing module distributed_ram_manual_syn. - -8.6.9. Rerunning OPT passes. (Maybe there is more to do..) - -8.6.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \block_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Running muxtree optimizer on module \distributed_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Running muxtree optimizer on module \distributed_ram_manual.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Running muxtree optimizer on module \distributed_ram_manual_syn.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -8.6.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \block_ram. - Optimizing cells in module \distributed_ram. - Optimizing cells in module \distributed_ram_manual. - Optimizing cells in module \distributed_ram_manual_syn. -Performed a total of 0 changes. - -8.6.12. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Finding identical cells in module `\distributed_ram'. -Finding identical cells in module `\distributed_ram_manual'. -Finding identical cells in module `\distributed_ram_manual_syn'. -Removed a total of 0 cells. - -8.6.13. Executing OPT_RMDFF pass (remove dff with constant values). - -8.6.14. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. -Finding unused cells or wires in module \distributed_ram.. -Finding unused cells or wires in module \distributed_ram_manual.. -Finding unused cells or wires in module \distributed_ram_manual_syn.. - -8.6.15. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. -Optimizing module distributed_ram. -Optimizing module distributed_ram_manual. -Optimizing module distributed_ram_manual_syn. - -8.6.16. Finished OPT passes. (There is nothing left to do.) - -8.7. Executing WREDUCE pass (reducing word size of cells). -Removed top 3 bits (of 4) from FF cell block_ram.$procdff$486 ($dff). -Removed top 7 bits (of 8) from FF cell distributed_ram.$procdff$482 ($dff). -Removed top 7 bits (of 8) from FF cell distributed_ram_manual.$procdff$475 ($dff). -Removed top 7 bits (of 8) from FF cell distributed_ram_manual_syn.$procdff$473 ($dff). - -8.8. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). -Checking cell `$memwr$\memory$attributes_test.v:16$425' in module `\block_ram': merged $dff to cell. -Checking cell `$memwr$\memory$attributes_test.v:38$432' in module `\distributed_ram': merged $dff to cell. -Checking cell `$memwr$\memory$attributes_test.v:60$439' in module `\distributed_ram_manual': merged $dff to cell. -Checking cell `$memwr$\memory$attributes_test.v:82$446' in module `\distributed_ram_manual_syn': merged $dff to cell. - -8.9. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. -Finding unused cells or wires in module \distributed_ram.. -Finding unused cells or wires in module \distributed_ram_manual.. -Finding unused cells or wires in module \distributed_ram_manual_syn.. -Removed 12 unused cells and 12 unused wires. - - -8.10. Executing MEMORY_COLLECT pass (generating $mem cells). -Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\block_ram': - $memwr$\memory$attributes_test.v:16$425 ($memwr) - $memrd$\memory$attributes_test.v:17$424 ($memrd) -Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\distributed_ram': - $memwr$\memory$attributes_test.v:38$432 ($memwr) - $memrd$\memory$attributes_test.v:39$431 ($memrd) -Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\distributed_ram_manual': - $memwr$\memory$attributes_test.v:60$439 ($memwr) - $memrd$\memory$attributes_test.v:61$438 ($memrd) -Collecting $memrd, $memwr and $meminit for memory `\memory' in module `\distributed_ram_manual_syn': - $memwr$\memory$attributes_test.v:82$446 ($memwr) - $memrd$\memory$attributes_test.v:83$445 ($memrd) - -8.11. Executing OPT pass (performing simple optimizations). - -8.11.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. -Optimizing module distributed_ram. -Optimizing module distributed_ram_manual. -Optimizing module distributed_ram_manual_syn. - -8.11.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Finding identical cells in module `\distributed_ram'. -Finding identical cells in module `\distributed_ram_manual'. -Finding identical cells in module `\distributed_ram_manual_syn'. -Removed a total of 0 cells. - -8.11.3. Executing OPT_RMDFF pass (remove dff with constant values). - -8.11.4. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. -Finding unused cells or wires in module \distributed_ram.. -Finding unused cells or wires in module \distributed_ram_manual.. -Finding unused cells or wires in module \distributed_ram_manual_syn.. - -8.11.5. Finished fast OPT passes. - -8.12. Printing statistics. - -=== block_ram === - - Number of wires: 10 - Number of wire bits: 46 - Number of public wires: 6 - Number of public wire bits: 24 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 5 - $dff 1 - $mem 1 - $mux 3 - -=== distributed_ram === - - Number of wires: 10 - Number of wire bits: 58 - Number of public wires: 6 - Number of public wire bits: 30 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 5 - $dff 1 - $mem 1 - $mux 3 - -=== distributed_ram_manual === - - Number of wires: 10 - Number of wire bits: 58 - Number of public wires: 6 - Number of public wire bits: 30 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 5 - $dff 1 - $mem 1 - $mux 3 - -=== distributed_ram_manual_syn === - - Number of wires: 10 - Number of wire bits: 58 - Number of public wires: 6 - Number of public wire bits: 30 - Number of memories: 0 - Number of memory bits: 0 - Number of processes: 0 - Number of cells: 5 - $dff 1 - $mem 1 - $mux 3 - -8.13. Executing CHECK pass (checking for obvious problems). -checking module block_ram.. -checking module distributed_ram.. -checking module distributed_ram_manual.. -checking module distributed_ram_manual_syn.. -found and reported 0 problems. - -9. Executing SYNTH_XILINX pass. - -9.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_sim.v' to AST representation. -Generating RTLIL representation for module `\VCC'. -Generating RTLIL representation for module `\GND'. -Generating RTLIL representation for module `\IBUF'. -Generating RTLIL representation for module `\IBUFG'. -Generating RTLIL representation for module `\OBUF'. -Generating RTLIL representation for module `\IOBUF'. -Generating RTLIL representation for module `\OBUFT'. -Generating RTLIL representation for module `\BUFG'. -Generating RTLIL representation for module `\BUFGCTRL'. -Generating RTLIL representation for module `\BUFHCE'. -Generating RTLIL representation for module `\INV'. -Generating RTLIL representation for module `\LUT1'. -Generating RTLIL representation for module `\LUT2'. -Generating RTLIL representation for module `\LUT3'. -Generating RTLIL representation for module `\LUT4'. -Generating RTLIL representation for module `\LUT5'. -Generating RTLIL representation for module `\LUT6'. -Generating RTLIL representation for module `\LUT6_2'. -Generating RTLIL representation for module `\MUXCY'. -Generating RTLIL representation for module `\MUXF7'. -Generating RTLIL representation for module `\MUXF8'. -Generating RTLIL representation for module `\XORCY'. -Generating RTLIL representation for module `\CARRY4'. -Generating RTLIL representation for module `\FDRE'. -Generating RTLIL representation for module `\FDSE'. -Generating RTLIL representation for module `\FDCE'. -Generating RTLIL representation for module `\FDPE'. -Generating RTLIL representation for module `\FDRE_1'. -Generating RTLIL representation for module `\FDSE_1'. -Generating RTLIL representation for module `\FDCE_1'. -Generating RTLIL representation for module `\FDPE_1'. -Generating RTLIL representation for module `\LDCE'. -Generating RTLIL representation for module `\LDPE'. -Generating RTLIL representation for module `\RAM16X1S'. -Generating RTLIL representation for module `\RAM16X1S_1'. -Generating RTLIL representation for module `\RAM32X1S'. -Generating RTLIL representation for module `\RAM32X1S_1'. -Generating RTLIL representation for module `\RAM64X1S'. -Generating RTLIL representation for module `\RAM64X1S_1'. -Generating RTLIL representation for module `\RAM128X1S'. -Generating RTLIL representation for module `\RAM128X1S_1'. -Generating RTLIL representation for module `\RAM256X1S'. -Generating RTLIL representation for module `\RAM512X1S'. -Generating RTLIL representation for module `\RAM16X2S'. -Generating RTLIL representation for module `\RAM32X2S'. -Generating RTLIL representation for module `\RAM64X2S'. -Generating RTLIL representation for module `\RAM16X4S'. -Generating RTLIL representation for module `\RAM32X4S'. -Generating RTLIL representation for module `\RAM16X8S'. -Generating RTLIL representation for module `\RAM32X8S'. -Generating RTLIL representation for module `\RAM16X1D'. -Generating RTLIL representation for module `\RAM16X1D_1'. -Generating RTLIL representation for module `\RAM32X1D'. -Generating RTLIL representation for module `\RAM32X1D_1'. -Generating RTLIL representation for module `\RAM64X1D'. -Generating RTLIL representation for module `\RAM64X1D_1'. -Generating RTLIL representation for module `\RAM128X1D'. -Generating RTLIL representation for module `\RAM256X1D'. -Generating RTLIL representation for module `\RAM32M'. -Generating RTLIL representation for module `\RAM32M16'. -Generating RTLIL representation for module `\RAM64M'. -Generating RTLIL representation for module `\RAM64M8'. -Generating RTLIL representation for module `\ROM16X1'. -Generating RTLIL representation for module `\ROM32X1'. -Generating RTLIL representation for module `\ROM64X1'. -Generating RTLIL representation for module `\ROM128X1'. -Generating RTLIL representation for module `\ROM256X1'. -Generating RTLIL representation for module `\SRL16E'. -Generating RTLIL representation for module `\SRLC16E'. -Generating RTLIL representation for module `\SRLC32E'. -Generating RTLIL representation for module `\MULT18X18'. -Generating RTLIL representation for module `\MULT18X18S'. -Generating RTLIL representation for module `\MULT18X18SIO'. -Generating RTLIL representation for module `\DSP48A'. -Generating RTLIL representation for module `\DSP48A1'. -Generating RTLIL representation for module `\DSP48E1'. -Successfully finished Verilog frontend. - -9.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/cells_xtra.v' to AST representation. -Generating RTLIL representation for module `\FDCPE'. -Generating RTLIL representation for module `\FDRSE'. -Generating RTLIL representation for module `\LDCPE'. -Generating RTLIL representation for module `\AND2B1L'. -Generating RTLIL representation for module `\OR2L'. -Generating RTLIL representation for module `\MUXF5'. -Generating RTLIL representation for module `\MUXF6'. -Generating RTLIL representation for module `\MUXF9'. -Generating RTLIL representation for module `\CARRY8'. -Generating RTLIL representation for module `\ORCY'. -Generating RTLIL representation for module `\MULT_AND'. -Generating RTLIL representation for module `\SRL16'. -Generating RTLIL representation for module `\SRLC16'. -Generating RTLIL representation for module `\CFGLUT5'. -Generating RTLIL representation for module `\RAMB16_S1'. -Generating RTLIL representation for module `\RAMB16_S2'. -Generating RTLIL representation for module `\RAMB16_S4'. -Generating RTLIL representation for module `\RAMB16_S9'. -Generating RTLIL representation for module `\RAMB16_S18'. -Generating RTLIL representation for module `\RAMB16_S36'. -Generating RTLIL representation for module `\RAMB16_S1_S1'. -Generating RTLIL representation for module `\RAMB16_S1_S2'. -Generating RTLIL representation for module `\RAMB16_S1_S4'. -Generating RTLIL representation for module `\RAMB16_S1_S9'. -Generating RTLIL representation for module `\RAMB16_S1_S18'. -Generating RTLIL representation for module `\RAMB16_S1_S36'. -Generating RTLIL representation for module `\RAMB16_S2_S2'. -Generating RTLIL representation for module `\RAMB16_S2_S4'. -Generating RTLIL representation for module `\RAMB16_S2_S9'. -Generating RTLIL representation for module `\RAMB16_S2_S18'. -Generating RTLIL representation for module `\RAMB16_S2_S36'. -Generating RTLIL representation for module `\RAMB16_S4_S4'. -Generating RTLIL representation for module `\RAMB16_S4_S9'. -Generating RTLIL representation for module `\RAMB16_S4_S18'. -Generating RTLIL representation for module `\RAMB16_S4_S36'. -Generating RTLIL representation for module `\RAMB16_S9_S9'. -Generating RTLIL representation for module `\RAMB16_S9_S18'. -Generating RTLIL representation for module `\RAMB16_S9_S36'. -Generating RTLIL representation for module `\RAMB16_S18_S18'. -Generating RTLIL representation for module `\RAMB16_S18_S36'. -Generating RTLIL representation for module `\RAMB16_S36_S36'. -Generating RTLIL representation for module `\RAMB16BWE_S18'. -Generating RTLIL representation for module `\RAMB16BWE_S36'. -Generating RTLIL representation for module `\RAMB16BWE_S18_S9'. -Generating RTLIL representation for module `\RAMB16BWE_S18_S18'. -Generating RTLIL representation for module `\RAMB16BWE_S36_S9'. -Generating RTLIL representation for module `\RAMB16BWE_S36_S18'. -Generating RTLIL representation for module `\RAMB16BWE_S36_S36'. -Generating RTLIL representation for module `\RAMB16BWER'. -Generating RTLIL representation for module `\RAMB8BWER'. -Generating RTLIL representation for module `\FIFO16'. -Generating RTLIL representation for module `\RAMB16'. -Generating RTLIL representation for module `\RAMB32_S64_ECC'. -Generating RTLIL representation for module `\FIFO18'. -Generating RTLIL representation for module `\FIFO18_36'. -Generating RTLIL representation for module `\FIFO36'. -Generating RTLIL representation for module `\FIFO36_72'. -Generating RTLIL representation for module `\RAMB18'. -Generating RTLIL representation for module `\RAMB36'. -Generating RTLIL representation for module `\RAMB18SDP'. -Generating RTLIL representation for module `\RAMB36SDP'. -Generating RTLIL representation for module `\FIFO18E1'. -Generating RTLIL representation for module `\FIFO36E1'. -Generating RTLIL representation for module `\RAMB18E1'. -Generating RTLIL representation for module `\RAMB36E1'. -Generating RTLIL representation for module `\FIFO18E2'. -Generating RTLIL representation for module `\FIFO36E2'. -Generating RTLIL representation for module `\RAMB18E2'. -Generating RTLIL representation for module `\RAMB36E2'. -Generating RTLIL representation for module `\URAM288'. -Generating RTLIL representation for module `\URAM288_BASE'. -Generating RTLIL representation for module `\DSP48'. -Generating RTLIL representation for module `\DSP48E'. -Generating RTLIL representation for module `\DSP48E2'. -Generating RTLIL representation for module `\IFDDRCPE'. -Generating RTLIL representation for module `\IFDDRRSE'. -Generating RTLIL representation for module `\OFDDRCPE'. -Generating RTLIL representation for module `\OFDDRRSE'. -Generating RTLIL representation for module `\OFDDRTCPE'. -Generating RTLIL representation for module `\OFDDRTRSE'. -Generating RTLIL representation for module `\IDDR2'. -Generating RTLIL representation for module `\ODDR2'. -Generating RTLIL representation for module `\IDDR'. -Generating RTLIL representation for module `\IDDR_2CLK'. -Generating RTLIL representation for module `\ODDR'. -Generating RTLIL representation for module `\IDELAYCTRL'. -Generating RTLIL representation for module `\IDELAY'. -Generating RTLIL representation for module `\ISERDES'. -Generating RTLIL representation for module `\OSERDES'. -Generating RTLIL representation for module `\IODELAY'. -Generating RTLIL representation for module `\ISERDES_NODELAY'. -Generating RTLIL representation for module `\IODELAYE1'. -Generating RTLIL representation for module `\ISERDESE1'. -Generating RTLIL representation for module `\OSERDESE1'. -Generating RTLIL representation for module `\IDELAYE2'. -Generating RTLIL representation for module `\ODELAYE2'. -Generating RTLIL representation for module `\ISERDESE2'. -Generating RTLIL representation for module `\OSERDESE2'. -Generating RTLIL representation for module `\PHASER_IN'. -Generating RTLIL representation for module `\PHASER_IN_PHY'. -Generating RTLIL representation for module `\PHASER_OUT'. -Generating RTLIL representation for module `\PHASER_OUT_PHY'. -Generating RTLIL representation for module `\PHASER_REF'. -Generating RTLIL representation for module `\PHY_CONTROL'. -Generating RTLIL representation for module `\IDDRE1'. -Generating RTLIL representation for module `\ODDRE1'. -Generating RTLIL representation for module `\IDELAYE3'. -Generating RTLIL representation for module `\ODELAYE3'. -Generating RTLIL representation for module `\ISERDESE3'. -Generating RTLIL representation for module `\OSERDESE3'. -Generating RTLIL representation for module `\BITSLICE_CONTROL'. -Generating RTLIL representation for module `\RIU_OR'. -Generating RTLIL representation for module `\RX_BITSLICE'. -Generating RTLIL representation for module `\RXTX_BITSLICE'. -Generating RTLIL representation for module `\TX_BITSLICE'. -Generating RTLIL representation for module `\TX_BITSLICE_TRI'. -Generating RTLIL representation for module `\IODELAY2'. -Generating RTLIL representation for module `\IODRP2'. -Generating RTLIL representation for module `\IODRP2_MCB'. -Generating RTLIL representation for module `\ISERDES2'. -Generating RTLIL representation for module `\OSERDES2'. -Generating RTLIL representation for module `\IBUF_DLY_ADJ'. -Generating RTLIL representation for module `\IBUF_IBUFDISABLE'. -Generating RTLIL representation for module `\IBUF_INTERMDISABLE'. -Generating RTLIL representation for module `\IBUF_ANALOG'. -Generating RTLIL representation for module `\IBUFE3'. -Generating RTLIL representation for module `\IBUFDS'. -Generating RTLIL representation for module `\IBUFDS_DLY_ADJ'. -Generating RTLIL representation for module `\IBUFDS_IBUFDISABLE'. -Generating RTLIL representation for module `\IBUFDS_INTERMDISABLE'. -Generating RTLIL representation for module `\IBUFDS_DIFF_OUT'. -Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_IBUFDISABLE'. -Generating RTLIL representation for module `\IBUFDS_DIFF_OUT_INTERMDISABLE'. -Generating RTLIL representation for module `\IBUFDSE3'. -Generating RTLIL representation for module `\IBUFDS_DPHY'. -Generating RTLIL representation for module `\IBUFGDS'. -Generating RTLIL representation for module `\IBUFGDS_DIFF_OUT'. -Generating RTLIL representation for module `\IOBUF_DCIEN'. -Generating RTLIL representation for module `\IOBUF_INTERMDISABLE'. -Generating RTLIL representation for module `\IOBUFE3'. -Generating RTLIL representation for module `\IOBUFDS'. -Generating RTLIL representation for module `\IOBUFDS_DCIEN'. -Generating RTLIL representation for module `\IOBUFDS_INTERMDISABLE'. -Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT'. -Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_DCIEN'. -Generating RTLIL representation for module `\IOBUFDS_DIFF_OUT_INTERMDISABLE'. -Generating RTLIL representation for module `\IOBUFDSE3'. -Generating RTLIL representation for module `\OBUFDS'. -Generating RTLIL representation for module `\OBUFDS_DPHY'. -Generating RTLIL representation for module `\OBUFTDS'. -Generating RTLIL representation for module `\KEEPER'. -Generating RTLIL representation for module `\PULLDOWN'. -Generating RTLIL representation for module `\PULLUP'. -Generating RTLIL representation for module `\DCIRESET'. -Generating RTLIL representation for module `\HPIO_VREF'. -Generating RTLIL representation for module `\BUFGCE'. -Generating RTLIL representation for module `\BUFGCE_1'. -Generating RTLIL representation for module `\BUFGMUX'. -Generating RTLIL representation for module `\BUFGMUX_1'. -Generating RTLIL representation for module `\BUFGMUX_CTRL'. -Generating RTLIL representation for module `\BUFGMUX_VIRTEX4'. -Generating RTLIL representation for module `\BUFG_GT'. -Generating RTLIL representation for module `\BUFG_GT_SYNC'. -Generating RTLIL representation for module `\BUFG_PS'. -Generating RTLIL representation for module `\BUFGCE_DIV'. -Generating RTLIL representation for module `\BUFH'. -Generating RTLIL representation for module `\BUFIO2'. -Generating RTLIL representation for module `\BUFIO2_2CLK'. -Generating RTLIL representation for module `\BUFIO2FB'. -Generating RTLIL representation for module `\BUFPLL'. -Generating RTLIL representation for module `\BUFPLL_MCB'. -Generating RTLIL representation for module `\BUFIO'. -Generating RTLIL representation for module `\BUFIODQS'. -Generating RTLIL representation for module `\BUFR'. -Generating RTLIL representation for module `\BUFMR'. -Generating RTLIL representation for module `\BUFMRCE'. -Generating RTLIL representation for module `\DCM'. -Generating RTLIL representation for module `\DCM_SP'. -Generating RTLIL representation for module `\DCM_CLKGEN'. -Generating RTLIL representation for module `\DCM_ADV'. -Generating RTLIL representation for module `\DCM_BASE'. -Generating RTLIL representation for module `\DCM_PS'. -Generating RTLIL representation for module `\PMCD'. -Generating RTLIL representation for module `\PLL_ADV'. -Generating RTLIL representation for module `\PLL_BASE'. -Generating RTLIL representation for module `\MMCM_ADV'. -Generating RTLIL representation for module `\MMCM_BASE'. -Generating RTLIL representation for module `\MMCME2_ADV'. -Generating RTLIL representation for module `\MMCME2_BASE'. -Generating RTLIL representation for module `\PLLE2_ADV'. -Generating RTLIL representation for module `\PLLE2_BASE'. -Generating RTLIL representation for module `\MMCME3_ADV'. -Generating RTLIL representation for module `\MMCME3_BASE'. -Generating RTLIL representation for module `\PLLE3_ADV'. -Generating RTLIL representation for module `\PLLE3_BASE'. -Generating RTLIL representation for module `\MMCME4_ADV'. -Generating RTLIL representation for module `\MMCME4_BASE'. -Generating RTLIL representation for module `\PLLE4_ADV'. -Generating RTLIL representation for module `\PLLE4_BASE'. -Generating RTLIL representation for module `\BUFT'. -Generating RTLIL representation for module `\IN_FIFO'. -Generating RTLIL representation for module `\OUT_FIFO'. -Generating RTLIL representation for module `\HARD_SYNC'. -Generating RTLIL representation for module `\STARTUP_SPARTAN3'. -Generating RTLIL representation for module `\STARTUP_SPARTAN3E'. -Generating RTLIL representation for module `\STARTUP_SPARTAN3A'. -Generating RTLIL representation for module `\STARTUP_SPARTAN6'. -Generating RTLIL representation for module `\STARTUP_VIRTEX4'. -Generating RTLIL representation for module `\STARTUP_VIRTEX5'. -Generating RTLIL representation for module `\STARTUP_VIRTEX6'. -Generating RTLIL representation for module `\STARTUPE2'. -Generating RTLIL representation for module `\STARTUPE3'. -Generating RTLIL representation for module `\CAPTURE_SPARTAN3'. -Generating RTLIL representation for module `\CAPTURE_SPARTAN3A'. -Generating RTLIL representation for module `\CAPTURE_VIRTEX4'. -Generating RTLIL representation for module `\CAPTURE_VIRTEX5'. -Generating RTLIL representation for module `\CAPTURE_VIRTEX6'. -Generating RTLIL representation for module `\CAPTUREE2'. -Generating RTLIL representation for module `\ICAP_SPARTAN3A'. -Generating RTLIL representation for module `\ICAP_SPARTAN6'. -Generating RTLIL representation for module `\ICAP_VIRTEX4'. -Generating RTLIL representation for module `\ICAP_VIRTEX5'. -Generating RTLIL representation for module `\ICAP_VIRTEX6'. -Generating RTLIL representation for module `\ICAPE2'. -Generating RTLIL representation for module `\ICAPE3'. -Generating RTLIL representation for module `\BSCAN_SPARTAN3'. -Generating RTLIL representation for module `\BSCAN_SPARTAN3A'. -Generating RTLIL representation for module `\BSCAN_SPARTAN6'. -Generating RTLIL representation for module `\BSCAN_VIRTEX4'. -Generating RTLIL representation for module `\BSCAN_VIRTEX5'. -Generating RTLIL representation for module `\BSCAN_VIRTEX6'. -Generating RTLIL representation for module `\BSCANE2'. -Generating RTLIL representation for module `\DNA_PORT'. -Generating RTLIL representation for module `\DNA_PORTE2'. -Generating RTLIL representation for module `\FRAME_ECC_VIRTEX4'. -Generating RTLIL representation for module `\FRAME_ECC_VIRTEX5'. -Generating RTLIL representation for module `\FRAME_ECC_VIRTEX6'. -Generating RTLIL representation for module `\FRAME_ECCE2'. -Generating RTLIL representation for module `\FRAME_ECCE3'. -Generating RTLIL representation for module `\USR_ACCESS_VIRTEX4'. -Generating RTLIL representation for module `\USR_ACCESS_VIRTEX5'. -Generating RTLIL representation for module `\USR_ACCESS_VIRTEX6'. -Generating RTLIL representation for module `\USR_ACCESSE2'. -Generating RTLIL representation for module `\POST_CRC_INTERNAL'. -Generating RTLIL representation for module `\SUSPEND_SYNC'. -Generating RTLIL representation for module `\KEY_CLEAR'. -Generating RTLIL representation for module `\MASTER_JTAG'. -Generating RTLIL representation for module `\SPI_ACCESS'. -Generating RTLIL representation for module `\EFUSE_USR'. -Generating RTLIL representation for module `\SYSMON'. -Generating RTLIL representation for module `\XADC'. -Generating RTLIL representation for module `\SYSMONE1'. -Generating RTLIL representation for module `\SYSMONE4'. -Generating RTLIL representation for module `\GTPA1_DUAL'. -Generating RTLIL representation for module `\GT11_CUSTOM'. -Generating RTLIL representation for module `\GT11_DUAL'. -Generating RTLIL representation for module `\GT11CLK'. -Generating RTLIL representation for module `\GT11CLK_MGT'. -Generating RTLIL representation for module `\GTP_DUAL'. -Generating RTLIL representation for module `\GTX_DUAL'. -Generating RTLIL representation for module `\CRC32'. -Generating RTLIL representation for module `\CRC64'. -Generating RTLIL representation for module `\GTHE1_QUAD'. -Generating RTLIL representation for module `\GTXE1'. -Generating RTLIL representation for module `\IBUFDS_GTXE1'. -Generating RTLIL representation for module `\IBUFDS_GTHE1'. -Generating RTLIL representation for module `\GTHE2_CHANNEL'. -Generating RTLIL representation for module `\GTHE2_COMMON'. -Generating RTLIL representation for module `\GTPE2_CHANNEL'. -Generating RTLIL representation for module `\GTPE2_COMMON'. -Generating RTLIL representation for module `\GTXE2_CHANNEL'. -Generating RTLIL representation for module `\GTXE2_COMMON'. -Generating RTLIL representation for module `\IBUFDS_GTE2'. -Generating RTLIL representation for module `\GTHE3_CHANNEL'. -Generating RTLIL representation for module `\GTHE3_COMMON'. -Generating RTLIL representation for module `\GTHE4_CHANNEL'. -Generating RTLIL representation for module `\GTHE4_COMMON'. -Generating RTLIL representation for module `\GTYE3_CHANNEL'. -Generating RTLIL representation for module `\GTYE3_COMMON'. -Generating RTLIL representation for module `\GTYE4_CHANNEL'. -Generating RTLIL representation for module `\GTYE4_COMMON'. -Generating RTLIL representation for module `\IBUFDS_GTE3'. -Generating RTLIL representation for module `\IBUFDS_GTE4'. -Generating RTLIL representation for module `\OBUFDS_GTE3'. -Generating RTLIL representation for module `\OBUFDS_GTE3_ADV'. -Generating RTLIL representation for module `\OBUFDS_GTE4'. -Generating RTLIL representation for module `\OBUFDS_GTE4_ADV'. -Generating RTLIL representation for module `\PCIE_A1'. -Generating RTLIL representation for module `\PCIE_EP'. -Generating RTLIL representation for module `\PCIE_2_0'. -Generating RTLIL representation for module `\PCIE_2_1'. -Generating RTLIL representation for module `\PCIE_3_0'. -Generating RTLIL representation for module `\PCIE_3_1'. -Generating RTLIL representation for module `\PCIE40E4'. -Generating RTLIL representation for module `\EMAC'. -Generating RTLIL representation for module `\TEMAC'. -Generating RTLIL representation for module `\TEMAC_SINGLE'. -Generating RTLIL representation for module `\CMAC'. -Generating RTLIL representation for module `\CMACE4'. -Generating RTLIL representation for module `\PPC405_ADV'. -Generating RTLIL representation for module `\PPC440'. -Generating RTLIL representation for module `\MCB'. -Generating RTLIL representation for module `\PS7'. -Generating RTLIL representation for module `\PS8'. -Generating RTLIL representation for module `\ILKN'. -Generating RTLIL representation for module `\ILKNE4'. -Successfully finished Verilog frontend. - -9.3. Executing HIERARCHY pass (managing design hierarchy). - -9.3.1. Analyzing design hierarchy.. -Top module: \block_ram - -9.3.2. Analyzing design hierarchy.. -Top module: \block_ram -Removing unused module `\distributed_ram'. -Removing unused module `\distributed_ram_manual'. -Removing unused module `\distributed_ram_manual_syn'. -Removed 3 unused modules. - -9.4. Executing PROC pass (convert processes to netlists). - -9.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. - -9.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). -Removed a total of 0 dead cases. - -9.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). -Removed 0 redundant assignments. -Promoted 0 assignments to connections. - -9.4.4. Executing PROC_INIT pass (extract init attributes). - -9.4.5. Executing PROC_ARST pass (detect async resets in processes). - -9.4.6. Executing PROC_MUX pass (convert decision trees to multiplexers). - -9.4.7. Executing PROC_DLATCH pass (convert process syncs to latches). - -9.4.8. Executing PROC_DFF pass (convert process syncs to FFs). - -9.4.9. Executing PROC_CLEAN pass (remove empty switches from decision trees). -Cleaned up 0 empty switches. - -9.5. Executing TRIBUF pass. - -9.6. Executing DEMINOUT pass (demote inout ports to input or output). - -9.7. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -9.8. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -9.9. Executing CHECK pass (checking for obvious problems). -checking module block_ram.. -found and reported 0 problems. - -9.10. Executing OPT pass (performing simple optimizations). - -9.10.1. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -9.10.2. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -9.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). -Running muxtree optimizer on module \block_ram.. - Creating internal representation of mux trees. - Evaluating internal representation of mux trees. - Analyzing evaluation results. -Removed 0 multiplexer ports. - - -9.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). - Optimizing cells in module \block_ram. -Performed a total of 0 changes. - -9.10.5. Executing OPT_MERGE pass (detect identical cells). -Finding identical cells in module `\block_ram'. -Removed a total of 0 cells. - -9.10.6. Executing OPT_RMDFF pass (remove dff with constant values). - -9.10.7. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. - -9.10.8. Executing OPT_EXPR pass (perform const folding). -Optimizing module block_ram. - -9.10.9. Finished OPT passes. (There is nothing left to do.) - -9.11. Executing WREDUCE pass (reducing word size of cells). -Removed cell block_ram.$procmux$469 ($mux). -Removed cell block_ram.$procmux$467 ($mux). - -9.12. Executing PEEPOPT pass (run peephole optimizers). - -9.13. Executing OPT_CLEAN pass (remove unused cells and wires). -Finding unused cells or wires in module \block_ram.. -Removed 0 unused cells and 2 unused wires. - - -9.14. Executing PMUX2SHIFTX pass. - -9.15. Executing TECHMAP pass (map to technology primitives). - -9.15.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/cmp2lut.v' to AST representation. -Generating RTLIL representation for module `\_90_lut_cmp_'. -Successfully finished Verilog frontend. - -9.15.2. Continuing TECHMAP pass. -No more expansions possible. - -9.16. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr). - -9.17. Executing TECHMAP pass (map to technology primitives). - -9.17.1. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/mul2dsp.v' to AST representation. -Generating RTLIL representation for module `\_80_mul'. -Generating RTLIL representation for module `\_90_soft_mul'. -Successfully finished Verilog frontend. - -9.17.2. Executing Verilog-2005 frontend: /opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v -Parsing Verilog input from `/opt/eda/fpga/FOSS/memattr/yosys_release/share/xilinx/xc7_dsp_map.v' to AST representation. -Generating RTLIL representation for module `\$__MUL25X18'. -Successfully finished Verilog frontend. - -9.17.3. Continuing TECHMAP pass. -No more expansions possible. - -9.18. Executing OPT_EXPR pass (perform const folding). - -9.19. Executing WREDUCE pass (reducing word size of cells). - -9.20. Executing XILINX_DSP pass (pack resources into DSPs). - -9.21. Executing ALUMACC pass (create $alu and $macc cells). -Extracting $alu and $macc cells in module block_ram: - created 0 $alu and 0 $macc cells. - -9.22. Executing SHARE pass (SAT-based resource sharing). -- cgit v1.2.3 From abcd82dacadc8b5af6b2b7f6d7cbdb635d276440 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Mon, 16 Dec 2019 13:09:31 +0100 Subject: add assert option to scratchpad command --- tests/various/scratchpad.sh | 14 -------------- tests/various/scratchpad.ys | 5 +++++ 2 files changed, 5 insertions(+), 14 deletions(-) delete mode 100755 tests/various/scratchpad.sh create mode 100644 tests/various/scratchpad.ys (limited to 'tests') diff --git a/tests/various/scratchpad.sh b/tests/various/scratchpad.sh deleted file mode 100755 index 4e92473f8..000000000 --- a/tests/various/scratchpad.sh +++ /dev/null @@ -1,14 +0,0 @@ -#!/bin/bash - -trap 'echo "ERROR in scratchpad.sh" >&2; exit 1' ERR - -../../yosys -qp "scratchpad -set foo \"bar baz\"; \ -scratchpad -copy foo oof; scratchpad -unset foo; \ -tee -o scratchpad1.log scratchpad -get oof; \ -tee -o scratchpad2.log scratchpad -get foo" - -test "$(cat scratchpad1.log)" = "bar baz" -test "$(cat scratchpad2.log)" = "\"foo\" not set" - -rm scratchpad1.log -rm scratchpad2.log diff --git a/tests/various/scratchpad.ys b/tests/various/scratchpad.ys new file mode 100644 index 000000000..dc94081ea --- /dev/null +++ b/tests/various/scratchpad.ys @@ -0,0 +1,5 @@ +scratchpad -set foo "bar baz" +scratchpad -copy foo oof +scratchpad -unset foo +scratchpad -assert oof "bar baz" +scratchpad -assert-unset foo -- cgit v1.2.3 From 87e21b0122bd682db8aeffae3e1ac503c9cea2d2 Mon Sep 17 00:00:00 2001 From: Diego H Date: Mon, 16 Dec 2019 10:23:45 -0600 Subject: Fixing compiler warning/issues. Moving test script to the correct place --- .../common/memory_attributes/attributes_test.ys | 47 ---------------------- tests/arch/xilinx/attributes_test.ys | 47 ++++++++++++++++++++++ 2 files changed, 47 insertions(+), 47 deletions(-) delete mode 100644 tests/arch/common/memory_attributes/attributes_test.ys create mode 100644 tests/arch/xilinx/attributes_test.ys (limited to 'tests') diff --git a/tests/arch/common/memory_attributes/attributes_test.ys b/tests/arch/common/memory_attributes/attributes_test.ys deleted file mode 100644 index 4e06a35e7..000000000 --- a/tests/arch/common/memory_attributes/attributes_test.ys +++ /dev/null @@ -1,47 +0,0 @@ -# Check that blockram memory without parameters is not modified -read_verilog attributes_test.v -hierarchy -top block_ram -synth_xilinx -top block_ram -cd block_ram # Constrain all select calls below inside the top module -select -assert-count 1 t:RAMB18E1 - -# Check that distributed memory without parameters is not modified -design -reset -read_verilog attributes_test.v -hierarchy -top distributed_ram -synth_xilinx -top distributed_ram -cd distributed_ram # Constrain all select calls below inside the top module -select -assert-count 8 t:RAM32X1D - -# Set ram_style distributed to blockram memory; will be implemented as distributed -design -reset -read_verilog attributes_test.v -prep -setattr -mod -set ram_style "distributed" block_ram -synth_xilinx -top block_ram -cd block_ram # Constrain all select calls below inside the top module -select -assert-count 32 t:RAM128X1D - -# Set synthesis, logic_block to blockram memory; will be implemented as distributed -design -reset -read_verilog attributes_test.v -prep -setattr -mod -set logic_block 1 block_ram -synth_xilinx -top block_ram -cd block_ram # Constrain all select calls below inside the top module -select -assert-count 0 t:RAMB18E1 -select -assert-count 32 t:RAM128X1D - -# Set ram_style block to a distributed memory; will be implemented as blockram -design -reset -read_verilog attributes_test.v -synth_xilinx -top distributed_ram_manual -cd distributed_ram_manual # Constrain all select calls below inside the top module -select -assert-count 1 t:RAMB18E1 - -# Set synthesis, ram_block block to a distributed memory; will be implemented as blockram -design -reset -read_verilog attributes_test.v -synth_xilinx -top distributed_ram_manual_syn -cd distributed_ram_manual_syn # Constrain all select calls below inside the top module -select -assert-count 1 t:RAMB18E1 diff --git a/tests/arch/xilinx/attributes_test.ys b/tests/arch/xilinx/attributes_test.ys new file mode 100644 index 000000000..4c881b280 --- /dev/null +++ b/tests/arch/xilinx/attributes_test.ys @@ -0,0 +1,47 @@ +# Check that blockram memory without parameters is not modified +read_verilog ../common/memory_attributes/attributes_test.v +hierarchy -top block_ram +synth_xilinx -top block_ram +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 + +# Check that distributed memory without parameters is not modified +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +hierarchy -top distributed_ram +synth_xilinx -top distributed_ram +cd distributed_ram # Constrain all select calls below inside the top module +select -assert-count 8 t:RAM32X1D + +# Set ram_style distributed to blockram memory; will be implemented as distributed +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +prep +setattr -mod -set ram_style "distributed" block_ram +synth_xilinx -top block_ram +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 32 t:RAM128X1D + +# Set synthesis, logic_block to blockram memory; will be implemented as distributed +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +prep +setattr -mod -set logic_block 1 block_ram +synth_xilinx -top block_ram +cd block_ram # Constrain all select calls below inside the top module +select -assert-count 0 t:RAMB18E1 +select -assert-count 32 t:RAM128X1D + +# Set ram_style block to a distributed memory; will be implemented as blockram +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +synth_xilinx -top distributed_ram_manual +cd distributed_ram_manual # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 + +# Set synthesis, ram_block block to a distributed memory; will be implemented as blockram +design -reset +read_verilog ../common/memory_attributes/attributes_test.v +synth_xilinx -top distributed_ram_manual_syn +cd distributed_ram_manual_syn # Constrain all select calls below inside the top module +select -assert-count 1 t:RAMB18E1 -- cgit v1.2.3 From e990c013c57da8149dbbd2fe2633e953ec8f471b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 16 Dec 2019 13:01:51 -0800 Subject: Merge blockram tests --- tests/arch/common/blockram.v | 45 ++++++++++++++++++++ tests/arch/common/blockram_params.v | 45 -------------------- tests/arch/xilinx/blockram.ys | 81 ++++++++++++++++++++++++++++++++++++ tests/arch/xilinx/blockram_params.ys | 47 --------------------- 4 files changed, 126 insertions(+), 92 deletions(-) create mode 100644 tests/arch/common/blockram.v delete mode 100644 tests/arch/common/blockram_params.v create mode 100644 tests/arch/xilinx/blockram.ys delete mode 100644 tests/arch/xilinx/blockram_params.ys (limited to 'tests') diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v new file mode 100644 index 000000000..dbc6ca65c --- /dev/null +++ b/tests/arch/common/blockram.v @@ -0,0 +1,45 @@ +`default_nettype none +module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) + (input wire write_enable, clk, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in] <= data_in; + data_out_r <= memory[address_in]; + end + + assign data_out = data_out_r; +endmodule // sync_ram_sp + + +`default_nettype none +module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) + (input wire clk, write_enable, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in_r, address_in_w, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in_w] <= data_in; + data_out_r <= memory[address_in_r]; + end + + assign data_out = data_out_r; +endmodule // sync_ram_sdp + diff --git a/tests/arch/common/blockram_params.v b/tests/arch/common/blockram_params.v deleted file mode 100644 index dbc6ca65c..000000000 --- a/tests/arch/common/blockram_params.v +++ /dev/null @@ -1,45 +0,0 @@ -`default_nettype none -module sync_ram_sp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) - (input wire write_enable, clk, - input wire [DATA_WIDTH-1:0] data_in, - input wire [ADDRESS_WIDTH-1:0] address_in, - output wire [DATA_WIDTH-1:0] data_out); - - localparam WORD = (DATA_WIDTH-1); - localparam DEPTH = (2**ADDRESS_WIDTH-1); - - reg [WORD:0] data_out_r; - reg [WORD:0] memory [0:DEPTH]; - - always @(posedge clk) begin - if (write_enable) - memory[address_in] <= data_in; - data_out_r <= memory[address_in]; - end - - assign data_out = data_out_r; -endmodule // sync_ram_sp - - -`default_nettype none -module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) - (input wire clk, write_enable, - input wire [DATA_WIDTH-1:0] data_in, - input wire [ADDRESS_WIDTH-1:0] address_in_r, address_in_w, - output wire [DATA_WIDTH-1:0] data_out); - - localparam WORD = (DATA_WIDTH-1); - localparam DEPTH = (2**ADDRESS_WIDTH-1); - - reg [WORD:0] data_out_r; - reg [WORD:0] memory [0:DEPTH]; - - always @(posedge clk) begin - if (write_enable) - memory[address_in_w] <= data_in; - data_out_r <= memory[address_in_r]; - end - - assign data_out = data_out_r; -endmodule // sync_ram_sdp - diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys new file mode 100644 index 000000000..362d33229 --- /dev/null +++ b/tests/arch/xilinx/blockram.ys @@ -0,0 +1,81 @@ +### TODO: Not running equivalence checking because BRAM models does not exists +### currently. Checking instance counts instead. +## Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 +#read_verilog ../common/blockram.v +#chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp +#synth_xilinx -top sync_ram_sdp +#cd sync_ram_sdp +#select -assert-count 1 t:RAMB18E1 +# +#design -reset +#read_verilog ../common/blockram.v +#chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp +#synth_xilinx -top sync_ram_sdp +#cd sync_ram_sdp +#select -assert-count 1 t:RAMB18E1 +# +#design -reset +#read_verilog ../common/blockram.v +#chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp +#synth_xilinx -top sync_ram_sdp +#cd sync_ram_sdp +#select -assert-count 1 t:RAMB18E1 +# +#design -reset +#read_verilog ../common/blockram.v +#chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp +#synth_xilinx -top sync_ram_sdp +#cd sync_ram_sdp +#select -assert-count 1 t:RAMB18E1 +# +## Anything memory bits < 1024 -> LUTRAM +#design -reset +#read_verilog ../common/blockram.v +#chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp +#synth_xilinx -top sync_ram_sdp +#cd sync_ram_sdp +#select -assert-count 0 t:RAMB18E1 +#select -assert-count 4 t:RAM128X1D +# +## More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 +#design -reset +#read_verilog ../common/blockram.v +#chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp +#synth_xilinx -top sync_ram_sdp +#cd sync_ram_sdp +#select -assert-count 1 t:RAMB36E1 +# +# +#### With parameters + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 +setattr -set ram_style "block" m:memory +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 +setattr -set ram_block 1 m:memory +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 +setattr -set ram_style "dont_infer_a_ram_pretty_please" m:memory +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 0 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 +setattr -set logic_block 1 m:memory +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 0 t:RAMB18E1 diff --git a/tests/arch/xilinx/blockram_params.ys b/tests/arch/xilinx/blockram_params.ys deleted file mode 100644 index 27a94834e..000000000 --- a/tests/arch/xilinx/blockram_params.ys +++ /dev/null @@ -1,47 +0,0 @@ -## TODO: Not running equivalence checking because BRAM models does not exists -## currently. Checking instance counts instead. -# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 -read_verilog ../common/blockram_params.v -chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 - -design -reset -read_verilog ../common/blockram_params.v -chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 - -design -reset -read_verilog ../common/blockram_params.v -chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 - -design -reset -read_verilog ../common/blockram_params.v -chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB18E1 - -# Anything memory bits < 1024 -> LUTRAM -design -reset -read_verilog ../common/blockram_params.v -chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 0 t:RAMB18E1 -select -assert-count 4 t:RAM128X1D - -# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 -design -reset -read_verilog ../common/blockram_params.v -chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp -synth_xilinx -top sync_ram_sdp -cd sync_ram_sdp -select -assert-count 1 t:RAMB36E1 - -- cgit v1.2.3 From 5a00d5578cea91ce84f3d95e6138c85d1a949b89 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 16 Dec 2019 13:31:15 -0800 Subject: Add unconditional match blocks for force RAM --- tests/arch/xilinx/blockram.ys | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'tests') diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys index 362d33229..b6e105854 100644 --- a/tests/arch/xilinx/blockram.ys +++ b/tests/arch/xilinx/blockram.ys @@ -79,3 +79,12 @@ setattr -set logic_block 1 m:memory synth_xilinx -top sync_ram_sdp cd sync_ram_sdp select -assert-count 0 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1 +setattr -set ram_style "block" m:memory +dump m:* +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 -- cgit v1.2.3 From db0003410ff35ab39e3ea408684f600e75c16e78 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 16 Dec 2019 13:31:47 -0800 Subject: Accidentally commented out tests --- tests/arch/xilinx/blockram.ys | 94 +++++++++++++++++++++---------------------- 1 file changed, 47 insertions(+), 47 deletions(-) (limited to 'tests') diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys index b6e105854..4b7716739 100644 --- a/tests/arch/xilinx/blockram.ys +++ b/tests/arch/xilinx/blockram.ys @@ -1,52 +1,52 @@ ### TODO: Not running equivalence checking because BRAM models does not exists ### currently. Checking instance counts instead. -## Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 -#read_verilog ../common/blockram.v -#chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp -#synth_xilinx -top sync_ram_sdp -#cd sync_ram_sdp -#select -assert-count 1 t:RAMB18E1 -# -#design -reset -#read_verilog ../common/blockram.v -#chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp -#synth_xilinx -top sync_ram_sdp -#cd sync_ram_sdp -#select -assert-count 1 t:RAMB18E1 -# -#design -reset -#read_verilog ../common/blockram.v -#chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp -#synth_xilinx -top sync_ram_sdp -#cd sync_ram_sdp -#select -assert-count 1 t:RAMB18E1 -# -#design -reset -#read_verilog ../common/blockram.v -#chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp -#synth_xilinx -top sync_ram_sdp -#cd sync_ram_sdp -#select -assert-count 1 t:RAMB18E1 -# -## Anything memory bits < 1024 -> LUTRAM -#design -reset -#read_verilog ../common/blockram.v -#chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp -#synth_xilinx -top sync_ram_sdp -#cd sync_ram_sdp -#select -assert-count 0 t:RAMB18E1 -#select -assert-count 4 t:RAM128X1D -# -## More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 -#design -reset -#read_verilog ../common/blockram.v -#chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp -#synth_xilinx -top sync_ram_sdp -#cd sync_ram_sdp -#select -assert-count 1 t:RAMB36E1 -# -# -#### With parameters +# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +# Anything memory bits < 1024 -> LUTRAM +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 0 t:RAMB18E1 +select -assert-count 4 t:RAM128X1D + +# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1 +design -reset +read_verilog ../common/blockram.v +chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB36E1 + + +### With parameters design -reset read_verilog ../common/blockram.v -- cgit v1.2.3 From 378d9e6e0c16e13cf161aec283ab366e2462745c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 16 Dec 2019 13:57:55 -0800 Subject: Add another test --- tests/arch/xilinx/blockram.ys | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys index 4b7716739..bb908cbbf 100644 --- a/tests/arch/xilinx/blockram.ys +++ b/tests/arch/xilinx/blockram.ys @@ -84,7 +84,14 @@ design -reset read_verilog ../common/blockram.v hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1 setattr -set ram_style "block" m:memory -dump m:* +synth_xilinx -top sync_ram_sdp +cd sync_ram_sdp +select -assert-count 1 t:RAMB18E1 + +design -reset +read_verilog ../common/blockram.v +hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1 +setattr -set ram_block 1 m:memory synth_xilinx -top sync_ram_sdp cd sync_ram_sdp select -assert-count 1 t:RAMB18E1 -- cgit v1.2.3 From aed67dd020575a393b21a65baebcce1d1f49d22a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 16 Dec 2019 18:41:56 -0800 Subject: abc9 needs a clean afterwards --- tests/simple_abc9/run-test.sh | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index 0d4262005..bc921daa9 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -20,10 +20,12 @@ fi cp ../simple/*.v . cp ../simple/*.sv . DOLLAR='?' -exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-n 300 -p '\ +exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v *.sv EXTRA_FLAGS="-n 300 -p '\ hierarchy; \ synth -run coarse; \ opt -full; \ - techmap; abc9 -lut 4 -box ../abc.box; \ + techmap; \ + abc9 -lut 4 -box ../abc.box; \ + clean; \ check -assert; \ select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'" -- cgit v1.2.3 From aff6ad1ce09264fb7fbf43a7456a746a586bea90 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Thu, 21 Nov 2019 06:30:06 +0100 Subject: xilinx: Improve flip-flop handling. This adds support for infering more kinds of flip-flops: - FFs with async set/reset and clock enable - FFs with sync set/reset - FFs with sync set/reset and clock enable Some passes have been moved (and some added) in order for dff2dffs to work correctly. This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop capabilities (though not latch capabilities). Older FPGAs also support having both a set and a reset input, which will be handled at a later data. --- tests/arch/xilinx/adffs.ys | 9 ++++----- tests/arch/xilinx/fsm.ys | 11 ++++++----- tests/arch/xilinx/macc.ys | 3 ++- 3 files changed, 12 insertions(+), 11 deletions(-) (limited to 'tests') diff --git a/tests/arch/xilinx/adffs.ys b/tests/arch/xilinx/adffs.ys index e73bfe0b9..c0ff6a2e2 100644 --- a/tests/arch/xilinx/adffs.ys +++ b/tests/arch/xilinx/adffs.ys @@ -32,10 +32,9 @@ equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivale design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG -select -assert-count 1 t:FDRE -select -assert-count 1 t:LUT2 +select -assert-count 1 t:FDSE -select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D +select -assert-none t:BUFG t:FDSE %% t:* %D design -load read @@ -46,6 +45,6 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE_1 -select -assert-count 1 t:LUT2 +select -assert-count 1 t:INV -select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D +select -assert-none t:BUFG t:FDRE_1 t:INV %% t:* %D diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys index 2a72c34e8..4545cf6d7 100644 --- a/tests/arch/xilinx/fsm.ys +++ b/tests/arch/xilinx/fsm.ys @@ -11,8 +11,9 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd fsm # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG -select -assert-count 5 t:FDRE -select -assert-count 1 t:LUT3 -select -assert-count 2 t:LUT4 -select -assert-count 4 t:LUT6 -select -assert-none t:BUFG t:FDRE t:LUT3 t:LUT4 t:LUT6 %% t:* %D +select -assert-count 4 t:FDRE +select -assert-count 1 t:FDSE +select -assert-count 1 t:LUT2 +select -assert-count 2 t:LUT3 +select -assert-count 4 t:LUT5 +select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT3 t:LUT5 %% t:* %D diff --git a/tests/arch/xilinx/macc.ys b/tests/arch/xilinx/macc.ys index 6e884b35a..11e959976 100644 --- a/tests/arch/xilinx/macc.ys +++ b/tests/arch/xilinx/macc.ys @@ -23,9 +23,10 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd macc2 # Constrain all select calls below inside the top module + select -assert-count 1 t:BUFG select -assert-count 1 t:DSP48E1 select -assert-count 1 t:FDRE select -assert-count 1 t:LUT2 -select -assert-count 41 t:LUT3 +select -assert-count 40 t:LUT3 select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 %% t:* %D -- cgit v1.2.3 From a2352504031ee69efd0aac214fc947737303eb5e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Wed, 18 Dec 2019 13:42:26 +0100 Subject: xilinx: Add xilinx_dffopt pass (#1557) --- tests/arch/xilinx/fsm.ys | 6 +- tests/arch/xilinx/xilinx_dffopt.ys | 216 ++++++++++++++++++++++++++ tests/arch/xilinx/xilinx_dffopt_blacklist.txt | 13 ++ 3 files changed, 232 insertions(+), 3 deletions(-) create mode 100644 tests/arch/xilinx/xilinx_dffopt.ys create mode 100644 tests/arch/xilinx/xilinx_dffopt_blacklist.txt (limited to 'tests') diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys index 4545cf6d7..f03400fe7 100644 --- a/tests/arch/xilinx/fsm.ys +++ b/tests/arch/xilinx/fsm.ys @@ -14,6 +14,6 @@ select -assert-count 1 t:BUFG select -assert-count 4 t:FDRE select -assert-count 1 t:FDSE select -assert-count 1 t:LUT2 -select -assert-count 2 t:LUT3 -select -assert-count 4 t:LUT5 -select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT3 t:LUT5 %% t:* %D +select -assert-count 3 t:LUT5 +select -assert-count 1 t:LUT6 +select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D diff --git a/tests/arch/xilinx/xilinx_dffopt.ys b/tests/arch/xilinx/xilinx_dffopt.ys new file mode 100644 index 000000000..dc036acfd --- /dev/null +++ b/tests/arch/xilinx/xilinx_dffopt.ys @@ -0,0 +1,216 @@ +read_verilog << EOT + +// FDRE, mergeable CE and R. + +module t0 (...); +input wire clk; +input wire [7:0] i; +output wire [7:0] o; + +wire [7:0] tmp ; + +LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0])); +LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1])); +LUT2 #(.INIT(4'h6)) lut2 (.I0(i[3]), .I1(i[4]), .O(tmp[2])); + +FDRE ff (.D(tmp[0]), .CE(tmp[1]), .R(tmp[2]), .Q(o[0])); + +endmodule + +EOT + +design -save t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt +design -load postopt +clean + +select -assert-count 1 t:FDRE +select -assert-count 1 t:LUT6 +select -assert-count 3 t:LUT2 +select -assert-none t:FDRE t:LUT6 t:LUT2 %% t:* %D + +design -load t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4 +design -load postopt +clean + +select -assert-count 1 t:FDRE +select -assert-count 1 t:LUT4 +select -assert-count 3 t:LUT2 +select -assert-none t:FDRE t:LUT4 t:LUT2 %% t:* %D + +design -reset + + +read_verilog << EOT + +// FDSE, mergeable CE and S, inversions. + +module t0 (...); +input wire clk; +input wire [7:0] i; +output wire [7:0] o; + +wire [7:0] tmp ; + +LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0])); +LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1])); +LUT2 #(.INIT(4'h6)) lut2 (.I0(i[3]), .I1(i[4]), .O(tmp[2])); + +FDSE #(.IS_D_INVERTED(1'b1), .IS_S_INVERTED(1'b1)) ff (.D(tmp[0]), .CE(tmp[1]), .S(tmp[2]), .Q(o[0])); + +endmodule + +EOT + +design -save t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt +design -load postopt +clean + +select -assert-count 1 t:FDSE +select -assert-count 1 t:LUT6 +select -assert-count 3 t:LUT2 +select -assert-none t:FDSE t:LUT6 t:LUT2 %% t:* %D + +design -load t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4 +design -load postopt +clean + +select -assert-count 1 t:FDSE +select -assert-count 1 t:LUT4 +select -assert-count 3 t:LUT2 +select -assert-none t:FDSE t:LUT4 t:LUT2 %% t:* %D + +design -reset + + +read_verilog << EOT + +// FDCE, mergeable CE. + +module t0 (...); +input wire clk; +input wire [7:0] i; +output wire [7:0] o; + +wire [7:0] tmp ; + +LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0])); +LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1])); +LUT2 #(.INIT(4'h6)) lut2 (.I0(i[3]), .I1(i[4]), .O(tmp[2])); + +FDCE ff (.D(tmp[0]), .CE(tmp[1]), .CLR(tmp[2]), .Q(o[0])); + +endmodule + +EOT + +design -save t0 + +equiv_opt -async2sync -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt +design -load postopt +clean + +select -assert-count 1 t:FDCE +select -assert-count 1 t:LUT4 +select -assert-count 3 t:LUT2 +select -assert-none t:FDCE t:LUT4 t:LUT2 %% t:* %D + +design -reset + + +read_verilog << EOT + +// FDSE, mergeable CE and S, but CE only not worth it. + +module t0 (...); +input wire clk; +input wire [7:0] i; +output wire [7:0] o; + +wire [7:0] tmp ; + +LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0])); +LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1])); + +FDSE ff (.D(tmp[0]), .CE(i[7]), .S(tmp[1]), .Q(o[0])); + +endmodule + +EOT + +design -save t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt +design -load postopt +clean + +select -assert-count 1 t:FDSE +select -assert-count 1 t:LUT5 +select -assert-count 2 t:LUT2 +select -assert-none t:FDSE t:LUT5 t:LUT2 %% t:* %D + +design -load t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4 +design -load postopt +clean + +select -assert-count 1 t:FDSE +select -assert-count 2 t:LUT2 +select -assert-none t:FDSE t:LUT2 %% t:* %D + +design -reset + + +read_verilog << EOT + +// FDRSE, mergeable CE, S, R. + +module t0 (...); +input wire clk; +input wire [7:0] i; +output wire [7:0] o; + +wire [7:0] tmp ; + +LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0])); +LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1])); +LUT2 #(.INIT(4'h8)) lut2 (.I0(i[2]), .I1(i[0]), .O(tmp[2])); +LUT2 #(.INIT(4'h6)) lut3 (.I0(i[3]), .I1(i[4]), .O(tmp[3])); + +FDRSE ff (.D(tmp[0]), .CE(tmp[1]), .S(tmp[2]), .R(tmp[3]), .Q(o[0])); + +endmodule + +EOT + +design -save t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt +design -load postopt +clean + +select -assert-count 1 t:FDRSE +select -assert-count 1 t:LUT6 +select -assert-count 4 t:LUT2 +select -assert-none t:FDRSE t:LUT6 t:LUT2 %% t:* %D + +design -load t0 + +equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4 +design -load postopt +clean + +select -assert-count 1 t:FDRSE +select -assert-count 1 t:LUT4 +select -assert-count 4 t:LUT2 +select -assert-none t:FDRSE t:LUT4 t:LUT2 %% t:* %D + +design -reset diff --git a/tests/arch/xilinx/xilinx_dffopt_blacklist.txt b/tests/arch/xilinx/xilinx_dffopt_blacklist.txt new file mode 100644 index 000000000..6a31a0cd3 --- /dev/null +++ b/tests/arch/xilinx/xilinx_dffopt_blacklist.txt @@ -0,0 +1,13 @@ +lut0 +lut1 +lut2 +lut3 +ff +ff.D +ff.R +ff.S +ff.CE +ff.d +ff.r +ff.s +ff.ce -- cgit v1.2.3 From f382164d6ed4e6fd6820322db5becf081a74f272 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Wed, 18 Dec 2019 15:53:20 +0100 Subject: tests/xilinx: fix flaky mux test --- tests/arch/xilinx/mux.ys | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys index 821d0fab7..388272449 100644 --- a/tests/arch/xilinx/mux.ys +++ b/tests/arch/xilinx/mux.ys @@ -40,6 +40,8 @@ proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 5 t:LUT6 +select -assert-min 5 t:LUT6 +select -assert-max 7 t:LUT6 +select -assert-max 2 t:MUXF7 -select -assert-none t:LUT6 %% t:* %D +select -assert-none t:LUT6 t:MUXF7 %% t:* %D -- cgit v1.2.3 From 477e43d921d204c6bc6403109fea6506802c948c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 21 Dec 2019 13:18:44 +0100 Subject: Fix xilinx tests, when iopads are default --- tests/arch/xilinx/add_sub.ys | 2 +- tests/arch/xilinx/adffs.ys | 8 ++++---- tests/arch/xilinx/bug1460.ys | 2 +- tests/arch/xilinx/counter.ys | 2 +- tests/arch/xilinx/dffs.ys | 4 ++-- tests/arch/xilinx/dsp_fastfir.ys | 2 +- tests/arch/xilinx/fsm.ys | 2 +- tests/arch/xilinx/latches.ys | 6 +++--- tests/arch/xilinx/logic.ys | 2 +- tests/arch/xilinx/lutram.ys | 14 +++++++------- tests/arch/xilinx/macc.ys | 4 ++-- tests/arch/xilinx/mul.ys | 2 +- tests/arch/xilinx/mul_unsigned.ys | 2 +- tests/arch/xilinx/mux.ys | 8 ++++---- tests/arch/xilinx/shifter.ys | 2 +- tests/arch/xilinx/tribuf.ys | 6 ++++-- tests/arch/xilinx/xilinx_dffopt.ys | 18 +++++++++--------- 17 files changed, 44 insertions(+), 42 deletions(-) (limited to 'tests') diff --git a/tests/arch/xilinx/add_sub.ys b/tests/arch/xilinx/add_sub.ys index 9dbddce47..920717a3d 100644 --- a/tests/arch/xilinx/add_sub.ys +++ b/tests/arch/xilinx/add_sub.ys @@ -7,5 +7,5 @@ cd top # Constrain all select calls below inside the top module select -assert-count 14 t:LUT2 select -assert-count 6 t:MUXCY select -assert-count 8 t:XORCY -select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D +select -assert-none t:LUT2 t:MUXCY t:XORCY t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/xilinx/adffs.ys b/tests/arch/xilinx/adffs.ys index c0ff6a2e2..ba9ddf90f 100644 --- a/tests/arch/xilinx/adffs.ys +++ b/tests/arch/xilinx/adffs.ys @@ -9,7 +9,7 @@ cd adff # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDCE -select -assert-none t:BUFG t:FDCE %% t:* %D +select -assert-none t:BUFG t:FDCE t:IBUF t:OBUF %% t:* %D design -load read @@ -22,7 +22,7 @@ select -assert-count 1 t:BUFG select -assert-count 1 t:FDCE select -assert-count 1 t:INV -select -assert-none t:BUFG t:FDCE t:INV %% t:* %D +select -assert-none t:BUFG t:FDCE t:INV t:IBUF t:OBUF %% t:* %D design -load read @@ -34,7 +34,7 @@ cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDSE -select -assert-none t:BUFG t:FDSE %% t:* %D +select -assert-none t:BUFG t:FDSE t:IBUF t:OBUF %% t:* %D design -load read @@ -47,4 +47,4 @@ select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE_1 select -assert-count 1 t:INV -select -assert-none t:BUFG t:FDRE_1 t:INV %% t:* %D +select -assert-none t:BUFG t:FDRE_1 t:INV t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/xilinx/bug1460.ys b/tests/arch/xilinx/bug1460.ys index 2018071cc..73fb662dc 100644 --- a/tests/arch/xilinx/bug1460.ys +++ b/tests/arch/xilinx/bug1460.ys @@ -31,4 +31,4 @@ EOT synth_xilinx cd register_file select -assert-count 32 t:RAM32M -select -assert-none t:* t:BUFG %d t:RAM32M %d +select -assert-none t:* t:BUFG %d t:IBUF %d t:OBUF %d t:RAM32M %d diff --git a/tests/arch/xilinx/counter.ys b/tests/arch/xilinx/counter.ys index 604acdbfc..e4217bbaf 100644 --- a/tests/arch/xilinx/counter.ys +++ b/tests/arch/xilinx/counter.ys @@ -11,4 +11,4 @@ select -assert-count 8 t:FDCE select -assert-count 1 t:INV select -assert-count 7 t:MUXCY select -assert-count 8 t:XORCY -select -assert-none t:BUFG t:FDCE t:INV t:MUXCY t:XORCY %% t:* %D +select -assert-none t:BUFG t:FDCE t:INV t:MUXCY t:XORCY t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/xilinx/dffs.ys b/tests/arch/xilinx/dffs.ys index 0bba4858f..b2cb70323 100644 --- a/tests/arch/xilinx/dffs.ys +++ b/tests/arch/xilinx/dffs.ys @@ -9,7 +9,7 @@ cd dff # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE -select -assert-none t:BUFG t:FDRE %% t:* %D +select -assert-none t:BUFG t:FDRE t:IBUF t:OBUF %% t:* %D design -load read @@ -21,5 +21,5 @@ cd dffe # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE -select -assert-none t:BUFG t:FDRE %% t:* %D +select -assert-none t:BUFG t:FDRE t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/xilinx/dsp_fastfir.ys b/tests/arch/xilinx/dsp_fastfir.ys index 0067a822b..05e1785d8 100644 --- a/tests/arch/xilinx/dsp_fastfir.ys +++ b/tests/arch/xilinx/dsp_fastfir.ys @@ -66,4 +66,4 @@ EOT synth_xilinx cd fastfir_dynamictaps select -assert-count 2 t:DSP48E1 -select -assert-none t:* t:DSP48E1 %d t:BUFG %d +select -assert-none t:* t:DSP48E1 %d t:BUFG %d t:IBUF %d t:OBUF %d diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys index f03400fe7..d60695e2c 100644 --- a/tests/arch/xilinx/fsm.ys +++ b/tests/arch/xilinx/fsm.ys @@ -16,4 +16,4 @@ select -assert-count 1 t:FDSE select -assert-count 1 t:LUT2 select -assert-count 3 t:LUT5 select -assert-count 1 t:LUT6 -select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D +select -assert-none t:BUFG t:IBUF t:OBUF t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D diff --git a/tests/arch/xilinx/latches.ys b/tests/arch/xilinx/latches.ys index c87a8e38b..c1caea27a 100644 --- a/tests/arch/xilinx/latches.ys +++ b/tests/arch/xilinx/latches.ys @@ -8,7 +8,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd latchp # Constrain all select calls below inside the top module select -assert-count 1 t:LDCE -select -assert-none t:LDCE %% t:* %D +select -assert-none t:LDCE t:IBUF t:OBUF %% t:* %D design -load read @@ -20,7 +20,7 @@ cd latchn # Constrain all select calls below inside the top module select -assert-count 1 t:LDCE select -assert-count 1 t:INV -select -assert-none t:LDCE t:INV %% t:* %D +select -assert-none t:LDCE t:INV t:IBUF t:OBUF %% t:* %D design -load read @@ -32,4 +32,4 @@ cd latchsr # Constrain all select calls below inside the top module select -assert-count 1 t:LDCE select -assert-count 2 t:LUT3 -select -assert-none t:LDCE t:LUT3 %% t:* %D +select -assert-none t:LDCE t:LUT3 t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/xilinx/logic.ys b/tests/arch/xilinx/logic.ys index d5b5c1a37..2372cca61 100644 --- a/tests/arch/xilinx/logic.ys +++ b/tests/arch/xilinx/logic.ys @@ -8,4 +8,4 @@ cd top # Constrain all select calls below inside the top module select -assert-count 1 t:INV select -assert-count 6 t:LUT2 select -assert-count 2 t:LUT4 -select -assert-none t:INV t:LUT2 t:LUT4 %% t:* %D +select -assert-none t:INV t:LUT2 t:LUT4 t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys index 6c9d1eae1..951517fa9 100644 --- a/tests/arch/xilinx/lutram.ys +++ b/tests/arch/xilinx/lutram.ys @@ -14,7 +14,7 @@ #select -assert-count 1 t:BUFG #select -assert-count 8 t:FDRE #select -assert-count 8 t:RAM16X1D -#select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D +#select -assert-none t:BUFG t:FDRE t:RAM16X1D t:IBUF t:OBUF %% t:* %D design -reset @@ -34,7 +34,7 @@ cd lutram_1w1r select -assert-count 1 t:BUFG select -assert-count 8 t:FDRE select -assert-count 8 t:RAM32X1D -select -assert-none t:BUFG t:FDRE t:RAM32X1D %% t:* %D +select -assert-none t:BUFG t:FDRE t:RAM32X1D t:IBUF t:OBUF %% t:* %D design -reset @@ -54,7 +54,7 @@ cd lutram_1w1r select -assert-count 1 t:BUFG select -assert-count 8 t:FDRE select -assert-count 8 t:RAM64X1D -select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D +select -assert-none t:BUFG t:FDRE t:RAM64X1D t:IBUF t:OBUF %% t:* %D design -reset @@ -74,7 +74,7 @@ cd lutram_1w3r select -assert-count 1 t:BUFG select -assert-count 24 t:FDRE select -assert-count 4 t:RAM32M -select -assert-none t:BUFG t:FDRE t:RAM32M %% t:* %D +select -assert-none t:BUFG t:FDRE t:RAM32M t:IBUF t:OBUF %% t:* %D design -reset @@ -94,7 +94,7 @@ cd lutram_1w3r select -assert-count 1 t:BUFG select -assert-count 24 t:FDRE select -assert-count 8 t:RAM64M -select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D +select -assert-none t:BUFG t:FDRE t:RAM64M t:IBUF t:OBUF %% t:* %D design -reset @@ -114,7 +114,7 @@ cd lutram_1w1r select -assert-count 1 t:BUFG select -assert-count 6 t:FDRE select -assert-count 1 t:RAM32M -select -assert-none t:BUFG t:FDRE t:RAM32M %% t:* %D +select -assert-none t:BUFG t:FDRE t:RAM32M t:IBUF t:OBUF %% t:* %D design -reset @@ -134,4 +134,4 @@ cd lutram_1w1r select -assert-count 1 t:BUFG select -assert-count 6 t:FDRE select -assert-count 2 t:RAM64M -select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D +select -assert-none t:BUFG t:FDRE t:RAM64M t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/xilinx/macc.ys b/tests/arch/xilinx/macc.ys index 11e959976..0869a8dae 100644 --- a/tests/arch/xilinx/macc.ys +++ b/tests/arch/xilinx/macc.ys @@ -12,7 +12,7 @@ cd macc # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE select -assert-count 1 t:DSP48E1 -select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D +select -assert-none t:BUFG t:FDRE t:DSP48E1 t:IBUF t:OBUF %% t:* %D design -load read hierarchy -top macc2 @@ -29,4 +29,4 @@ select -assert-count 1 t:DSP48E1 select -assert-count 1 t:FDRE select -assert-count 1 t:LUT2 select -assert-count 40 t:LUT3 -select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 %% t:* %D +select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/xilinx/mul.ys b/tests/arch/xilinx/mul.ys index d76814966..100de6629 100644 --- a/tests/arch/xilinx/mul.ys +++ b/tests/arch/xilinx/mul.ys @@ -6,4 +6,4 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd top # Constrain all select calls below inside the top module select -assert-count 1 t:DSP48E1 -select -assert-none t:DSP48E1 %% t:* %D +select -assert-none t:DSP48E1 t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/xilinx/mul_unsigned.ys b/tests/arch/xilinx/mul_unsigned.ys index 62495b90c..59ead5cda 100644 --- a/tests/arch/xilinx/mul_unsigned.ys +++ b/tests/arch/xilinx/mul_unsigned.ys @@ -8,4 +8,4 @@ cd mul_unsigned # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:DSP48E1 select -assert-count 30 t:FDRE -select -assert-none t:DSP48E1 t:FDRE t:BUFG %% t:* %D +select -assert-none t:DSP48E1 t:FDRE t:BUFG t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys index 388272449..faad64cc5 100644 --- a/tests/arch/xilinx/mux.ys +++ b/tests/arch/xilinx/mux.ys @@ -8,7 +8,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd mux2 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT3 -select -assert-none t:LUT3 %% t:* %D +select -assert-none t:LUT3 t:IBUF t:OBUF %% t:* %D design -load read @@ -19,7 +19,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd mux4 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT6 -select -assert-none t:LUT6 %% t:* %D +select -assert-none t:LUT6 t:IBUF t:OBUF %% t:* %D design -load read @@ -31,7 +31,7 @@ cd mux8 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT3 select -assert-count 2 t:LUT6 -select -assert-none t:LUT3 t:LUT6 %% t:* %D +select -assert-none t:LUT3 t:LUT6 t:IBUF t:OBUF %% t:* %D design -load read @@ -44,4 +44,4 @@ select -assert-min 5 t:LUT6 select -assert-max 7 t:LUT6 select -assert-max 2 t:MUXF7 -select -assert-none t:LUT6 t:MUXF7 %% t:* %D +select -assert-none t:LUT6 t:MUXF7 t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/xilinx/shifter.ys b/tests/arch/xilinx/shifter.ys index 455437f18..4d63ba9c2 100644 --- a/tests/arch/xilinx/shifter.ys +++ b/tests/arch/xilinx/shifter.ys @@ -8,4 +8,4 @@ cd top # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 8 t:FDRE -select -assert-none t:BUFG t:FDRE %% t:* %D +select -assert-none t:BUFG t:FDRE t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/xilinx/tribuf.ys b/tests/arch/xilinx/tribuf.ys index 4697703ca..55e20c37b 100644 --- a/tests/arch/xilinx/tribuf.ys +++ b/tests/arch/xilinx/tribuf.ys @@ -8,5 +8,7 @@ equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equ design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd tristate # Constrain all select calls below inside the top module # TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225 -select -assert-count 1 t:$_TBUF_ -select -assert-none t:$_TBUF_ %% t:* %D +select -assert-count 2 t:IBUF +select -assert-count 1 t:INV +select -assert-count 1 t:OBUFT +select -assert-none t:IBUF t:INV t:OBUFT %% t:* %D diff --git a/tests/arch/xilinx/xilinx_dffopt.ys b/tests/arch/xilinx/xilinx_dffopt.ys index dc036acfd..5dbe11b27 100644 --- a/tests/arch/xilinx/xilinx_dffopt.ys +++ b/tests/arch/xilinx/xilinx_dffopt.ys @@ -28,7 +28,7 @@ clean select -assert-count 1 t:FDRE select -assert-count 1 t:LUT6 select -assert-count 3 t:LUT2 -select -assert-none t:FDRE t:LUT6 t:LUT2 %% t:* %D +select -assert-none t:FDRE t:LUT6 t:LUT2 t:IBUF t:OBUF %% t:* %D design -load t0 @@ -39,7 +39,7 @@ clean select -assert-count 1 t:FDRE select -assert-count 1 t:LUT4 select -assert-count 3 t:LUT2 -select -assert-none t:FDRE t:LUT4 t:LUT2 %% t:* %D +select -assert-none t:FDRE t:LUT4 t:LUT2 t:IBUF t:OBUF %% t:* %D design -reset @@ -74,7 +74,7 @@ clean select -assert-count 1 t:FDSE select -assert-count 1 t:LUT6 select -assert-count 3 t:LUT2 -select -assert-none t:FDSE t:LUT6 t:LUT2 %% t:* %D +select -assert-none t:FDSE t:LUT6 t:LUT2 t:IBUF t:OBUF %% t:* %D design -load t0 @@ -85,7 +85,7 @@ clean select -assert-count 1 t:FDSE select -assert-count 1 t:LUT4 select -assert-count 3 t:LUT2 -select -assert-none t:FDSE t:LUT4 t:LUT2 %% t:* %D +select -assert-none t:FDSE t:LUT4 t:LUT2 t:IBUF t:OBUF %% t:* %D design -reset @@ -120,7 +120,7 @@ clean select -assert-count 1 t:FDCE select -assert-count 1 t:LUT4 select -assert-count 3 t:LUT2 -select -assert-none t:FDCE t:LUT4 t:LUT2 %% t:* %D +select -assert-none t:FDCE t:LUT4 t:LUT2 t:IBUF t:OBUF %% t:* %D design -reset @@ -154,7 +154,7 @@ clean select -assert-count 1 t:FDSE select -assert-count 1 t:LUT5 select -assert-count 2 t:LUT2 -select -assert-none t:FDSE t:LUT5 t:LUT2 %% t:* %D +select -assert-none t:FDSE t:LUT5 t:LUT2 t:IBUF t:OBUF %% t:* %D design -load t0 @@ -164,7 +164,7 @@ clean select -assert-count 1 t:FDSE select -assert-count 2 t:LUT2 -select -assert-none t:FDSE t:LUT2 %% t:* %D +select -assert-none t:FDSE t:LUT2 t:IBUF t:OBUF %% t:* %D design -reset @@ -200,7 +200,7 @@ clean select -assert-count 1 t:FDRSE select -assert-count 1 t:LUT6 select -assert-count 4 t:LUT2 -select -assert-none t:FDRSE t:LUT6 t:LUT2 %% t:* %D +select -assert-none t:FDRSE t:LUT6 t:LUT2 t:IBUF t:OBUF %% t:* %D design -load t0 @@ -211,6 +211,6 @@ clean select -assert-count 1 t:FDRSE select -assert-count 1 t:LUT4 select -assert-count 4 t:LUT2 -select -assert-none t:FDRSE t:LUT4 t:LUT2 %% t:* %D +select -assert-none t:FDRSE t:LUT4 t:LUT2 t:IBUF t:OBUF %% t:* %D design -reset -- cgit v1.2.3 From 436fea9e6990c66369d7c30b571920ae115efb44 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 21 Dec 2019 20:23:23 +0100 Subject: Addressed review comments --- tests/arch/xilinx/tribuf.ys | 1 - 1 file changed, 1 deletion(-) (limited to 'tests') diff --git a/tests/arch/xilinx/tribuf.ys b/tests/arch/xilinx/tribuf.ys index 55e20c37b..eaccab126 100644 --- a/tests/arch/xilinx/tribuf.ys +++ b/tests/arch/xilinx/tribuf.ys @@ -7,7 +7,6 @@ synth equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd tristate # Constrain all select calls below inside the top module -# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225 select -assert-count 2 t:IBUF select -assert-count 1 t:INV select -assert-count 1 t:OBUFT -- cgit v1.2.3 From 666c6128a90de588ab26c876a257ea48edfded30 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Sun, 22 Dec 2019 20:43:39 +0100 Subject: xilinx_dsp: Initial DSP48A/DSP48A1 support. --- tests/arch/xilinx/macc.sh | 3 +++ tests/arch/xilinx/mul.ys | 12 ++++++++++++ tests/arch/xilinx/mul_unsigned.ys | 14 ++++++++++++++ 3 files changed, 29 insertions(+) (limited to 'tests') diff --git a/tests/arch/xilinx/macc.sh b/tests/arch/xilinx/macc.sh index 154a29848..58b97b646 100644 --- a/tests/arch/xilinx/macc.sh +++ b/tests/arch/xilinx/macc.sh @@ -1,3 +1,6 @@ ../../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v vvp -N ./test_macc +../../../yosys -qp "synth_xilinx -family xc6s -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v +iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v +vvp -N ./test_macc diff --git a/tests/arch/xilinx/mul.ys b/tests/arch/xilinx/mul.ys index d76814966..6cf994fbf 100644 --- a/tests/arch/xilinx/mul.ys +++ b/tests/arch/xilinx/mul.ys @@ -7,3 +7,15 @@ cd top # Constrain all select calls below inside the top module select -assert-count 1 t:DSP48E1 select -assert-none t:DSP48E1 %% t:* %D + +design -reset + +read_verilog ../common/mul.v +hierarchy -top top +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:DSP48A1 +select -assert-none t:DSP48A1 %% t:* %D diff --git a/tests/arch/xilinx/mul_unsigned.ys b/tests/arch/xilinx/mul_unsigned.ys index 62495b90c..c714680af 100644 --- a/tests/arch/xilinx/mul_unsigned.ys +++ b/tests/arch/xilinx/mul_unsigned.ys @@ -9,3 +9,17 @@ select -assert-count 1 t:BUFG select -assert-count 1 t:DSP48E1 select -assert-count 30 t:FDRE select -assert-none t:DSP48E1 t:FDRE t:BUFG %% t:* %D + +design -reset + +read_verilog mul_unsigned.v +hierarchy -top mul_unsigned +proc + +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mul_unsigned # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:DSP48A1 +select -assert-count 30 t:FDRE +select -assert-none t:DSP48A1 t:FDRE t:BUFG %% t:* %D -- cgit v1.2.3 From 2e21aa59a296c666f8e8fa0033efce4504ebd9ba Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 23 Dec 2019 14:58:06 -0800 Subject: Add DSP cascade tests --- tests/arch/xilinx/dsp_cascade.ys | 89 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) create mode 100644 tests/arch/xilinx/dsp_cascade.ys (limited to 'tests') diff --git a/tests/arch/xilinx/dsp_cascade.ys b/tests/arch/xilinx/dsp_cascade.ys new file mode 100644 index 000000000..f9185551b --- /dev/null +++ b/tests/arch/xilinx/dsp_cascade.ys @@ -0,0 +1,89 @@ +design -reset +read_verilog < DSP48E1.PCIN +# (i.e. Take all DSP48E1s, expand to find all wires connected +# to its PCOUT port, then remove all DSP48E1s from this +# selection, then expand again to find all cells where +# those wires are connected to the PCIN port, then remove +# all wires from this selection, and lastly intersect +# this selection with all DSP48E1 cells (to check that +# the connected cells are indeed DSPs) +select -assert-count 2 t:DSP48E1 %co:+[PCOUT] t:DSP48E1 %d %co:+[PCIN] w:* %d t:DSP48E1 %i + +design -load read +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s +design -load postopt +cd cascade +select -assert-count 3 t:DSP48A1 +select -assert-count 5 t:FDRE # No cascade for A input +select -assert-none t:DSP48A1 t:BUFG t:FDRE %% t:* %D +# Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN +# (see above for explanation) +select -assert-count 2 t:DSP48A1 %co:+[PCOUT] t:DSP48A1 %d %co:+[PCIN] w:* %d t:DSP48A1 %i + +design -reset +read_verilog < DSP48E1.PCIN +# (see above for explanation) +select -assert-count 1 t:DSP48E1 %co:+[PCOUT] t:DSP48E1 %d %co:+[PCIN] w:* %d t:DSP48E1 %i + +design -load read +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s +design -load postopt +cd cascade +select -assert-count 2 t:DSP48A1 +select -assert-count 10 t:FDRE # Cannot cascade because first 'm' DSP + # uses both B0REG and B1REG, whereas 'o' + # only requires 1 +select -assert-none t:DSP48A1 t:BUFG t:FDRE %% t:* %D +# Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN +# (see above for explanation) +select -assert-count 1 t:DSP48A1 %co:+[PCOUT] t:DSP48A1 %d %co:+[PCIN] w:* %d t:DSP48A1 %i + -- cgit v1.2.3 From a24596def375bd9edcbeac1b73d7c3ea76244a77 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Sun, 22 Dec 2019 01:08:56 +0100 Subject: iopadmap: Emit tristate buffers with const OE for some edge cases. --- tests/techmap/iopadmap.ys | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'tests') diff --git a/tests/techmap/iopadmap.ys b/tests/techmap/iopadmap.ys index f4345e906..c058d1607 100644 --- a/tests/techmap/iopadmap.ys +++ b/tests/techmap/iopadmap.ys @@ -28,6 +28,20 @@ assign io = oe ? i : 1'bz; assign o2 = io; assign o3 = ~io; endmodule + +module f(output o, o2); +assign o = 1'bz; +endmodule + +module g(inout io, output o); +assign o = io; +endmodule + +module h(inout io, output o, input i); +assign io = i; +assign o = io; +endmodule + EOT opt_clean @@ -97,3 +111,12 @@ select -assert-count 1 @oeb %co %co @iob %i select -assert-count 1 @iob %co %co @o2b %i select -assert-count 1 @iob %co %co t:$_NOT_ %i select -assert-count 1 @o3b %ci %ci t:$_NOT_ %i + +select -assert-count 2 f/t:obuft + +select -assert-count 1 g/t:obuf +select -assert-count 1 g/t:iobuf + +select -assert-count 1 h/t:ibuf +select -assert-count 1 h/t:iobuf +select -assert-count 1 h/t:obuf -- cgit v1.2.3 From d45869855c6fc86dc6a0225018a8e383866dacb4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 27 Dec 2019 16:44:57 -0800 Subject: Add #1598 testcase --- tests/arch/ecp5/bug1598.ys | 16 ++++++++++++++++ tests/arch/ice40/bug1598.ys | 16 ++++++++++++++++ tests/arch/xilinx/bug1598.ys | 16 ++++++++++++++++ 3 files changed, 48 insertions(+) create mode 100644 tests/arch/ecp5/bug1598.ys create mode 100644 tests/arch/ice40/bug1598.ys create mode 100644 tests/arch/xilinx/bug1598.ys (limited to 'tests') diff --git a/tests/arch/ecp5/bug1598.ys b/tests/arch/ecp5/bug1598.ys new file mode 100644 index 000000000..1d1682fcd --- /dev/null +++ b/tests/arch/ecp5/bug1598.ys @@ -0,0 +1,16 @@ +read_verilog < Date: Sat, 28 Dec 2019 02:15:11 -0800 Subject: Update resource count --- tests/arch/ecp5/mux.ys | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/arch/ecp5/mux.ys b/tests/arch/ecp5/mux.ys index 92463aa32..22866832d 100644 --- a/tests/arch/ecp5/mux.ys +++ b/tests/arch/ecp5/mux.ys @@ -39,8 +39,8 @@ proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 8 t:L6MUX21 -select -assert-count 26 t:LUT4 -select -assert-count 12 t:PFUMX +select -assert-count 12 t:L6MUX21 +select -assert-count 34 t:LUT4 +select -assert-count 17 t:PFUMX select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D -- cgit v1.2.3 From 509da7ed1a1e27066451f57868108b473cf516a0 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 28 Dec 2019 16:12:45 +0100 Subject: Revert "Fix xilinx tests, when iopads are default" This reverts commit 477e43d921d204c6bc6403109fea6506802c948c. --- tests/arch/xilinx/add_sub.ys | 2 +- tests/arch/xilinx/adffs.ys | 8 ++++---- tests/arch/xilinx/bug1460.ys | 2 +- tests/arch/xilinx/counter.ys | 2 +- tests/arch/xilinx/dffs.ys | 4 ++-- tests/arch/xilinx/dsp_fastfir.ys | 2 +- tests/arch/xilinx/fsm.ys | 2 +- tests/arch/xilinx/latches.ys | 6 +++--- tests/arch/xilinx/logic.ys | 2 +- tests/arch/xilinx/lutram.ys | 14 +++++++------- tests/arch/xilinx/macc.ys | 4 ++-- tests/arch/xilinx/mul.ys | 2 +- tests/arch/xilinx/mul_unsigned.ys | 2 +- tests/arch/xilinx/mux.ys | 8 ++++---- tests/arch/xilinx/shifter.ys | 2 +- tests/arch/xilinx/xilinx_dffopt.ys | 18 +++++++++--------- 16 files changed, 40 insertions(+), 40 deletions(-) (limited to 'tests') diff --git a/tests/arch/xilinx/add_sub.ys b/tests/arch/xilinx/add_sub.ys index 920717a3d..9dbddce47 100644 --- a/tests/arch/xilinx/add_sub.ys +++ b/tests/arch/xilinx/add_sub.ys @@ -7,5 +7,5 @@ cd top # Constrain all select calls below inside the top module select -assert-count 14 t:LUT2 select -assert-count 6 t:MUXCY select -assert-count 8 t:XORCY -select -assert-none t:LUT2 t:MUXCY t:XORCY t:IBUF t:OBUF %% t:* %D +select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D diff --git a/tests/arch/xilinx/adffs.ys b/tests/arch/xilinx/adffs.ys index ba9ddf90f..c0ff6a2e2 100644 --- a/tests/arch/xilinx/adffs.ys +++ b/tests/arch/xilinx/adffs.ys @@ -9,7 +9,7 @@ cd adff # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDCE -select -assert-none t:BUFG t:FDCE t:IBUF t:OBUF %% t:* %D +select -assert-none t:BUFG t:FDCE %% t:* %D design -load read @@ -22,7 +22,7 @@ select -assert-count 1 t:BUFG select -assert-count 1 t:FDCE select -assert-count 1 t:INV -select -assert-none t:BUFG t:FDCE t:INV t:IBUF t:OBUF %% t:* %D +select -assert-none t:BUFG t:FDCE t:INV %% t:* %D design -load read @@ -34,7 +34,7 @@ cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDSE -select -assert-none t:BUFG t:FDSE t:IBUF t:OBUF %% t:* %D +select -assert-none t:BUFG t:FDSE %% t:* %D design -load read @@ -47,4 +47,4 @@ select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE_1 select -assert-count 1 t:INV -select -assert-none t:BUFG t:FDRE_1 t:INV t:IBUF t:OBUF %% t:* %D +select -assert-none t:BUFG t:FDRE_1 t:INV %% t:* %D diff --git a/tests/arch/xilinx/bug1460.ys b/tests/arch/xilinx/bug1460.ys index 73fb662dc..2018071cc 100644 --- a/tests/arch/xilinx/bug1460.ys +++ b/tests/arch/xilinx/bug1460.ys @@ -31,4 +31,4 @@ EOT synth_xilinx cd register_file select -assert-count 32 t:RAM32M -select -assert-none t:* t:BUFG %d t:IBUF %d t:OBUF %d t:RAM32M %d +select -assert-none t:* t:BUFG %d t:RAM32M %d diff --git a/tests/arch/xilinx/counter.ys b/tests/arch/xilinx/counter.ys index e4217bbaf..604acdbfc 100644 --- a/tests/arch/xilinx/counter.ys +++ b/tests/arch/xilinx/counter.ys @@ -11,4 +11,4 @@ select -assert-count 8 t:FDCE select -assert-count 1 t:INV select -assert-count 7 t:MUXCY select -assert-count 8 t:XORCY -select -assert-none t:BUFG t:FDCE t:INV t:MUXCY t:XORCY t:IBUF t:OBUF %% t:* %D +select -assert-none t:BUFG t:FDCE t:INV t:MUXCY t:XORCY %% t:* %D diff --git a/tests/arch/xilinx/dffs.ys b/tests/arch/xilinx/dffs.ys index b2cb70323..0bba4858f 100644 --- a/tests/arch/xilinx/dffs.ys +++ b/tests/arch/xilinx/dffs.ys @@ -9,7 +9,7 @@ cd dff # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE -select -assert-none t:BUFG t:FDRE t:IBUF t:OBUF %% t:* %D +select -assert-none t:BUFG t:FDRE %% t:* %D design -load read @@ -21,5 +21,5 @@ cd dffe # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE -select -assert-none t:BUFG t:FDRE t:IBUF t:OBUF %% t:* %D +select -assert-none t:BUFG t:FDRE %% t:* %D diff --git a/tests/arch/xilinx/dsp_fastfir.ys b/tests/arch/xilinx/dsp_fastfir.ys index 05e1785d8..0067a822b 100644 --- a/tests/arch/xilinx/dsp_fastfir.ys +++ b/tests/arch/xilinx/dsp_fastfir.ys @@ -66,4 +66,4 @@ EOT synth_xilinx cd fastfir_dynamictaps select -assert-count 2 t:DSP48E1 -select -assert-none t:* t:DSP48E1 %d t:BUFG %d t:IBUF %d t:OBUF %d +select -assert-none t:* t:DSP48E1 %d t:BUFG %d diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys index d60695e2c..f03400fe7 100644 --- a/tests/arch/xilinx/fsm.ys +++ b/tests/arch/xilinx/fsm.ys @@ -16,4 +16,4 @@ select -assert-count 1 t:FDSE select -assert-count 1 t:LUT2 select -assert-count 3 t:LUT5 select -assert-count 1 t:LUT6 -select -assert-none t:BUFG t:IBUF t:OBUF t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D +select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D diff --git a/tests/arch/xilinx/latches.ys b/tests/arch/xilinx/latches.ys index c1caea27a..c87a8e38b 100644 --- a/tests/arch/xilinx/latches.ys +++ b/tests/arch/xilinx/latches.ys @@ -8,7 +8,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd latchp # Constrain all select calls below inside the top module select -assert-count 1 t:LDCE -select -assert-none t:LDCE t:IBUF t:OBUF %% t:* %D +select -assert-none t:LDCE %% t:* %D design -load read @@ -20,7 +20,7 @@ cd latchn # Constrain all select calls below inside the top module select -assert-count 1 t:LDCE select -assert-count 1 t:INV -select -assert-none t:LDCE t:INV t:IBUF t:OBUF %% t:* %D +select -assert-none t:LDCE t:INV %% t:* %D design -load read @@ -32,4 +32,4 @@ cd latchsr # Constrain all select calls below inside the top module select -assert-count 1 t:LDCE select -assert-count 2 t:LUT3 -select -assert-none t:LDCE t:LUT3 t:IBUF t:OBUF %% t:* %D +select -assert-none t:LDCE t:LUT3 %% t:* %D diff --git a/tests/arch/xilinx/logic.ys b/tests/arch/xilinx/logic.ys index 2372cca61..d5b5c1a37 100644 --- a/tests/arch/xilinx/logic.ys +++ b/tests/arch/xilinx/logic.ys @@ -8,4 +8,4 @@ cd top # Constrain all select calls below inside the top module select -assert-count 1 t:INV select -assert-count 6 t:LUT2 select -assert-count 2 t:LUT4 -select -assert-none t:INV t:LUT2 t:LUT4 t:IBUF t:OBUF %% t:* %D +select -assert-none t:INV t:LUT2 t:LUT4 %% t:* %D diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys index 951517fa9..6c9d1eae1 100644 --- a/tests/arch/xilinx/lutram.ys +++ b/tests/arch/xilinx/lutram.ys @@ -14,7 +14,7 @@ #select -assert-count 1 t:BUFG #select -assert-count 8 t:FDRE #select -assert-count 8 t:RAM16X1D -#select -assert-none t:BUFG t:FDRE t:RAM16X1D t:IBUF t:OBUF %% t:* %D +#select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D design -reset @@ -34,7 +34,7 @@ cd lutram_1w1r select -assert-count 1 t:BUFG select -assert-count 8 t:FDRE select -assert-count 8 t:RAM32X1D -select -assert-none t:BUFG t:FDRE t:RAM32X1D t:IBUF t:OBUF %% t:* %D +select -assert-none t:BUFG t:FDRE t:RAM32X1D %% t:* %D design -reset @@ -54,7 +54,7 @@ cd lutram_1w1r select -assert-count 1 t:BUFG select -assert-count 8 t:FDRE select -assert-count 8 t:RAM64X1D -select -assert-none t:BUFG t:FDRE t:RAM64X1D t:IBUF t:OBUF %% t:* %D +select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D design -reset @@ -74,7 +74,7 @@ cd lutram_1w3r select -assert-count 1 t:BUFG select -assert-count 24 t:FDRE select -assert-count 4 t:RAM32M -select -assert-none t:BUFG t:FDRE t:RAM32M t:IBUF t:OBUF %% t:* %D +select -assert-none t:BUFG t:FDRE t:RAM32M %% t:* %D design -reset @@ -94,7 +94,7 @@ cd lutram_1w3r select -assert-count 1 t:BUFG select -assert-count 24 t:FDRE select -assert-count 8 t:RAM64M -select -assert-none t:BUFG t:FDRE t:RAM64M t:IBUF t:OBUF %% t:* %D +select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D design -reset @@ -114,7 +114,7 @@ cd lutram_1w1r select -assert-count 1 t:BUFG select -assert-count 6 t:FDRE select -assert-count 1 t:RAM32M -select -assert-none t:BUFG t:FDRE t:RAM32M t:IBUF t:OBUF %% t:* %D +select -assert-none t:BUFG t:FDRE t:RAM32M %% t:* %D design -reset @@ -134,4 +134,4 @@ cd lutram_1w1r select -assert-count 1 t:BUFG select -assert-count 6 t:FDRE select -assert-count 2 t:RAM64M -select -assert-none t:BUFG t:FDRE t:RAM64M t:IBUF t:OBUF %% t:* %D +select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D diff --git a/tests/arch/xilinx/macc.ys b/tests/arch/xilinx/macc.ys index 0869a8dae..11e959976 100644 --- a/tests/arch/xilinx/macc.ys +++ b/tests/arch/xilinx/macc.ys @@ -12,7 +12,7 @@ cd macc # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE select -assert-count 1 t:DSP48E1 -select -assert-none t:BUFG t:FDRE t:DSP48E1 t:IBUF t:OBUF %% t:* %D +select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D design -load read hierarchy -top macc2 @@ -29,4 +29,4 @@ select -assert-count 1 t:DSP48E1 select -assert-count 1 t:FDRE select -assert-count 1 t:LUT2 select -assert-count 40 t:LUT3 -select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 t:IBUF t:OBUF %% t:* %D +select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 %% t:* %D diff --git a/tests/arch/xilinx/mul.ys b/tests/arch/xilinx/mul.ys index 100de6629..d76814966 100644 --- a/tests/arch/xilinx/mul.ys +++ b/tests/arch/xilinx/mul.ys @@ -6,4 +6,4 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd top # Constrain all select calls below inside the top module select -assert-count 1 t:DSP48E1 -select -assert-none t:DSP48E1 t:IBUF t:OBUF %% t:* %D +select -assert-none t:DSP48E1 %% t:* %D diff --git a/tests/arch/xilinx/mul_unsigned.ys b/tests/arch/xilinx/mul_unsigned.ys index 59ead5cda..62495b90c 100644 --- a/tests/arch/xilinx/mul_unsigned.ys +++ b/tests/arch/xilinx/mul_unsigned.ys @@ -8,4 +8,4 @@ cd mul_unsigned # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:DSP48E1 select -assert-count 30 t:FDRE -select -assert-none t:DSP48E1 t:FDRE t:BUFG t:IBUF t:OBUF %% t:* %D +select -assert-none t:DSP48E1 t:FDRE t:BUFG %% t:* %D diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys index faad64cc5..388272449 100644 --- a/tests/arch/xilinx/mux.ys +++ b/tests/arch/xilinx/mux.ys @@ -8,7 +8,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd mux2 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT3 -select -assert-none t:LUT3 t:IBUF t:OBUF %% t:* %D +select -assert-none t:LUT3 %% t:* %D design -load read @@ -19,7 +19,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd mux4 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT6 -select -assert-none t:LUT6 t:IBUF t:OBUF %% t:* %D +select -assert-none t:LUT6 %% t:* %D design -load read @@ -31,7 +31,7 @@ cd mux8 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT3 select -assert-count 2 t:LUT6 -select -assert-none t:LUT3 t:LUT6 t:IBUF t:OBUF %% t:* %D +select -assert-none t:LUT3 t:LUT6 %% t:* %D design -load read @@ -44,4 +44,4 @@ select -assert-min 5 t:LUT6 select -assert-max 7 t:LUT6 select -assert-max 2 t:MUXF7 -select -assert-none t:LUT6 t:MUXF7 t:IBUF t:OBUF %% t:* %D +select -assert-none t:LUT6 t:MUXF7 %% t:* %D diff --git a/tests/arch/xilinx/shifter.ys b/tests/arch/xilinx/shifter.ys index 4d63ba9c2..455437f18 100644 --- a/tests/arch/xilinx/shifter.ys +++ b/tests/arch/xilinx/shifter.ys @@ -8,4 +8,4 @@ cd top # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 8 t:FDRE -select -assert-none t:BUFG t:FDRE t:IBUF t:OBUF %% t:* %D +select -assert-none t:BUFG t:FDRE %% t:* %D diff --git a/tests/arch/xilinx/xilinx_dffopt.ys b/tests/arch/xilinx/xilinx_dffopt.ys index 5dbe11b27..dc036acfd 100644 --- a/tests/arch/xilinx/xilinx_dffopt.ys +++ b/tests/arch/xilinx/xilinx_dffopt.ys @@ -28,7 +28,7 @@ clean select -assert-count 1 t:FDRE select -assert-count 1 t:LUT6 select -assert-count 3 t:LUT2 -select -assert-none t:FDRE t:LUT6 t:LUT2 t:IBUF t:OBUF %% t:* %D +select -assert-none t:FDRE t:LUT6 t:LUT2 %% t:* %D design -load t0 @@ -39,7 +39,7 @@ clean select -assert-count 1 t:FDRE select -assert-count 1 t:LUT4 select -assert-count 3 t:LUT2 -select -assert-none t:FDRE t:LUT4 t:LUT2 t:IBUF t:OBUF %% t:* %D +select -assert-none t:FDRE t:LUT4 t:LUT2 %% t:* %D design -reset @@ -74,7 +74,7 @@ clean select -assert-count 1 t:FDSE select -assert-count 1 t:LUT6 select -assert-count 3 t:LUT2 -select -assert-none t:FDSE t:LUT6 t:LUT2 t:IBUF t:OBUF %% t:* %D +select -assert-none t:FDSE t:LUT6 t:LUT2 %% t:* %D design -load t0 @@ -85,7 +85,7 @@ clean select -assert-count 1 t:FDSE select -assert-count 1 t:LUT4 select -assert-count 3 t:LUT2 -select -assert-none t:FDSE t:LUT4 t:LUT2 t:IBUF t:OBUF %% t:* %D +select -assert-none t:FDSE t:LUT4 t:LUT2 %% t:* %D design -reset @@ -120,7 +120,7 @@ clean select -assert-count 1 t:FDCE select -assert-count 1 t:LUT4 select -assert-count 3 t:LUT2 -select -assert-none t:FDCE t:LUT4 t:LUT2 t:IBUF t:OBUF %% t:* %D +select -assert-none t:FDCE t:LUT4 t:LUT2 %% t:* %D design -reset @@ -154,7 +154,7 @@ clean select -assert-count 1 t:FDSE select -assert-count 1 t:LUT5 select -assert-count 2 t:LUT2 -select -assert-none t:FDSE t:LUT5 t:LUT2 t:IBUF t:OBUF %% t:* %D +select -assert-none t:FDSE t:LUT5 t:LUT2 %% t:* %D design -load t0 @@ -164,7 +164,7 @@ clean select -assert-count 1 t:FDSE select -assert-count 2 t:LUT2 -select -assert-none t:FDSE t:LUT2 t:IBUF t:OBUF %% t:* %D +select -assert-none t:FDSE t:LUT2 %% t:* %D design -reset @@ -200,7 +200,7 @@ clean select -assert-count 1 t:FDRSE select -assert-count 1 t:LUT6 select -assert-count 4 t:LUT2 -select -assert-none t:FDRSE t:LUT6 t:LUT2 t:IBUF t:OBUF %% t:* %D +select -assert-none t:FDRSE t:LUT6 t:LUT2 %% t:* %D design -load t0 @@ -211,6 +211,6 @@ clean select -assert-count 1 t:FDRSE select -assert-count 1 t:LUT4 select -assert-count 4 t:LUT2 -select -assert-none t:FDRSE t:LUT4 t:LUT2 t:IBUF t:OBUF %% t:* %D +select -assert-none t:FDRSE t:LUT4 t:LUT2 %% t:* %D design -reset -- cgit v1.2.3 From a82c701668d8197c01e54cb68bc45f2278f3172f Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 28 Dec 2019 16:22:24 +0100 Subject: Make test without iopads --- tests/arch/xilinx/add_sub.ys | 2 +- tests/arch/xilinx/adffs.ys | 8 ++++---- tests/arch/xilinx/attributes_test.ys | 12 ++++++------ tests/arch/xilinx/blockram.ys | 24 ++++++++++++------------ tests/arch/xilinx/bug1460.ys | 2 +- tests/arch/xilinx/counter.ys | 2 +- tests/arch/xilinx/dffs.ys | 4 ++-- tests/arch/xilinx/dsp_fastfir.ys | 2 +- tests/arch/xilinx/fsm.ys | 2 +- tests/arch/xilinx/latches.ys | 6 +++--- tests/arch/xilinx/logic.ys | 2 +- tests/arch/xilinx/lutram.ys | 14 +++++++------- tests/arch/xilinx/macc.ys | 8 ++++---- tests/arch/xilinx/mul.ys | 2 +- tests/arch/xilinx/mul_unsigned.ys | 2 +- tests/arch/xilinx/mux.ys | 8 ++++---- tests/arch/xilinx/shifter.ys | 2 +- 17 files changed, 51 insertions(+), 51 deletions(-) (limited to 'tests') diff --git a/tests/arch/xilinx/add_sub.ys b/tests/arch/xilinx/add_sub.ys index 9dbddce47..313948cc5 100644 --- a/tests/arch/xilinx/add_sub.ys +++ b/tests/arch/xilinx/add_sub.ys @@ -1,7 +1,7 @@ read_verilog ../common/add_sub.v hierarchy -top top proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 14 t:LUT2 diff --git a/tests/arch/xilinx/adffs.ys b/tests/arch/xilinx/adffs.ys index c0ff6a2e2..3328f9edc 100644 --- a/tests/arch/xilinx/adffs.ys +++ b/tests/arch/xilinx/adffs.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top adff proc -equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG @@ -15,7 +15,7 @@ select -assert-none t:BUFG t:FDCE %% t:* %D design -load read hierarchy -top adffn proc -equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG @@ -28,7 +28,7 @@ select -assert-none t:BUFG t:FDCE t:INV %% t:* %D design -load read hierarchy -top dffs proc -equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG @@ -40,7 +40,7 @@ select -assert-none t:BUFG t:FDSE %% t:* %D design -load read hierarchy -top ndffnr proc -equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG diff --git a/tests/arch/xilinx/attributes_test.ys b/tests/arch/xilinx/attributes_test.ys index 4c881b280..7bdd94a63 100644 --- a/tests/arch/xilinx/attributes_test.ys +++ b/tests/arch/xilinx/attributes_test.ys @@ -1,7 +1,7 @@ # Check that blockram memory without parameters is not modified read_verilog ../common/memory_attributes/attributes_test.v hierarchy -top block_ram -synth_xilinx -top block_ram +synth_xilinx -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module select -assert-count 1 t:RAMB18E1 @@ -9,7 +9,7 @@ select -assert-count 1 t:RAMB18E1 design -reset read_verilog ../common/memory_attributes/attributes_test.v hierarchy -top distributed_ram -synth_xilinx -top distributed_ram +synth_xilinx -top distributed_ram -noiopad cd distributed_ram # Constrain all select calls below inside the top module select -assert-count 8 t:RAM32X1D @@ -18,7 +18,7 @@ design -reset read_verilog ../common/memory_attributes/attributes_test.v prep setattr -mod -set ram_style "distributed" block_ram -synth_xilinx -top block_ram +synth_xilinx -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module select -assert-count 32 t:RAM128X1D @@ -27,7 +27,7 @@ design -reset read_verilog ../common/memory_attributes/attributes_test.v prep setattr -mod -set logic_block 1 block_ram -synth_xilinx -top block_ram +synth_xilinx -top block_ram -noiopad cd block_ram # Constrain all select calls below inside the top module select -assert-count 0 t:RAMB18E1 select -assert-count 32 t:RAM128X1D @@ -35,13 +35,13 @@ select -assert-count 32 t:RAM128X1D # Set ram_style block to a distributed memory; will be implemented as blockram design -reset read_verilog ../common/memory_attributes/attributes_test.v -synth_xilinx -top distributed_ram_manual +synth_xilinx -top distributed_ram_manual -noiopad cd distributed_ram_manual # Constrain all select calls below inside the top module select -assert-count 1 t:RAMB18E1 # Set synthesis, ram_block block to a distributed memory; will be implemented as blockram design -reset read_verilog ../common/memory_attributes/attributes_test.v -synth_xilinx -top distributed_ram_manual_syn +synth_xilinx -top distributed_ram_manual_syn -noiopad cd distributed_ram_manual_syn # Constrain all select calls below inside the top module select -assert-count 1 t:RAMB18E1 diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys index bb908cbbf..ed743cf44 100644 --- a/tests/arch/xilinx/blockram.ys +++ b/tests/arch/xilinx/blockram.ys @@ -3,28 +3,28 @@ # Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1 read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp -synth_xilinx -top sync_ram_sdp +synth_xilinx -top sync_ram_sdp -noiopad cd sync_ram_sdp select -assert-count 1 t:RAMB18E1 design -reset read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp -synth_xilinx -top sync_ram_sdp +synth_xilinx -top sync_ram_sdp -noiopad cd sync_ram_sdp select -assert-count 1 t:RAMB18E1 design -reset read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp -synth_xilinx -top sync_ram_sdp +synth_xilinx -top sync_ram_sdp -noiopad cd sync_ram_sdp select -assert-count 1 t:RAMB18E1 design -reset read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp -synth_xilinx -top sync_ram_sdp +synth_xilinx -top sync_ram_sdp -noiopad cd sync_ram_sdp select -assert-count 1 t:RAMB18E1 @@ -32,7 +32,7 @@ select -assert-count 1 t:RAMB18E1 design -reset read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp -synth_xilinx -top sync_ram_sdp +synth_xilinx -top sync_ram_sdp -noiopad cd sync_ram_sdp select -assert-count 0 t:RAMB18E1 select -assert-count 4 t:RAM128X1D @@ -41,7 +41,7 @@ select -assert-count 4 t:RAM128X1D design -reset read_verilog ../common/blockram.v chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp -synth_xilinx -top sync_ram_sdp +synth_xilinx -top sync_ram_sdp -noiopad cd sync_ram_sdp select -assert-count 1 t:RAMB36E1 @@ -52,7 +52,7 @@ design -reset read_verilog ../common/blockram.v hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 setattr -set ram_style "block" m:memory -synth_xilinx -top sync_ram_sdp +synth_xilinx -top sync_ram_sdp -noiopad cd sync_ram_sdp select -assert-count 1 t:RAMB18E1 @@ -60,7 +60,7 @@ design -reset read_verilog ../common/blockram.v hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 setattr -set ram_block 1 m:memory -synth_xilinx -top sync_ram_sdp +synth_xilinx -top sync_ram_sdp -noiopad cd sync_ram_sdp select -assert-count 1 t:RAMB18E1 @@ -68,7 +68,7 @@ design -reset read_verilog ../common/blockram.v hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 setattr -set ram_style "dont_infer_a_ram_pretty_please" m:memory -synth_xilinx -top sync_ram_sdp +synth_xilinx -top sync_ram_sdp -noiopad cd sync_ram_sdp select -assert-count 0 t:RAMB18E1 @@ -76,7 +76,7 @@ design -reset read_verilog ../common/blockram.v hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 setattr -set logic_block 1 m:memory -synth_xilinx -top sync_ram_sdp +synth_xilinx -top sync_ram_sdp -noiopad cd sync_ram_sdp select -assert-count 0 t:RAMB18E1 @@ -84,7 +84,7 @@ design -reset read_verilog ../common/blockram.v hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1 setattr -set ram_style "block" m:memory -synth_xilinx -top sync_ram_sdp +synth_xilinx -top sync_ram_sdp -noiopad cd sync_ram_sdp select -assert-count 1 t:RAMB18E1 @@ -92,6 +92,6 @@ design -reset read_verilog ../common/blockram.v hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1 setattr -set ram_block 1 m:memory -synth_xilinx -top sync_ram_sdp +synth_xilinx -top sync_ram_sdp -noiopad cd sync_ram_sdp select -assert-count 1 t:RAMB18E1 diff --git a/tests/arch/xilinx/bug1460.ys b/tests/arch/xilinx/bug1460.ys index 2018071cc..09935ccd8 100644 --- a/tests/arch/xilinx/bug1460.ys +++ b/tests/arch/xilinx/bug1460.ys @@ -28,7 +28,7 @@ module register_file( endmodule EOT -synth_xilinx +synth_xilinx -noiopad cd register_file select -assert-count 32 t:RAM32M select -assert-none t:* t:BUFG %d t:RAM32M %d diff --git a/tests/arch/xilinx/counter.ys b/tests/arch/xilinx/counter.ys index 604acdbfc..11c29922e 100644 --- a/tests/arch/xilinx/counter.ys +++ b/tests/arch/xilinx/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/xilinx/dffs.ys b/tests/arch/xilinx/dffs.ys index 0bba4858f..dc764b033 100644 --- a/tests/arch/xilinx/dffs.ys +++ b/tests/arch/xilinx/dffs.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top dff proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG @@ -15,7 +15,7 @@ select -assert-none t:BUFG t:FDRE %% t:* %D design -load read hierarchy -top dffe proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG diff --git a/tests/arch/xilinx/dsp_fastfir.ys b/tests/arch/xilinx/dsp_fastfir.ys index 0067a822b..57fe49bde 100644 --- a/tests/arch/xilinx/dsp_fastfir.ys +++ b/tests/arch/xilinx/dsp_fastfir.ys @@ -63,7 +63,7 @@ module fastfir_dynamictaps(i_clk, i_reset, i_tap_wr, i_tap, i_ce, i_sample, o_re endmodule EOT -synth_xilinx +synth_xilinx -noiopad cd fastfir_dynamictaps select -assert-count 2 t:DSP48E1 select -assert-none t:* t:DSP48E1 %d t:BUFG %d diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys index f03400fe7..3235d5af3 100644 --- a/tests/arch/xilinx/fsm.ys +++ b/tests/arch/xilinx/fsm.ys @@ -3,7 +3,7 @@ hierarchy -top fsm proc flatten -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad miter -equiv -make_assert -flatten gold gate miter sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter diff --git a/tests/arch/xilinx/latches.ys b/tests/arch/xilinx/latches.ys index c87a8e38b..e226c2ec8 100644 --- a/tests/arch/xilinx/latches.ys +++ b/tests/arch/xilinx/latches.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top latchp proc -equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchp # Constrain all select calls below inside the top module select -assert-count 1 t:LDCE @@ -14,7 +14,7 @@ select -assert-none t:LDCE %% t:* %D design -load read hierarchy -top latchn proc -equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchn # Constrain all select calls below inside the top module select -assert-count 1 t:LDCE @@ -26,7 +26,7 @@ select -assert-none t:LDCE t:INV %% t:* %D design -load read hierarchy -top latchsr proc -equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchsr # Constrain all select calls below inside the top module select -assert-count 1 t:LDCE diff --git a/tests/arch/xilinx/logic.ys b/tests/arch/xilinx/logic.ys index d5b5c1a37..61a9314cc 100644 --- a/tests/arch/xilinx/logic.ys +++ b/tests/arch/xilinx/logic.ys @@ -1,7 +1,7 @@ read_verilog ../common/logic.v hierarchy -top top proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys index 6c9d1eae1..3f127a77e 100644 --- a/tests/arch/xilinx/lutram.ys +++ b/tests/arch/xilinx/lutram.ys @@ -2,7 +2,7 @@ #hierarchy -top lutram_1w1r -chparam A_WIDTH 4 #proc #memory -nomap -#equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +#equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad #memory #opt -full # @@ -22,7 +22,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r -chparam A_WIDTH 5 proc memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad memory opt -full @@ -42,7 +42,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r proc memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad memory opt -full @@ -62,7 +62,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w3r proc memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad memory opt -full @@ -82,7 +82,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w3r -chparam A_WIDTH 6 proc memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad memory opt -full @@ -102,7 +102,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 6 proc memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad memory opt -full @@ -122,7 +122,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r -chparam A_WIDTH 6 -chparam D_WIDTH 6 proc memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad memory opt -full diff --git a/tests/arch/xilinx/macc.ys b/tests/arch/xilinx/macc.ys index 11e959976..bf2b36320 100644 --- a/tests/arch/xilinx/macc.ys +++ b/tests/arch/xilinx/macc.ys @@ -3,8 +3,8 @@ design -save read hierarchy -top macc proc -#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad ### TODO +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) @@ -17,8 +17,8 @@ select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D design -load read hierarchy -top macc2 proc -#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad ### TODO +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -noiopad miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) diff --git a/tests/arch/xilinx/mul.ys b/tests/arch/xilinx/mul.ys index d76814966..b04833a43 100644 --- a/tests/arch/xilinx/mul.ys +++ b/tests/arch/xilinx/mul.ys @@ -1,7 +1,7 @@ read_verilog ../common/mul.v hierarchy -top top proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/xilinx/mul_unsigned.ys b/tests/arch/xilinx/mul_unsigned.ys index 62495b90c..0a7644b65 100644 --- a/tests/arch/xilinx/mul_unsigned.ys +++ b/tests/arch/xilinx/mul_unsigned.ys @@ -2,7 +2,7 @@ read_verilog mul_unsigned.v hierarchy -top mul_unsigned proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mul_unsigned # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys index 388272449..99817738d 100644 --- a/tests/arch/xilinx/mux.ys +++ b/tests/arch/xilinx/mux.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top mux2 proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT3 @@ -14,7 +14,7 @@ select -assert-none t:LUT3 %% t:* %D design -load read hierarchy -top mux4 proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT6 @@ -25,7 +25,7 @@ select -assert-none t:LUT6 %% t:* %D design -load read hierarchy -top mux8 proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT3 @@ -37,7 +37,7 @@ select -assert-none t:LUT3 t:LUT6 %% t:* %D design -load read hierarchy -top mux16 proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module select -assert-min 5 t:LUT6 diff --git a/tests/arch/xilinx/shifter.ys b/tests/arch/xilinx/shifter.ys index 455437f18..3652319a0 100644 --- a/tests/arch/xilinx/shifter.ys +++ b/tests/arch/xilinx/shifter.ys @@ -2,7 +2,7 @@ read_verilog ../common/shifter.v hierarchy -top top proc flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -- cgit v1.2.3 From f9749c202c93e1c9c6edb522999eacc323039b95 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Sat, 28 Dec 2019 16:43:19 +0100 Subject: Fix new tests --- tests/arch/xilinx/dsp_cascade.ys | 8 ++++---- tests/arch/xilinx/mul.ys | 2 +- tests/arch/xilinx/mul_unsigned.ys | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'tests') diff --git a/tests/arch/xilinx/dsp_cascade.ys b/tests/arch/xilinx/dsp_cascade.ys index f9185551b..ca6b619b9 100644 --- a/tests/arch/xilinx/dsp_cascade.ys +++ b/tests/arch/xilinx/dsp_cascade.ys @@ -19,7 +19,7 @@ EOT proc design -save read -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad design -load postopt cd cascade select -assert-count 3 t:DSP48E1 @@ -35,7 +35,7 @@ select -assert-none t:DSP48E1 t:BUFG %% t:* %D select -assert-count 2 t:DSP48E1 %co:+[PCOUT] t:DSP48E1 %d %co:+[PCIN] w:* %d t:DSP48E1 %i design -load read -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad design -load postopt cd cascade select -assert-count 3 t:DSP48A1 @@ -65,7 +65,7 @@ EOT proc design -save read -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad design -load postopt cd cascade select -assert-count 2 t:DSP48E1 @@ -75,7 +75,7 @@ select -assert-none t:DSP48E1 t:BUFG %% t:* %D select -assert-count 1 t:DSP48E1 %co:+[PCOUT] t:DSP48E1 %d %co:+[PCIN] w:* %d t:DSP48E1 %i design -load read -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad design -load postopt cd cascade select -assert-count 2 t:DSP48A1 diff --git a/tests/arch/xilinx/mul.ys b/tests/arch/xilinx/mul.ys index 049a3da7e..490846ff1 100644 --- a/tests/arch/xilinx/mul.ys +++ b/tests/arch/xilinx/mul.ys @@ -13,7 +13,7 @@ design -reset read_verilog ../common/mul.v hierarchy -top top proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/xilinx/mul_unsigned.ys b/tests/arch/xilinx/mul_unsigned.ys index 830dd639c..980263cbd 100644 --- a/tests/arch/xilinx/mul_unsigned.ys +++ b/tests/arch/xilinx/mul_unsigned.ys @@ -16,7 +16,7 @@ read_verilog mul_unsigned.v hierarchy -top mul_unsigned proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mul_unsigned # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG -- cgit v1.2.3 From fc4b8b89912c14f42b04a7c9f2ce350db3ce7c0b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Dec 2019 14:56:14 -0800 Subject: Remove submod changes --- tests/various/submod.ys | 102 ------------------------------------------------ 1 file changed, 102 deletions(-) delete mode 100644 tests/various/submod.ys (limited to 'tests') diff --git a/tests/various/submod.ys b/tests/various/submod.ys deleted file mode 100644 index 9d7dabdd7..000000000 --- a/tests/various/submod.ys +++ /dev/null @@ -1,102 +0,0 @@ -read_verilog < Date: Mon, 30 Dec 2019 20:13:25 -0800 Subject: Add -D DFF_MODE to abc9_map test --- tests/arch/xilinx/abc9_map.ys | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'tests') diff --git a/tests/arch/xilinx/abc9_map.ys b/tests/arch/xilinx/abc9_map.ys index 6823589f1..4a7b9384a 100644 --- a/tests/arch/xilinx/abc9_map.ys +++ b/tests/arch/xilinx/abc9_map.ys @@ -6,7 +6,7 @@ endmodule EOT design -save gold -techmap -map +/xilinx/abc9_map.v -max_iter 1 +techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE techmap -map +/xilinx/abc9_unmap.v select -assert-count 1 t:FDSE select -assert-count 1 t:FDSE_1 @@ -29,7 +29,7 @@ endmodule EOT design -save gold -techmap -map +/xilinx/abc9_map.v -max_iter 1 +techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE techmap -map +/xilinx/abc9_unmap.v select -assert-count 1 t:FDRE select -assert-count 1 t:FDRE_1 @@ -52,7 +52,7 @@ endmodule EOT design -save gold -techmap -map +/xilinx/abc9_map.v -max_iter 1 +techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE techmap -map +/xilinx/abc9_unmap.v select -assert-count 1 t:FDCE select -assert-count 1 t:FDCE_1 @@ -76,7 +76,7 @@ endmodule EOT design -save gold -techmap -map +/xilinx/abc9_map.v -max_iter 1 +techmap -map +/xilinx/abc9_map.v -max_iter 1 -D DFF_MODE techmap -map +/xilinx/abc9_unmap.v select -assert-count 1 t:FDPE techmap -autoproc -map +/xilinx/cells_sim.v -- cgit v1.2.3 From ccc0a740d254e6895b49037681bc484d6572342d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 31 Dec 2019 16:16:05 -0800 Subject: Add some abc9 dff tests --- tests/arch/xilinx/abc9_dff.ys | 55 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 tests/arch/xilinx/abc9_dff.ys (limited to 'tests') diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys new file mode 100644 index 000000000..6611b4f18 --- /dev/null +++ b/tests/arch/xilinx/abc9_dff.ys @@ -0,0 +1,55 @@ +read_verilog < Date: Tue, 31 Dec 2019 18:39:32 -0800 Subject: Call equiv_opt with -multiclock and -assert --- tests/arch/anlogic/counter.ys | 2 +- tests/arch/ecp5/counter.ys | 2 +- tests/arch/efinix/counter.ys | 2 +- tests/arch/gowin/counter.ys | 2 +- tests/arch/ice40/counter.ys | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'tests') diff --git a/tests/arch/anlogic/counter.ys b/tests/arch/anlogic/counter.ys index d363ec24e..a6eab248c 100644 --- a/tests/arch/anlogic/counter.ys +++ b/tests/arch/anlogic/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +equiv_opt -assert -multiclock -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/ecp5/counter.ys b/tests/arch/ecp5/counter.ys index f9f60fbff..e46001ffe 100644 --- a/tests/arch/ecp5/counter.ys +++ b/tests/arch/ecp5/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -assert -multiclock -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 4 t:CCU2C diff --git a/tests/arch/efinix/counter.ys b/tests/arch/efinix/counter.ys index d20b8ae27..f8fb29a87 100644 --- a/tests/arch/efinix/counter.ys +++ b/tests/arch/efinix/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check +equiv_opt -assert -multiclock -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/gowin/counter.ys b/tests/arch/gowin/counter.ys index 920479d44..bdbc7ee24 100644 --- a/tests/arch/gowin/counter.ys +++ b/tests/arch/gowin/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -map +/gowin/cells_sim.v synth_gowin # equivalency check +equiv_opt -assert -multiclock -map +/gowin/cells_sim.v synth_gowin # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/ice40/counter.ys b/tests/arch/ice40/counter.ys index f112eb97d..7bbc4f2c3 100644 --- a/tests/arch/ice40/counter.ys +++ b/tests/arch/ice40/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 6 t:SB_CARRY -- cgit v1.2.3 From a59016b146e91311324bc87f9a9437d7ff31d9f2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 31 Dec 2019 18:40:11 -0800 Subject: Fix warnings --- tests/arch/ice40/mul.ys | 2 +- tests/arch/ice40/rom.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/arch/ice40/mul.ys b/tests/arch/ice40/mul.ys index 9891b77d6..b8c3eb941 100644 --- a/tests/arch/ice40/mul.ys +++ b/tests/arch/ice40/mul.ys @@ -1,6 +1,6 @@ read_verilog ../common/mul.v hierarchy -top top -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check +equiv_opt -assert -multiclock -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:SB_MAC16 diff --git a/tests/arch/ice40/rom.v b/tests/arch/ice40/rom.v index 0a0f41f37..c4c677c1e 100644 --- a/tests/arch/ice40/rom.v +++ b/tests/arch/ice40/rom.v @@ -2,7 +2,7 @@ Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 74]. */ module top(data, addr); -output [3:0] data; +output reg [3:0] data; input [4:0] addr; always @(addr) begin case (addr) -- cgit v1.2.3 From 713484fa66da705d2a274cdea590bd4634f48d5d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 31 Dec 2019 18:40:30 -0800 Subject: Do not do call equiv_opt when no sim model exists --- tests/arch/ecp5/macc.ys | 4 ++-- tests/arch/ecp5/mul.ys | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'tests') diff --git a/tests/arch/ecp5/macc.ys b/tests/arch/ecp5/macc.ys index 1863ea4d2..8da8d2f8e 100644 --- a/tests/arch/ecp5/macc.ys +++ b/tests/arch/ecp5/macc.ys @@ -3,8 +3,8 @@ hierarchy -top top proc # Blocked by issue #1358 (Missing ECP5 simulation models) #equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +synth_ecp5 +#design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:MULT18X18D select -assert-count 4 t:CCU2C diff --git a/tests/arch/ecp5/mul.ys b/tests/arch/ecp5/mul.ys index 2105be52c..f887e9585 100644 --- a/tests/arch/ecp5/mul.ys +++ b/tests/arch/ecp5/mul.ys @@ -3,9 +3,9 @@ hierarchy -top top proc # Blocked by issue #1358 (Missing ECP5 simulation models) #equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +synth_ecp5 -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +#design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:MULT18X18D select -assert-none t:MULT18X18D %% t:* %D -- cgit v1.2.3 From a1344ec06ead35a3b7933ee93b5757eeff2e5d4a Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Wed, 1 Jan 2020 16:24:30 +0100 Subject: Added a test case --- tests/arch/xilinx/bug1605.ys | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 tests/arch/xilinx/bug1605.ys (limited to 'tests') diff --git a/tests/arch/xilinx/bug1605.ys b/tests/arch/xilinx/bug1605.ys new file mode 100644 index 000000000..4be659860 --- /dev/null +++ b/tests/arch/xilinx/bug1605.ys @@ -0,0 +1,19 @@ +read_verilog < Date: Wed, 1 Jan 2020 09:05:46 -0800 Subject: Revert insertion of 'reg', leave note behind --- tests/arch/ice40/rom.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/arch/ice40/rom.v b/tests/arch/ice40/rom.v index c4c677c1e..71459fe38 100644 --- a/tests/arch/ice40/rom.v +++ b/tests/arch/ice40/rom.v @@ -2,7 +2,8 @@ Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 74]. */ module top(data, addr); -output reg [3:0] data; +output [3:0] data; // Note: this prompts a Yosys warning, but + // vendor doc does not contain 'reg' input [4:0] addr; always @(addr) begin case (addr) -- cgit v1.2.3 From 6e866030c286d70f6ccff805e58b1fdd9a1a322b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 2 Jan 2020 14:38:59 -0800 Subject: Combine tests to check multiple clock domains --- tests/arch/xilinx/abc9_dff.ys | 43 ++++++++++--------------------------------- 1 file changed, 10 insertions(+), 33 deletions(-) (limited to 'tests') diff --git a/tests/arch/xilinx/abc9_dff.ys b/tests/arch/xilinx/abc9_dff.ys index 6611b4f18..b457cefce 100644 --- a/tests/arch/xilinx/abc9_dff.ys +++ b/tests/arch/xilinx/abc9_dff.ys @@ -1,55 +1,32 @@ read_verilog < Date: Mon, 6 Jan 2020 16:22:22 -0800 Subject: Add testcase from #1459 --- tests/arch/ecp5/bug1459.ys | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 tests/arch/ecp5/bug1459.ys (limited to 'tests') diff --git a/tests/arch/ecp5/bug1459.ys b/tests/arch/ecp5/bug1459.ys new file mode 100644 index 000000000..1142ae0b5 --- /dev/null +++ b/tests/arch/ecp5/bug1459.ys @@ -0,0 +1,25 @@ +read_verilog < Date: Tue, 7 Jan 2020 11:44:03 -0800 Subject: tests/aiger: write Yosys output --- tests/aiger/run-test.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh index deaf48a3d..8e932b091 100755 --- a/tests/aiger/run-test.sh +++ b/tests/aiger/run-test.sh @@ -33,7 +33,7 @@ design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports -seq 16 miter -" +" -l ${aag}.log done for aig in *.aig; do @@ -50,5 +50,5 @@ design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports -seq 16 miter -" +" -l ${aig}.log done -- cgit v1.2.3 From 0d3f10d3cc55e83ae6a39881227feb843769d6b1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 7 Jan 2020 11:44:20 -0800 Subject: Add testcases --- tests/aiger/symbols.aag | 9 +++++++++ tests/aiger/symbols.aig | 8 ++++++++ 2 files changed, 17 insertions(+) create mode 100644 tests/aiger/symbols.aag create mode 100644 tests/aiger/symbols.aig (limited to 'tests') diff --git a/tests/aiger/symbols.aag b/tests/aiger/symbols.aag new file mode 100644 index 000000000..93f8989f2 --- /dev/null +++ b/tests/aiger/symbols.aag @@ -0,0 +1,9 @@ +aag 2 1 1 1 0 +2 +4 2 1 +4 +i0 d +l0 q +o0 q +c +Generated by Yosys 0.9+932 (git sha1 baba33fb, clang 9.0.0-2 -fPIC -Os) diff --git a/tests/aiger/symbols.aig b/tests/aiger/symbols.aig new file mode 100644 index 000000000..a7922ab46 --- /dev/null +++ b/tests/aiger/symbols.aig @@ -0,0 +1,8 @@ +aig 2 1 1 1 0 +2 1 +4 +i0 d +l0 q +o0 q +c +Generated by Yosys 0.9+932 (git sha1 baba33fb, clang 9.0.0-2 -fPIC -Os) -- cgit v1.2.3 From a10016ccc57638aa837acd76fc93f296eda83b32 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 9 Jan 2020 18:17:06 -0800 Subject: Add abc9 sanity test --- tests/techmap/abc9.ys | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 tests/techmap/abc9.ys (limited to 'tests') diff --git a/tests/techmap/abc9.ys b/tests/techmap/abc9.ys new file mode 100644 index 000000000..20f263da8 --- /dev/null +++ b/tests/techmap/abc9.ys @@ -0,0 +1,40 @@ +read_verilog < Date: Fri, 10 Jan 2020 14:48:01 +0100 Subject: Fix tests --- tests/arch/xilinx/add_sub.ys | 8 ++++---- tests/arch/xilinx/counter.ys | 7 +++---- tests/arch/xilinx/fsm.ys | 8 ++++---- 3 files changed, 11 insertions(+), 12 deletions(-) (limited to 'tests') diff --git a/tests/arch/xilinx/add_sub.ys b/tests/arch/xilinx/add_sub.ys index 313948cc5..70cfe81a3 100644 --- a/tests/arch/xilinx/add_sub.ys +++ b/tests/arch/xilinx/add_sub.ys @@ -4,8 +4,8 @@ proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 14 t:LUT2 -select -assert-count 6 t:MUXCY -select -assert-count 8 t:XORCY -select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D +stat +select -assert-count 16 t:LUT2 +select -assert-count 2 t:CARRY4 +select -assert-none t:LUT2 t:CARRY4 %% t:* %D diff --git a/tests/arch/xilinx/counter.ys b/tests/arch/xilinx/counter.ys index 11c29922e..064519ce7 100644 --- a/tests/arch/xilinx/counter.ys +++ b/tests/arch/xilinx/counter.ys @@ -5,10 +5,9 @@ flatten equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module - +stat select -assert-count 1 t:BUFG select -assert-count 8 t:FDCE select -assert-count 1 t:INV -select -assert-count 7 t:MUXCY -select -assert-count 8 t:XORCY -select -assert-none t:BUFG t:FDCE t:INV t:MUXCY t:XORCY %% t:* %D +select -assert-count 2 t:CARRY4 +select -assert-none t:BUFG t:FDCE t:INV t:CARRY4 %% t:* %D diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys index 3235d5af3..3cef84388 100644 --- a/tests/arch/xilinx/fsm.ys +++ b/tests/arch/xilinx/fsm.ys @@ -9,11 +9,11 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module - +stat select -assert-count 1 t:BUFG select -assert-count 4 t:FDRE select -assert-count 1 t:FDSE select -assert-count 1 t:LUT2 -select -assert-count 3 t:LUT5 -select -assert-count 1 t:LUT6 -select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D +select -assert-count 2 t:LUT3 +select -assert-count 4 t:LUT5 +select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT3 t:LUT5 %% t:* %D -- cgit v1.2.3 From ccfe1e5909ba6093e49ebdfaa1aac6c4aa267036 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 10 Jan 2020 15:20:50 +0100 Subject: this one is fine --- tests/arch/xilinx/fsm.ys | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'tests') diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys index 3cef84388..a464fcfdb 100644 --- a/tests/arch/xilinx/fsm.ys +++ b/tests/arch/xilinx/fsm.ys @@ -14,6 +14,6 @@ select -assert-count 1 t:BUFG select -assert-count 4 t:FDRE select -assert-count 1 t:FDSE select -assert-count 1 t:LUT2 -select -assert-count 2 t:LUT3 -select -assert-count 4 t:LUT5 -select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT3 t:LUT5 %% t:* %D +select -assert-count 3 t:LUT5 +select -assert-count 1 t:LUT6 +select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D -- cgit v1.2.3 From ae619ba87a58ee530549206eee7f5ea1ad8e1072 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Sun, 12 Jan 2020 15:21:26 -0800 Subject: Add #1626 testcase --- tests/arch/ice40/bug1626.ys | 217 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 217 insertions(+) create mode 100644 tests/arch/ice40/bug1626.ys (limited to 'tests') diff --git a/tests/arch/ice40/bug1626.ys b/tests/arch/ice40/bug1626.ys new file mode 100644 index 000000000..27b6fb5e8 --- /dev/null +++ b/tests/arch/ice40/bug1626.ys @@ -0,0 +1,217 @@ +read_ilang < Date: Mon, 13 Jan 2020 19:07:55 -0800 Subject: write_xaiger: add support and test for (* keep *) on wires --- tests/techmap/abc9.ys | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'tests') diff --git a/tests/techmap/abc9.ys b/tests/techmap/abc9.ys index 20f263da8..46b6f08d2 100644 --- a/tests/techmap/abc9.ys +++ b/tests/techmap/abc9.ys @@ -38,3 +38,16 @@ abc9 -lut 4 design -load gold scratchpad -copy abc9.script.flow3 abc9.script abc9 -lut 4 + +design -reset +read_verilog < Date: Mon, 13 Jan 2020 19:21:11 -0800 Subject: abc9: respect (* keep *) on cells --- tests/techmap/abc9.ys | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'tests') diff --git a/tests/techmap/abc9.ys b/tests/techmap/abc9.ys index 46b6f08d2..d5a63e1cb 100644 --- a/tests/techmap/abc9.ys +++ b/tests/techmap/abc9.ys @@ -51,3 +51,18 @@ simplemap equiv_opt -assert abc9 -lut 4 design -load postopt select -assert-count 2 t:$lut + +design -reset +read_verilog -icells < Date: Mon, 13 Jan 2020 21:27:53 -0800 Subject: Add #1630 testcase --- tests/arch/ecp5/bug1630.il.gz | Bin 0 -> 8527 bytes tests/arch/ecp5/bug1630.ys | 2 ++ 2 files changed, 2 insertions(+) create mode 100644 tests/arch/ecp5/bug1630.il.gz create mode 100644 tests/arch/ecp5/bug1630.ys (limited to 'tests') diff --git a/tests/arch/ecp5/bug1630.il.gz b/tests/arch/ecp5/bug1630.il.gz new file mode 100644 index 000000000..37bcf2be2 Binary files /dev/null and b/tests/arch/ecp5/bug1630.il.gz differ diff --git a/tests/arch/ecp5/bug1630.ys b/tests/arch/ecp5/bug1630.ys new file mode 100644 index 000000000..b419fb9bb --- /dev/null +++ b/tests/arch/ecp5/bug1630.ys @@ -0,0 +1,2 @@ +read_ilang bug1630.il.gz +abc9 -lut +/ecp5/abc9_5g.lut -- cgit v1.2.3 From 00964e999d5bc1825ff664e1514efcacb6d2e23f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 14 Jan 2020 10:13:03 -0800 Subject: autoname: add testcase with $-prefix-ed port --- tests/various/autoname.ys | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 tests/various/autoname.ys (limited to 'tests') diff --git a/tests/various/autoname.ys b/tests/various/autoname.ys new file mode 100644 index 000000000..830962e81 --- /dev/null +++ b/tests/various/autoname.ys @@ -0,0 +1,19 @@ +read_ilang < Date: Wed, 15 Jan 2020 14:36:05 -0800 Subject: abc9: aAdd test to check $_NOT_s are absorbed --- tests/techmap/abc9.ys | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'tests') diff --git a/tests/techmap/abc9.ys b/tests/techmap/abc9.ys index 20f263da8..62b5dfef6 100644 --- a/tests/techmap/abc9.ys +++ b/tests/techmap/abc9.ys @@ -38,3 +38,15 @@ abc9 -lut 4 design -load gold scratchpad -copy abc9.script.flow3 abc9.script abc9 -lut 4 + + +design -reset +read_verilog -icells < Date: Fri, 17 Jan 2020 15:38:26 -0800 Subject: ice40_dsp: add test --- tests/arch/ice40/ice40_dsp.ys | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 tests/arch/ice40/ice40_dsp.ys (limited to 'tests') diff --git a/tests/arch/ice40/ice40_dsp.ys b/tests/arch/ice40/ice40_dsp.ys new file mode 100644 index 000000000..250273859 --- /dev/null +++ b/tests/arch/ice40/ice40_dsp.ys @@ -0,0 +1,11 @@ +read_verilog < Date: Fri, 17 Jan 2020 15:57:52 -0800 Subject: Add #1644 testcase --- tests/arch/ice40/bug1644.il.gz | Bin 0 -> 25669 bytes tests/arch/ice40/bug1644.ys | 2 ++ 2 files changed, 2 insertions(+) create mode 100644 tests/arch/ice40/bug1644.il.gz create mode 100644 tests/arch/ice40/bug1644.ys (limited to 'tests') diff --git a/tests/arch/ice40/bug1644.il.gz b/tests/arch/ice40/bug1644.il.gz new file mode 100644 index 000000000..363c510ef Binary files /dev/null and b/tests/arch/ice40/bug1644.il.gz differ diff --git a/tests/arch/ice40/bug1644.ys b/tests/arch/ice40/bug1644.ys new file mode 100644 index 000000000..5950f0e3c --- /dev/null +++ b/tests/arch/ice40/bug1644.ys @@ -0,0 +1,2 @@ +read_ilang bug1644.il.gz +synth_ice40 -top top -dsp -json adc_dac_pass_through.json -run :map_bram -- cgit v1.2.3 From db68e4c2a7a39eda46863fba8b8c8313a831f606 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 17 Jan 2020 16:08:04 -0800 Subject: ice40_dsp: fix typo --- tests/arch/xilinx/xilinx_dsp.ys | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 tests/arch/xilinx/xilinx_dsp.ys (limited to 'tests') diff --git a/tests/arch/xilinx/xilinx_dsp.ys b/tests/arch/xilinx/xilinx_dsp.ys new file mode 100644 index 000000000..3b9f52930 --- /dev/null +++ b/tests/arch/xilinx/xilinx_dsp.ys @@ -0,0 +1,11 @@ +read_verilog < Date: Fri, 17 Jan 2020 17:07:03 -0800 Subject: xilinx_dsp: another typo; move xilinx specific test --- tests/arch/xilinx/bug1462.ys | 11 +++++++++++ tests/various/bug1462.ys | 11 ----------- 2 files changed, 11 insertions(+), 11 deletions(-) create mode 100644 tests/arch/xilinx/bug1462.ys delete mode 100644 tests/various/bug1462.ys (limited to 'tests') diff --git a/tests/arch/xilinx/bug1462.ys b/tests/arch/xilinx/bug1462.ys new file mode 100644 index 000000000..15cab5121 --- /dev/null +++ b/tests/arch/xilinx/bug1462.ys @@ -0,0 +1,11 @@ +read_verilog << EOF +module top(...); +input wire [31:0] A; +output wire [31:0] P; + +assign P = A * 32'h12300000; + +endmodule +EOF + +synth_xilinx diff --git a/tests/various/bug1462.ys b/tests/various/bug1462.ys deleted file mode 100644 index 15cab5121..000000000 --- a/tests/various/bug1462.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog << EOF -module top(...); -input wire [31:0] A; -output wire [31:0] P; - -assign P = A * 32'h12300000; - -endmodule -EOF - -synth_xilinx -- cgit v1.2.3 From cd8f55a91100b8dcf8b4775803cbacf70f5a998c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 21 Jan 2020 09:43:04 -0800 Subject: write_xaiger: fix for (* keep *) on flop output --- tests/various/abc9.ys | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'tests') diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys index 81d0afd1b..0c7695089 100644 --- a/tests/various/abc9.ys +++ b/tests/various/abc9.ys @@ -14,6 +14,7 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter + design -load read hierarchy -top abc9_test028 proc @@ -23,6 +24,7 @@ select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i select -assert-count 1 t:unknown select -assert-none t:$lut t:unknown %% t: %D + design -load read hierarchy -top abc9_test032 proc @@ -38,3 +40,16 @@ design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -seq 10 -verify -prove-asserts -show-ports miter + + +design -reset +read_verilog -icells < Date: Thu, 23 Jan 2020 18:53:14 -0800 Subject: abc_box_id -> abc9_box_id in test --- tests/simple_abc9/abc9.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 8afd0ce96..ee01ab5dc 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -213,7 +213,7 @@ module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encode input rst; endmodule -(* abc_box_id=1 *) +(* abc9_box_id=1 *) module MUXF8(input I0, I1, S, output O); endmodule -- cgit v1.2.3 From 11e50c0e9ecec6439d44064a0e1a016dc2b3188b Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 23 Jan 2020 18:56:25 -0800 Subject: Test for (* keep *)-ed abc9_box_id --- tests/simple_abc9/abc9.v | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'tests') diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index ee01ab5dc..52ccb3e1d 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -291,3 +291,19 @@ module abc9_test035(input clk, d, output reg [1:0] q); always @(posedge clk) q[0] <= d; always @(negedge clk) q[1] <= q[0]; endmodule + +module abc9_test036(input A, B, S, output [1:0] O); + (* keep *) + MUXF8 m ( + .I0(I0), + .I1(I1), + .O(O[0]), + .S(S) + ); + MUXF8 m2 ( + .I0(I0), + .I1(I1), + .O(O[1]), + .S(S) + ); +endmodule -- cgit v1.2.3 From e471b330ac6107c63f80baaba4fee7782e2dc396 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 23 Jan 2020 18:53:14 -0800 Subject: abc_box_id -> abc9_box_id in test --- tests/simple_abc9/abc9.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'tests') diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 8afd0ce96..ee01ab5dc 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -213,7 +213,7 @@ module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encode input rst; endmodule -(* abc_box_id=1 *) +(* abc9_box_id=1 *) module MUXF8(input I0, I1, S, output O); endmodule -- cgit v1.2.3 From dca1c806eca0219fb609acfd111fbf9073c6908f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 23 Jan 2020 19:55:11 -0800 Subject: simple_abc9 tests to discard whitebox before write for sim --- tests/simple_abc9/abc9.v | 2 +- tests/simple_abc9/run-test.sh | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 52ccb3e1d..e5837d480 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -213,7 +213,7 @@ module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encode input rst; endmodule -(* abc9_box_id=1 *) +(* abc9_box_id=1, whitebox *) module MUXF8(input I0, I1, S, output O); endmodule diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index bc921daa9..32d7a80ca 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -28,4 +28,5 @@ exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v *.sv EXTRA_FLAGS="-n 300 -p abc9 -lut 4 -box ../abc.box; \ clean; \ check -assert; \ - select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'" + select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%; \ + setattr -mod -unset whitebox'" -- cgit v1.2.3 From 2d795fb8c0546ed2b65ee75ffdfd769c48b1164c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 23 Jan 2020 19:55:11 -0800 Subject: simple_abc9 tests to discard whitebox before write for sim --- tests/simple_abc9/abc9.v | 2 +- tests/simple_abc9/run-test.sh | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index ee01ab5dc..4dc5ad689 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -213,7 +213,7 @@ module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encode input rst; endmodule -(* abc9_box_id=1 *) +(* abc9_box_id=1, whitebox *) module MUXF8(input I0, I1, S, output O); endmodule diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index bc921daa9..32d7a80ca 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -28,4 +28,5 @@ exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v *.sv EXTRA_FLAGS="-n 300 -p abc9 -lut 4 -box ../abc.box; \ clean; \ check -assert; \ - select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'" + select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%; \ + setattr -mod -unset whitebox'" -- cgit v1.2.3 From b1787615514f84c83c27d08011427e90c9bd0f4a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 24 Jan 2020 11:59:48 -0800 Subject: ice40: reduce ABC9 internal fanout warnings with a param for CI->I3 --- tests/arch/ice40/ice40_opt.ys | 27 ++++----------------------- 1 file changed, 4 insertions(+), 23 deletions(-) (limited to 'tests') diff --git a/tests/arch/ice40/ice40_opt.ys b/tests/arch/ice40/ice40_opt.ys index 5186d4800..011d98fef 100644 --- a/tests/arch/ice40/ice40_opt.ys +++ b/tests/arch/ice40/ice40_opt.ys @@ -1,23 +1,3 @@ -read_verilog -icells -formal < Date: Mon, 27 Jan 2020 13:56:16 -0800 Subject: Import tests from #1628 --- tests/arch/ice40/bug1597.ys | 72 +++++++++++++++++++++++++++++++++++++++++++ tests/arch/ice40/ice40_opt.ys | 30 ++++++++++++++++++ 2 files changed, 102 insertions(+) create mode 100644 tests/arch/ice40/bug1597.ys (limited to 'tests') diff --git a/tests/arch/ice40/bug1597.ys b/tests/arch/ice40/bug1597.ys new file mode 100644 index 000000000..b7983cfa4 --- /dev/null +++ b/tests/arch/ice40/bug1597.ys @@ -0,0 +1,72 @@ +read_verilog <