read_verilog dpram.v hierarchy -top top proc memory -nomap equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 memory opt -full miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter design -load postopt cd top select -assert-count 1 t:SB_RAM40_4K select -assert-none t:SB_RAM40_4K %% t:* %D on/atom+xml'/>
aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/ramips/dts/ALL5002.dts
blob: 7c23fe51754e87e5b8207d373a664f9d70a4109e (plain) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93