read_verilog muxpack.v design -save read hierarchy -top mux_if_unbal_4_1 prep design -save gold muxpack opt #stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter design -load read hierarchy -top mux_if_unbal_5_3 prep design -save gold muxpack opt #stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter # TODO: Currently ExclusiveDatabase only analyses $eq cells #design -load read #hierarchy -top mux_if_unbal_5_3_invert #prep #design -save gold #muxpack #opt #stat #select -assert-count 0 t:$mux #select -assert-count 1 t:$pmux #design -stash gate #design -import gold -as gold #design -import gate -as gate #miter -equiv -flatten -make_assert -make_outputs gold gate miter #sat -verify -prove-asserts -show-ports miter design -load read hierarchy -top mux_if_unbal_5_3_width_mismatch prep design -save gold muxpack opt #stat select -assert-count 0 t:$mux select -assert-count 2 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter design -load read hierarchy -top mux_if_unbal_4_1_missing prep design -save gold muxpack opt #stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter design -load read hierarchy -top mux_if_unbal_5_3_order prep design -save gold muxpack opt #stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter design -load read hierarchy -top mux_if_unbal_4_1_nonexcl prep design -save gold muxpack opt #stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter design -load read hierarchy -top mux_if_unbal_5_3_nonexcl prep design -save gold muxpack opt #stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter design -load read hierarchy -top mux_case_unbal_8_7 prep design -save gold muxpack opt #stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter design -load read hierarchy -top mux_if_bal_8_2 prep design -save gold muxpack opt #stat select -assert-count 7 t:$mux select -assert-count 0 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter design -load read hierarchy -top mux_if_bal_5_1 prep design -save gold muxpack opt #stat select -assert-count 4 t:$mux select -assert-count 0 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter design -load read hierarchy -top cliffordwolf_nonexclusive_select prep design -save gold muxpack opt #stat select -assert-count 3 t:$mux select -assert-count 0 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter #design -load read #hierarchy -top cliffordwolf_freduce #prep #design -save gold #proc; opt; freduce; opt #show #muxpack #opt #stat #select -assert-count 0 t:$mux #select -assert-count 1 t:$pmux #design -stash gate #design -import gold -as gold #design -import gate -as gate #miter -equiv -flatten -make_assert -make_outputs gold gate miter #sat -verify -prove-asserts -show-ports miter design -load read hierarchy -top case_nonexclusive_select prep design -save gold muxpack opt #stat select -assert-count 0 t:$mux select -assert-count 2 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter design -load read hierarchy -top case_nonoverlap #prep # Do not prep otherwise $pmux's overlapping entry will get removed proc design -save gold opt -fast -mux_undef select -assert-count 2 t:$pmux muxpack opt #stat select -assert-count 0 t:$mux select -assert-count 1 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter design -load read hierarchy -top case_overlap #prep # Do not prep otherwise $pmux's overlapping entry will get removed proc design -save gold opt -fast -mux_undef select -assert-count 2 t:$pmux muxpack opt #stat select -assert-count 0 t:$mux select -assert-count 2 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter design -load read hierarchy -top case_overlap2 #prep # Do not prep otherwise $pmux's overlapping entry will get removed proc design -save gold opt -fast -mux_undef select -assert-count 2 t:$pmux muxpack opt #stat select -assert-count 0 t:$mux select -assert-count 2 t:$pmux design -stash gate design -import gold -as gold design -import gate -as gate miter -equiv -flatten -make_assert -make_outputs gold gate miter sat -verify -prove-asserts -show-ports miter id='n112' href='#n112'>112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344