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<div class='path'>path: <a href='/cgit.cgi/iCE40/ghdl/tree/?id=e8b7ef1517e546b56d3a7ecf83bf242a1ac85d82'>root</a>/<a href='/cgit.cgi/iCE40/ghdl/tree/testsuite?id=e8b7ef1517e546b56d3a7ecf83bf242a1ac85d82'>testsuite</a>/<a href='/cgit.cgi/iCE40/ghdl/tree/testsuite/synth?id=e8b7ef1517e546b56d3a7ecf83bf242a1ac85d82'>synth</a>/<a href='/cgit.cgi/iCE40/ghdl/tree/testsuite/synth/issue1090?id=e8b7ef1517e546b56d3a7ecf83bf242a1ac85d82'>issue1090</a></div><div class='content'><table summary='tree listing' class='list'>
<tr class='nohover'><th class='left'>Mode</th><th class='left'>Name</th><th class='right'>Size</th><th/></tr>
<tr><td class='ls-mode'>-rw-r--r--</td><td><a class='ls-blob vhdl' href='/cgit.cgi/iCE40/ghdl/tree/testsuite/synth/issue1090/bootrom.vhdl?id=e8b7ef1517e546b56d3a7ecf83bf242a1ac85d82'>bootrom.vhdl</a></td><td class='ls-size'>442</td><td><a class='button' href='/cgit.cgi/iCE40/ghdl/log/testsuite/synth/issue1090/bootrom.vhdl?id=e8b7ef1517e546b56d3a7ecf83bf242a1ac85d82'>log</a><a class='button' href='/cgit.cgi/iCE40/ghdl/stats/testsuite/synth/issue1090/bootrom.vhdl'>stats</a><a class='button' href='/cgit.cgi/iCE40/ghdl/plain/testsuite/synth/issue1090/bootrom.vhdl?id=e8b7ef1517e546b56d3a7ecf83bf242a1ac85d82'>plain</a></td></tr>
<tr><td class='ls-mode'>-rw-r--r--</td><td><a class='ls-blob vhdl' href='/cgit.cgi/iCE40/ghdl/tree/testsuite/synth/issue1090/simple_ram-orig.vhdl?id=e8b7ef1517e546b56d3a7ecf83bf242a1ac85d82'>simple_ram-orig.vhdl</a></td><td class='ls-size'>1599</td><td><a class='button' href='/cgit.cgi/iCE40/ghdl/log/testsuite/synth/issue1090/simple_ram-orig.vhdl?id=e8b7ef1517e546b56d3a7ecf83bf242a1ac85d82'>log</a><a class='button' href='/cgit.cgi/iCE40/ghdl/stats/testsuite/synth/issue1090/simple_ram-orig.vhdl'>stats</a><a class='button' href='/cgit.cgi/iCE40/ghdl/plain/testsuite/synth/issue1090/simple_ram-orig.vhdl?id=e8b7ef1517e546b56d3a7ecf83bf242a1ac85d82'>plain</a></td></tr>
<tr><td class='ls-mode'>-rw-r--r--</td><td><a class='ls-blob vhdl' href='/cgit.cgi/iCE40/ghdl/tree/testsuite/synth/issue1090/simple_ram.vhdl?id=e8b7ef1517e546b56d3a7ecf83bf242a1ac85d82'>simple_ram.vhdl</a></td><td class='ls-size'>2035</td><td><a class='button' href='/cgit.cgi/iCE40/ghdl/log/testsuite/synth/issue1090/simple_ram.vhdl?id=e8b7ef1517e546b56d3a7ecf83bf242a1ac85d82'>log</a><a class='button' href='/cgit.cgi/iCE40/ghdl/stats/testsuite/synth/issue1090/simple_ram.vhdl'>stats</a><a class='button' href='/cgit.cgi/iCE40/ghdl/plain/testsuite/synth/issue1090/simple_ram.vhdl?id=e8b7ef1517e546b56d3a7ecf83bf242a1ac85d82'>plain</a></td></tr>
<tr><td class='ls-mode'>-rw-r--r--</td><td><a class='ls-blob vhdl' href='/cgit.cgi/iCE40/ghdl/tree/testsuite/synth/issue1090/tb_simple_ram.vhdl?id=e8b7ef1517e546b56d3a7ecf83bf242a1ac85d82'>tb_simple_ram.vhdl</a></td><td class='ls-size'>1062</td><td><a class='button' href='/cgit.cgi/iCE40/ghdl/log/testsuite/synth/issue1090/tb_simple_ram.vhdl?id=e8b7ef1517e546b56d3a7ecf83bf242a1ac85d82'>log</a><a class='button' href='/cgit.cgi/iCE40/ghdl/stats/testsuite/synth/issue1090/tb_simple_ram.vhdl'>stats</a><a class='button' href='/cgit.cgi/iCE40/ghdl/plain/testsuite/synth/issue1090/tb_simple_ram.vhdl?id=e8b7ef1517e546b56d3a7ecf83bf242a1ac85d82'>plain</a></td></tr>
<tr><td class='ls-mode'>-rwxr-xr-x</td><td><a class='ls-blob sh' href='/cgit.cgi/iCE40/ghdl/tree/testsuite/synth/issue1090/testsuite.sh?id=e8b7ef1517e546b56d3a7ecf83bf242a1ac85d82'>testsuite.sh</a></td><td class='ls-size'>286</td><td><a class='button' href='/cgit.cgi/iCE40/ghdl/log/testsuite/synth/issue1090/testsuite.sh?id=e8b7ef1517e546b56d3a7ecf83bf242a1ac85d82'>log</a><a class='button' href='/cgit.cgi/iCE40/ghdl/stats/testsuite/synth/issue1090/testsuite.sh'>stats</a><a class='button' href='/cgit.cgi/iCE40/ghdl/plain/testsuite/synth/issue1090/testsuite.sh?id=e8b7ef1517e546b56d3a7ecf83bf242a1ac85d82'>plain</a></td></tr>
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<a id='n382' href='#n382'>382</a>
<a id='n383' href='#n383'>383</a>
<a id='n384' href='#n384'>384</a>
<a id='n385' href='#n385'>385</a>
<a id='n386' href='#n386'>386</a>
<a id='n387' href='#n387'>387</a>
<a id='n388' href='#n388'>388</a>
<a id='n389' href='#n389'>389</a>
<a id='n390' href='#n390'>390</a>
<a id='n391' href='#n391'>391</a>
<a id='n392' href='#n392'>392</a>
<a id='n393' href='#n393'>393</a>
<a id='n394' href='#n394'>394</a>
<a id='n395' href='#n395'>395</a>
<a id='n396' href='#n396'>396</a>
<a id='n397' href='#n397'>397</a>
<a id='n398' href='#n398'>398</a>
<a id='n399' href='#n399'>399</a>
<a id='n400' href='#n400'>400</a>
<a id='n401' href='#n401'>401</a>
<a id='n402' href='#n402'>402</a>
<a id='n403' href='#n403'>403</a>
<a id='n404' href='#n404'>404</a>
<a id='n405' href='#n405'>405</a>
<a id='n406' href='#n406'>406</a>
<a id='n407' href='#n407'>407</a>
<a id='n408' href='#n408'>408</a>
<a id='n409' href='#n409'>409</a>
<a id='n410' href='#n410'>410</a>
<a id='n411' href='#n411'>411</a>
<a id='n412' href='#n412'>412</a>
<a id='n413' href='#n413'>413</a>
<a id='n414' href='#n414'>414</a>
<a id='n415' href='#n415'>415</a>
<a id='n416' href='#n416'>416</a>
<a id='n417' href='#n417'>417</a>
<a id='n418' href='#n418'>418</a>
<a id='n419' href='#n419'>419</a>
<a id='n420' href='#n420'>420</a>
<a id='n421' href='#n421'>421</a>
<a id='n422' href='#n422'>422</a>
<a id='n423' href='#n423'>423</a>
<a id='n424' href='#n424'>424</a>
<a id='n425' href='#n425'>425</a>
<a id='n426' href='#n426'>426</a>
<a id='n427' href='#n427'>427</a>
<a id='n428' href='#n428'>428</a>
<a id='n429' href='#n429'>429</a>
<a id='n430' href='#n430'>430</a>
<a id='n431' href='#n431'>431</a>
<a id='n432' href='#n432'>432</a>
<a id='n433' href='#n433'>433</a>
<a id='n434' href='#n434'>434</a>
<a id='n435' href='#n435'>435</a>
<a id='n436' href='#n436'>436</a>
<a id='n437' href='#n437'>437</a>
<a id='n438' href='#n438'>438</a>
<a id='n439' href='#n439'>439</a>
<a id='n440' href='#n440'>440</a>
<a id='n441' href='#n441'>441</a>
<a id='n442' href='#n442'>442</a>
<a id='n443' href='#n443'>443</a>
<a id='n444' href='#n444'>444</a>
<a id='n445' href='#n445'>445</a>
<a id='n446' href='#n446'>446</a>
<a id='n447' href='#n447'>447</a>
<a id='n448' href='#n448'>448</a>
<a id='n449' href='#n449'>449</a>
<a id='n450' href='#n450'>450</a>
<a id='n451' href='#n451'>451</a>
<a id='n452' href='#n452'>452</a>
<a id='n453' href='#n453'>453</a>
<a id='n454' href='#n454'>454</a>
<a id='n455' href='#n455'>455</a>
<a id='n456' href='#n456'>456</a>
<a id='n457' href='#n457'>457</a>
<a id='n458' href='#n458'>458</a>
<a id='n459' href='#n459'>459</a>
<a id='n460' href='#n460'>460</a>
<a id='n461' href='#n461'>461</a>
<a id='n462' href='#n462'>462</a>
<a id='n463' href='#n463'>463</a>
<a id='n464' href='#n464'>464</a>
<a id='n465' href='#n465'>465</a>
<a id='n466' href='#n466'>466</a>
<a id='n467' href='#n467'>467</a>
<a id='n468' href='#n468'>468</a>
<a id='n469' href='#n469'>469</a>
<a id='n470' href='#n470'>470</a>
<a id='n471' href='#n471'>471</a>
<a id='n472' href='#n472'>472</a>
<a id='n473' href='#n473'>473</a>
<a id='n474' href='#n474'>474</a>
<a id='n475' href='#n475'>475</a>
<a id='n476' href='#n476'>476</a>
<a id='n477' href='#n477'>477</a>
<a id='n478' href='#n478'>478</a>
<a id='n479' href='#n479'>479</a>
<a id='n480' href='#n480'>480</a>
<a id='n481' href='#n481'>481</a>
<a id='n482' href='#n482'>482</a>
<a id='n483' href='#n483'>483</a>
<a id='n484' href='#n484'>484</a>
<a id='n485' href='#n485'>485</a>
<a id='n486' href='#n486'>486</a>
<a id='n487' href='#n487'>487</a>
<a id='n488' href='#n488'>488</a>
<a id='n489' href='#n489'>489</a>
<a id='n490' href='#n490'>490</a>
<a id='n491' href='#n491'>491</a>
<a id='n492' href='#n492'>492</a>
<a id='n493' href='#n493'>493</a>
<a id='n494' href='#n494'>494</a>
<a id='n495' href='#n495'>495</a>
<a id='n496' href='#n496'>496</a>
<a id='n497' href='#n497'>497</a>
<a id='n498' href='#n498'>498</a>
<a id='n499' href='#n499'>499</a>
<a id='n500' href='#n500'>500</a>
<a id='n501' href='#n501'>501</a>
<a id='n502' href='#n502'>502</a>
<a id='n503' href='#n503'>503</a>
<a id='n504' href='#n504'>504</a>
<a id='n505' href='#n505'>505</a>
<a id='n506' href='#n506'>506</a>
<a id='n507' href='#n507'>507</a>
<a id='n508' href='#n508'>508</a>
<a id='n509' href='#n509'>509</a>
<a id='n510' href='#n510'>510</a>
<a id='n511' href='#n511'>511</a>
<a id='n512' href='#n512'>512</a>
<a id='n513' href='#n513'>513</a>
<a id='n514' href='#n514'>514</a>
<a id='n515' href='#n515'>515</a>
<a id='n516' href='#n516'>516</a>
<a id='n517' href='#n517'>517</a>
<a id='n518' href='#n518'>518</a>
<a id='n519' href='#n519'>519</a>
<a id='n520' href='#n520'>520</a>
<a id='n521' href='#n521'>521</a>
<a id='n522' href='#n522'>522</a>
<a id='n523' href='#n523'>523</a>
<a id='n524' href='#n524'>524</a>
<a id='n525' href='#n525'>525</a>
<a id='n526' href='#n526'>526</a>
<a id='n527' href='#n527'>527</a>
<a id='n528' href='#n528'>528</a>
<a id='n529' href='#n529'>529</a>
<a id='n530' href='#n530'>530</a>
<a id='n531' href='#n531'>531</a>
<a id='n532' href='#n532'>532</a>
<a id='n533' href='#n533'>533</a>
<a id='n534' href='#n534'>534</a>
<a id='n535' href='#n535'>535</a>
<a id='n536' href='#n536'>536</a>
<a id='n537' href='#n537'>537</a>
<a id='n538' href='#n538'>538</a>
<a id='n539' href='#n539'>539</a>
<a id='n540' href='#n540'>540</a>
<a id='n541' href='#n541'>541</a>
<a id='n542' href='#n542'>542</a>
<a id='n543' href='#n543'>543</a>
<a id='n544' href='#n544'>544</a>
<a id='n545' href='#n545'>545</a>
<a id='n546' href='#n546'>546</a>
<a id='n547' href='#n547'>547</a>
<a id='n548' href='#n548'>548</a>
<a id='n549' href='#n549'>549</a>
<a id='n550' href='#n550'>550</a>
<a id='n551' href='#n551'>551</a>
<a id='n552' href='#n552'>552</a>
<a id='n553' href='#n553'>553</a>
<a id='n554' href='#n554'>554</a>
<a id='n555' href='#n555'>555</a>
<a id='n556' href='#n556'>556</a>
<a id='n557' href='#n557'>557</a>
<a id='n558' href='#n558'>558</a>
<a id='n559' href='#n559'>559</a>
<a id='n560' href='#n560'>560</a>
<a id='n561' href='#n561'>561</a>
<a id='n562' href='#n562'>562</a>
<a id='n563' href='#n563'>563</a>
<a id='n564' href='#n564'>564</a>
<a id='n565' href='#n565'>565</a>
<a id='n566' href='#n566'>566</a>
<a id='n567' href='#n567'>567</a>
<a id='n568' href='#n568'>568</a>
<a id='n569' href='#n569'>569</a>
<a id='n570' href='#n570'>570</a>
<a id='n571' href='#n571'>571</a>
<a id='n572' href='#n572'>572</a>
<a id='n573' href='#n573'>573</a>
<a id='n574' href='#n574'>574</a>
<a id='n575' href='#n575'>575</a>
<a id='n576' href='#n576'>576</a>
<a id='n577' href='#n577'>577</a>
<a id='n578' href='#n578'>578</a>
<a id='n579' href='#n579'>579</a>
<a id='n580' href='#n580'>580</a>
<a id='n581' href='#n581'>581</a>
<a id='n582' href='#n582'>582</a>
<a id='n583' href='#n583'>583</a>
<a id='n584' href='#n584'>584</a>
<a id='n585' href='#n585'>585</a>
<a id='n586' href='#n586'>586</a>
<a id='n587' href='#n587'>587</a>
<a id='n588' href='#n588'>588</a>
<a id='n589' href='#n589'>589</a>
<a id='n590' href='#n590'>590</a>
<a id='n591' href='#n591'>591</a>
<a id='n592' href='#n592'>592</a>
<a id='n593' href='#n593'>593</a>
<a id='n594' href='#n594'>594</a>
<a id='n595' href='#n595'>595</a>
<a id='n596' href='#n596'>596</a>
<a id='n597' href='#n597'>597</a>
<a id='n598' href='#n598'>598</a>
<a id='n599' href='#n599'>599</a>
<a id='n600' href='#n600'>600</a>
<a id='n601' href='#n601'>601</a>
<a id='n602' href='#n602'>602</a>
<a id='n603' href='#n603'>603</a>
<a id='n604' href='#n604'>604</a>
<a id='n605' href='#n605'>605</a>
<a id='n606' href='#n606'>606</a>
<a id='n607' href='#n607'>607</a>
<a id='n608' href='#n608'>608</a>
<a id='n609' href='#n609'>609</a>
<a id='n610' href='#n610'>610</a>
<a id='n611' href='#n611'>611</a>
<a id='n612' href='#n612'>612</a>
<a id='n613' href='#n613'>613</a>
<a id='n614' href='#n614'>614</a>
<a id='n615' href='#n615'>615</a>
<a id='n616' href='#n616'>616</a>
<a id='n617' href='#n617'>617</a>
<a id='n618' href='#n618'>618</a>
<a id='n619' href='#n619'>619</a>
<a id='n620' href='#n620'>620</a>
<a id='n621' href='#n621'>621</a>
<a id='n622' href='#n622'>622</a>
<a id='n623' href='#n623'>623</a>
<a id='n624' href='#n624'>624</a>
<a id='n625' href='#n625'>625</a>
<a id='n626' href='#n626'>626</a>
<a id='n627' href='#n627'>627</a>
<a id='n628' href='#n628'>628</a>
<a id='n629' href='#n629'>629</a>
<a id='n630' href='#n630'>630</a>
<a id='n631' href='#n631'>631</a>
<a id='n632' href='#n632'>632</a>
<a id='n633' href='#n633'>633</a>
<a id='n634' href='#n634'>634</a>
<a id='n635' href='#n635'>635</a>
<a id='n636' href='#n636'>636</a>
<a id='n637' href='#n637'>637</a>
<a id='n638' href='#n638'>638</a>
<a id='n639' href='#n639'>639</a>
<a id='n640' href='#n640'>640</a>
<a id='n641' href='#n641'>641</a>
<a id='n642' href='#n642'>642</a>
<a id='n643' href='#n643'>643</a>
<a id='n644' href='#n644'>644</a>
<a id='n645' href='#n645'>645</a>
<a id='n646' href='#n646'>646</a>
<a id='n647' href='#n647'>647</a>
<a id='n648' href='#n648'>648</a>
<a id='n649' href='#n649'>649</a>
<a id='n650' href='#n650'>650</a>
<a id='n651' href='#n651'>651</a>
<a id='n652' href='#n652'>652</a>
<a id='n653' href='#n653'>653</a>
<a id='n654' href='#n654'>654</a>
<a id='n655' href='#n655'>655</a>
<a id='n656' href='#n656'>656</a>
<a id='n657' href='#n657'>657</a>
<a id='n658' href='#n658'>658</a>
<a id='n659' href='#n659'>659</a>
<a id='n660' href='#n660'>660</a>
<a id='n661' href='#n661'>661</a>
<a id='n662' href='#n662'>662</a>
<a id='n663' href='#n663'>663</a>
<a id='n664' href='#n664'>664</a>
<a id='n665' href='#n665'>665</a>
<a id='n666' href='#n666'>666</a>
<a id='n667' href='#n667'>667</a>
<a id='n668' href='#n668'>668</a>
<a id='n669' href='#n669'>669</a>
<a id='n670' href='#n670'>670</a>
<a id='n671' href='#n671'>671</a>
<a id='n672' href='#n672'>672</a>
<a id='n673' href='#n673'>673</a>
<a id='n674' href='#n674'>674</a>
<a id='n675' href='#n675'>675</a>
<a id='n676' href='#n676'>676</a>
<a id='n677' href='#n677'>677</a>
<a id='n678' href='#n678'>678</a>
<a id='n679' href='#n679'>679</a>
<a id='n680' href='#n680'>680</a>
<a id='n681' href='#n681'>681</a>
<a id='n682' href='#n682'>682</a>
<a id='n683' href='#n683'>683</a>
<a id='n684' href='#n684'>684</a>
<a id='n685' href='#n685'>685</a>
<a id='n686' href='#n686'>686</a>
<a id='n687' href='#n687'>687</a>
<a id='n688' href='#n688'>688</a>
<a id='n689' href='#n689'>689</a>
<a id='n690' href='#n690'>690</a>
<a id='n691' href='#n691'>691</a>
<a id='n692' href='#n692'>692</a>
<a id='n693' href='#n693'>693</a>
<a id='n694' href='#n694'>694</a>
<a id='n695' href='#n695'>695</a>
<a id='n696' href='#n696'>696</a>
<a id='n697' href='#n697'>697</a>
<a id='n698' href='#n698'>698</a>
<a id='n699' href='#n699'>699</a>
<a id='n700' href='#n700'>700</a>
<a id='n701' href='#n701'>701</a>
<a id='n702' href='#n702'>702</a>
<a id='n703' href='#n703'>703</a>
<a id='n704' href='#n704'>704</a>
<a id='n705' href='#n705'>705</a>
<a id='n706' href='#n706'>706</a>
<a id='n707' href='#n707'>707</a>
<a id='n708' href='#n708'>708</a>
<a id='n709' href='#n709'>709</a>
<a id='n710' href='#n710'>710</a>
<a id='n711' href='#n711'>711</a>
<a id='n712' href='#n712'>712</a>
<a id='n713' href='#n713'>713</a>
<a id='n714' href='#n714'>714</a>
<a id='n715' href='#n715'>715</a>
<a id='n716' href='#n716'>716</a>
<a id='n717' href='#n717'>717</a>
<a id='n718' href='#n718'>718</a>
<a id='n719' href='#n719'>719</a>
<a id='n720' href='#n720'>720</a>
<a id='n721' href='#n721'>721</a>
<a id='n722' href='#n722'>722</a>
<a id='n723' href='#n723'>723</a>
<a id='n724' href='#n724'>724</a>
<a id='n725' href='#n725'>725</a>
<a id='n726' href='#n726'>726</a>
<a id='n727' href='#n727'>727</a>
<a id='n728' href='#n728'>728</a>
<a id='n729' href='#n729'>729</a>
<a id='n730' href='#n730'>730</a>
<a id='n731' href='#n731'>731</a>
<a id='n732' href='#n732'>732</a>
<a id='n733' href='#n733'>733</a>
<a id='n734' href='#n734'>734</a>
<a id='n735' href='#n735'>735</a>
<a id='n736' href='#n736'>736</a>
<a id='n737' href='#n737'>737</a>
<a id='n738' href='#n738'>738</a>
<a id='n739' href='#n739'>739</a>
<a id='n740' href='#n740'>740</a>
<a id='n741' href='#n741'>741</a>
<a id='n742' href='#n742'>742</a>
<a id='n743' href='#n743'>743</a>
<a id='n744' href='#n744'>744</a>
<a id='n745' href='#n745'>745</a>
<a id='n746' href='#n746'>746</a>
<a id='n747' href='#n747'>747</a>
<a id='n748' href='#n748'>748</a>
<a id='n749' href='#n749'>749</a>
<a id='n750' href='#n750'>750</a>
<a id='n751' href='#n751'>751</a>
<a id='n752' href='#n752'>752</a>
<a id='n753' href='#n753'>753</a>
<a id='n754' href='#n754'>754</a>
<a id='n755' href='#n755'>755</a>
<a id='n756' href='#n756'>756</a>
<a id='n757' href='#n757'>757</a>
<a id='n758' href='#n758'>758</a>
<a id='n759' href='#n759'>759</a>
<a id='n760' href='#n760'>760</a>
<a id='n761' href='#n761'>761</a>
<a id='n762' href='#n762'>762</a>
<a id='n763' href='#n763'>763</a>
<a id='n764' href='#n764'>764</a>
<a id='n765' href='#n765'>765</a>
<a id='n766' href='#n766'>766</a>
<a id='n767' href='#n767'>767</a>
<a id='n768' href='#n768'>768</a>
<a id='n769' href='#n769'>769</a>
<a id='n770' href='#n770'>770</a>
<a id='n771' href='#n771'>771</a>
<a id='n772' href='#n772'>772</a>
<a id='n773' href='#n773'>773</a>
<a id='n774' href='#n774'>774</a>
<a id='n775' href='#n775'>775</a>
<a id='n776' href='#n776'>776</a>
<a id='n777' href='#n777'>777</a>
<a id='n778' href='#n778'>778</a>
<a id='n779' href='#n779'>779</a>
<a id='n780' href='#n780'>780</a>
<a id='n781' href='#n781'>781</a>
<a id='n782' href='#n782'>782</a>
<a id='n783' href='#n783'>783</a>
<a id='n784' href='#n784'>784</a>
<a id='n785' href='#n785'>785</a>
<a id='n786' href='#n786'>786</a>
<a id='n787' href='#n787'>787</a>
<a id='n788' href='#n788'>788</a>
<a id='n789' href='#n789'>789</a>
<a id='n790' href='#n790'>790</a>
<a id='n791' href='#n791'>791</a>
<a id='n792' href='#n792'>792</a>
<a id='n793' href='#n793'>793</a>
<a id='n794' href='#n794'>794</a>
<a id='n795' href='#n795'>795</a>
<a id='n796' href='#n796'>796</a>
<a id='n797' href='#n797'>797</a>
<a id='n798' href='#n798'>798</a>
<a id='n799' href='#n799'>799</a>
<a id='n800' href='#n800'>800</a>
<a id='n801' href='#n801'>801</a>
<a id='n802' href='#n802'>802</a>
<a id='n803' href='#n803'>803</a>
<a id='n804' href='#n804'>804</a>
<a id='n805' href='#n805'>805</a>
<a id='n806' href='#n806'>806</a>
<a id='n807' href='#n807'>807</a>
<a id='n808' href='#n808'>808</a>
<a id='n809' href='#n809'>809</a>
<a id='n810' href='#n810'>810</a>
<a id='n811' href='#n811'>811</a>
<a id='n812' href='#n812'>812</a>
<a id='n813' href='#n813'>813</a>
<a id='n814' href='#n814'>814</a>
<a id='n815' href='#n815'>815</a>
<a id='n816' href='#n816'>816</a>
<a id='n817' href='#n817'>817</a>
<a id='n818' href='#n818'>818</a>
<a id='n819' href='#n819'>819</a>
<a id='n820' href='#n820'>820</a>
<a id='n821' href='#n821'>821</a>
<a id='n822' href='#n822'>822</a>
<a id='n823' href='#n823'>823</a>
<a id='n824' href='#n824'>824</a>
<a id='n825' href='#n825'>825</a>
<a id='n826' href='#n826'>826</a>
<a id='n827' href='#n827'>827</a>
<a id='n828' href='#n828'>828</a>
<a id='n829' href='#n829'>829</a>
<a id='n830' href='#n830'>830</a>
<a id='n831' href='#n831'>831</a>
<a id='n832' href='#n832'>832</a>
<a id='n833' href='#n833'>833</a>
<a id='n834' href='#n834'>834</a>
<a id='n835' href='#n835'>835</a>
<a id='n836' href='#n836'>836</a>
<a id='n837' href='#n837'>837</a>
<a id='n838' href='#n838'>838</a>
<a id='n839' href='#n839'>839</a>
<a id='n840' href='#n840'>840</a>
<a id='n841' href='#n841'>841</a>
<a id='n842' href='#n842'>842</a>
<a id='n843' href='#n843'>843</a>
<a id='n844' href='#n844'>844</a>
<a id='n845' href='#n845'>845</a>
<a id='n846' href='#n846'>846</a>
<a id='n847' href='#n847'>847</a>
<a id='n848' href='#n848'>848</a>
<a id='n849' href='#n849'>849</a>
</pre></td>
<td class='lines'><pre><code><style>pre { line-height: 125%; margin: 0; }
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.highlight .vm { color: #336699 } /* Name.Variable.Magic */
.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */</style><div class="highlight"><pre><span></span><span class="k">\chapter</span><span class="nb">{</span>The Verilog and AST Frontends<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>chapter:verilog<span class="nb">}</span>

This chapter provides an overview of the implementation of the Yosys Verilog
and AST frontends. The Verilog frontend reads Verilog-2005 code and creates
an abstract syntax tree (AST) representation of the input. This AST representation
is then passed to the AST frontend that converts it to RTLIL data, as illustrated
in Fig.~<span class="k">\ref</span><span class="nb">{</span>fig:Verilog<span class="nb">_</span>flow<span class="nb">}</span>.

<span class="k">\begin</span><span class="nb">{</span>figure<span class="nb">}</span>[b!]
	<span class="k">\hfil</span>
	<span class="k">\begin</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>
		<span class="k">\tikzstyle</span><span class="nb">{</span>process<span class="nb">}</span> = [draw, fill=green!10, rectangle, minimum height=3em, minimum width=10em, node distance=5em, font=<span class="nb">{</span><span class="k">\ttfamily</span><span class="nb">}</span>]
		<span class="k">\tikzstyle</span><span class="nb">{</span>data<span class="nb">}</span> = [draw, fill=blue!10, ellipse, minimum height=3em, minimum width=7em, node distance=5em, font=<span class="nb">{</span><span class="k">\ttfamily</span><span class="nb">}</span>]

		<span class="k">\node</span><span class="na">[data]</span>    (n1)               <span class="nb">{</span>Verilog Source<span class="nb">}</span>;
		<span class="k">\node</span><span class="na">[process]</span> (n2) [below of=n1] <span class="nb">{</span>Verilog Frontend<span class="nb">}</span>;
		<span class="k">\node</span><span class="na">[data]</span>    (n3) [below of=n2] <span class="nb">{</span>AST<span class="nb">}</span>;
		<span class="k">\node</span><span class="na">[process]</span> (n4) [below of=n3] <span class="nb">{</span>AST Frontend<span class="nb">}</span>;
		<span class="k">\node</span><span class="na">[data]</span>    (n5) [below of=n4] <span class="nb">{</span>RTLIL<span class="nb">}</span>;

		<span class="k">\draw</span><span class="na">[-latex]</span> (n1) -- (n2);
		<span class="k">\draw</span><span class="na">[-latex]</span> (n2) -- (n3);
		<span class="k">\draw</span><span class="na">[-latex]</span> (n3) -- (n4);
		<span class="k">\draw</span><span class="na">[-latex]</span> (n4) -- (n5);

		<span class="k">\tikzstyle</span><span class="nb">{</span>details<span class="nb">}</span> = [draw, fill=yellow!5, rectangle, node distance=6cm, font=<span class="nb">{</span><span class="k">\ttfamily</span><span class="nb">}</span>]

		<span class="k">\node</span><span class="na">[details]</span> (d1) [right of=n2] <span class="nb">{</span><span class="k">\begin</span><span class="nb">{</span>minipage<span class="nb">}{</span>5cm<span class="nb">}</span>
			<span class="k">\hfil</span>
			<span class="k">\begin</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>
				<span class="k">\tikzstyle</span><span class="nb">{</span>subproc<span class="nb">}</span> = [draw, fill=green!10, rectangle, minimum height=2em, minimum width=10em, node distance=3em, font=<span class="nb">{</span><span class="k">\ttfamily</span><span class="nb">}</span>]
				<span class="k">\node</span> (s0) <span class="nb">{}</span>;
				<span class="k">\node</span><span class="na">[subproc]</span> (s1) [below of=s0] <span class="nb">{</span>Preprocessor<span class="nb">}</span>;
				<span class="k">\node</span><span class="na">[subproc]</span> (s2) [below of=s1] <span class="nb">{</span>Lexer<span class="nb">}</span>;
				<span class="k">\node</span><span class="na">[subproc]</span> (s3) [below of=s2] <span class="nb">{</span>Parser<span class="nb">}</span>;
				<span class="k">\node</span><span class="na">[node distance=3em]</span> (s4) [below of=s3] <span class="nb">{}</span>;
				<span class="k">\draw</span><span class="na">[-latex]</span> (s0) -- (s1);
				<span class="k">\draw</span><span class="na">[-latex]</span> (s1) -- (s2);
				<span class="k">\draw</span><span class="na">[-latex]</span> (s2) -- (s3);
				<span class="k">\draw</span><span class="na">[-latex]</span> (s3) -- (s4);
			<span class="k">\end</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>
		<span class="k">\end</span><span class="nb">{</span>minipage<span class="nb">}}</span>;

		<span class="k">\draw</span><span class="na">[dashed]</span> (n2.north east) -- (d1.north west);
		<span class="k">\draw</span><span class="na">[dashed]</span> (n2.south east) -- (d1.south west);

		<span class="k">\node</span><span class="na">[details]</span> (d2) [right of=n4] <span class="nb">{</span><span class="k">\begin</span><span class="nb">{</span>minipage<span class="nb">}{</span>5cm<span class="nb">}</span>
			<span class="k">\hfil</span>
			<span class="k">\begin</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>
				<span class="k">\tikzstyle</span><span class="nb">{</span>subproc<span class="nb">}</span> = [draw, fill=green!10, rectangle, minimum height=2em, minimum width=10em, node distance=3em, font=<span class="nb">{</span><span class="k">\ttfamily</span><span class="nb">}</span>]
				<span class="k">\node</span> (s0) <span class="nb">{}</span>;
				<span class="k">\node</span><span class="na">[subproc]</span> (s1) [below of=s0] <span class="nb">{</span>Simplifier<span class="nb">}</span>;
				<span class="k">\node</span><span class="na">[subproc]</span> (s2) [below of=s1] <span class="nb">{</span>RTLIL Generator<span class="nb">}</span>;
				<span class="k">\node</span><span class="na">[node distance=3em]</span> (s3) [below of=s2] <span class="nb">{}</span>;
				<span class="k">\draw</span><span class="na">[-latex]</span> (s0) -- (s1);
				<span class="k">\draw</span><span class="na">[-latex]</span> (s1) -- (s2);
				<span class="k">\draw</span><span class="na">[-latex]</span> (s2) -- (s3);
			<span class="k">\end</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>
		<span class="k">\end</span><span class="nb">{</span>minipage<span class="nb">}}</span>;

		<span class="k">\draw</span><span class="na">[dashed]</span> (n4.north east) -- (d2.north west);
		<span class="k">\draw</span><span class="na">[dashed]</span> (n4.south east) -- (d2.south west);

	<span class="k">\end</span><span class="nb">{</span>tikzpicture<span class="nb">}</span>
	<span class="k">\caption</span><span class="nb">{</span>Simplified Verilog to RTLIL data flow<span class="nb">}</span>
	<span class="k">\label</span><span class="nb">{</span>fig:Verilog<span class="nb">_</span>flow<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>figure<span class="nb">}</span>


<span class="k">\section</span><span class="nb">{</span>Transforming Verilog to AST<span class="nb">}</span>

The <span class="nb">{</span><span class="k">\it</span> Verilog frontend<span class="nb">}</span> converts the Verilog sources to an internal AST representation that closely resembles
the structure of the original Verilog code. The Verilog frontend consists of three components, the
<span class="nb">{</span><span class="k">\it</span> Preprocessor<span class="nb">}</span>, the <span class="nb">{</span><span class="k">\it</span> Lexer<span class="nb">}</span> and the <span class="nb">{</span><span class="k">\it</span> Parser<span class="nb">}</span>.

The source code to the Verilog frontend can be found in <span class="nb">{</span><span class="k">\tt</span> frontends/verilog/<span class="nb">}</span> in the Yosys source tree.

<span class="k">\subsection</span><span class="nb">{</span>The Verilog Preprocessor<span class="nb">}</span>

The Verilog preprocessor scans over the Verilog source code and interprets some of the Verilog compiler
directives such as <span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>`include<span class="nb">}</span>, <span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>`define<span class="nb">}</span> and
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>`ifdef<span class="nb">}</span>.

It is implemented as a C++ function that is passed a file descriptor as input and returns the
pre-processed Verilog code as a <span class="k">\lstinline</span><span class="na">[language=C++]</span><span class="nb">{</span>std::string<span class="nb">}</span>.

The source code to the Verilog Preprocessor can be found in <span class="nb">{</span><span class="k">\tt</span>
frontends/verilog/preproc.cc<span class="nb">}</span> in the Yosys source tree.

<span class="k">\subsection</span><span class="nb">{</span>The Verilog Lexer<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>sloppypar<span class="nb">}</span>
The Verilog Lexer is written using the lexer generator <span class="nb">{</span><span class="k">\it</span> flex<span class="nb">}</span> <span class="k">\citeweblink</span><span class="nb">{</span>flex<span class="nb">}</span>. Its source code
can be found in <span class="nb">{</span><span class="k">\tt</span> frontends/verilog/lexer.l<span class="nb">}</span> in the Yosys source tree.
The lexer does little more than identifying all keywords and literals
recognised by the Yosys Verilog frontend.
<span class="k">\end</span><span class="nb">{</span>sloppypar<span class="nb">}</span>

The lexer keeps track of the current location in the Verilog source code using
some global variables. These variables are used by the constructor of AST nodes
to annotate each node with the source code location it originated from.

<span class="k">\begin</span><span class="nb">{</span>sloppypar<span class="nb">}</span>
Finally the lexer identifies and handles special comments such as
``<span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>// synopsys translate<span class="nb">_</span>off<span class="nb">}</span>&#39;&#39; and
``<span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>// synopsys full<span class="nb">_</span>case<span class="nb">}</span>&#39;&#39;. (It is recommended to
use <span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>`ifdef<span class="nb">}</span> constructs instead of the Synsopsys
translate<span class="k">\_</span>on/off comments and attributes such as
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>(* full<span class="nb">_</span>case *)<span class="nb">}</span> over ``<span class="k">\lstinline</span><span class="na">[language=Verilog]</span><span class="nb">{</span>// synopsys full<span class="nb">_</span>case<span class="nb">}</span>&#39;&#39;
whenever possible.)
<span class="k">\end</span><span class="nb">{</span>sloppypar<span class="nb">}</span>

<span class="k">\subsection</span><span class="nb">{</span>The Verilog Parser<span class="nb">}</span>

The Verilog Parser is written using the parser generator <span class="nb">{</span><span class="k">\it</span> bison<span class="nb">}</span> <span class="k">\citeweblink</span><span class="nb">{</span>bison<span class="nb">}</span>. Its source code
can be found in <span class="nb">{</span><span class="k">\tt</span> frontends/verilog/parser.y<span class="nb">}</span> in the Yosys source tree.

It generates an AST using the <span class="k">\lstinline</span><span class="na">[language=C++]</span><span class="nb">{</span>AST::AstNode<span class="nb">}</span> data structure
defined in <span class="nb">{</span><span class="k">\tt</span> frontends/ast/ast.h<span class="nb">}</span>. An <span class="k">\lstinline</span><span class="na">[language=C++]</span><span class="nb">{</span>AST::AstNode<span class="nb">}</span> object has
the following properties:

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\begin</span><span class="nb">{</span>table<span class="nb">}</span>[b!]
<span class="k">\hfil</span>
<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}{</span>&gt;<span class="nb">{</span><span class="k">\raggedright\arraybackslash</span><span class="nb">}</span>p<span class="nb">{</span>7cm<span class="nb">}</span>&gt;<span class="nb">{</span><span class="k">\raggedright\arraybackslash</span><span class="nb">}</span>p<span class="nb">{</span>8cm<span class="nb">}}</span>
AST Node Type <span class="nb">&amp;</span> Corresponding Verilog Construct <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\hline</span>
<span class="k">\arrayrulecolor</span><span class="nb">{</span>gray<span class="nb">}</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>NONE<span class="nb">}</span> <span class="nb">&amp;</span> This Node type should never be used. <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>DESIGN<span class="nb">}</span> <span class="nb">&amp;</span> This node type is used for the top node of the AST tree. It
has no corresponding Verilog construct. <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>MODULE<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>TASK<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>FUNCTION<span class="nb">}</span> <span class="nb">&amp;</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;module;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;task; and
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;function; <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>WIRE<span class="nb">}</span> <span class="nb">&amp;</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;input;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;output;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;wire;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;reg; and
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;integer; <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>MEMORY<span class="nb">}</span>  <span class="nb">&amp;</span>
Verilog Arrays <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>AUTOWIRE<span class="nb">}</span> <span class="nb">&amp;</span>
Created by the simplifier when an undeclared signal name is used. <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>PARAMETER<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>LOCALPARAM<span class="nb">}</span> <span class="nb">&amp;</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;parameter; and
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;localparam; <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>PARASET<span class="nb">}</span> <span class="nb">&amp;</span>
Parameter set in cell instantiation <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>ARGUMENT<span class="nb">}</span> <span class="nb">&amp;</span>
Port connection in cell instantiation <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>RANGE<span class="nb">}</span> <span class="nb">&amp;</span>
Bit-Index in a signal or element index in array <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>CONSTANT<span class="nb">}</span> <span class="nb">&amp;</span>
A literal value <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>CELLTYPE<span class="nb">}</span> <span class="nb">&amp;</span>
The type of cell in cell instantiation <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>IDENTIFIER<span class="nb">}</span> <span class="nb">&amp;</span>
An Identifier (signal name in expression or cell/task/etc. name in other contexts) <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>PREFIX<span class="nb">}</span> <span class="nb">&amp;</span>
Construct an identifier in the form <span class="nb">{</span><span class="k">\tt</span> &lt;prefix&gt;[&lt;index&gt;].&lt;suffix&gt;<span class="nb">}</span> (used only in
advanced generate constructs) <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>FCALL<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>TCALL<span class="nb">}</span> <span class="nb">&amp;</span>
Call to function or task <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>TO<span class="k">\_</span>SIGNED<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>TO<span class="k">\_</span>UNSIGNED<span class="nb">}</span> <span class="nb">&amp;</span>
The <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;<span class="s">$</span><span class="nb">signed</span><span class="o">()</span><span class="nb">; and</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">;</span><span class="s">$</span>unsigned(); functions <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span>AST node types with their corresponding Verilog constructs. <span class="k">\\</span> (continued on next page)<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>tab:Verilog<span class="nb">_</span>AstNodeType<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>table<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>table<span class="nb">}</span>[t!]
<span class="k">\ContinuedFloat</span>
<span class="k">\hfil</span>
<span class="k">\begin</span><span class="nb">{</span>tabular<span class="nb">}{</span>&gt;<span class="nb">{</span><span class="k">\raggedright\arraybackslash</span><span class="nb">}</span>p<span class="nb">{</span>7cm<span class="nb">}</span>&gt;<span class="nb">{</span><span class="k">\raggedright\arraybackslash</span><span class="nb">}</span>p<span class="nb">{</span>8cm<span class="nb">}}</span>
AST Node Type <span class="nb">&amp;</span> Corresponding Verilog Construct <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\hline</span>
<span class="k">\arrayrulecolor</span><span class="nb">{</span>gray<span class="nb">}</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>CONCAT<span class="nb">}</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>REPLICATE<span class="nb">}</span> <span class="nb">&amp;</span>
The <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;<span class="nb">{</span>...<span class="nb">}</span>; and
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;<span class="nb">{</span>...<span class="nb">{</span>...<span class="nb">}}</span>; operators <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>BIT<span class="k">\_</span>NOT<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>BIT<span class="k">\_</span>AND<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>BIT<span class="k">\_</span>OR<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>BIT<span class="k">\_</span>XOR<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>BIT<span class="k">\_</span>XNOR<span class="nb">}</span> <span class="nb">&amp;</span>
The bitwise operators <span class="k">\break</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;~;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;<span class="nb">&amp;</span>;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;|;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;<span class="nb">^</span>; and
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;~<span class="nb">^</span>; <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>REDUCE<span class="k">\_</span>AND<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>REDUCE<span class="k">\_</span>OR<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>REDUCE<span class="k">\_</span>XOR<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>REDUCE<span class="k">\_</span>XNOR<span class="nb">}</span> <span class="nb">&amp;</span>
The unary reduction operators <span class="k">\break</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;~;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;<span class="nb">&amp;</span>;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;|;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;<span class="nb">^</span>; and
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;~<span class="nb">^</span>; <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>REDUCE<span class="k">\_</span>BOOL<span class="nb">}</span> <span class="nb">&amp;</span>
Conversion from multi-bit value to boolean value
(equivalent to <span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>REDUCE<span class="k">\_</span>OR<span class="nb">}</span>) <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>SHIFT<span class="k">\_</span>LEFT<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>SHIFT<span class="k">\_</span>RIGHT<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>SHIFT<span class="k">\_</span>SLEFT<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>SHIFT<span class="k">\_</span>SRIGHT<span class="nb">}</span> <span class="nb">&amp;</span>
The shift operators <span class="k">\break</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;&lt;&lt;;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;&gt;&gt;;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;&lt;&lt;&lt;; and
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;&gt;&gt;&gt;; <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>LT<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>LE<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>EQ<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>NE<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>GE<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>GT<span class="nb">}</span> <span class="nb">&amp;</span>
The relational operators <span class="k">\break</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;&lt;;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;&lt;=;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;==;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;!=;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;&gt;=; and
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;&gt;; <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>ADD<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>SUB<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>MUL<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>DIV<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>MOD<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>POW<span class="nb">}</span> <span class="nb">&amp;</span>
The binary operators <span class="k">\break</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;+;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;-;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;*;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;/;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;<span class="c">%; and</span>
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;**; <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>POS<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>NEG<span class="nb">}</span> <span class="nb">&amp;</span>
The prefix operators
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;+; and
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;-; <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>LOGIC<span class="k">\_</span>AND<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>LOGIC<span class="k">\_</span>OR<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>LOGIC<span class="k">\_</span>NOT<span class="nb">}</span> <span class="nb">&amp;</span>
The logic operators
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;<span class="nb">&amp;&amp;</span>;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;||; and
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;!; <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>TERNARY<span class="nb">}</span> <span class="nb">&amp;</span>
The ternary <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;?:;-operator <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>MEMRD<span class="nb">}</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>MEMWR<span class="nb">}</span> <span class="nb">&amp;</span>
Read and write memories. These nodes are generated by
the AST simplifier for writes/reads to/from Verilog arrays. <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>ASSIGN<span class="nb">}</span> <span class="nb">&amp;</span>
An <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;assign; statement <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>CELL<span class="nb">}</span> <span class="nb">&amp;</span>
A cell instantiation <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>PRIMITIVE<span class="nb">}</span> <span class="nb">&amp;</span>
A primitive cell (<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;and;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;nand;,
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;or;, etc.) <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>ALWAYS<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>INITIAL<span class="nb">}</span> <span class="nb">&amp;</span>
Verilog <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;always;- and <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;initial;-blocks <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>BLOCK<span class="nb">}</span> <span class="nb">&amp;</span>
A <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;begin;-<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;end;-block <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>ASSIGN<span class="k">\_</span>EQ<span class="nb">}</span>.
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>ASSIGN<span class="k">\_</span>LE<span class="nb">}</span> <span class="nb">&amp;</span>
Blocking (<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;=;) and nonblocking (<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;&lt;=;)
assignments within an <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;always;- or <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;initial;-block <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>CASE<span class="nb">}</span>.
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>COND<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>DEFAULT<span class="nb">}</span> <span class="nb">&amp;</span>
The <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;case; (<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;if;) statements, conditions within a case
and the default case respectively <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>FOR<span class="nb">}</span> <span class="nb">&amp;</span>
A <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;for;-loop with an
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;always;- or
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;initial;-block <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>GENVAR<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>GENBLOCK<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>GENFOR<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>GENIF<span class="nb">}</span> <span class="nb">&amp;</span>
The <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;genvar; and
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;generate; keywords and
<span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;for; and <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;if; within a
generate block. <span class="k">\\</span>
<span class="k">\hline</span>
<span class="c">%</span>
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>POSEDGE<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>NEGEDGE<span class="nb">}</span>,
<span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>EDGE<span class="nb">}</span> <span class="nb">&amp;</span>
Event conditions for <span class="k">\lstinline</span><span class="na">[language=Verilog]</span>;always; blocks. <span class="k">\\</span>
<span class="k">\hline</span>
<span class="k">\end</span><span class="nb">{</span>tabular<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span>AST node types with their corresponding Verilog constructs. <span class="k">\\</span> (continuation from previous page)<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>tab:Verilog<span class="nb">_</span>AstNodeTypeCont<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>table<span class="nb">}</span>

<span class="c">%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%</span>

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> <span class="nb">{</span><span class="k">\bf</span> The node type<span class="nb">}</span> <span class="k">\\</span>
This enum (<span class="k">\lstinline</span><span class="na">[language=C++]</span><span class="nb">{</span>AST::AstNodeType<span class="nb">}</span>) specifies the role of the node.
Table~<span class="k">\ref</span><span class="nb">{</span>tab:Verilog<span class="nb">_</span>AstNodeType<span class="nb">}</span> contains a list of all node types.
<span class="k">\item</span> <span class="nb">{</span><span class="k">\bf</span> The child nodes<span class="nb">}</span> <span class="k">\\</span>
This is a list of pointers to all children in the abstract syntax tree.
<span class="k">\item</span> <span class="nb">{</span><span class="k">\bf</span> Attributes<span class="nb">}</span> <span class="k">\\</span>
As almost every AST node might have Verilog attributes assigned to it, the
<span class="k">\lstinline</span><span class="na">[language=C++]</span><span class="nb">{</span>AST::AstNode<span class="nb">}</span> has direct support for attributes. Note that the
attribute values are again AST nodes.
<span class="k">\item</span> <span class="nb">{</span><span class="k">\bf</span> Node content<span class="nb">}</span> <span class="k">\\</span>
Each node might have additional content data. A series of member variables exist to hold such data.
For example the member <span class="k">\lstinline</span><span class="na">[language=C++]</span><span class="nb">{</span>std::string str<span class="nb">}</span> can hold a string value and is
used e.g.~in the <span class="nb">{</span><span class="k">\tt</span> AST<span class="k">\_</span>IDENTIFIER<span class="nb">}</span> node type to store the identifier name.
<span class="k">\item</span> <span class="nb">{</span><span class="k">\bf</span> Source code location<span class="nb">}</span> <span class="k">\\</span>
Each <span class="k">\lstinline</span><span class="na">[language=C++]</span><span class="nb">{</span>AST::AstNode<span class="nb">}</span> is automatically annotated with the current
source code location by the <span class="k">\lstinline</span><span class="na">[language=C++]</span><span class="nb">{</span>AST::AstNode<span class="nb">}</span> constructor. It is
stored in the <span class="k">\lstinline</span><span class="na">[language=C++]</span><span class="nb">{</span>std::string filename<span class="nb">}</span> and <span class="k">\lstinline</span><span class="na">[language=C++]</span><span class="nb">{</span>int linenum<span class="nb">}</span>
member variables.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

The <span class="k">\lstinline</span><span class="na">[language=C++]</span><span class="nb">{</span>AST::AstNode<span class="nb">}</span> constructor can be called with up to
two child nodes that are automatically added to the list of child nodes for the new object.
This simplifies the creation of AST nodes for simple expressions a bit. For example the bison
code for parsing multiplications:

<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[numbers=left,frame=single]
        basic<span class="nb">_</span>expr &#39;*&#39; attr basic<span class="nb">_</span>expr <span class="nb">{</span>
                <span class="sb">$$</span><span class="nb"> </span><span class="o">=</span><span class="nb"> new AstNode</span><span class="o">(</span><span class="nb">AST_MUL, $</span><span class="m">1</span><span class="nb">, $</span><span class="m">4</span><span class="o">)</span><span class="nb">;</span>
<span class="nb">                append_attr</span><span class="o">(</span><span class="s">$$</span>, <span class="s">$</span><span class="m">3</span><span class="o">)</span><span class="nb">;</span>
<span class="nb">        } |</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nb">The generated AST data structure is then passed directly to the AST frontend</span>
<span class="nb">that performs the actual conversion to RTLIL.</span>

<span class="nb">Note that the Yosys command {</span><span class="nv">\tt</span><span class="nb"> read</span><span class="nv">\_</span><span class="nb">verilog} provides the options {</span><span class="nv">\tt</span><span class="nb"> </span><span class="o">-</span><span class="nb">yydebug}</span>
<span class="nb">and {</span><span class="nv">\tt</span><span class="nb"> </span><span class="o">-</span><span class="nb">dump</span><span class="nv">\_</span><span class="nb">ast} that can be used to print the parse tree or abstract syntax tree</span>
<span class="nb">respectively.</span>

<span class="nv">\section</span><span class="nb">{Transforming AST to RTLIL}</span>

<span class="nb">The {</span><span class="nv">\it</span><span class="nb"> AST Frontend} converts a set of modules in AST representation to</span>
<span class="nb">modules in RTLIL representation and adds them to the current design. This is done</span>
<span class="nb">in two steps: {</span><span class="nv">\it</span><span class="nb"> simplification} and {</span><span class="nv">\it</span><span class="nb"> RTLIL generation}.</span>

<span class="nb">The source code to the AST frontend can be found in {</span><span class="nv">\tt</span><span class="nb"> frontends</span><span class="o">/</span><span class="nb">ast</span><span class="o">/</span><span class="nb">} in the Yosys source tree.</span>

<span class="nv">\subsection</span><span class="nb">{AST Simplification}</span>

<span class="nb">A full</span><span class="o">-</span><span class="nb">featured AST is too complex to be transformed into RTLIL directly. Therefore it must</span>
<span class="nb">first be brought into a simpler form. This is done by calling the </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{AST::AstNode::simplify</span><span class="o">()</span><span class="nb">}</span>
<span class="nb">method of all {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">MODULE} nodes in the AST. This initiates a recursive process that performs the following transformations</span>
<span class="nb">on the AST data structure:</span>

<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Inline all task and function calls.</span>
<span class="nv">\item</span><span class="nb"> Evaluate all </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">{generate}</span><span class="o">-</span><span class="nb">statements and unroll all </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">{for}</span><span class="o">-</span><span class="nb">loops.</span>
<span class="nv">\item</span><span class="nb"> Perform const folding where it is necessary </span><span class="o">(</span><span class="nb">e.g.~in the value part of {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">PARAMETER}, {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">LOCALPARAM},</span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">PARASET} and {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">RANGE} nodes</span><span class="o">)</span><span class="nb">.</span>
<span class="nv">\item</span><span class="nb"> Replace {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">PRIMITIVE} nodes with appropriate {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">ASSIGN} nodes.</span>
<span class="nv">\item</span><span class="nb"> Replace dynamic bit ranges in the left</span><span class="o">-</span><span class="nb">hand</span><span class="o">-</span><span class="nb">side of assignments with {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">CASE} nodes with {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">COND} children</span>
<span class="nb">for each possible case.</span>
<span class="nv">\item</span><span class="nb"> Detect array access patterns that are too complicated for the {</span><span class="nv">\tt</span><span class="nb"> RTLIL::Memory} abstraction and replace them</span>
<span class="nb">with a set of signals and cases for all reads and</span><span class="o">/</span><span class="nb">or writes.</span>
<span class="nv">\item</span><span class="nb"> Otherwise replace array accesses with {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">MEMRD} and {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">MEMWR} nodes.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>

<span class="nb">In addition to these transformations, the simplifier also annotates the AST with additional information that is needed</span>
<span class="nb">for the RTLIL generator, namely:</span>

<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> All ranges </span><span class="o">(</span><span class="nb">width of signals and bit selections</span><span class="o">)</span><span class="nb"> are not only const folded but </span><span class="o">(</span><span class="nb">when a constant value</span>
<span class="nb">is found</span><span class="o">)</span><span class="nb"> are also written to member variables in the {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">RANGE} node.</span>
<span class="nv">\item</span><span class="nb"> All identifiers are resolved and all {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">IDENTIFIER} nodes are annotated with a pointer to the AST node</span>
<span class="nb">that contains the declaration of the identifier. If no declaration has been found, an {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">AUTOWIRE} node</span>
<span class="nb">is created and used for the annotation.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>

<span class="nb">This produces an AST that is fairly easy to convert to the RTLIL format.</span>

<span class="nv">\subsection</span><span class="nb">{Generating RTLIL}</span>

<span class="nb">After AST simplification, the </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{AST::AstNode::genRTLIL</span><span class="o">()</span><span class="nb">} method of each {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">MODULE} node</span>
<span class="nb">in the AST is called. This initiates a recursive process that generates equivalent RTLIL data for the AST data.</span>

<span class="nb">The </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{AST::AstNode::genRTLIL</span><span class="o">()</span><span class="nb">} method returns an </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::SigSpec} structure.</span>
<span class="nb">For nodes that represent expressions </span><span class="o">(</span><span class="nb">operators, constants, signals, etc.</span><span class="o">)</span><span class="nb">, the cells needed to implement the calculation</span>
<span class="nb">described by the expression are created and the resulting signal is returned. That way it is easy to generate the circuits</span>
<span class="nb">for large expressions using depth</span><span class="o">-</span><span class="nb">first recursion. For nodes that do not represent an expression </span><span class="o">(</span><span class="nb">such as {</span><span class="nv">\tt</span><span class="nb"></span>
<span class="nb">AST</span><span class="nv">\_</span><span class="nb">CELL}</span><span class="o">)</span><span class="nb">, the corresponding circuit is generated and an empty </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::SigSpec} is returned.</span>

<span class="nv">\section</span><span class="nb">{Synthesizing Verilog always Blocks}</span>

<span class="nb">For behavioural Verilog code </span><span class="o">(</span><span class="nb">code utilizing </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">{always}</span><span class="o">-</span><span class="nb"> and</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">{initial}</span><span class="o">-</span><span class="nb">blocks</span><span class="o">)</span><span class="nb"> it is necessary to also generate </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::Process}</span>
<span class="nb">objects. This is done in the following way:</span>

<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Whenever </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{AST::AstNode::genRTLIL</span><span class="o">()</span><span class="nb">} encounters an </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">{always}</span><span class="o">-</span><span class="nb"></span>
<span class="nb">or </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">{initial}</span><span class="o">-</span><span class="nb">block, it creates an instance of</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">{AST_INTERNAL::ProcessGenerator}. This object then generates the</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::Process} object for the block. It also calls </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{AST::AstNode::genRTLIL</span><span class="o">()</span><span class="nb">}</span>
<span class="nb">for all right</span><span class="o">-</span><span class="nb">hand</span><span class="o">-</span><span class="nb">side expressions contained within the block.</span>
<span class="c">%</span>
<span class="nv">\begin</span><span class="nb">{sloppypar}</span>
<span class="nv">\item</span><span class="nb"> First the  </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">{AST_INTERNAL::ProcessGenerator} creates a list of all signals assigned</span>
<span class="nb">within the block. It then creates a set of temporary signals using the naming scheme {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$\it</span><span class="nb">&lt;number&gt;</span><span class="nv">\tt</span><span class="nb"></span>
<span class="nv">\textbackslash\it</span><span class="nb"> &lt;original</span><span class="nv">\_</span><span class="nb">name&gt;} for each of the assigned signals.</span>
<span class="nv">\end</span><span class="nb">{sloppypar}</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> Then an </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::Process} is created that assigns all intermediate values for each left</span><span class="o">-</span><span class="nb">hand</span><span class="o">-</span><span class="nb">side</span>
<span class="nb">signal to the temporary signal in its </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::CaseRule}</span><span class="o">/</span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::SwitchRule} tree.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> Finally a </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::SyncRule} is created for the </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::Process} that</span>
<span class="nb">assigns the temporary signals for the final values to the actual signals.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> Calls to </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{AST::AstNode::genRTLIL</span><span class="o">()</span><span class="nb">} are generated for right hand sides as needed. When blocking</span>
<span class="nb">assignments are used, </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{AST::AstNode::genRTLIL</span><span class="o">()</span><span class="nb">} is configured using global variables to use</span>
<span class="nb">the temporary signals that hold the correct intermediate values whenever one of the previously assigned signals is used</span>
<span class="nb">in an expression.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>

<span class="nb">Unfortunately the generation of a correct </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::CaseRule}</span><span class="o">/</span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::SwitchRule}</span>
<span class="nb">tree for behavioural code is a non</span><span class="o">-</span><span class="nb">trivial task. The AST frontend solves the problem using the approach described on the following</span>
<span class="nb">pages. The following example illustrates what the algorithm is supposed to do. Consider the following Verilog code:</span>

<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single,language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb"></span>
<span class="nb">always @</span><span class="o">(</span><span class="nb">posedge clock</span><span class="o">)</span><span class="nb"> begin</span>
<span class="nb">	out</span><span class="m">1</span><span class="nb"> </span><span class="o">=</span><span class="nb"> in</span><span class="m">1</span><span class="nb">;</span>
<span class="nb">	if </span><span class="o">(</span><span class="nb">in</span><span class="m">2</span><span class="o">)</span><span class="nb"></span>
<span class="nb">		out</span><span class="m">1</span><span class="nb"> </span><span class="o">=</span><span class="nb"> </span><span class="o">!</span><span class="nb">out</span><span class="m">1</span><span class="nb">;</span>
<span class="nb">	out</span><span class="m">2</span><span class="nb"> &lt;</span><span class="o">=</span><span class="nb"> out</span><span class="m">1</span><span class="nb">;</span>
<span class="nb">	if </span><span class="o">(</span><span class="nb">in</span><span class="m">3</span><span class="o">)</span><span class="nb"></span>
<span class="nb">		out</span><span class="m">2</span><span class="nb"> &lt;</span><span class="o">=</span><span class="nb"> out</span><span class="m">2</span><span class="nb">;</span>
<span class="nb">	if </span><span class="o">(</span><span class="nb">in</span><span class="m">4</span><span class="o">)</span><span class="nb"></span>
<span class="nb">		if </span><span class="o">(</span><span class="nb">in</span><span class="m">5</span><span class="o">)</span><span class="nb"></span>
<span class="nb">			out</span><span class="m">3</span><span class="nb"> &lt;</span><span class="o">=</span><span class="nb"> in</span><span class="m">6</span><span class="nb">;</span>
<span class="nb">		else</span>
<span class="nb">			out</span><span class="m">3</span><span class="nb"> &lt;</span><span class="o">=</span><span class="nb"> in</span><span class="m">7</span><span class="nb">;</span>
<span class="nb">	out</span><span class="m">1</span><span class="nb"> </span><span class="o">=</span><span class="nb"> out</span><span class="m">1</span><span class="nb"> ^ out</span><span class="m">2</span><span class="nb">;</span>
<span class="nb">end</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nb">This is translated by the Verilog and AST frontends into the following RTLIL code </span><span class="o">(</span><span class="nb">attributes, cell parameters</span>
<span class="nb">and wire declarations not included</span><span class="o">)</span><span class="nb">:</span>

<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">numbers</span><span class="o">=</span><span class="nb">left,frame</span><span class="o">=</span><span class="nb">single,language</span><span class="o">=</span><span class="nb">rtlil</span><span class="o">]</span><span class="nb"></span>
<span class="nb">cell </span><span class="s">$</span>logic<span class="nb">_</span>not <span class="s">$</span><span class="nb">logic_not</span><span class="s">$</span>&lt;input&gt;:4<span class="s">$</span><span class="m">2</span><span class="nb"></span>
<span class="nb">  connect </span><span class="nv">\A</span><span class="nb"> </span><span class="nv">\in</span><span class="m">1</span><span class="nb"></span>
<span class="nb">  connect </span><span class="nv">\Y</span><span class="nb"> </span><span class="s">$</span>logic<span class="nb">_</span>not<span class="s">$</span><span class="nb">&lt;input&gt;:</span><span class="m">4</span><span class="s">$</span>2<span class="nb">_</span>Y
end
cell <span class="s">$</span><span class="nb">xor </span><span class="s">$</span>xor<span class="s">$</span><span class="nb">&lt;input&gt;:</span><span class="m">13</span><span class="s">$</span>3
  connect <span class="k">\A</span> <span class="s">$</span><span class="m">1</span><span class="nv">\out</span><span class="m">1</span><span class="o">[</span><span class="m">0</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"></span>
<span class="nb">  connect </span><span class="nv">\B</span><span class="nb"> </span><span class="nv">\out</span><span class="m">2</span><span class="nb"></span>
<span class="nb">  connect </span><span class="nv">\Y</span><span class="nb"> </span><span class="s">$</span>xor<span class="s">$</span><span class="nb">&lt;input&gt;:</span><span class="m">13</span><span class="s">$</span>3<span class="nb">_</span>Y
end
process <span class="s">$</span><span class="nb">proc</span><span class="s">$</span>&lt;input&gt;:1<span class="s">$</span><span class="m">1</span><span class="nb"></span>
<span class="nb">  assign </span><span class="s">$</span>0<span class="k">\out</span>3[0:0] <span class="k">\out</span>3
  assign <span class="s">$</span><span class="m">0</span><span class="nv">\out</span><span class="m">2</span><span class="o">[</span><span class="m">0</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> </span><span class="s">$</span>1<span class="k">\out</span>1[0:0]
  assign <span class="s">$</span><span class="m">0</span><span class="nv">\out</span><span class="m">1</span><span class="o">[</span><span class="m">0</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> </span><span class="s">$</span>xor<span class="s">$</span><span class="nb">&lt;input&gt;:</span><span class="m">13</span><span class="s">$</span>3<span class="nb">_</span>Y
  switch <span class="k">\in</span>2
    case 1&#39;1
      assign <span class="s">$</span><span class="m">1</span><span class="nv">\out</span><span class="m">1</span><span class="o">[</span><span class="m">0</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> </span><span class="s">$</span>logic<span class="nb">_</span>not<span class="s">$</span><span class="nb">&lt;input&gt;:</span><span class="m">4</span><span class="s">$</span>2<span class="nb">_</span>Y
    case
      assign <span class="s">$</span><span class="m">1</span><span class="nv">\out</span><span class="m">1</span><span class="o">[</span><span class="m">0</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> </span><span class="nv">\in</span><span class="m">1</span><span class="nb"></span>
<span class="nb">  end</span>
<span class="nb">  switch </span><span class="nv">\in</span><span class="m">3</span><span class="nb"></span>
<span class="nb">    case </span><span class="m">1</span><span class="nb">&#39;</span><span class="m">1</span><span class="nb"></span>
<span class="nb">      assign </span><span class="s">$</span>0<span class="k">\out</span>2[0:0] <span class="k">\out</span>2
    case
  end
  switch <span class="k">\in</span>4
    case 1&#39;1
      switch <span class="k">\in</span>5
        case 1&#39;1
          assign <span class="s">$</span><span class="m">0</span><span class="nv">\out</span><span class="m">3</span><span class="o">[</span><span class="m">0</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> </span><span class="nv">\in</span><span class="m">6</span><span class="nb"></span>
<span class="nb">        case</span>
<span class="nb">          assign </span><span class="s">$</span>0<span class="k">\out</span>3[0:0] <span class="k">\in</span>7
      end
    case
  end
  sync posedge <span class="k">\clock</span>
    update <span class="k">\out</span>1 <span class="s">$</span><span class="m">0</span><span class="nv">\out</span><span class="m">1</span><span class="o">[</span><span class="m">0</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"></span>
<span class="nb">    update </span><span class="nv">\out</span><span class="m">2</span><span class="nb"> </span><span class="s">$</span>0<span class="k">\out</span>2[0:0]
    update <span class="k">\out</span>3 <span class="s">$</span><span class="m">0</span><span class="nv">\out</span><span class="m">3</span><span class="o">[</span><span class="m">0</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"></span>
<span class="nb">end</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>

<span class="nb">Note that the two operators are translated into separate cells outside the generated process. The signal</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">{out</span><span class="m">1</span><span class="nb">} is assigned using blocking assignments and therefore </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">{out</span><span class="m">1</span><span class="nb">}</span>
<span class="nb">has been replaced with a different signal in all expressions after the initial assignment. The signal</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">{out</span><span class="m">2</span><span class="nb">} is assigned using nonblocking assignments and therefore is not substituted</span>
<span class="nb">on the right</span><span class="o">-</span><span class="nb">hand</span><span class="o">-</span><span class="nb">side expressions.</span>

<span class="nb">The </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::CaseRule}</span><span class="o">/</span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::SwitchRule}</span>
<span class="nb">tree must be interpreted the following way:</span>

<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> On each case level </span><span class="o">(</span><span class="nb">the body of the process is the {</span><span class="nv">\it</span><span class="nb"> root case}</span><span class="o">)</span><span class="nb">, first the actions on this level are</span>
<span class="nb">evaluated and then the switches within the case are evaluated. </span><span class="o">(</span><span class="nb">Note that the last assignment on line </span><span class="m">13</span><span class="nb"> of the</span>
<span class="nb">Verilog code has been moved to the beginning of the RTLIL process to line </span><span class="m">13</span><span class="nb"> of the RTLIL listing.</span><span class="o">)</span><span class="nb"></span>

<span class="nb">I.e.~the special cases deeper in the switch hierarchy override the defaults on the upper levels. The assignments</span>
<span class="nb">in lines </span><span class="m">12</span><span class="nb"> and </span><span class="m">22</span><span class="nb"> of the RTLIL code serve as an example for this.</span>

<span class="nb">Note that in contrast to this, the order within the </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::SwitchRule} objects</span>
<span class="nb">within a </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::CaseRule} is preserved with respect to the original AST and</span>
<span class="nb">Verilog code.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> </span><span class="nv">\begin</span><span class="nb">{sloppypar}</span>
<span class="nb">The whole </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::CaseRule}</span><span class="o">/</span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::SwitchRule} tree</span>
<span class="nb">describes an asynchronous circuit. I.e.~the decision tree formed by the switches can be seen independently for</span>
<span class="nb">each assigned signal. Whenever one assigned signal changes, all signals that depend on the changed signals</span>
<span class="nb">are to be updated. For example the assignments in lines </span><span class="m">16</span><span class="nb"> and </span><span class="m">18</span><span class="nb"> in the RTLIL code in fact influence the assignment</span>
<span class="nb">in line </span><span class="m">12</span><span class="nb">, even though they are in the ``wrong order&#39;&#39;.</span>
<span class="nv">\end</span><span class="nb">{sloppypar}</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>

<span class="nb">The only synchronous part of the process is in the </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::SyncRule} object generated at line</span>
<span class="m">35</span><span class="nb"> in the RTLIL code. The sync rule is the only part of the process where the original signals are assigned. The</span>
<span class="nb">synchronization event from the original Verilog code has been translated into the synchronization type </span><span class="o">(</span><span class="nb">{</span><span class="nv">\tt</span><span class="nb"> posedge}</span><span class="o">)</span><span class="nb"></span>
<span class="nb">and signal </span><span class="o">(</span><span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\textbackslash</span><span class="nb"> clock}</span><span class="o">)</span><span class="nb"> for the </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::SyncRule} object. In the case of</span>
<span class="nb">this simple example the </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::SyncRule} object is later simply transformed into a set of</span>
<span class="nb">d</span><span class="o">-</span><span class="nb">type flip</span><span class="o">-</span><span class="nb">flops and the </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::CaseRule}</span><span class="o">/</span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::SwitchRule} tree</span>
<span class="nb">to a decision tree using multiplexers.</span>

<span class="nv">\begin</span><span class="nb">{sloppypar}</span>
<span class="nb">In more complex examples </span><span class="o">(</span><span class="nb">e.g.~asynchronous resets</span><span class="o">)</span><span class="nb"> the part of the</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::CaseRule}</span><span class="o">/</span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::SwitchRule}</span>
<span class="nb">tree that describes the asynchronous reset must first be transformed to the</span>
<span class="nb">correct </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::SyncRule} objects. This is done by the {</span><span class="nv">\tt</span><span class="nb"> proc</span><span class="nv">\_</span><span class="nb">adff} pass.</span>
<span class="nv">\end</span><span class="nb">{sloppypar}</span>

<span class="nv">\subsection</span><span class="nb">{The ProcessGenerator Algorithm}</span>

<span class="nb">The </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{AST_INTERNAL::ProcessGenerator} uses the following internal state variables:</span>

<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> </span><span class="nv">\begin</span><span class="nb">{sloppypar}</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_from} and </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_to} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">These two variables hold the replacement pattern that should be used by </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{AST::AstNode::genRTLIL</span><span class="o">()</span><span class="nb">}</span>
<span class="nb">for signals with blocking assignments. After initialization of </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{AST_INTERNAL::ProcessGenerator}</span>
<span class="nb">these two variables are empty.</span>
<span class="nv">\end</span><span class="nb">{sloppypar}</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_lvalue_from} and </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_lvalue_to} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">These two variables contain the mapping from left</span><span class="o">-</span><span class="nb">hand</span><span class="o">-</span><span class="nb">side signals </span><span class="o">(</span><span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\textbackslash</span><span class="nb"> </span><span class="nv">\it</span><span class="nb"> &lt;name&gt;}</span><span class="o">)</span><span class="nb"> to the current</span>
<span class="nb">temporary signal for the same thing </span><span class="o">(</span><span class="nb">initially {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$</span><span class="m">0</span><span class="nv">\textbackslash</span><span class="nb"> </span><span class="nv">\it</span><span class="nb"> &lt;name&gt;}</span><span class="o">)</span><span class="nb">.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{current_case} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">A pointer to a </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::CaseRule} object. Initially this is the root case of the</span>
<span class="nb">generated </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::Process}.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>

<span class="nb">As the algorithm runs these variables are continuously modified as well as pushed</span>
<span class="nb">to the stack and later restored to their earlier values by popping from the stack.</span>

<span class="nb">On startup the ProcessGenerator generates a new</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::Process} object with an empty root case and</span>
<span class="nb">initializes its state variables as described above. Then the </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::SyncRule} objects</span>
<span class="nb">are created using the synchronization events from the {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">ALWAYS} node and the initial values of</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_lvalue_from} and </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_lvalue_to}. Then the</span>
<span class="nb">AST for this process is evaluated recursively.</span>

<span class="nb">During this recursive evaluation, three different relevant types of AST nodes can be discovered:</span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">ASSIGN</span><span class="nv">\_</span><span class="nb">LE} </span><span class="o">(</span><span class="nb">nonblocking assignments</span><span class="o">)</span><span class="nb">, {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">ASSIGN</span><span class="nv">\_</span><span class="nb">EQ} </span><span class="o">(</span><span class="nb">blocking assignments</span><span class="o">)</span><span class="nb"> and</span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">CASE} </span><span class="o">(</span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">{if} or </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">Verilog</span><span class="o">]</span><span class="nb">{case} statement</span><span class="o">)</span><span class="nb">.</span>

<span class="nv">\subsubsection</span><span class="nb">{Handling of Nonblocking Assignments}</span>

<span class="nb">When an {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">ASSIGN</span><span class="nv">\_</span><span class="nb">LE} node is discovered, the following actions are performed by the</span>
<span class="nb">ProcessGenerator:</span>

<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> The left</span><span class="o">-</span><span class="nb">hand</span><span class="o">-</span><span class="nb">side is evaluated using </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{AST::AstNode::genRTLIL</span><span class="o">()</span><span class="nb">} and mapped to</span>
<span class="nb">a temporary signal name using </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_lvalue_from} and </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_lvalue_to}.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> The right</span><span class="o">-</span><span class="nb">hand</span><span class="o">-</span><span class="nb">side is evaluated using </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{AST::AstNode::genRTLIL</span><span class="o">()</span><span class="nb">}. For this call,</span>
<span class="nb">the values of </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_from} and </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_to} are used to</span>
<span class="nb">map blocking</span><span class="o">-</span><span class="nb">assigned signals correctly.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> Remove all assignments to the same left</span><span class="o">-</span><span class="nb">hand</span><span class="o">-</span><span class="nb">side as this assignment from the </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{current_case}</span>
<span class="nb">and all cases within it.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> Add the new assignment to the </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{current_case}.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>

<span class="nv">\subsubsection</span><span class="nb">{Handling of Blocking Assignments}</span>

<span class="nb">When an {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">ASSIGN</span><span class="nv">\_</span><span class="nb">EQ} node is discovered, the following actions are performed by</span>
<span class="nb">the ProcessGenerator:</span>

<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Perform all the steps that would be performed for a nonblocking assignment </span><span class="o">(</span><span class="nb">see above</span><span class="o">)</span><span class="nb">.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> Remove the found left</span><span class="o">-</span><span class="nb">hand</span><span class="o">-</span><span class="nb">side </span><span class="o">(</span><span class="nb">before lvalue mapping</span><span class="o">)</span><span class="nb"> from</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_from} and also remove the respective</span>
<span class="nb">bits from </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_to}.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> Append the found left</span><span class="o">-</span><span class="nb">hand</span><span class="o">-</span><span class="nb">side </span><span class="o">(</span><span class="nb">before lvalue mapping</span><span class="o">)</span><span class="nb"> to </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_from}</span>
<span class="nb">and append the found right</span><span class="o">-</span><span class="nb">hand</span><span class="o">-</span><span class="nb">side to </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_to}.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>

<span class="nv">\subsubsection</span><span class="nb">{Handling of Cases and if</span><span class="o">-</span><span class="nb">Statements}</span>

<span class="nv">\begin</span><span class="nb">{sloppypar}</span>
<span class="nb">When an {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">CASE} node is discovered, the following actions are performed by</span>
<span class="nb">the ProcessGenerator:</span>

<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> The values of </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_from}, </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_to},</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_lvalue_from} and </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_lvalue_to} are pushed to the stack.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> A new </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::SwitchRule} object is generated, the selection expression is evaluated using</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{AST::AstNode::genRTLIL</span><span class="o">()</span><span class="nb">} </span><span class="o">(</span><span class="nb">with the use of </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_from} and</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_to}</span><span class="o">)</span><span class="nb"> and added to the </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::SwitchRule} object and the</span>
<span class="nb">object is added to the </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{current_case}.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> All lvalues assigned to within the {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">CASE} node using blocking assignments are collected and</span>
<span class="nb">saved in the local variable </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{this_case_eq_lvalue}.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> New temporary signals are generated for all signals in </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{this_case_eq_lvalue} and stored</span>
<span class="nb">in </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{this_case_eq_ltemp}.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> The signals in </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{this_case_eq_lvalue} are mapped using </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_from}</span>
<span class="nb">and </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_to} and the resulting set of signals is stored in</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{this_case_eq_rvalue}.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>

<span class="nb">Then the following steps are performed for each {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">COND} node within the {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">CASE} node:</span>

<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> Set </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_from}, </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_to},</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_lvalue_from} and </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_lvalue_to} to the values</span>
<span class="nb">that have been pushed to the stack.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> Remove </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{this_case_eq_lvalue} from</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_lvalue_from}</span><span class="o">/</span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_lvalue_to}.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> Append </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{this_case_eq_lvalue} to </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_lvalue_from} and append</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{this_case_eq_ltemp} to </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_lvalue_to}.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> Push the value of </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{current_case}.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> Create a new </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::CaseRule}. Set </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{current_case} to the</span>
<span class="nb">new object and add the new object to the </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::SwitchRule} created above.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> Add an assignment from </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{this_case_eq_rvalue} to </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{this_case_eq_ltemp}</span>
<span class="nb">to the new </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{current_case}.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> Evaluate the compare value for this case using </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{AST::AstNode::genRTLIL</span><span class="o">()</span><span class="nb">} </span><span class="o">(</span><span class="nb">with the use of</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_from} and </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_to}</span><span class="o">)</span><span class="nb"> modify the new</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{current_case} accordingly.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> Recursion into the children of the {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">COND} node.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> Restore </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{current_case} by popping the old value from the stack.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>

<span class="nb">Finally the following steps are performed:</span>

<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> The values of </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_from}, </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_to},</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_lvalue_from} and </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_lvalue_to} are popped from the stack.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> The signals from </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{this_case_eq_lvalue} are removed from the</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_from}</span><span class="o">/</span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_to}</span><span class="o">-</span><span class="nb">pair.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> The value of </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{this_case_eq_lvalue} is appended to </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_from}</span>
<span class="nb">and the value of </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{this_case_eq_ltemp} is appended to </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_to}.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> Map the signals in </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{this_case_eq_lvalue} using</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_lvalue_from}</span><span class="o">/</span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_lvalue_to}.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> Remove all assignments to signals in </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{this_case_eq_lvalue} in </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{current_case}</span>
<span class="nb">and all cases within it.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> Add an assignment from </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{this_case_eq_ltemp} to </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{this_case_eq_lvalue}</span>
<span class="nb">to </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{current_case}.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>
<span class="nv">\end</span><span class="nb">{sloppypar}</span>

<span class="nv">\subsubsection</span><span class="nb">{Further Analysis of the Algorithm for Cases and if</span><span class="o">-</span><span class="nb">Statements}</span>

<span class="nb">With respect to nonblocking assignments the algorithm is easy: later assignments invalidate earlier assignments.</span>
<span class="nb">For each signal assigned using nonblocking assignments exactly one temporary variable is generated </span><span class="o">(</span><span class="nb">with the</span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$</span><span class="m">0</span><span class="nb">}</span><span class="o">-</span><span class="nb">prefix</span><span class="o">)</span><span class="nb"> and this variable is used for all assignments of the variable.</span>

<span class="nb">Note how all the </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{_eq_}</span><span class="o">-</span><span class="nb">variables become empty when no blocking assignments are used</span>
<span class="nb">and many of the steps in the algorithm can then be ignored as a result of this.</span>

<span class="nb">For a variable with blocking assignments the algorithm shows the following behaviour: First a new temporary variable</span>
<span class="nb">is created. This new temporary variable is then registered as the assignment target for all assignments for this</span>
<span class="nb">variable within the cases for this {</span><span class="nv">\tt</span><span class="nb"> AST</span><span class="nv">\_</span><span class="nb">CASE} node. Then for each case the new temporary variable is first</span>
<span class="nb">assigned the old temporary variable. This assignment is overwritten if the variable is actually assigned in this</span>
<span class="nb">case and is kept as a default value otherwise.</span>

<span class="nb">This yields an </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::CaseRule} that assigns the new temporary variable in all branches.</span>
<span class="nb">So when all cases have been processed a final assignment is added to the containing block that assigns the new</span>
<span class="nb">temporary variable to the old one. Note how this step always overrides a previous assignment to the old temporary</span>
<span class="nb">variable. Other than nonblocking assignments, the old assignment could still have an effect somewhere</span>
<span class="nb">in the design, as there have been calls to </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{AST::AstNode::genRTLIL</span><span class="o">()</span><span class="nb">} with a</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_from}</span><span class="o">/</span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{subst_rvalue_to}</span><span class="o">-</span><span class="nb">tuple that contained</span>
<span class="nb">the right</span><span class="o">-</span><span class="nb">hand</span><span class="o">-</span><span class="nb">side of the old assignment.</span>

<span class="nv">\subsection</span><span class="nb">{The proc pass}</span>

<span class="nb">The ProcessGenerator converts a behavioural model in AST representation to a behavioural model in</span>
<span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::Process} representation. The actual conversion from a behavioural</span>
<span class="nb">model to an RTL representation is performed by the {</span><span class="nv">\tt</span><span class="nb"> proc} pass and the passes it launches:</span>

<span class="nv">\begin</span><span class="nb">{itemize}</span>
<span class="nv">\item</span><span class="nb"> {</span><span class="nv">\tt</span><span class="nb"> proc</span><span class="nv">\_</span><span class="nb">clean} and {</span><span class="nv">\tt</span><span class="nb"> proc</span><span class="nv">\_</span><span class="nb">rmdead} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">These two passes just clean up the </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::Process} structure. The {</span><span class="nv">\tt</span><span class="nb"> proc</span><span class="nv">\_</span><span class="nb">clean}</span>
<span class="nb">pass removes empty parts </span><span class="o">(</span><span class="nb">eg. empty assignments</span><span class="o">)</span><span class="nb"> from the process and {</span><span class="nv">\tt</span><span class="nb"> proc</span><span class="nv">\_</span><span class="nb">rmdead} detects and removes</span>
<span class="nb">unreachable branches from the process&#39;s decision trees.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> {</span><span class="nv">\tt</span><span class="nb"> proc</span><span class="nv">\_</span><span class="nb">arst} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">This pass detects processes that describe d</span><span class="o">-</span><span class="nb">type flip</span><span class="o">-</span><span class="nb">flops with asynchronous</span>
<span class="nb">resets and rewrites the process to better reflect what they are modelling:</span>
<span class="nb">Before this pass, an asynchronous reset has two edge</span><span class="o">-</span><span class="nb">sensitive sync rules and</span>
<span class="nb">one top</span><span class="o">-</span><span class="nb">level </span><span class="nv">\C</span><span class="nb">{RTLIL::SwitchRule} for the reset path. After this pass the</span>
<span class="nb">sync rule for the reset is level</span><span class="o">-</span><span class="nb">sensitive and the top</span><span class="o">-</span><span class="nb">level</span>
<span class="nv">\C</span><span class="nb">{RTLIL::SwitchRule} has been removed.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> {</span><span class="nv">\tt</span><span class="nb"> proc</span><span class="nv">\_</span><span class="nb">mux} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">This pass converts the </span><span class="nv">\C</span><span class="nb">{RTLIL::CaseRule}</span><span class="o">/</span><span class="nv">\C</span><span class="nb">{RTLIL::SwitchRule}</span><span class="o">-</span><span class="nb">tree to a tree</span>
<span class="nb">of multiplexers per written signal. After this, the </span><span class="nv">\C</span><span class="nb">{RTLIL::Process} structure only contains</span>
<span class="nb">the </span><span class="nv">\C</span><span class="nb">{RTLIL::SyncRule}s that describe the output registers.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> {</span><span class="nv">\tt</span><span class="nb"> proc</span><span class="nv">\_</span><span class="nb">dff} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">This pass replaces the </span><span class="nv">\C</span><span class="nb">{RTLIL::SyncRule}s to d</span><span class="o">-</span><span class="nb">type flip</span><span class="o">-</span><span class="nb">flops </span><span class="o">(</span><span class="nb">with</span>
<span class="nb">asynchronous resets if necessary</span><span class="o">)</span><span class="nb">.</span>
<span class="c">%</span>
<span class="nv">\item</span><span class="nb"> {</span><span class="nv">\tt</span><span class="nb"> proc</span><span class="nv">\_</span><span class="nb">clean} </span><span class="nv">\\</span><span class="nb"></span>
<span class="nb">A final call to {</span><span class="nv">\tt</span><span class="nb"> proc</span><span class="nv">\_</span><span class="nb">clean} removes the now empty </span><span class="nv">\C</span><span class="nb">{RTLIL::Process} objects.</span>
<span class="nv">\end</span><span class="nb">{itemize}</span>

<span class="nb">Performing these last processing steps in passes instead of in the Verilog frontend has two important benefits:</span>

<span class="nb">First it improves the transparency of the process. Everything that happens in a separate pass is easier to debug,</span>
<span class="nb">as the RTLIL data structures can be easily investigated before and after each of the steps.</span>

<span class="nb">Second it improves flexibility. This scheme can easily be extended to support other types of storage</span><span class="o">-</span><span class="nb">elements, such</span>
<span class="nb">as sr</span><span class="o">-</span><span class="nb">latches or d</span><span class="o">-</span><span class="nb">latches, without having to extend the actual Verilog frontend.</span>

<span class="nv">\section</span><span class="nb">{Synthesizing Verilog Arrays}</span>

<span class="nv">\begin</span><span class="nb">{fixme}</span>
<span class="nb">Add some information on the generation of {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$</span><span class="nb">memrd} and {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$</span><span class="nb">memwr} cells</span>
<span class="nb">and how they are processed in the {</span><span class="nv">\tt</span><span class="nb"> memory} pass.</span>
<span class="nv">\end</span><span class="nb">{fixme}</span>

<span class="nv">\section</span><span class="nb">{Synthesizing Parametric Designs}</span>

<span class="nv">\begin</span><span class="nb">{fixme}</span>
<span class="nb">Add some information on the </span><span class="nv">\lstinline</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">++]</span><span class="nb">{RTLIL::Module::derive</span><span class="o">()</span><span class="nb">} method and how it</span>
<span class="nb">is used to synthesize parametric modules via the {</span><span class="nv">\tt</span><span class="nb"> hierarchy} pass.</span>
<span class="nv">\end</span><span class="nb">{fixme}</span>
</pre></div>
</code></pre></td></tr></table>
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