From 849369d6c66d3054688672f97d31fceb8e8230fb Mon Sep 17 00:00:00 2001 From: root Date: Fri, 25 Dec 2015 04:40:36 +0000 Subject: initial_commit --- arch/arm/mach-tegra/common.c | 83 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 arch/arm/mach-tegra/common.c (limited to 'arch/arm/mach-tegra/common.c') diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c new file mode 100644 index 00000000..d5e3f89b --- /dev/null +++ b/arch/arm/mach-tegra/common.c @@ -0,0 +1,83 @@ +/* + * arch/arm/mach-tegra/board-harmony.c + * + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Colin Cross + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include + +#include + +#include +#include + +#include "board.h" +#include "clock.h" +#include "fuse.h" + +void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset; + +void tegra_assert_system_reset(char mode, const char *cmd) +{ + void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04); + u32 reg; + + /* use *_related to avoid spinlock since caches are off */ + reg = readl_relaxed(reset); + reg |= 0x04; + writel_relaxed(reg, reset); +} + +static __initdata struct tegra_clk_init_table common_clk_init_table[] = { + /* name parent rate enabled */ + { "clk_m", NULL, 0, true }, + { "pll_p", "clk_m", 216000000, true }, + { "pll_p_out1", "pll_p", 28800000, true }, + { "pll_p_out2", "pll_p", 48000000, true }, + { "pll_p_out3", "pll_p", 72000000, true }, + { "pll_p_out4", "pll_p", 108000000, true }, + { "sclk", "pll_p_out4", 108000000, true }, + { "hclk", "sclk", 108000000, true }, + { "pclk", "hclk", 54000000, true }, + { "csite", NULL, 0, true }, + { "emc", NULL, 0, true }, + { "cpu", NULL, 0, true }, + { NULL, NULL, 0, 0}, +}; + +void __init tegra_init_cache(void) +{ +#ifdef CONFIG_CACHE_L2X0 + void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; + + writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL); + writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL); + + l2x0_init(p, 0x6C080001, 0x8200c3fe); +#endif + +} + +void __init tegra_init_early(void) +{ + tegra_init_fuse(); + tegra_init_clock(); + tegra_clk_init_from_table(common_clk_init_table); + tegra_init_cache(); +} -- cgit v1.2.3