/* ZD1211 USB-WLAN driver for Linux * * Copyright (C) 2005-2007 Ulrich Kunitz * Copyright (C) 2006-2007 Daniel Drake * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef _ZD_CHIP_H #define _ZD_CHIP_H #include "zd_rf.h" #include "zd_usb.h" /* Header for the Media Access Controller (MAC) and the Baseband Processor * (BBP). It appears that the ZD1211 wraps the old ZD1205 with USB glue and * adds a processor for handling the USB protocol. */ /* Address space */ enum { /* CONTROL REGISTERS */ CR_START = 0x9000, /* FIRMWARE */ FW_START = 0xee00, /* EEPROM */ E2P_START = 0xf800, E2P_LEN = 0x800, /* EEPROM layout */ E2P_LOAD_CODE_LEN = 0xe, /* base 0xf800 */ E2P_LOAD_VECT_LEN = 0x9, /* base 0xf80e */ /* E2P_DATA indexes into this */ E2P_DATA_LEN = 0x7e, /* base 0xf817 */ E2P_BOOT_CODE_LEN = 0x760, /* base 0xf895 */ E2P_INTR_VECT_LEN = 0xb, /* base 0xfff5 */ /* Some precomputed offsets into the EEPROM */ E2P_DATA_OFFSET = E2P_LOAD_CODE_LEN + E2P_LOAD_VECT_LEN, E2P_BOOT_CODE_OFFSET = E2P_DATA_OFFSET + E2P_DATA_LEN, }; #define CTL_REG(offset) ((zd_addr_t)(CR_START + (offset))) #define E2P_DATA(offset) ((zd_addr_t)(E2P_START + E2P_DATA_OFFSET + (offset))) #define FWRAW_DATA(offset) ((zd_addr_t)(FW_START + (offset))) /* 8-bit hardware registers */ #define ZD_CR0 CTL_REG(0x0000) #define ZD_CR1 CTL_REG(0x0004) #define ZD_CR2 CTL_REG(0x0008) #define ZD_CR3 CTL_REG(0x000C) #define ZD_CR5 CTL_REG(0x0010) /* bit 5: if set short preamble used * bit 6: filter band - Japan channel 14 on, else off */ #define ZD_CR6 CTL_REG(0x0014) #define ZD_CR7 CTL_REG(0x0018) #define ZD_CR8 CTL_REG(0x001C) #define ZD_CR4 CTL_REG(0x0020) #define ZD_CR9 CTL_REG(0x0024) /* bit 2: antenna switch (together with ZD_CR10) */ #define ZD_CR10 CTL_REG(0x0028) /* bit 1: antenna switch (together with ZD_CR9) * RF2959 controls with ZD_CR11 radion on and off */ #define ZD_CR11 CTL_REG(0x002C) /* bit 6: TX power control for OFDM * RF2959 controls with ZD_CR10 radio on and off */ #define ZD_CR12 CTL_REG(0x0030) #define ZD_CR13 CTL_REG(0x0034) #define ZD_CR14 CTL_REG(0x0038) #define ZD_CR15 CTL_REG(0x003C) #define ZD_CR16 CTL_REG(0x0040) #define ZD_CR17 CTL_REG(0x0044) #define ZD_CR18 CTL_REG(0x0048) #define ZD_CR19 CTL_REG(0x004C) #define ZD_CR20 CTL_REG(0x0050) #define ZD_CR21 CTL_REG(0x0054) #define ZD_CR22 CTL_REG(0x0058) #define ZD_CR23 CTL_REG(0x005C) #define ZD_CR24 CTL_REG(0x0060) /* CCA threshold */ #define ZD_CR25 CTL_REG(0x0064) #define ZD_CR26 CTL_REG(0x0068) #define ZD_CR27 CTL_REG(0x006C) #define ZD_CR28 CTL_REG(0x0070) #define ZD_CR29 CTL_REG(0x0074) #define ZD_CR30 CTL_REG(0x0078) #define ZD_CR31 CTL_REG(0x007C) /* TX power control for RF in * CCK mode */ #define ZD_CR32 CTL_REG(0x0080) #define ZD_CR33 CTL_REG(0x0084) #define ZD_CR34 CTL_REG(0x0088) #define ZD_CR35 CTL_REG(0x008C) #define ZD_CR36 CTL_REG(0x0090) #define ZD_CR37 CTL_REG(0x0094) #define ZD_CR38 CTL_REG(0x0098) #define ZD_CR39 CTL_REG(0x009C) #define ZD_CR40 CTL_REG(0x00A0) #define ZD_CR41 CTL_REG(0x00A4) #define ZD_CR42 CTL_REG(0x00A8) #define ZD_CR43 CTL_REG(0x00AC) #define ZD_CR44 CTL_REG(0x00B0) #define ZD_CR45 CTL_REG(0x00B4) #define ZD_CR46 CTL_REG(0x00B8) #define ZD_CR47 CTL_REG(0x00BC) /* CCK baseband gain * (patch value might be in EEPROM) */ #define ZD_CR48 CTL_REG(0x00C0) #define ZD_CR49 CTL_REG(0x00C4) #define ZD_CR50 CTL_REG(0x00C8) #define ZD_CR51 CTL_REG(0x00CC) /* TX power control for RF in * 6-36M modes */ #define ZD_CR52 CTL_REG(0x00D0) /* TX power control for RF in * 48M mode */ #define ZD_CR53 CTL_REG(0x00D4) /* TX power control for RF in * 54M mode */ #define ZD_CR54 CTL_REG(0x00D8) #define ZD_CR55 CTL_REG(0x00DC) #define ZD_CR56 CTL_REG(0x00E0) #define ZD_CR57 CTL_REG(0x00E4) #define ZD_CR58 CTL_REG(0x00E8) #define ZD_CR59 CTL_REG(0x00EC) #define ZD_CR60 CTL_REG(0x00F0) #define ZD_CR61 CTL_REG(0x00F4) #define ZD_CR62 CTL_REG(0x00F8) #define ZD_CR63 CTL_REG(0x00FC) #define ZD_CR64 CTL_REG(0x0100) #define ZD_CR65 CTL_REG(0x0104) /* OFDM 54M calibration */ #define ZD_CR66 CTL_REG(0x0108) /* OFDM 48M calibration */ #define ZD_CR67 CTL_REG(0x010C) /* OFDM 36M calibration */ #define ZD_CR68 CTL_REG(0x0110) /* CCK calibration */ #define ZD_CR69 CTL_REG(0x0114) #define ZD_CR70 CTL_REG(0x0118) #define ZD_CR71 CTL_REG(0x011C) #define ZD_CR72 CTL_REG(0x0120) #define ZD_CR73 CTL_REG(0x0124) #define ZD_CR74 CTL_REG(0x0128) #define ZD_CR75 CTL_REG(0x012C) #define ZD_CR76 CTL_REG(0x0130) #define ZD_CR77 CTL_REG(0x0134) #define ZD_CR78 CTL_REG(0x0138) #define ZD_CR79 CTL_REG(0x013C) #define ZD_CR80 CTL_REG(0x0140) #define ZD_CR81 CTL_REG(0x0144) #define ZD_CR82 CTL_REG(0x0148) #define ZD_CR83 CTL_REG(0x014C) #define ZD_CR84 CTL_REG(0x0150) #define ZD_CR85 CTL_REG(0x0154) #define ZD_CR86 CTL_REG(0x0158) #define ZD_CR87 CTL_REG(0x015C) #define ZD_CR88 CTL_REG(0x0160) #define ZD_CR89 CTL_REG(0x0164) #define ZD_CR90 CTL_REG(0x0168) #define ZD_CR91 CTL_REG(0x016C) #define ZD_CR92 CTL_REG(0x0170) #define ZD_CR93 CTL_REG(0x0174) #define ZD_CR94 CTL_REG(0x0178) #define ZD_CR95 CTL_REG(0x017C) #define ZD_CR96 CTL_REG(0x0180) #define ZD_CR97 CTL_REG(0x0184) #define ZD_CR98 CTL_REG(0x0188) #define ZD_CR99 CTL_REG(0x018C) #define ZD_CR100 CTL_REG(0x0190) #define ZD_CR101 CTL_REG(0x0194) #define ZD_CR102 CTL_REG(0x0198) #define ZD_CR103 CTL_REG(0x019C) #define ZD_CR104 CTL_REG(0x01A0) #define ZD_CR105 CTL_REG(0x01A4) #define ZD_CR106 CTL_REG(0x01A8) #define ZD_CR107 CTL_REG(0x01AC) #define ZD_CR108 CTL_REG(0x01B0) #define ZD_CR109 CTL_REG(0x01B4) #define ZD_CR110 CTL_REG(0x01B8) #define ZD_CR111 CTL_REG(0x01BC) #define ZD_CR112 CTL_REG(0x01C0) #define ZD_CR113 CTL_REG(0x01C4) #define ZD_CR114 CTL_REG(0x01C8) #define ZD_CR115 CTL_REG(0x01CC) #define ZD_CR116 CTL_REG(0x01D0) #define ZD_CR117 CTL_REG(0x01D4) #define ZD_CR118 CTL_REG(0x01D8) #define ZD_CR119 CTL_REG(0x01DC) #define ZD_CR120 CTL_REG(0x01E0) #define ZD_CR121 CTL_REG(0x01E4) #define ZD_CR122 CTL_REG(0x01E8) #define ZD_CR123 CTL_REG(0x01EC) #define ZD_CR124 CTL_REG(0x01F0) #define ZD_CR125 CTL_REG(0x01F4) #define ZD_CR126 CTL_REG(0x01F8) #define ZD_CR127 CTL_REG(0x01FC) #define ZD_CR128 CTL_REG(0x0200) #define ZD_CR129 CTL_REG(0x0204) #define ZD_CR130 CTL_REG(0x0208) #define ZD_CR131 CTL_REG(0x020C) #define ZD_CR132 CTL_REG(0x0210) #define ZD_CR133 CTL_REG(0x0214) #define ZD_CR134 CTL_REG(0x0218) #define ZD_CR135 CTL_REG(0x021C) #define ZD_CR136 CTL_REG(0x0220) #define ZD_CR137 CTL_REG(0x0224) #define ZD_CR138 CTL_REG(0x0228) #define ZD_CR139 CTL_REG(0x022C) #define ZD_CR140 CTL_REG(0x0230) #define ZD_CR141 CTL_REG(0x0234) #define ZD_CR142 CTL_REG(0x0238) #define ZD_CR143 CTL_REG(0x023C) #define ZD_CR144 CTL_REG(0x0240) #define ZD_CR145 CTL_REG(0x0244) #define ZD_CR146 CTL_REG(0x0248) #define ZD_CR147 CTL_REG(0x024C) #define ZD_CR148 CTL_REG(0x0250) #define ZD_CR149 CTL_REG(0x0254) #define ZD_CR150 CTL_REG(0x0258) #define ZD_CR151 CTL_REG(0x025C) #define ZD_CR152 CTL_REG(0x0260) #define ZD_CR153 CTL_REG(0x0264) #define ZD_CR154 CTL_REG(0x0268) #define ZD_CR155 CTL_REG(0x026C) #define ZD_CR156 CTL_REG(0x0270) #define ZD_CR157 CTL_REG(0x0274) #define ZD_CR158 CTL_REG(0x0278) #define ZD_CR159 CTL_REG(0x027C) #define ZD_CR160 CTL_REG(0x0280) #define ZD_CR161 CTL_REG(0x0284) #define ZD_CR162 CTL_REG(0x0288) #define ZD_CR163 CTL_REG(0x028C) #define ZD_CR164 CTL_REG(0x0290) #define ZD_CR165 CTL_REG(0x0294) #define ZD_CR166 CTL_REG(0x0298) #define ZD_CR167 CTL_REG(0x029C) #define ZD_CR168 CTL_REG(0x02A0) #define ZD_CR169 CTL_REG(0x02A4) #define ZD_CR170 CTL_REG(0x02A8) #define ZD_CR171 CTL_REG(0x02AC) #define ZD_CR172 CTL_REG(0x02B0) #define ZD_CR173 CTL_REG(0x02B4) #define ZD_CR174 CTL_REG(0x02B8) #define ZD_CR175 CTL_REG(0x02BC) #define ZD_CR176 CTL_REG(0x02C0) #define ZD_CR177 CTL_REG(0x02C4) #define ZD_CR178 CTL_REG(0x02C8) #define ZD_CR179 CTL_REG(0x02CC) #define ZD_CR180 CTL_REG(0x02D0) #define ZD_CR181 CTL_REG(0x02D4) #define ZD_CR182 CTL_REG(0x02D8) #define ZD_CR183 CTL_REG(0x02DC) #define ZD_CR184 CTL_REG(0x02E0) #define ZD_CR185 CTL_REG(0x02E4) #define ZD_CR186 CTL_REG(0x02E8) #define ZD_CR187 CTL_REG(0x02EC) #define ZD_CR188 CTL_REG(0x02F0) #define ZD_CR189 CTL_REG(0x02F4) #define ZD_CR190 CTL_REG(0x02F8) #define ZD_CR191 CTL_REG(0x02FC) #define ZD_CR192 CTL_REG(0x0300) #define ZD_CR193 CTL_REG(0x0304) #define ZD_CR194 CTL_REG(0x0308) #define ZD_CR195 CTL_REG(0x030C) #define ZD_CR196 CTL_REG(0x0310) #define ZD_CR197 CTL_REG(0x0314) #define ZD_CR198 CTL_REG(0x0318) #define ZD_CR199 CTL_REG(0x031C) #define ZD_CR200 CTL_REG(0x0320) #define ZD_CR201 CTL_REG(0x0324) #define ZD_CR202 CTL_REG(0x0328) #define ZD_CR203 CTL_REG(0x032C) /* I2C bus template value & flash * control */ #define ZD_CR204 CTL_REG(0x0330) #define ZD_CR205 CTL_REG(0x0334) #define ZD_CR206 CTL_REG(0x0338) #define ZD_CR207 CTL_REG(0x033C) #define ZD_CR208 CTL_REG(0x0340) #define ZD_CR209 CTL_REG(0x0344) #define ZD_CR210 CTL_REG(0x0348) #define ZD_CR211 CTL_REG(0x034C) #define ZD_CR212 CTL_REG(0x0350) #define ZD_CR213 CTL_REG(0x0354) #define ZD_CR214 CTL_REG(0x0358) #define ZD_CR215 CTL_REG(0x035C) #define ZD_CR216 CTL_REG(0x0360) #define ZD_CR217 CTL_REG(0x0364) #define ZD_CR218 CTL_REG(0x0368) #define ZD_CR219 CTL_REG(0x036C) #define ZD_CR220 CTL_REG(0x0370) #define ZD_CR221 CTL_REG(0x0374) #define ZD_CR222 CTL_REG(0x0378) #define ZD_CR223 CTL_REG(0x037C) #define ZD_CR224 CTL_REG(0x0380) #define ZD_CR225 CTL_REG(0x0384) #define ZD_CR226 CTL_REG(0x0388) #define ZD_CR227 CTL_REG(0x038C) #define ZD_CR228 CTL_REG(0x0390) #define ZD_CR229 CTL_REG(0x0394) #define ZD_CR230 CTL_REG(0x0398) #define ZD_CR231 CTL_REG(0x039C) #define ZD_CR232 CTL_REG(0x03A0) #define ZD_CR233 CTL_REG(0x03A4) #define ZD_CR234 CTL_REG(0x03A8) #define ZD_CR235 CTL_REG(0x03AC) #define ZD_CR236 CTL_REG(0x03B0) #define ZD_CR240 CTL_REG(0x03C0) /* bit 7: host-controlled RF register writes * ZD_CR241-ZD_CR245: for hardware controlled writing of RF bits, not needed for * USB */ #define ZD_CR241 CTL_REG(0x03C4) #define ZD_CR242 CTL_REG(0x03C8) #define ZD_CR243 CTL_REG(0x03CC) #define ZD_CR244 CTL_REG(0x03D0) #define ZD_CR245 CTL_REG(0x03D4) #define ZD_CR251 CTL_REG(0x03EC) /* only used for activation and * deactivation of Airoha RFs AL2230 * and AL7230B */ #define ZD_CR252 CTL_REG(0x03F0) #define ZD_CR253 CTL_REG(0x03F4) #define ZD_CR254 CTL_REG(0x03F8) #define ZD_CR255 CTL_REG(0x03FC) #define CR_MAX_PHY_REG 255 /* Taken from the ZYDAS driver, not all of them are relevant for the ZD1211 * driver. */ #define CR_RF_IF_CLK CTL_REG(0x0400) #define CR_RF_IF_DATA CTL_REG(0x0404) #define CR_PE1_PE2 CTL_REG(0x0408) #define CR_PE2_DLY CTL_REG(0x040C) #define CR_LE1 CTL_REG(0x0410) #define CR_LE2 CTL_REG(0x0414) /* Seems to enable/disable GPI (General Purpose IO?) */ #define CR_GPI_EN CTL_REG(0x0418) #define CR_RADIO_PD CTL_REG(0x042C) #define CR_RF2948_PD CTL_REG(0x042C) #define CR_ENABLE_PS_MANUAL_AGC CTL_REG(0x043C) #define CR_CONFIG_PHILIPS CTL_REG(0x0440) #define CR_SA2400_SER_AP CTL_REG(0x0444) #define CR_I2C_WRITE CTL_REG(0x0444) #define CR_SA2400_SER_RP CTL_REG(0x0448) #define CR_RADIO_PE CTL_REG(0x0458) #define CR_RST_BUS_MASTER CTL_REG(0x045C) #define CR_RFCFG CTL_REG(0x0464) #define CR_HSTSCHG CTL_REG(0x046C) #define CR_PHY_ON CTL_REG(0x0474) #define CR_RX_DELAY CTL_REG(0x0478) #define CR_RX_PE_DELAY CTL_REG(0x047C) #define CR_GPIO_1 CTL_REG(0x0490) #define CR_GPIO_2 CTL_REG(0x0494) #define CR_EncryBufMux CTL_REG(0x04A8) #define CR_PS_CTRL CTL_REG(0x0500) #define CR_ADDA_PWR_DWN CTL_REG(0x0504) #define CR_ADDA_MBIAS_WARMTIME CTL_REG(0x0508) #define CR_MAC_PS_STATE CTL_REG(0x050C) #define CR_INTERRUPT CTL_REG(0x0510) #define INT_TX_COMPLETE (1 << 0) #define INT_RX_COMPLETE (1 << 1) #define INT_RETRY_FAIL (1 << 2) #define INT_WAKEUP (1 << 3) #define INT_DTIM_NOTIFY (1 << 5) #define INT_CFG_NEXT_BCN (1 << 6) #define INT_BUS_ABORT (1 << 7) #define INT_TX_FIFO_READY (1 << 8) #define INT_UART (1 << 9) #define INT_TX_COMPLETE_EN (1 << 16) #define INT_RX_COMPLETE_EN (1 << 17) #define INT_RETRY_
/******************************************************************************
 *
 * This file is provided under a dual BSD/GPLv2 license.  When using or
 * redistributing this file, you may do so under either license.
 *
 * GPL LICENSE SUMMARY
 *
 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
 * USA
 *
 * The full GNU General Public License is included in this distribution
 * in the file called LICENSE.GPL.
 *
 * Contact Information:
 *  Intel Linux Wireless <ilw@linux.intel.com>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 * BSD LICENSE
 *
 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 *  * Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *  * Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in
 *    the documentation and/or other materials provided with the
 *    distribution.
 *  * Neither the name Intel Corporation nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *****************************************************************************/
/*
 * Please use this file (iwl-3945-hw.h) only for hardware-related definitions.
 * Please use iwl-commands.h for uCode API definitions.
 * Please use iwl-3945.h for driver implementation definitions.
 */

#ifndef __iwl_3945_hw__
#define __iwl_3945_hw__

#include "iwl-eeprom.h"

/* RSSI to dBm */
#define IWL39_RSSI_OFFSET	95

/*
 * EEPROM related constants, enums, and structures.
 */
#define EEPROM_SKU_CAP_OP_MODE_MRC                      (1 << 7)

/*
 * Mapping of a Tx power level, at factory calibration temperature,
 *   to a radio/DSP gain table index.
 * One for each of 5 "sample" power levels in each band.
 * v_det is measured at the factory, using the 3945's built-in power amplifier
 *   (PA) output voltage detector.  This same detector is used during Tx of
 *   long packets in normal operation to provide feedback as to proper output
 *   level.
 * Data copied from EEPROM.
 * DO NOT ALTER THIS STRUCTURE!!!
 */
struct iwl3945_eeprom_txpower_sample {
	u8 gain_index;		/* index into power (gain) setup table ... */
	s8 power;		/* ... for this pwr level for this chnl group */
	u16 v_det;		/* PA output voltage */
} __packed;

/*
 * Mappings of Tx power levels -> nominal radio/DSP gain table indexes.
 * One for each channel group (a.k.a. "band") (1 for BG, 4 for A).
 * Tx power setup code interpolates between the 5 "sample" power levels
 *    to determine the nominal setup for a requested power level.
 * Data copied from EEPROM.
 * DO NOT ALTER THIS STRUCTURE!!!
 */
struct iwl3945_eeprom_txpower_group {
	struct iwl3945_eeprom_txpower_sample samples[5];  /* 5 power levels */
	s32 a, b, c, d, e;	/* coefficients for voltage->power
				 * formula (signed) */
	s32 Fa, Fb, Fc, Fd, Fe;	/* these modify coeffs based on
				 * frequency (signed) */
	s8 saturation_power;	/* highest power possible by h/w in this
				 * band */
	u8 group_channel;	/* "representative" channel # in this band */
	s16 temperature;	/* h/w temperature at factory calib this band
				 * (signed) */
} __packed;

/*
 * Temperature-based Tx-power compensation data, not band-specific.
 * These coefficients are use to modify a/b/c/d/e coeffs based on
 *   difference between current temperature and factory calib temperature.
 * Data copied from EEPROM.
 */
struct iwl3945_eeprom_temperature_corr {
	u32 Ta;
	u32 Tb;
	u32 Tc;
	u32 Td;
	u32 Te;
} __packed;

/*
 * EEPROM map
 */
struct iwl3945_eeprom {
	u8 reserved0[16];
	u16 device_id;	/* abs.ofs: 16 */
	u8 reserved1[2];
	u16 pmc;		/* abs.ofs: 20 */
	u8 reserved2[20];
	u8 mac_address[6];	/* abs.ofs: 42 */
	u8 reserved3[58];
	u16 board_revision;	/* abs.ofs: 106 */
	u8 reserved4[11];
	u8 board_pba_number[9];	/* abs.ofs: 119 */
	u8 reserved5[8];
	u16 version;		/* abs.ofs: 136 */
	u8 sku_cap;		/* abs.ofs: 138 */
	u8 leds_mode;		/* abs.ofs: 139 */
	u16 oem_mode;
	u16 wowlan_mode;	/* abs.ofs: 142 */
	u16 leds_time_interval;	/* abs.ofs: 144 */
	u8 leds_off_time;	/* abs.ofs: 146 */
	u8 leds_on_time;	/* abs.ofs: 147 */
	u8 almgor_m_version;	/* abs.ofs: 148 */
	u8 antenna_switch_type;	/* abs.ofs: 149 */
	u8 reserved6[42];
	u8 sku_id[4];		/* abs.ofs: 192 */

/*
 * Per-channel regulatory data.
 *
 * Each channel that *might* be supported by 3945 has a fixed location
 * in EEPROM containing EEPROM_CHANNEL_* usage flags (LSB) and max regulatory
 * txpower (MSB).
 *
 * Entries immediately below are for 20 MHz channel width.
 *
 * 2.4 GHz channels 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
 */
	u16 band_1_count;	/* abs.ofs: 196 */
	struct iwl_eeprom_channel band_1_channels[14];  /* abs.ofs: 198 */

/*
 * 4.9 GHz channels 183, 184, 185, 187, 188, 189, 192, 196,
 * 5.0 GHz channels 7, 8, 11, 12, 16
 * (4915-5080MHz) (none of these is ever supported)
 */
	u16 band_2_count;	/* abs.ofs: 226 */
	struct iwl_eeprom_channel band_2_channels[13];  /* abs.ofs: 228 */

/*
 * 5.2 GHz channels 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
 * (5170-5320MHz)
 */
	u16 band_3_count;	/* abs.ofs: 254 */
	struct iwl_eeprom_channel band_3_channels[12];  /* abs.ofs: 256 */

/*
 * 5.5 GHz channels 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
 * (5500-5700MHz)
 */
	u16 band_4_count;	/* abs.ofs: 280 */
	struct iwl_eeprom_channel band_4_channels[11];  /* abs.ofs: 282 */

/*
 * 5.7 GHz channels 145, 149, 153, 157, 161, 165
 * (5725-5825MHz)
 */
	u16 band_5_count;	/* abs.ofs: 304 */
	struct iwl_eeprom_channel band_5_channels[6];  /* abs.ofs: 306 */

	u8 reserved9[194];

/*
 * 3945 Txpower calibration data.
 */
#define IWL_NUM_TX_CALIB_GROUPS 5
	struct iwl3945_eeprom_txpower_group groups[IWL_NUM_TX_CALIB_GROUPS];
/* abs.ofs: 512 */
	struct iwl3945_eeprom_temperature_corr corrections;  /* abs.ofs: 832 */
	u8 reserved16[172];	/* fill out to full 1024 byte block */
} __packed;

#define IWL3945_EEPROM_IMG_SIZE 1024

/* End of EEPROM */

#define PCI_CFG_REV_ID_BIT_BASIC_SKU                (0x40)	/* bit 6    */
#define PCI_CFG_REV_ID_BIT_RTP                      (0x80)	/* bit 7    */

/* 4 DATA + 1 CMD. There are 2 HCCA queues that are not used. */
#define IWL39_NUM_QUEUES        5
#define IWL39_CMD_QUEUE_NUM	4

#define IWL_DEFAULT_TX_RETRY  15

/*********************************************/

#define RFD_SIZE                              4
#define NUM_TFD_CHUNKS                        4

#define RX_QUEUE_SIZE                         256
#define RX_QUEUE_MASK                         255
#define RX_QUEUE_SIZE_LOG                     8

#define U32_PAD(n)		((4-(n))&0x3)

#define TFD_CTL_COUNT_SET(n)       (n << 24)
#define TFD_CTL_COUNT_GET(ctl)     ((ctl >> 24) & 7)
#define TFD_CTL_PAD_SET(n)         (n << 28)
#define TFD_CTL_PAD_GET(ctl)       (ctl >> 28)

/* Sizes and addresses for instruction and data memory (SRAM) in
 * 3945's embedded processor.  Driver access is via HBUS_TARG_MEM_* regs. */
#define IWL39_RTC_INST_LOWER_BOUND		(0x000000)
#define IWL39_RTC_INST_UPPER_BOUND		(0x014000)

#define IWL39_RTC_DATA_LOWER_BOUND		(0x800000)
#define IWL39_RTC_DATA_UPPER_BOUND		(0x808000)

#define IWL39_RTC_INST_SIZE (IWL39_RTC_INST_UPPER_BOUND - \
				IWL39_RTC_INST_LOWER_BOUND)
#define IWL39_RTC_DATA_SIZE (IWL39_RTC_DATA_UPPER_BOUND - \
				IWL39_RTC_DATA_LOWER_BOUND)

#define IWL39_MAX_INST_SIZE IWL39_RTC_INST_SIZE
#define IWL39_MAX_DATA_SIZE IWL39_RTC_DATA_SIZE

/* Size of uCode instruction memory in bootstrap state machine */
#define IWL39_MAX_BSM_SIZE IWL39_RTC_INST_SIZE

static inline int iwl3945_hw_valid_rtc_data_addr(u32 addr)
{
	return (addr >= IWL39_RTC_DATA_LOWER_BOUND) &&
	       (addr < IWL39_RTC_DATA_UPPER_BOUND);
}

/* Base physical address of iwl3945_shared is provided to FH_TSSR_CBB_BASE
 * and &iwl3945_shared.rx_read_ptr[0] is provided to FH_RCSR_RPTR_ADDR(0) */
struct iwl3945_shared {
	__le32 tx_base_ptr[8];
} __packed;

static inline u8 iwl3945_hw_get_rate(__le16 rate_n_flags)
{
	return le16_to_cpu(rate_n_flags) & 0xFF;
}

static inline u16 iwl3945_hw_get_rate_n_flags(__le16 rate_n_flags)
{
	return le16_to_cpu(rate_n_flags);
}

static inline __le16 iwl3945_hw_set_rate_n_flags(u8 rate, u16 flags)
{
	return cpu_to_le16((u16)rate|flags);
}
#endif
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-25 21:15:50 +0000