From 1dc7d758f96dd2b9bd7b03f01ca032d68b696cf0 Mon Sep 17 00:00:00 2001 From: root Date: Sun, 2 Nov 2014 10:14:39 +0000 Subject: fish --- libopencm3/include/libopencm3/cm3/assert.h | 137 ++ libopencm3/include/libopencm3/cm3/common.h | 96 ++ libopencm3/include/libopencm3/cm3/cortex.h | 278 ++++ libopencm3/include/libopencm3/cm3/doc-cm3.h | 22 + libopencm3/include/libopencm3/cm3/dwt.h | 152 +++ libopencm3/include/libopencm3/cm3/fpb.h | 87 ++ libopencm3/include/libopencm3/cm3/itm.h | 88 ++ libopencm3/include/libopencm3/cm3/memorymap.h | 87 ++ libopencm3/include/libopencm3/cm3/mpu.h | 110 ++ libopencm3/include/libopencm3/cm3/scb.h | 444 +++++++ libopencm3/include/libopencm3/cm3/scs.h | 350 +++++ libopencm3/include/libopencm3/cm3/sync.h | 54 + libopencm3/include/libopencm3/cm3/systick.h | 134 ++ libopencm3/include/libopencm3/cm3/tpiu.h | 97 ++ libopencm3/include/libopencm3/cm3/vector.h | 64 + libopencm3/include/libopencm3/docmain.dox | 21 + .../include/libopencm3/efm32/efm32g/doc-efm32g.h | 32 + .../include/libopencm3/efm32/efm32g/irq.json | 38 + .../include/libopencm3/efm32/efm32gg/doc-efm32gg.h | 32 + .../include/libopencm3/efm32/efm32gg/irq.json | 46 + .../include/libopencm3/efm32/efm32lg/doc-efm32lg.h | 33 + .../include/libopencm3/efm32/efm32lg/irq.json | 46 + .../include/libopencm3/efm32/efm32tg/doc-efm32tg.h | 32 + .../include/libopencm3/efm32/efm32tg/irq.json | 31 + .../include/libopencm3/efm32/efm32tg/memorymap.h | 76 ++ libopencm3/include/libopencm3/efm32/memorymap.h | 37 + libopencm3/include/libopencm3/ethernet/mac.h | 46 + .../include/libopencm3/ethernet/mac_stm32fxx7.h | 752 +++++++++++ libopencm3/include/libopencm3/ethernet/phy.h | 91 ++ .../include/libopencm3/ethernet/phy_ksz8051mll.h | 60 + libopencm3/include/libopencm3/license.dox | 16 + libopencm3/include/libopencm3/lm3s/doc-lm3s.h | 32 + libopencm3/include/libopencm3/lm3s/gpio.h | 99 ++ libopencm3/include/libopencm3/lm3s/irq.json | 126 ++ libopencm3/include/libopencm3/lm3s/memorymap.h | 47 + libopencm3/include/libopencm3/lm3s/systemcontrol.h | 81 ++ libopencm3/include/libopencm3/lm4f/doc-lm4f.h | 32 + libopencm3/include/libopencm3/lm4f/gpio.h | 380 ++++++ libopencm3/include/libopencm3/lm4f/memorymap.h | 71 ++ libopencm3/include/libopencm3/lm4f/rcc.h | 133 ++ libopencm3/include/libopencm3/lm4f/ssi.h | 118 ++ libopencm3/include/libopencm3/lm4f/systemcontrol.h | 743 +++++++++++ libopencm3/include/libopencm3/lm4f/uart.h | 550 ++++++++ libopencm3/include/libopencm3/lm4f/usb.h | 422 ++++++ .../include/libopencm3/lpc13xx/doc-lpc13xx.h | 32 + libopencm3/include/libopencm3/lpc13xx/gpio.h | 124 ++ libopencm3/include/libopencm3/lpc13xx/irq.json | 63 + libopencm3/include/libopencm3/lpc13xx/memorymap.h | 58 + .../include/libopencm3/lpc17xx/doc-lpc17xx.h | 32 + libopencm3/include/libopencm3/lpc17xx/gpio.h | 160 +++ libopencm3/include/libopencm3/lpc17xx/irq.json | 42 + libopencm3/include/libopencm3/lpc17xx/memorymap.h | 65 + libopencm3/include/libopencm3/lpc43xx/adc.h | 113 ++ libopencm3/include/libopencm3/lpc43xx/atimer.h | 70 + libopencm3/include/libopencm3/lpc43xx/ccu.h | 402 ++++++ libopencm3/include/libopencm3/lpc43xx/cgu.h | 964 ++++++++++++++ libopencm3/include/libopencm3/lpc43xx/creg.h | 354 ++++++ .../include/libopencm3/lpc43xx/doc-lpc43xx.h | 32 + .../include/libopencm3/lpc43xx/eventrouter.h | 70 + libopencm3/include/libopencm3/lpc43xx/gima.h | 137 ++ libopencm3/include/libopencm3/lpc43xx/gpdma.h | 552 ++++++++ libopencm3/include/libopencm3/lpc43xx/gpio.h | 784 ++++++++++++ libopencm3/include/libopencm3/lpc43xx/i2c.h | 164 +++ libopencm3/include/libopencm3/lpc43xx/i2s.h | 122 ++ libopencm3/include/libopencm3/lpc43xx/ipc.h | 30 + libopencm3/include/libopencm3/lpc43xx/m0/irq.json | 36 + libopencm3/include/libopencm3/lpc43xx/m4/irq.json | 54 + libopencm3/include/libopencm3/lpc43xx/memorymap.h | 138 ++ libopencm3/include/libopencm3/lpc43xx/rgu.h | 1206 ++++++++++++++++++ libopencm3/include/libopencm3/lpc43xx/ritimer.h | 59 + libopencm3/include/libopencm3/lpc43xx/scu.h | 780 ++++++++++++ libopencm3/include/libopencm3/lpc43xx/sdio.h | 151 +++ libopencm3/include/libopencm3/lpc43xx/sgpio.h | 691 ++++++++++ libopencm3/include/libopencm3/lpc43xx/ssp.h | 209 +++ libopencm3/include/libopencm3/lpc43xx/timer.h | 270 ++++ libopencm3/include/libopencm3/lpc43xx/uart.h | 438 +++++++ libopencm3/include/libopencm3/lpc43xx/usb.h | 1337 ++++++++++++++++++++ libopencm3/include/libopencm3/lpc43xx/wwdt.h | 65 + libopencm3/include/libopencm3/sam/3a/irq.json | 52 + libopencm3/include/libopencm3/sam/3a/memorymap.h | 77 ++ libopencm3/include/libopencm3/sam/3n/irq.json | 39 + libopencm3/include/libopencm3/sam/3n/memorymap.h | 60 + libopencm3/include/libopencm3/sam/3s/irq.json | 42 + libopencm3/include/libopencm3/sam/3s/memorymap.h | 66 + libopencm3/include/libopencm3/sam/3u/irq.json | 37 + libopencm3/include/libopencm3/sam/3u/memorymap.h | 63 + libopencm3/include/libopencm3/sam/3x/irq.json | 52 + libopencm3/include/libopencm3/sam/3x/memorymap.h | 78 ++ libopencm3/include/libopencm3/sam/eefc.h | 83 ++ libopencm3/include/libopencm3/sam/gpio.h | 51 + libopencm3/include/libopencm3/sam/memorymap.h | 39 + libopencm3/include/libopencm3/sam/pio.h | 96 ++ libopencm3/include/libopencm3/sam/pmc.h | 146 +++ libopencm3/include/libopencm3/sam/pwm.h | 109 ++ libopencm3/include/libopencm3/sam/tc.h | 52 + libopencm3/include/libopencm3/sam/uart.h | 85 ++ libopencm3/include/libopencm3/sam/usart.h | 217 ++++ libopencm3/include/libopencm3/sam/wdt.h | 57 + libopencm3/include/libopencm3/stm32/adc.h | 36 + libopencm3/include/libopencm3/stm32/can.h | 679 ++++++++++ libopencm3/include/libopencm3/stm32/cec.h | 28 + .../libopencm3/stm32/common/adc_common_v1.h | 410 ++++++ .../libopencm3/stm32/common/crc_common_all.h | 118 ++ .../libopencm3/stm32/common/crypto_common_f24.h | 290 +++++ .../libopencm3/stm32/common/dac_common_all.h | 422 ++++++ .../libopencm3/stm32/common/dma_common_f24.h | 626 +++++++++ .../libopencm3/stm32/common/dma_common_l1f013.h | 425 +++++++ .../libopencm3/stm32/common/exti_common_all.h | 87 ++ .../libopencm3/stm32/common/exti_common_l1f24.h | 45 + .../libopencm3/stm32/common/flash_common_f01.h | 130 ++ .../libopencm3/stm32/common/flash_common_f234.h | 93 ++ .../libopencm3/stm32/common/flash_common_f24.h | 148 +++ .../libopencm3/stm32/common/gpio_common_all.h | 91 ++ .../libopencm3/stm32/common/gpio_common_f234.h | 272 ++++ .../libopencm3/stm32/common/gpio_common_f24.h | 111 ++ .../libopencm3/stm32/common/hash_common_f24.h | 181 +++ .../libopencm3/stm32/common/i2c_common_all.h | 401 ++++++ .../libopencm3/stm32/common/i2c_common_f24.h | 51 + .../libopencm3/stm32/common/iwdg_common_all.h | 121 ++ .../libopencm3/stm32/common/pwr_common_all.h | 132 ++ .../libopencm3/stm32/common/rcc_common_all.h | 61 + .../libopencm3/stm32/common/rng_common_f24.h | 71 ++ .../libopencm3/stm32/common/rtc_common_l1f024.h | 347 +++++ .../libopencm3/stm32/common/spi_common_all.h | 405 ++++++ .../libopencm3/stm32/common/spi_common_f03.h | 124 ++ .../libopencm3/stm32/common/spi_common_f24.h | 66 + .../libopencm3/stm32/common/spi_common_l1f124.h | 65 + .../libopencm3/stm32/common/syscfg_common_l1f234.h | 61 + .../libopencm3/stm32/common/timer_common_all.h | 1129 +++++++++++++++++ .../libopencm3/stm32/common/timer_common_f24.h | 114 ++ .../libopencm3/stm32/common/usart_common_all.h | 141 +++ .../libopencm3/stm32/common/usart_common_f124.h | 288 +++++ .../libopencm3/stm32/common/usart_common_f24.h | 98 ++ libopencm3/include/libopencm3/stm32/comparator.h | 28 + libopencm3/include/libopencm3/stm32/crc.h | 38 + libopencm3/include/libopencm3/stm32/crs.h | 28 + libopencm3/include/libopencm3/stm32/crypto.h | 30 + libopencm3/include/libopencm3/stm32/dac.h | 38 + libopencm3/include/libopencm3/stm32/dbgmcu.h | 72 ++ libopencm3/include/libopencm3/stm32/desig.h | 57 + libopencm3/include/libopencm3/stm32/dma.h | 38 + libopencm3/include/libopencm3/stm32/ethernet.h | 27 + libopencm3/include/libopencm3/stm32/exti.h | 40 + libopencm3/include/libopencm3/stm32/f0/adc.h | 352 ++++++ libopencm3/include/libopencm3/stm32/f0/cec.h | 125 ++ .../include/libopencm3/stm32/f0/comparator.h | 124 ++ libopencm3/include/libopencm3/stm32/f0/crc.h | 89 ++ libopencm3/include/libopencm3/stm32/f0/crs.h | 131 ++ libopencm3/include/libopencm3/stm32/f0/dac.h | 117 ++ libopencm3/include/libopencm3/stm32/f0/dma.h | 37 + .../include/libopencm3/stm32/f0/doc-stm32f0.h | 32 + libopencm3/include/libopencm3/stm32/f0/exti.h | 40 + libopencm3/include/libopencm3/stm32/f0/flash.h | 116 ++ libopencm3/include/libopencm3/stm32/f0/gpio.h | 75 ++ libopencm3/include/libopencm3/stm32/f0/i2c.h | 256 ++++ libopencm3/include/libopencm3/stm32/f0/irq.json | 39 + libopencm3/include/libopencm3/stm32/f0/iwdg.h | 70 + libopencm3/include/libopencm3/stm32/f0/memorymap.h | 116 ++ libopencm3/include/libopencm3/stm32/f0/pwr.h | 67 + libopencm3/include/libopencm3/stm32/f0/rcc.h | 524 ++++++++ libopencm3/include/libopencm3/stm32/f0/rtc.h | 36 + libopencm3/include/libopencm3/stm32/f0/spi.h | 36 + libopencm3/include/libopencm3/stm32/f0/syscfg.h | 110 ++ libopencm3/include/libopencm3/stm32/f0/timer.h | 37 + libopencm3/include/libopencm3/stm32/f0/tsc.h | 159 +++ libopencm3/include/libopencm3/stm32/f0/usart.h | 343 +++++ libopencm3/include/libopencm3/stm32/f1/adc.h | 420 ++++++ libopencm3/include/libopencm3/stm32/f1/bkp.h | 205 +++ libopencm3/include/libopencm3/stm32/f1/crc.h | 38 + libopencm3/include/libopencm3/stm32/f1/dac.h | 37 + libopencm3/include/libopencm3/stm32/f1/dma.h | 37 + .../include/libopencm3/stm32/f1/doc-stm32f1.h | 32 + libopencm3/include/libopencm3/stm32/f1/ethernet.h | 210 +++ libopencm3/include/libopencm3/stm32/f1/exti.h | 41 + libopencm3/include/libopencm3/stm32/f1/flash.h | 120 ++ libopencm3/include/libopencm3/stm32/f1/gpio.h | 955 ++++++++++++++ libopencm3/include/libopencm3/stm32/f1/i2c.h | 37 + libopencm3/include/libopencm3/stm32/f1/irq.json | 75 ++ libopencm3/include/libopencm3/stm32/f1/iwdg.h | 39 + libopencm3/include/libopencm3/stm32/f1/memorymap.h | 127 ++ libopencm3/include/libopencm3/stm32/f1/pwr.h | 37 + libopencm3/include/libopencm3/stm32/f1/rcc.h | 718 +++++++++++ libopencm3/include/libopencm3/stm32/f1/rtc.h | 170 +++ libopencm3/include/libopencm3/stm32/f1/spi.h | 37 + libopencm3/include/libopencm3/stm32/f1/timer.h | 56 + libopencm3/include/libopencm3/stm32/f1/usart.h | 37 + libopencm3/include/libopencm3/stm32/f2/crc.h | 38 + libopencm3/include/libopencm3/stm32/f2/crypto.h | 36 + libopencm3/include/libopencm3/stm32/f2/dac.h | 37 + libopencm3/include/libopencm3/stm32/f2/dma.h | 37 + .../include/libopencm3/stm32/f2/doc-stm32f2.h | 33 + libopencm3/include/libopencm3/stm32/f2/exti.h | 41 + libopencm3/include/libopencm3/stm32/f2/flash.h | 37 + libopencm3/include/libopencm3/stm32/f2/gpio.h | 37 + libopencm3/include/libopencm3/stm32/f2/hash.h | 36 + libopencm3/include/libopencm3/stm32/f2/i2c.h | 37 + libopencm3/include/libopencm3/stm32/f2/irq.json | 88 ++ libopencm3/include/libopencm3/stm32/f2/iwdg.h | 39 + libopencm3/include/libopencm3/stm32/f2/memorymap.h | 141 +++ libopencm3/include/libopencm3/stm32/f2/pwr.h | 59 + libopencm3/include/libopencm3/stm32/f2/rcc.h | 756 +++++++++++ libopencm3/include/libopencm3/stm32/f2/rng.h | 23 + libopencm3/include/libopencm3/stm32/f2/rtc.h | 36 + libopencm3/include/libopencm3/stm32/f2/spi.h | 37 + libopencm3/include/libopencm3/stm32/f2/syscfg.h | 44 + libopencm3/include/libopencm3/stm32/f2/timer.h | 39 + libopencm3/include/libopencm3/stm32/f2/usart.h | 37 + libopencm3/include/libopencm3/stm32/f3/adc.h | 939 ++++++++++++++ libopencm3/include/libopencm3/stm32/f3/crc.h | 70 + libopencm3/include/libopencm3/stm32/f3/dac.h | 37 + libopencm3/include/libopencm3/stm32/f3/dma.h | 37 + .../include/libopencm3/stm32/f3/doc-stm32f3.h | 32 + libopencm3/include/libopencm3/stm32/f3/exti.h | 51 + libopencm3/include/libopencm3/stm32/f3/flash.h | 73 ++ libopencm3/include/libopencm3/stm32/f3/gpio.h | 38 + libopencm3/include/libopencm3/stm32/f3/i2c.h | 443 +++++++ libopencm3/include/libopencm3/stm32/f3/irq.json | 88 ++ libopencm3/include/libopencm3/stm32/f3/iwdg.h | 53 + libopencm3/include/libopencm3/stm32/f3/memorymap.h | 129 ++ libopencm3/include/libopencm3/stm32/f3/pwr.h | 69 + libopencm3/include/libopencm3/stm32/f3/rcc.h | 602 +++++++++ libopencm3/include/libopencm3/stm32/f3/rtc.h | 42 + libopencm3/include/libopencm3/stm32/f3/spi.h | 36 + libopencm3/include/libopencm3/stm32/f3/syscfg.h | 41 + libopencm3/include/libopencm3/stm32/f3/timer.h | 39 + libopencm3/include/libopencm3/stm32/f3/usart.h | 527 ++++++++ libopencm3/include/libopencm3/stm32/f4/adc.h | 586 +++++++++ libopencm3/include/libopencm3/stm32/f4/crc.h | 38 + libopencm3/include/libopencm3/stm32/f4/crypto.h | 97 ++ libopencm3/include/libopencm3/stm32/f4/dac.h | 37 + libopencm3/include/libopencm3/stm32/f4/dma.h | 37 + .../include/libopencm3/stm32/f4/doc-stm32f4.h | 32 + libopencm3/include/libopencm3/stm32/f4/exti.h | 41 + libopencm3/include/libopencm3/stm32/f4/flash.h | 37 + libopencm3/include/libopencm3/stm32/f4/fmc.h | 247 ++++ libopencm3/include/libopencm3/stm32/f4/gpio.h | 37 + libopencm3/include/libopencm3/stm32/f4/hash.h | 36 + libopencm3/include/libopencm3/stm32/f4/i2c.h | 37 + libopencm3/include/libopencm3/stm32/f4/irq.json | 98 ++ libopencm3/include/libopencm3/stm32/f4/iwdg.h | 39 + libopencm3/include/libopencm3/stm32/f4/memorymap.h | 155 +++ libopencm3/include/libopencm3/stm32/f4/pwr.h | 86 ++ libopencm3/include/libopencm3/stm32/f4/rcc.h | 784 ++++++++++++ libopencm3/include/libopencm3/stm32/f4/rng.h | 23 + libopencm3/include/libopencm3/stm32/f4/rtc.h | 45 + libopencm3/include/libopencm3/stm32/f4/spi.h | 37 + libopencm3/include/libopencm3/stm32/f4/syscfg.h | 41 + libopencm3/include/libopencm3/stm32/f4/timer.h | 39 + libopencm3/include/libopencm3/stm32/f4/usart.h | 37 + libopencm3/include/libopencm3/stm32/flash.h | 38 + libopencm3/include/libopencm3/stm32/fsmc.h | 308 +++++ libopencm3/include/libopencm3/stm32/gpio.h | 38 + libopencm3/include/libopencm3/stm32/hash.h | 30 + libopencm3/include/libopencm3/stm32/i2c.h | 38 + libopencm3/include/libopencm3/stm32/iwdg.h | 38 + libopencm3/include/libopencm3/stm32/l1/adc.h | 227 ++++ libopencm3/include/libopencm3/stm32/l1/crc.h | 38 + libopencm3/include/libopencm3/stm32/l1/dac.h | 37 + libopencm3/include/libopencm3/stm32/l1/dma.h | 42 + .../include/libopencm3/stm32/l1/doc-stm32l1.h | 32 + libopencm3/include/libopencm3/stm32/l1/exti.h | 41 + libopencm3/include/libopencm3/stm32/l1/flash.h | 156 +++ libopencm3/include/libopencm3/stm32/l1/gpio.h | 263 ++++ libopencm3/include/libopencm3/stm32/l1/i2c.h | 37 + libopencm3/include/libopencm3/stm32/l1/irq.json | 64 + libopencm3/include/libopencm3/stm32/l1/iwdg.h | 39 + libopencm3/include/libopencm3/stm32/l1/lcd.h | 231 ++++ libopencm3/include/libopencm3/stm32/l1/memorymap.h | 126 ++ libopencm3/include/libopencm3/stm32/l1/pwr.h | 111 ++ libopencm3/include/libopencm3/stm32/l1/rcc.h | 612 +++++++++ libopencm3/include/libopencm3/stm32/l1/rtc.h | 36 + libopencm3/include/libopencm3/stm32/l1/spi.h | 37 + libopencm3/include/libopencm3/stm32/l1/syscfg.h | 41 + libopencm3/include/libopencm3/stm32/l1/timer.h | 89 ++ libopencm3/include/libopencm3/stm32/l1/usart.h | 37 + libopencm3/include/libopencm3/stm32/memorymap.h | 39 + libopencm3/include/libopencm3/stm32/otg_fs.h | 350 +++++ libopencm3/include/libopencm3/stm32/otg_hs.h | 398 ++++++ libopencm3/include/libopencm3/stm32/pwr.h | 38 + libopencm3/include/libopencm3/stm32/rcc.h | 38 + libopencm3/include/libopencm3/stm32/rtc.h | 36 + libopencm3/include/libopencm3/stm32/sdio.h | 425 +++++++ libopencm3/include/libopencm3/stm32/spi.h | 38 + libopencm3/include/libopencm3/stm32/syscfg.h | 36 + libopencm3/include/libopencm3/stm32/timer.h | 40 + libopencm3/include/libopencm3/stm32/tools.h | 65 + libopencm3/include/libopencm3/stm32/tsc.h | 28 + libopencm3/include/libopencm3/stm32/usart.h | 38 + libopencm3/include/libopencm3/stm32/usb.h | 303 +++++ libopencm3/include/libopencm3/stm32/usb_desc.h | 101 ++ libopencm3/include/libopencm3/stm32/wwdg.h | 83 ++ libopencm3/include/libopencm3/usb/cdc.h | 162 +++ libopencm3/include/libopencm3/usb/dfu.h | 102 ++ libopencm3/include/libopencm3/usb/doc-usb.h | 32 + libopencm3/include/libopencm3/usb/hid.h | 59 + libopencm3/include/libopencm3/usb/msc.h | 93 ++ libopencm3/include/libopencm3/usb/usbd.h | 120 ++ libopencm3/include/libopencm3/usb/usbstd.h | 255 ++++ libopencm3/include/libopencmsis/core_cm3.h | 183 +++ .../include/libopencmsis/dispatch/irqhandlers.h | 50 + 300 files changed, 46008 insertions(+) create mode 100644 libopencm3/include/libopencm3/cm3/assert.h create mode 100644 libopencm3/include/libopencm3/cm3/common.h create mode 100644 libopencm3/include/libopencm3/cm3/cortex.h create mode 100644 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libopencm3/include/libopencm3/usb/usbstd.h create mode 100644 libopencm3/include/libopencmsis/core_cm3.h create mode 100644 libopencm3/include/libopencmsis/dispatch/irqhandlers.h (limited to 'libopencm3/include') diff --git a/libopencm3/include/libopencm3/cm3/assert.h b/libopencm3/include/libopencm3/cm3/assert.h new file mode 100644 index 0000000..f1aabc3 --- /dev/null +++ b/libopencm3/include/libopencm3/cm3/assert.h @@ -0,0 +1,137 @@ +/** @defgroup debugging Debugging + +@brief Macros and functions to aid in debugging + +@version 1.0.0 + +@date 25 September 2012 + +Two preprocessor defines control the behavior of assertion check macros in +this module. They allow the choice between generated code size and ease of +debugging. + +If NDEBUG is defined, all assertion checks are disabled and macros do not +generate any code. + +If CM3_ASSERT_VERBOSE is defined, information regarding the position of +assertion checks will be stored in the binary, allowing for more +informative error messages, but also significantly increased code size. As +default assertion checks do not use this information it is only useful if +the application linked with libopencm3 defines its own +cm3_assert_failed_verbose() implementation. + +LGPL License Terms @ref lgpl_license +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Tomaz Solc + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#ifndef LIBOPENCM3_CM3_ASSERT_H +#define LIBOPENCM3_CM3_ASSERT_H + +#include + +#define CM3_LIKELY(expr) (__builtin_expect(!!(expr), 1)) + +#ifdef NDEBUG +# define cm3_assert(expr) (void)0 +# define cm3_assert_not_reached() do { } while (1) +#else +# ifdef CM3_ASSERT_VERBOSE +# define cm3_assert(expr) do { \ + if (CM3_LIKELY(expr)) { \ + (void)0; \ + } else { \ + cm3_assert_failed_verbose( \ + __FILE__, __LINE__, \ + __func__, #expr); \ + } \ + } while (0) +# define cm3_assert_not_reached() \ + cm3_assert_failed_verbose( \ + __FILE__, __LINE__, \ + __func__, 0) +# else +/** @brief Check if assertion is true. + * + * If NDEBUG macro is defined, this macro generates no code. Otherwise + * cm3_assert_failed() or cm3_assert_failed_verbose() is called if assertion + * is false. + * + * The purpose of this macro is to aid in debugging libopencm3 and + * applications using it. It can be used for example to check if function + * arguments are within expected ranges and stop execution in case an + * unexpected state is reached. + * + * @param expr expression to check */ +# define cm3_assert(expr) do { \ + if (CM3_LIKELY(expr)) { \ + (void)0; \ + } else { \ + cm3_assert_failed(); \ + } \ + } while (0) +/** @brief Check if unreachable code is reached. + * + * If NDEBUG macro is defined, this macro generates code for an infinite loop. + * Otherwise cm3_assert_failed() or cm3_assert_failed_verbose() is called if + * the macro is ever reached. + * + * The purpose of this macro is to aid in debugging libopencm3 and + * applications using it. It can be used for example to stop execution if an + * unreachable portion of code is reached. */ +# define cm3_assert_not_reached() cm3_assert_failed() +# endif +#endif + +BEGIN_DECLS + +/** @brief Called on a failed assertion. + * + * Halts execution in an infinite loop. This function never returns. + * + * Defined as a weak symbol, so applications can define their own + * implementation. Usually, a custom implementation of this function should + * report an error in some way (print a message to a debug console, display, + * LED, ...) and halt execution or reboot the device. */ +void cm3_assert_failed(void) __attribute__((__noreturn__)); + +/** @brief Called on a failed assertion with verbose messages enabled. + * + * Halts execution in an infinite loop. This function never returns. + * + * Defined as a weak symbol, so applications can define their own + * implementation. Usually, a custom implementation of this function should + * report an error in some way (print a message to a debug console, display, + * LED, ...) and halt execution or reboot the device. + * + * @param file File name where the failed assertion occurred + * @param line Line number where the failed assertion occurred + * @param func Name of the function where the failed assertion occurred + * @param assert_expr Expression that evaluated to false (can be NULL) */ +void cm3_assert_failed_verbose(const char *file, int line, const char *func, + const char *assert_expr) __attribute__((__noreturn__)); + +END_DECLS + +#endif + +/**@}*/ diff --git a/libopencm3/include/libopencm3/cm3/common.h b/libopencm3/include/libopencm3/cm3/common.h new file mode 100644 index 0000000..a7a8df8 --- /dev/null +++ b/libopencm3/include/libopencm3/cm3/common.h @@ -0,0 +1,96 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CM3_COMMON_H +#define LIBOPENCM3_CM3_COMMON_H + +#include +#include + +/* This must be placed around external function declaration for C++ + * support. */ +#ifdef __cplusplus +# define BEGIN_DECLS extern "C" { +# define END_DECLS } +#else +# define BEGIN_DECLS +# define END_DECLS +#endif + +/* Full-featured deprecation attribute with fallback for older compilers. */ + +#ifdef __GNUC__ +# if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ > 4) +# define LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x))) +# else +# define LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated)) +# endif +#else +# define LIBOPENCM3_DEPRECATED(x) +#endif + + +/* Generic memory-mapped I/O accessor functions */ +#define MMIO8(addr) (*(volatile uint8_t *)(addr)) +#define MMIO16(addr) (*(volatile uint16_t *)(addr)) +#define MMIO32(addr) (*(volatile uint32_t *)(addr)) +#define MMIO64(addr) (*(volatile uint64_t *)(addr)) + +/* Generic bit-band I/O accessor functions */ +#define BBIO_SRAM(addr, bit) \ + MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x22000000 + (bit) * 4) + +#define BBIO_PERIPH(addr, bit) \ + MMIO32((((uint32_t)addr) & 0x0FFFFF) * 32 + 0x42000000 + (bit) * 4) + +/* Generic bit definition */ +#define BIT0 (1<<0) +#define BIT1 (1<<1) +#define BIT2 (1<<2) +#define BIT3 (1<<3) +#define BIT4 (1<<4) +#define BIT5 (1<<5) +#define BIT6 (1<<6) +#define BIT7 (1<<7) +#define BIT8 (1<<8) +#define BIT9 (1<<9) +#define BIT10 (1<<10) +#define BIT11 (1<<11) +#define BIT12 (1<<12) +#define BIT13 (1<<13) +#define BIT14 (1<<14) +#define BIT15 (1<<15) +#define BIT16 (1<<16) +#define BIT17 (1<<17) +#define BIT18 (1<<18) +#define BIT19 (1<<19) +#define BIT20 (1<<20) +#define BIT21 (1<<21) +#define BIT22 (1<<22) +#define BIT23 (1<<23) +#define BIT24 (1<<24) +#define BIT25 (1<<25) +#define BIT26 (1<<26) +#define BIT27 (1<<27) +#define BIT28 (1<<28) +#define BIT29 (1<<29) +#define BIT30 (1<<30) +#define BIT31 (1<<31) + +#endif diff --git a/libopencm3/include/libopencm3/cm3/cortex.h b/libopencm3/include/libopencm3/cm3/cortex.h new file mode 100644 index 0000000..eb9cb09 --- /dev/null +++ b/libopencm3/include/libopencm3/cm3/cortex.h @@ -0,0 +1,278 @@ +/** @defgroup CM3_cortex_defines Cortex Core Defines + * + * @brief libopencm3 Defined Constants and Types for the Cortex Core + * + * @ingroup CM3_defines + * + * @version 1.0.0 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Ben Gamari + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CORTEX_H +#define LIBOPENCM3_CORTEX_H + +/**@{*/ + +/*---------------------------------------------------------------------------*/ +/** @brief Cortex M Enable interrupts + * + * Disable the interrupt mask and enable interrupts globally + */ +static inline void cm_enable_interrupts(void) +{ + __asm__("CPSIE I\n"); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Cortex M Disable interrupts + * + * Mask all interrupts globally + */ +static inline void cm_disable_interrupts(void) +{ + __asm__("CPSID I\n"); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Cortex M Enable faults + * + * Disable the HardFault mask and enable fault interrupt globally + */ +static inline void cm_enable_faults(void) +{ + __asm__("CPSIE F\n"); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Cortex M Disable faults + * + * Mask the HardFault interrupt globally + */ +static inline void cm_disable_faults(void) +{ + __asm__("CPSID F\n"); +} + +/*---------------------------------------------------------------------------*/ +/** @brief Cortex M Check if interrupts are masked + * + * Checks, if interrupts are masked (disabled). + * + * @returns true, if interrupts are disabled. + */ +__attribute__((always_inline)) +static inline bool cm_is_masked_interrupts(void) +{ + register uint32_t result; + __asm__ ("MRS %0, PRIMASK" : "=r" (result)); + return result; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Cortex M Check if Fault interrupt is masked + * + * Checks, if HardFault interrupt is masked (disabled). + * + * @returns bool true, if HardFault interrupt is disabled. + */ +__attribute__((always_inline)) +static inline bool cm_is_masked_faults(void) +{ + register uint32_t result; + __asm__ ("MRS %0, FAULTMASK" : "=r" (result)); + return result; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Cortex M Mask interrupts + * + * This function switches the mask of the interrupts. If mask is true, the + * interrupts will be disabled. The result of this function can be used for + * restoring previous state of the mask. + * + * @param[in] mask bool New state of the interrupt mask + * @returns bool old state of the interrupt mask + */ +__attribute__((always_inline)) +static inline bool cm_mask_interrupts(bool mask) +{ + register bool old; + __asm__ __volatile__("MRS %0, PRIMASK" : "=r" (old)); + __asm__ __volatile__("" : : : "memory"); + __asm__ __volatile__("MSR PRIMASK, %0" : : "r" (mask)); + return old; +} + +/*---------------------------------------------------------------------------*/ +/** @brief Cortex M Mask HardFault interrupt + * + * This function switches the mask of the HardFault interrupt. If mask is true, + * the HardFault interrupt will be disabled. The result of this function can be + * used for restoring previous state of the mask. + * + * @param[in] mask bool New state of the HardFault interrupt mask + * @returns bool old state of the HardFault interrupt mask + */ +__attribute__((always_inline)) +static inline bool cm_mask_faults(bool mask) +{ + register bool old; + __asm__ __volatile__ ("MRS %0, FAULTMASK" : "=r" (old)); + __asm__ __volatile__ ("" : : : "memory"); + __asm__ __volatile__ ("MSR FAULTMASK, %0" : : "r" (mask)); + return old; +} + +/**@}*/ + +/*===========================================================================*/ +/** @defgroup CM3_cortex_atomic_defines Cortex Core Atomic support Defines + * + * @brief Atomic operation support + * + * @ingroup CM3_cortex_defines + */ +/**@{*/ + +#if !defined(__DOXYGEN__) +/* Do not populate this definition outside */ +static inline bool __cm_atomic_set(bool *val) +{ + return cm_mask_interrupts(*val); +} + +#define __CM_SAVER(state) \ + __val = state, \ + __save __attribute__((__cleanup__(__cm_atomic_set))) = \ + __cm_atomic_set(&__val) + +#endif /* !defined(__DOXYGEN) */ + + +/*---------------------------------------------------------------------------*/ +/** @brief Cortex M Atomic Declare block + * + * This macro disables interrupts for the next command or block of code. The + * interrupt mask is automatically restored after exit of the boundary of the + * code block. Therefore restore of interrupt is done automatically after call + * of return or goto control sentence jumping outside of the block. + * + * @warning The usage of sentences break or continue is prohibited in the block + * due to implementation of this macro! + * + * @note It is safe to use this block inside normal code and in interrupt + * routine. + * + * @example 1: Basic usage of atomic block + * + * @code + * uint64_t value; // This value is used somewhere in interrupt + * + * ... + * + * CM_ATOMIC_BLOCK() { // interrupts are masked in this block + * value = value * 1024 + 651; // access value as atomic + * } // interrupts is restored automatically + * @endcode + * + * @example 2: Use of return inside block: + * + * @code + * uint64_t value; // This value is used somewhere in interrupt + * + * ... + * + * uint64_t allocval(void) + * { + * CM_ATOMIC_BLOCK() { // interrupts are masked in this block + * value = value * 1024 + 651; // do long atomic operation + * return value; // interrupts is restored automatically + * } + * } + * @endcode + */ +#if defined(__DOXYGEN__) +#define CM_ATOMIC_BLOCK() +#else /* defined(__DOXYGEN__) */ +#define CM_ATOMIC_BLOCK() \ + for (bool ___CM_SAVER(true), __my = true; __my; __my = false) +#endif /* defined(__DOXYGEN__) */ + +/*---------------------------------------------------------------------------*/ +/** @brief Cortex M Atomic Declare context + * + * This macro disables interrupts in the current block of code from the place + * where it is defined to the end of the block. The interrupt mask is + * automatically restored after exit of the boundary of the code block. + * Therefore restore of interrupt is done automatically after call of return, + * continue, break, or goto control sentence jumping outside of the block. + * + * @note This function is intended for use in for- cycles to enable the use of + * break and contine sentences inside the block, and for securing the atomic + * reader-like functions. + * + * @note It is safe to use this block inside normal code and in interrupt + * routine. + * + * @example 1: Basic usage of atomic context + * + * @code + * uint64_t value; // This value is used somewhere in interrupt + * + * ... + * + * for (int i=0;i < 100; i++) { + * CM_ATOMIC_CONTEXT(); // interrupts are masked in this block + * value += 100; // access value as atomic + * if ((value % 16) == 0) { + * break; // restore interrupts and break cycle + * } + * } // interrupts is restored automatically + * @endcode + * + * @example 2: Usage of atomic context inside atomic reader fcn. + * + * @code + * uint64_t value; // This value is used somewhere in interrupt + * + * ... + * + * uint64_t getnextval(void) + * { + * CM_ATOMIC_CONTEXT(); // interrupts are masked in this block + * value = value + 3; // do long atomic operation + * return value; // interrupts is restored automatically + * } + * @endcode + */ +#if defined(__DOXYGEN__) +#define CM_ATOMIC_CONTEXT() +#else /* defined(__DOXYGEN__) */ +#define CM_ATOMIC_CONTEXT() bool __CM_SAVER(true) +#endif /* defined(__DOXYGEN__) */ + +/**@}*/ + + + +#endif diff --git a/libopencm3/include/libopencm3/cm3/doc-cm3.h b/libopencm3/include/libopencm3/cm3/doc-cm3.h new file mode 100644 index 0000000..0f76370 --- /dev/null +++ b/libopencm3/include/libopencm3/cm3/doc-cm3.h @@ -0,0 +1,22 @@ +/** @mainpage libopencm3 Core CM3 + +@version 1.0.0 + +@date 14 September 2012 + +API documentation for Cortex M3 core features. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup CM3_defines CM3 Defines + +@brief Defined Constants and Types for Cortex M3 core features + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/libopencm3/include/libopencm3/cm3/dwt.h b/libopencm3/include/libopencm3/cm3/dwt.h new file mode 100644 index 0000000..184b509 --- /dev/null +++ b/libopencm3/include/libopencm3/cm3/dwt.h @@ -0,0 +1,152 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CM3_DWT_H +#define LIBOPENCM3_CM3_DWT_H + +#include +#include + +/*****************************************************************************/ +/* Register definitions */ +/*****************************************************************************/ + +#define DWT_CTRL MMIO32(DWT_BASE + 0x00) + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + +#define DWT_CYCCNT MMIO32(DWT_BASE + 0x04) +#define DWT_CPICNT MMIO32(DWT_BASE + 0x08) +#define DWT_EXCCNT MMIO32(DWT_BASE + 0x0C) +#define DWT_SLEEPCNT MMIO32(DWT_BASE + 0x10) +#define DWT_LSUCNT MMIO32(DWT_BASE + 0x14) +#define DWT_FOLDCNT MMIO32(DWT_BASE + 0x18) + +#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */ + +#define DWT_PCSR MMIO32(DWT_BASE + 0x1C) +#define DWT_COMP(n) MMIO32(DWT_BASE + 0x20 + (n) * 16) +#define DWT_MASK(n) MMIO32(DWT_BASE + 0x24 + (n) * 16) +#define DWT_FUNCTION(n) MMIO32(DWT_BASE + 0x28 + (n) * 16) + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +/* --- DWT_CTRL values ---------------------------------------------------- */ + +#define DWT_CTRL_NUMCOMP_SHIFT 28 +#define DWT_CTRL_NUMCOMP (0x0F << DWT_CTRL_NUMCOMP_SHIFT) + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + +#define DWT_CTRL_NOTRCPKT (1 << 27) +#define DWT_CTRL_NOEXTTRIG (1 << 26) +#define DWT_CTRL_NOCYCCNT (1 << 25) +#define DWT_CTRL_NOPRFCCNT (1 << 24) + +#define DWT_CTRL_CYCEVTENA (1 << 22) +#define DWT_CTRL_FOLDEVTENA (1 << 21) +#define DWT_CTRL_LSUEVTENA (1 << 20) +#define DWT_CTRL_SLEEPEVTENA (1 << 19) +#define DWT_CTRL_EXCEVTENA (1 << 18) +#define DWT_CTRL_CPIEVTENA (1 << 17) +#define DWT_CTRL_EXCTRCENA (1 << 16) +#define DWT_CTRL_PCSAMPLENA (1 << 12) + +#define DWT_CTRL_SYNCTAP_SHIFT 10 +#define DWT_CTRL_SYNCTAP (3 << DWT_CTRL_SYNCTAP_SHIFT) +#define DWT_CTRL_SYNCTAP_DISABLED (0 << DWT_CTRL_SYNCTAP_SHIFT) +#define DWT_CTRL_SYNCTAP_BIT24 (1 << DWT_CTRL_SYNCTAP_SHIFT) +#define DWT_CTRL_SYNCTAP_BIT26 (2 << DWT_CTRL_SYNCTAP_SHIFT) +#define DWT_CTRL_SYNCTAP_BIT28 (3 << DWT_CTRL_SYNCTAP_SHIFT) + +#define DWT_CTRL_CYCTAP (1 << 9) + +#define DWT_CTRL_POSTCNT_SHIFT 5 +#define DWT_CTRL_POSTCNT (0x0F << DWT_CTRL_POSTCNT_SHIFT) + +#define DWT_CTRL_POSTPRESET_SHIFT 1 +#define DWT_CTRL_POSTPRESET (0x0F << DWT_CTRL_POSTPRESET_SHIFT) + +#define DWT_CTRL_CYCCNTENA (1 << 0) + +#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */ + +/* --- DWT_MASK(x) values -------------------------------------------------- */ + +#define DWT_MASKx_MASK 0x0F + +/* --- DWT_FUNCTION(x) values ---------------------------------------------- */ + +#define DWT_FUNCTIONx_MATCHED (1 << 24) + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + +#define DWT_FUNCTIONx_DATAVADDR1_SHIFT 16 +#define DWT_FUNCTIONx_DATAVADDR1 (15 << DWT_FUNCTIONx_DATAVADDR1_SHIFT) + +#define DWT_FUNCTIONx_DATAVADDR0_SHIFT 12 +#define DWT_FUNCTIONx_DATAVADDR0 (15 << DWT_FUNCTIONx_DATAVADDR0_SHIFT) + +#define DWT_FUNCTIONx_DATAVSIZE_SHIFT 10 +#define DWT_FUNCTIONx_DATAVSIZE (3 << DWT_FUNCTIONx_DATAVSIZE_SHIFT) +#define DWT_FUNCTIONx_DATAVSIZE_BYTE (0 << DWT_FUNCTIONx_DATAVSIZE_SHIFT) +#define DWT_FUNCTIONx_DATAVSIZE_HALF (1 << DWT_FUNCTIONx_DATAVSIZE_SHIFT) +#define DWT_FUNCTIONx_DATAVSIZE_WORD (2 << DWT_FUNCTIONx_DATAVSIZE_SHIFT) + +#define DWT_FUNCTIONx_LNK1ENA (1 << 9) +#define DWT_FUNCTIONx_DATAVMATCH (1 << 8) +#define DWT_FUNCTIONx_CYCMATCH (1 << 7) +#define DWT_FUNCTIONx_EMITRANGE (1 << 5) + +#endif /* defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) */ + +#define DWT_FUNCTIONx_FUNCTION 15 +#define DWT_FUNCTIONx_FUNCTION_DISABLED 0 + +/* Those defined only on ARMv6 */ +#if defined(__ARM_ARCH_6M__) + +#define DWT_FUNCTIONx_FUNCTION_PCWATCH 4 +#define DWT_FUNCTIONx_FUNCTION_DWATCH_R 5 +#define DWT_FUNCTIONx_FUNCTION_DWATCH_W 6 +#define DWT_FUNCTIONx_FUNCTION_DWATCH_RW 7 + +#endif /* defined(__ARM_ARCH_6M__)*/ + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + +BEGIN_DECLS + +bool dwt_enable_cycle_counter(void); +uint32_t dwt_read_cycle_counter(void); + +END_DECLS + +#endif /* LIBOPENCM3_CM3_DWT_H */ diff --git a/libopencm3/include/libopencm3/cm3/fpb.h b/libopencm3/include/libopencm3/cm3/fpb.h new file mode 100644 index 0000000..fe624da --- /dev/null +++ b/libopencm3/include/libopencm3/cm3/fpb.h @@ -0,0 +1,87 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CM3_FPB_H +#define LIBOPENCM3_CM3_FPB_H + +/* Cortex-M3 Flash Patch and Breakpoint (FPB) unit */ + +/* Those defined only on ARMv7 and above */ +#if !defined(__ARM_ARCH_7M__) || !defined(__ARM_ARCH_7EM__) +#error "Flash Patch and Breakpoint not available in CM0" +#endif + +/* Note: We always use "FPB" as abbreviation, docs sometimes use only "FP". */ + +/* --- FPB registers ------------------------------------------------------- */ + +/* Flash Patch Control (FPB_CTRL) */ +#define FPB_CTRL MMIO32(FPB_BASE + 0) + +/* Flash Patch Remap (FPB_REMAP) */ +#define FPB_REMAP MMIO32(FPB_BASE + 4) + +/* Flash Patch Comparator (FPB_COMPx) */ +#define FPB_COMP (&MMIO32(FPB_BASE + 8)) + +/* CoreSight Lock Status Register for this peripheral */ +#define FPB_LSR MMIO32(FPB_BASE + 0xFB4) +/* CoreSight Lock Access Register for this peripheral */ +#define FPB_LAR MMIO32(FPB_BASE + 0xFB0) + + +/* TODO: PID, CID */ + +/* --- FPB_CTRL values ----------------------------------------------------- */ + +/* Bits [31:15]: Reserved, read as zero, writes ignored */ + +#define FPB_CTRL_NUM_CODE2_MASK (0x7 << 12) + +#define FPB_CTRL_NUM_LIT_MASK (0xf << 8) + +#define FPB_CTRL_NUM_CODE1_MASK (0xf << 4) + +/* Bits [3:2]: Reserved */ + +#define FPB_CTRL_KEY (1 << 1) + +#define FPB_CTRL_ENABLE (1 << 0) + +/* --- FPB_REMAP values ---------------------------------------------------- */ + +/* TODO */ + +/* --- FPB_COMPx values ---------------------------------------------------- */ + +#define FPB_COMP_REPLACE_REMAP (0x0 << 30) +#define FPB_COMP_REPLACE_BREAK_LOWER (0x1 << 30) +#define FPB_COMP_REPLACE_BREAK_UPPER (0x2 << 30) +#define FPB_COMP_REPLACE_BREAK_BOTH (0x3 << 30) +#define FPB_COMP_REPLACE_MASK (0x3 << 30) + +/* Bit 29: Reserved */ + +/* TODO */ + +/* Bit 1: Reserved */ + +#define FPB_COMP_ENABLE (1 << 0) + +#endif diff --git a/libopencm3/include/libopencm3/cm3/itm.h b/libopencm3/include/libopencm3/cm3/itm.h new file mode 100644 index 0000000..8b55119 --- /dev/null +++ b/libopencm3/include/libopencm3/cm3/itm.h @@ -0,0 +1,88 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CM3_ITM_H +#define LIBOPENCM3_CM3_ITM_H + +/* Cortex-M3 Instrumentation Trace Macrocell (ITM) */ + +/* Those defined only on ARMv7 and above */ +#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) +#error "Instrumentation Trace Macrocell not available in CM0" +#endif + +/* --- ITM registers ------------------------------------------------------- */ + +/* Stimulus Port x (ITM_STIM(x)) */ +#define ITM_STIM8(n) (MMIO8(ITM_BASE + (n*4))) +#define ITM_STIM16(n) (MMIO16(ITM_BASE + (n*4))) +#define ITM_STIM32(n) (MMIO32(ITM_BASE + (n*4))) + +/* Trace Enable ports (ITM_TER[x]) */ +#define ITM_TER (&MMIO32(ITM_BASE + 0xE00)) + +/* Trace Privilege (ITM_TPR) */ +#define ITM_TPR MMIO32(ITM_BASE + 0xE40) + +/* Trace Control (ITM_TCR) */ +#define ITM_TCR MMIO32(ITM_BASE + 0xE80) + +/* CoreSight Lock Status Register for this peripheral */ +#define ITM_LSR MMIO32(ITM_BASE + 0xFB4) +/* CoreSight Lock Access Register for this peripheral */ +#define ITM_LAR MMIO32(ITM_BASE + 0xFB0) + +/* TODO: PID, CID */ + +/* --- ITM_STIM values ----------------------------------------------------- */ + +/* Bits 31:0 - Write to port FIFO for forwarding as software event packet */ +/* Bits 31:1 - RAZ */ +#define ITM_STIM_FIFOREADY (1 << 0) + +/* --- ITM_TER values ------------------------------------------------------ */ + +/* Bits 31:0 - Stimulus port #N is enabled with STIMENA[N] is set */ + +/* --- ITM_TPR values ------------------------------------------------------ */ +/* + * Bits 31:0 - Bit [N] of PRIVMASK controls stimulus ports 8N to 8N+7 + * 0: User access allowed to stimulus ports + * 1: Privileged access only to stimulus ports + */ + +/* --- ITM_TCR values ------------------------------------------------------ */ + +/* Bits 31:24 - Reserved */ +#define ITM_TCR_BUSY (1 << 23) +#define ITM_TCR_TRACE_BUS_ID_MASK (0x3f << 16) +/* Bits 15:10 - Reserved */ +#define ITM_TCR_TSPRESCALE_NONE (0 << 8) +#define ITM_TCR_TSPRESCALE_DIV4 (1 << 8) +#define ITM_TCR_TSPRESCALE_DIV16 (2 << 8) +#define ITM_TCR_TSPRESCALE_DIV64 (3 << 8) +#define ITM_TCR_TSPRESCALE_MASK (3 << 8) +/* Bits 7:5 - Reserved */ +#define ITM_TCR_SWOENA (1 << 4) +#define ITM_TCR_TXENA (1 << 3) +#define ITM_TCR_SYNCENA (1 << 2) +#define ITM_TCR_TSENA (1 << 1) +#define ITM_TCR_ITMENA (1 << 0) + +#endif diff --git a/libopencm3/include/libopencm3/cm3/memorymap.h b/libopencm3/include/libopencm3/cm3/memorymap.h new file mode 100644 index 0000000..a7a5694 --- /dev/null +++ b/libopencm3/include/libopencm3/cm3/memorymap.h @@ -0,0 +1,87 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CM3_MEMORYMAP_H +#define LIBOPENCM3_CM3_MEMORYMAP_H + +/* --- ARM Cortex-M0, M3 and M4 specific definitions ----------------------- */ + +/* Private peripheral bus - Internal */ +#define PPBI_BASE (0xE0000000U) + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) +/* ITM: Instrumentation Trace Macrocell */ +#define ITM_BASE (PPBI_BASE + 0x0000) + +/* DWT: Data Watchpoint and Trace unit */ +#define DWT_BASE (PPBI_BASE + 0x1000) + +/* FPB: Flash Patch and Breakpoint unit */ +#define FPB_BASE (PPBI_BASE + 0x2000) +#endif + +/* PPBI_BASE + 0x3000 (0xE000 3000 - 0xE000 DFFF): Reserved */ + +#define SCS_BASE (PPBI_BASE + 0xE000) + +/* PPBI_BASE + 0xF000 (0xE000 F000 - 0xE003 FFFF): Reserved */ + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) +#define TPIU_BASE (PPBI_BASE + 0x40000) +#endif + +/* --- SCS: System Control Space --- */ + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) +/* ITR: Interrupt Type Register */ +#define ITR_BASE (SCS_BASE + 0x0000) +#endif + +/* SYS_TICK: System Timer */ +#define SYS_TICK_BASE (SCS_BASE + 0x0010) + +/* NVIC: Nested Vector Interrupt Controller */ +#define NVIC_BASE (SCS_BASE + 0x0100) + +/* SCB: System Control Block */ +#define SCB_BASE (SCS_BASE + 0x0D00) + +#ifdef CM0_PLUS +/* MPU: Memory protection unit */ +#define MPU_BASE (SCS_BASE + 0x0D90) +#endif + +/* Those defined only on CM0*/ +#if defined(__ARM_ARCH_6M__) +/* DEBUG: Debug control and configuration */ +#define DEBUG_BASE (SCS_BASE + 0x0DF0) +#endif + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) +/* STE: Software Trigger Interrupt Register */ +#define STIR_BASE (SCS_BASE + 0x0F00) +/* ID: ID space */ +#define ID_BASE (SCS_BASE + 0x0FD0) +#endif + +#endif diff --git a/libopencm3/include/libopencm3/cm3/mpu.h b/libopencm3/include/libopencm3/cm3/mpu.h new file mode 100644 index 0000000..9efa83e --- /dev/null +++ b/libopencm3/include/libopencm3/cm3/mpu.h @@ -0,0 +1,110 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CM0_MPU_H +#define LIBOPENCM3_CM0_MPU_H + +#ifndef CM0_PLUS +#error "mpu is supported only on CM0+ architecture" +#else + +#include +#include + +/* --- SCB: Registers ------------------------------------------------------ */ + +#define MPU_TYPE MMIO32(MPU_BASE + 0x00) +#define MPU_CTRL MMIO32(MPU_BASE + 0x04) +#define MPU_RNR MMIO32(MPU_BASE + 0x08) +#define MPU_RBAR MMIO32(MPU_BASE + 0x0C) +#define MPU_RASR MMIO32(MPU_BASE + 0x10) + +/* --- MPU values ---------------------------------------------------------- */ + +/* --- MPU_TYPE values ----------------------------------------------------- */ + +#define MPU_TYPE_IREGION_LSB 16 +#define MPU_TYPE_IREGION (0xFF << MPU_TYPE_IREGION_LSB) +#define MPU_TYPE_DREGION_LSB 8 +#define MPU_TYPE_DREGION (0xFF << MPU_TYPE_DREGION_LSB) +#define MPU_TYPE_SEPARATE (1<<0) + +/* --- MPU_CTRL values ----------------------------------------------------- */ + +#define MPU_CTRL_PRIVDEFENA (1<<2) +#define MPU_CTRL_HFNMIENA (1<<1) +#define MPU_CTRL_ENABLE (1<<0) + +/* --- MPU_RNR values ------------------------------------------------------ */ + +#define MPU_RNR_REGION_LSB 0 +#define MPU_RNR_REGION (0xFF << MPU_RNR_REGION_LSB) + +/* --- MPU_RBAR values ----------------------------------------------------- */ + +#define MPU_RBAR_ADDR_LSB 8 +#define MPU_RBAR_ADDR (0x00FFFFFF << MPU_RBAR_REGION_LSB) +#define MPU_RBAR_VALID (1<<4) +#define MPU_RBAR_REGION_LSB 0 +#define MPU_RBAR_REGION (0xF << MPU_RBAR_REGION_LSB) + +/* --- MPU_RASR values ----------------------------------------------------- */ + +#define MPU_RASR_ATTRS_LSB 16 +#define MPU_RASR_ATTRS (0xFFFF << MPU_RASR_ATTRS_LSB) +#define MPU_RASR_SRD_LSB 8 +#define MPU_RASR_SRD (0xFF << MPU_RASR_SRD_LSB) +#define MPU_RASR_SIZE_LSB 1 +#define MPU_RASR_SIZE (0x1F << MPU_RASR_SIZE_LSB) +#define MPU_RASR_ENABLE (1 << 0) + + +#define MPU_RASR_ATTR_XN (1 << 28) +#define MPU_RASR_ATTR_AP (7 << 24) +#define MPU_RASR_ATTR_AP_PNO_UNO (0 << 24) +#define MPU_RASR_ATTR_AP_PRW_UNO (1 << 24) +#define MPU_RASR_ATTR_AP_PRW_URO (2 << 24) +#define MPU_RASR_ATTR_AP_PRW_URW (3 << 24) +#define MPU_RASR_ATTR_AP_PRO_UNO (5 << 24) +#define MPU_RASR_ATTR_AP_PRO_URO (6 << 24) +#define MPU_RASR_ATTR_AP_PRO_URO (7 << 24) +#define MPU_RASR_ATTR_TEX (7 << 19) +#define MPU_RASR_ATTR_S (1 << 18) +#define MPU_RASR_ATTR_C (1 << 17) +#define MPU_RASR_ATTR_B (1 << 16) +#define MPU_RASR_ATTR_SCB (7 << 16) +#define MPU_RASR_ATTR_SCB_SH_STRONG (0 << 16) +#define MPU_RASR_ATTR_SCB_SH_DEVICE (1 << 16) +#define MPU_RASR_ATTR_SCB_NSH_WT (2 << 16) +#define MPU_RASR_ATTR_SCB_NSH_WB (3 << 16) +#define MPU_RASR_ATTR_SCB_SH_STRONG (4 << 16) +#define MPU_RASR_ATTR_SCB_SH_DEVICE (5 << 16) +#define MPU_RASR_ATTR_SCB_SH_WT (6 << 16) +#define MPU_RASR_ATTR_SCB_SH_WB (7 << 16) + +/* --- MPU functions ------------------------------------------------------- */ + +BEGIN_DECLS + + +END_DECLS + +#endif /* CM0_PLUS */ + +#endif diff --git a/libopencm3/include/libopencm3/cm3/scb.h b/libopencm3/include/libopencm3/cm3/scb.h new file mode 100644 index 0000000..0a6dcae --- /dev/null +++ b/libopencm3/include/libopencm3/cm3/scb.h @@ -0,0 +1,444 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_SCB_H +#define LIBOPENCM3_SCB_H + +#include +#include + +/* --- SCB: Registers ------------------------------------------------------ */ + +/* CPUID: CPUID base register */ +#define SCB_CPUID MMIO32(SCB_BASE + 0x00) + +/* ICSR: Interrupt Control State Register */ +#define SCB_ICSR MMIO32(SCB_BASE + 0x04) + +/* VTOR: Vector Table Offset Register */ +#define SCB_VTOR MMIO32(SCB_BASE + 0x08) + +/* AIRCR: Application Interrupt and Reset Control Register */ +#define SCB_AIRCR MMIO32(SCB_BASE + 0x0C) + +/* SCR: System Control Register */ +#define SCB_SCR MMIO32(SCB_BASE + 0x10) + +/* CCR: Configuration Control Register */ +#define SCB_CCR MMIO32(SCB_BASE + 0x14) + +/* SHP: System Handler Priority Registers */ +/* Note: 12 8bit registers */ +#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id) +#define SCB_SHPR1 MMIO32(SCB_BASE + 0x18) +#define SCB_SHPR2 MMIO32(SCB_BASE + 0x1C) +#define SCB_SHPR3 MMIO32(SCB_BASE + 0x20) + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) +/* SHCSR: System Handler Control and State Register */ +#define SCB_SHCSR MMIO32(SCB_BASE + 0x24) + +/* CFSR: Configurable Fault Status Registers */ +#define SCB_CFSR MMIO32(SCB_BASE + 0x28) + +/* HFSR: Hard Fault Status Register */ +#define SCB_HFSR MMIO32(SCB_BASE + 0x2C) + +/* DFSR: Debug Fault Status Register */ +#define SCB_DFSR MMIO32(SCB_BASE + 0x30) + +/* MMFAR: Memory Manage Fault Address Register */ +#define SCB_MMFAR MMIO32(SCB_BASE + 0x34) + +/* BFAR: Bus Fault Address Register */ +#define SCB_BFAR MMIO32(SCB_BASE + 0x38) + +/* AFSR: Auxiliary Fault Status Register */ +#define SCB_AFSR MMIO32(SCB_BASE + 0x3C) + +/* ID_PFR0: Processor Feature Register 0 */ +#define SCB_ID_PFR0 MMIO32(SCB_BASE + 0x40) + +/* ID_PFR1: Processor Feature Register 1 */ +#define SCB_ID_PFR1 MMIO32(SCB_BASE + 0x44) + +/* ID_DFR0: Debug Features Register 0 */ +#define SCB_ID_DFR0 MMIO32(SCB_BASE + 0x48) + +/* ID_AFR0: Auxiliary Features Register 0 */ +#define SCB_ID_AFR0 MMIO32(SCB_BASE + 0x4C) + +/* ID_MMFR0: Memory Model Feature Register 0 */ +#define SCB_ID_MMFR0 MMIO32(SCB_BASE + 0x50) + +/* ID_MMFR1: Memory Model Feature Register 1 */ +#define SCB_ID_MMFR1 MMIO32(SCB_BASE + 0x54) + +/* ID_MMFR2: Memory Model Feature Register 2 */ +#define SCB_ID_MMFR2 MMIO32(SCB_BASE + 0x58) + +/* ID_MMFR3: Memory Model Feature Register 3 */ +#define SCB_ID_MMFR3 MMIO32(SCB_BASE + 0x5C) + +/* ID_ISAR0: Instruction Set Attributes Register 0 */ +#define SCB_ID_ISAR0 MMIO32(SCB_BASE + 0x60) + +/* ID_ISAR1: Instruction Set Attributes Register 1 */ +#define SCB_ID_ISAR1 MMIO32(SCB_BASE + 0x64) + +/* ID_ISAR2: Instruction Set Attributes Register 2 */ +#define SCB_ID_ISAR2 MMIO32(SCB_BASE + 0x68) + +/* ID_ISAR3: Instruction Set Attributes Register 3 */ +#define SCB_ID_ISAR3 MMIO32(SCB_BASE + 0x6C) + +/* ID_ISAR4: Instruction Set Attributes Register 4 */ +#define SCB_ID_ISAR4 MMIO32(SCB_BASE + 0x70) + +/* CPACR: Coprocessor Access Control Register */ +#define SCB_CPACR MMIO32(SCB_BASE + 0x88) + +/* FPCCR: Floating-Point Context Control Register */ +#define SCB_FPCCR MMIO32(SCB_BASE + 0x234) + +/* FPCAR: Floating-Point Context Address Register */ +#define SCB_FPCAR MMIO32(SCB_BASE + 0x238) + +/* FPDSCR: Floating-Point Default Status Control Register */ +#define SCB_FPDSCR MMIO32(SCB_BASE + 0x23C) + +/* MVFR0: Media and Floating-Point Feature Register 0 */ +#define SCB_MVFR0 MMIO32(SCB_BASE + 0x240) + +/* MVFR1: Media and Floating-Point Feature Register 1 */ +#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244) +#endif + +/* --- SCB values ---------------------------------------------------------- */ + +/* --- SCB_CPUID values ---------------------------------------------------- */ + +/* Implementer[31:24]: Implementer code */ +#define SCB_CPUID_IMPLEMENTER_LSB 24 +#define SCB_CPUID_IMPLEMENTER (0xFF << SCB_CPUID_IMPLEMENTER_LSB) +/* Variant[23:20]: Variant number */ +#define SCB_CPUID_VARIANT_LSB 20 +#define SCB_CPUID_VARIANT (0xF << SCB_CPUID_VARIANT_LSB) +/* Constant[19:16]: Reads as 0xF (ARMv7-M) M3, M4 */ +/* Constant[19:16]: Reads as 0xC (ARMv6-M) M0, M0+ */ +#define SCB_CPUID_CONSTANT_LSB 16 +#define SCB_CPUID_CONSTANT (0xF << SCB_CPUID_CONSTANT_LSB) +#define SCB_CPUID_CONSTANT_ARMV6 (0xC << SCB_CPUID_CONSTANT_LSB) +#define SCB_CPUID_CONSTANT_ARMV7 (0xF << SCB_CPUID_CONSTANT_LSB) + +/* PartNo[15:4]: Part number of the processor */ +#define SCB_CPUID_PARTNO_LSB 4 +#define SCB_CPUID_PARTNO (0xFFF << SCB_CPUID_PARTNO_LSB) +/* Revision[3:0]: Revision number */ +#define SCB_CPUID_REVISION_LSB 0 +#define SCB_CPUID_REVISION (0xF << SCB_CPUID_REVISION_LSB) + +/* --- SCB_ICSR values ----------------------------------------------------- */ + +/* NMIPENDSET: NMI set-pending bit */ +#define SCB_ICSR_NMIPENDSET (1 << 31) +/* Bits [30:29]: reserved - must be kept cleared */ +/* PENDSVSET: PendSV set-pending bit */ +#define SCB_ICSR_PENDSVSET (1 << 28) +/* PENDSVCLR: PendSV clear-pending bit */ +#define SCB_ICSR_PENDSVCLR (1 << 27) +/* PENDSTSET: SysTick exception set-pending bit */ +#define SCB_ICSR_PENDSTSET (1 << 26) +/* PENDSTCLR: SysTick exception clear-pending bit */ +#define SCB_ICSR_PENDSTCLR (1 << 25) +/* Bit 24: reserved - must be kept cleared */ +/* Bit 23: reserved for debug - reads as 0 when not in debug mode */ +#define SCB_ICSR_ISRPREEMPT (1 << 23) +/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */ +#define SCB_ICSR_ISRPENDING (1 << 22) +/* VECTPENDING[21:12] Pending vector */ +#define SCB_ICSR_VECTPENDING_LSB 12 +#define SCB_ICSR_VECTPENDING (0x1FF << SCB_ICSR_VECTPENDING_LSB) +/* RETOBASE: Return to base level */ +#define SCB_ICSR_RETOBASE (1 << 11) +/* Bits [10:9]: reserved - must be kept cleared */ +/* VECTACTIVE[8:0] Active vector */ +#define SCB_ICSR_VECTACTIVE_LSB 0 +#define SCB_ICSR_VECTACTIVE (0x1FF << SCB_ICSR_VECTACTIVE_LSB) + + +/* --- SCB_VTOR values ----------------------------------------------------- */ + +/* IMPLEMENTATION DEFINED */ + +#if defined(__ARM_ARCH_6M__) + +#define SCB_VTOR_TBLOFF_LSB 7 +#define SCB_VTOR_TBLOFF (0x1FFFFFF << SCB_VTOR_TBLOFF_LSB) + +#elif defined(CM1) +/* VTOR not defined there */ + +#elif defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + +/* Bits [31:30]: reserved - must be kept cleared */ +/* TBLOFF[29:9]: Vector table base offset field */ +/* inconsistent datasheet - LSB could be 11 */ +/* BUG: TBLOFF is in the ARMv6 Architecture reference manual defined from b7 */ +#define SCB_VTOR_TBLOFF_LSB 9 +#define SCB_VTOR_TBLOFF (0x7FFFFF << SCB_VTOR_TBLOFF_LSB) + +#endif + +/* --- SCB_AIRCR values ---------------------------------------------------- */ + +/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */ +#define SCB_AIRCR_VECTKEYSTAT_LSB 16 +#define SCB_AIRCR_VECTKEYSTAT (0xFFFF << SCB_AIRCR_VECTKEYSTAT_LSB) +#define SCB_AIRCR_VECTKEY (0x05FA << SCB_AIRCR_VECTKEYSTAT_LSB) + +/* ENDIANESS Data endianness bit */ +#define SCB_AIRCR_ENDIANESS (1 << 15) + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) +/* Bits [14:11]: reserved - must be kept cleared */ +/* PRIGROUP[10:8]: Interrupt priority grouping field */ +#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8) +#define SCB_AIRCR_PRIGROUP_GROUP8_SUB2 (0x4 << 8) +#define SCB_AIRCR_PRIGROUP_GROUP4_SUB4 (0x5 << 8) +#define SCB_AIRCR_PRIGROUP_GROUP2_SUB8 (0x6 << 8) +#define SCB_AIRCR_PRIGROUP_NOGROUP_SUB16 (0x7 << 8) +#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8) +#define SCB_AIRCR_PRIGROUP_SHIFT 8 +/* Bits [7:3]: reserved - must be kept cleared */ +#endif + +/* SYSRESETREQ System reset request */ +#define SCB_AIRCR_SYSRESETREQ (1 << 2) +/* VECTCLRACTIVE */ +#define SCB_AIRCR_VECTCLRACTIVE (1 << 1) + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) +/* VECTRESET */ +#define SCB_AIRCR_VECTRESET (1 << 0) +#endif + +/* --- SCB_SCR values ------------------------------------------------------ */ + +/* Bits [31:5]: reserved - must be kept cleared */ +/* SEVEONPEND Send Event on Pending bit */ +#define SCB_SCR_SEVEONPEND (1 << 4) +/* Bit 3: reserved - must be kept cleared */ +/* SLEEPDEEP */ +#define SCB_SCR_SLEEPDEEP (1 << 2) +/* SLEEPONEXIT */ +#define SCB_SCR_SLEEPONEXIT (1 << 1) +/* Bit 0: reserved - must be kept cleared */ + +/* --- SCB_CCR values ------------------------------------------------------ */ + +/* Bits [31:10]: reserved - must be kept cleared */ +/* STKALIGN */ +#define SCB_CCR_STKALIGN (1 << 9) + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) +/* BFHFNMIGN */ +#define SCB_CCR_BFHFNMIGN (1 << 8) +/* Bits [7:5]: reserved - must be kept cleared */ +/* DIV_0_TRP */ +#define SCB_CCR_DIV_0_TRP (1 << 4) +#endif + +/* UNALIGN_TRP */ +#define SCB_CCR_UNALIGN_TRP (1 << 3) + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) +/* Bit 2: reserved - must be kept cleared */ +/* USERSETMPEND */ +#define SCB_CCR_USERSETMPEND (1 << 1) +/* NONBASETHRDENA */ +#define SCB_CCR_NONBASETHRDENA (1 << 0) +#endif + +/* These numbers are designed to be used with the SCB_SHPR() macro */ +/* SCB_SHPR1 */ +#define SCB_SHPR_PRI_4_MEMMANAGE 0 +#define SCB_SHPR_PRI_5_BUSFAULT 1 +#define SCB_SHPR_PRI_6_USAGEFAULT 2 +#define SCB_SHPR_PRI_7_RESERVED 3 +/* SCB_SHPR2 */ +#define SCB_SHPR_PRI_8_RESERVED 4 +#define SCB_SHPR_PRI_9_RESERVED 5 +#define SCB_SHPR_PRI_10_RESERVED 6 +#define SCB_SHPR_PRI_11_SVCALL 7 +/* SCB_SHPR3 */ +#define SCB_SHPR_PRI_12_RESERVED 8 +#define SCB_SHPR_PRI_13_RESERVED 9 +#define SCB_SHPR_PRI_14_PENDSV 10 +#define SCB_SHPR_PRI_15_SYSTICK 11 + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) +/* --- SCB_SHCSR values ---------------------------------------------------- */ + +/* Bits [31:19]: reserved - must be kept cleared */ +/* USGFAULTENA: Usage fault enable */ +#define SCB_SHCSR_USGFAULTENA (1 << 18) +/* BUSFAULTENA: Bus fault enable */ +#define SCB_SHCSR_BUSFAULTENA (1 << 17) +/* MEMFAULTENA: Memory management fault enable */ +#define SCB_SHCSR_MEMFAULTENA (1 << 16) +/* SVCALLPENDED: SVC call pending */ +#define SCB_SHCSR_SVCALLPENDED (1 << 15) +/* BUSFAULTPENDED: Bus fault exception pending */ +#define SCB_SHCSR_BUSFAULTPENDED (1 << 14) +/* MEMFAULTPENDED: Memory management fault exception pending */ +#define SCB_SHCSR_MEMFAULTPENDED (1 << 13) +/* USGFAULTPENDED: Usage fault exception pending */ +#define SCB_SHCSR_USGFAULTPENDED (1 << 12) +/* SYSTICKACT: SysTick exception active */ +#define SCB_SHCSR_SYSTICKACT (1 << 11) +/* PENDSVACT: PendSV exception active */ +#define SCB_SHCSR_PENDSVACT (1 << 10) +/* Bit 9: reserved - must be kept cleared */ +/* MONITORACT: Debug monitor active */ +#define SCB_SHCSR_MONITORACT (1 << 8) +/* SVCALLACT: SVC call active */ +#define SCB_SHCSR_SVCALLACT (1 << 7) +/* Bits [6:4]: reserved - must be kept cleared */ +/* USGFAULTACT: Usage fault exception active */ +#define SCB_SHCSR_USGFAULTACT (1 << 3) +/* Bit 2: reserved - must be kept cleared */ +/* BUSFAULTACT: Bus fault exception active */ +#define SCB_SHCSR_BUSFAULTACT (1 << 1) +/* MEMFAULTACT: Memory management fault exception active */ +#define SCB_SHCSR_MEMFAULTACT (1 << 0) + +/* --- SCB_CFSR values ----------------------------------------------------- */ + +/* Bits [31:26]: reserved - must be kept cleared */ +/* DIVBYZERO: Divide by zero usage fault */ +#define SCB_CFSR_DIVBYZERO (1 << 25) +/* UNALIGNED: Unaligned access usage fault */ +#define SCB_CFSR_UNALIGNED (1 << 24) +/* Bits [23:20]: reserved - must be kept cleared */ +/* NOCP: No coprocessor usage fault */ +#define SCB_CFSR_NOCP (1 << 19) +/* INVPC: Invalid PC load usage fault */ +#define SCB_CFSR_INVPC (1 << 18) +/* INVSTATE: Invalid state usage fault */ +#define SCB_CFSR_INVSTATE (1 << 17) +/* UNDEFINSTR: Undefined instruction usage fault */ +#define SCB_CFSR_UNDEFINSTR (1 << 16) +/* BFARVALID: Bus Fault Address Register (BFAR) valid flag */ +#define SCB_CFSR_BFARVALID (1 << 15) +/* Bits [14:13]: reserved - must be kept cleared */ +/* STKERR: Bus fault on stacking for exception entry */ +#define SCB_CFSR_STKERR (1 << 12) +/* UNSTKERR: Bus fault on unstacking for a return from exception */ +#define SCB_CFSR_UNSTKERR (1 << 11) +/* IMPRECISERR: Imprecise data bus error */ +#define SCB_CFSR_IMPRECISERR (1 << 10) +/* PRECISERR: Precise data bus error */ +#define SCB_CFSR_PRECISERR (1 << 9) +/* IBUSERR: Instruction bus error */ +#define SCB_CFSR_IBUSERR (1 << 8) +/* MMARVALID: Memory Management Fault Address Register (MMAR) valid flag */ +#define SCB_CFSR_MMARVALID (1 << 7) +/* Bits [6:5]: reserved - must be kept cleared */ +/* MSTKERR: Memory manager fault on stacking for exception entry */ +#define SCB_CFSR_MSTKERR (1 << 4) +/* MUNSTKERR: Memory manager fault on unstacking for a return from exception */ +#define SCB_CFSR_MUNSTKERR (1 << 3) +/* Bit 2: reserved - must be kept cleared */ +/* DACCVIOL: Data access violation flag */ +#define SCB_CFSR_DACCVIOL (1 << 1) +/* IACCVIOL: Instruction access violation flag */ +#define SCB_CFSR_IACCVIOL (1 << 0) + +/* --- SCB_HFSR values ----------------------------------------------------- */ + +/* DEBUG_VT: reserved for debug use */ +#define SCB_HFSR_DEBUG_VT (1 << 31) +/* FORCED: Forced hard fault */ +#define SCB_HFSR_FORCED (1 << 30) +/* Bits [29:2]: reserved - must be kept cleared */ +/* VECTTBL: Vector table hard fault */ +#define SCB_HFSR_VECTTBL (1 << 1) +/* Bit 0: reserved - must be kept cleared */ + +/* --- SCB_MMFAR values ---------------------------------------------------- */ + +/* MMFAR [31:0]: Memory management fault address */ + +/* --- SCB_BFAR values ----------------------------------------------------- */ + +/* BFAR [31:0]: Bus fault address */ + +/* --- SCB_CPACR values ---------------------------------------------------- */ + +/* CPACR CPn: Access privileges values */ +#define SCB_CPACR_NONE 0 /* Access denied */ +#define SCB_CPACR_PRIV 1 /* Privileged access only */ +#define SCB_CPACR_FULL 3 /* Full access */ + +/* CPACR [20:21]: Access privileges for coprocessor 10 */ +#define SCB_CPACR_CP10 (1 << 20) +/* CPACR [22:23]: Access privileges for coprocessor 11 */ +#define SCB_CPACR_CP11 (1 << 22) +#endif + +/* --- SCB functions ------------------------------------------------------- */ + +BEGIN_DECLS + +struct scb_exception_stack_frame { + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r12; + uint32_t lr; + uint32_t pc; + uint32_t xpsr; +} __attribute__((packed)); + +#define SCB_GET_EXCEPTION_STACK_FRAME(f) \ + do { \ + asm volatile ("mov %[frameptr], sp" \ + : [frameptr]"=r" (f)); \ + } while (0) + +void scb_reset_system(void) __attribute__((noreturn, naked)); + +/* Those defined only on ARMv7 and above */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) +void scb_reset_core(void) __attribute__((noreturn, naked)); +void scb_set_priority_grouping(uint32_t prigroup); +#endif + +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/cm3/scs.h b/libopencm3/include/libopencm3/cm3/scs.h new file mode 100644 index 0000000..7bf9860 --- /dev/null +++ b/libopencm3/include/libopencm3/cm3/scs.h @@ -0,0 +1,350 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CM3_SCS_H +#define LIBOPENCM3_CM3_SCS_H + +/* + * All the definition hereafter are generic for CortexMx ARMv7-M + * See ARM document "ARMv7-M Architecture Reference Manual" for more details. + * See also ARM document "ARM Compiler toolchain Developing Software for ARM + * Processors" for details on System Timer/SysTick. + */ + +/* + * The System Control Space (SCS) is a memory-mapped 4KB address space that + * provides 32-bit registers for configuration, status reporting and control. + * The SCS registers divide into the following groups: + * - system control and identification + * - the CPUID processor identification space + * - system configuration and status + * - fault reporting + * - a system timer, SysTick + * - a Nested Vectored Interrupt Controller (NVIC) + * - a Protected Memory System Architecture (PMSA) + * - system debug. + */ + +/* System Handler Priority 8 bits Registers, SHPR1/2/3 */ +/* Note: 12 8bit Registers */ +#define SCS_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + ipr_id) + +/* + * Debug Halting Control and Status Register (DHCSR). + * + * Purpose Controls halting debug. + * Usage constraints: The effect of modifying the C_STEP or C_MASKINTS bit when + * the system is running with halting debug enabled is UNPREDICTABLE. + * Halting debug is enabled when C_DEBUGEN is set to 1. The system is running + * when S_HALT is set to 0. + * - When C_DEBUGEN is set to 0, the processor ignores the values of all other + * bits in this register. + * - For more information about the use of DHCSR see Debug stepping on page + * C1-824. + * Configurations Always implemented. + */ +/* SCS_DHCSR register */ +#define SCS_DHCSR MMIO32(SCS_BASE + 0xDF0) +/* + * Debug Core Register Selector Register (DCRSR). + * + * Purpose With the DCRDR, the DCRSR provides debug access to the ARM core + * registers, special-purpose registers, and Floating-point extension + * registers. A write to DCRSR specifies the register to transfer, whether the + * transfer is a read or a write, and starts the transfer. + * Usage constraints: Only accessible in Debug state. + * Configurations Always implemented. + * + */ +/* SCS_DCRS register */ +#define SCS_DCRSR MMIO32(SCS_BASE + 0xDF4) +/* + * Debug Core Register Data Register (DCRDR) + * + * Purpose With the DCRSR, see Debug Core Register Selector Register, the DCRDR + * provides debug access to the ARM core registers, special-purpose registers, + * and Floating-point extension registers. The DCRDR is the data register for + * these accesses. + * - Used on its own, the DCRDR provides a message passing resource between an + * external debugger and a debug agent running on the processor. + * Note: + * The architecture does not define any handshaking mechanism for this use of + * DCRDR. + * Usage constraints: See Use of DCRSR and DCRDR for constraints that apply to + * particular transfers using the DCRSR and DCRDR. + * Configurations Always implemented. + * + */ +/* SCS_DCRDR register */ +#define SCS_DCRDR MMIO32(SCS_BASE + 0xDF8) +/* + * Debug Exception and Monitor Control Register (DEMCR). + * + * Purpose Manages vector catch behavior and DebugMonitor handling when + * debugging. + * Usage constraints: + * - Bits [23:16] provide DebugMonitor exception control. + * - Bits [15:0] provide Debug state, halting debug, control. + * Configurations Always implemented. + * + */ +/* SCS_DEMCR register */ +#define SCS_DEMCR MMIO32(SCS_BASE + 0xDFC) + +/* Debug Halting Control and Status Register (DHCSR) */ +#define SCS_DHCSR_DBGKEY 0xA05F0000 +#define SCS_DHCSR_C_DEBUGEN 0x00000001 +#define SCS_DHCSR_C_HALT 0x00000002 +#define SCS_DHCSR_C_STEP 0x00000004 +#define SCS_DHCSR_C_MASKINTS 0x00000008 +#define SCS_DHCSR_C_SNAPSTALL 0x00000020 +#define SCS_DHCSR_S_REGRDY 0x00010000 +#define SCS_DHCSR_S_HALT 0x00020000 +#define SCS_DHCSR_S_SLEEP 0x00040000 +#define SCS_DHCSR_S_LOCKUP 0x00080000 +#define SCS_DHCSR_S_RETIRE_ST 0x01000000 +#define SCS_DHCSR_S_RESET_ST 0x02000000 + +/* Debug Core Register Selector Register (DCRSR) */ +#define SCS_DCRSR_REGSEL_MASK 0x0000001F +#define SCS_DCRSR_REGSEL_XPSR 0x00000010 +#define SCS_DCRSR_REGSEL_MSP 0x00000011 +#define SCS_DCRSR_REGSEL_PSP 0x00000012 + +/* Debug Exception and Monitor Control Register (DEMCR) */ +/* Bits 31:25 - Reserved */ +#define SCS_DEMCR_TRCENA (1 << 24) +/* Bits 23:20 - Reserved */ +#define SCS_DEMCR_MON_REQ (1 << 19) +#define SCS_DEMCR_MON_STEP (1 << 18) +#define SCS_DEMCR_VC_MON_PEND (1 << 17) +#define SCS_DEMCR_VC_MON_EN (1 << 16) +/* Bits 15:11 - Reserved */ +#define SCS_DEMCR_VC_HARDERR (1 << 10) +#define SCS_DEMCR_VC_INTERR (1 << 9) +#define SCS_DEMCR_VC_BUSERR (1 << 8) +#define SCS_DEMCR_VC_STATERR (1 << 7) +#define SCS_DEMCR_VC_CHKERR (1 << 6) +#define SCS_DEMCR_VC_NOCPERR (1 << 5) +#define SCS_DEMCR_VC_MMERR (1 << 4) +/* Bits 3:1 - Reserved */ +#define SCS_DEMCR_VC_CORERESET (1 << 0) + +/* + * System Control Space (SCS) => System timer register support in the SCS. + * To configure SysTick, load the interval required between SysTick events to + * the SysTick Reload Value register. The timer interrupt, or COUNTFLAG bit in + * the SysTick Control and Status register, is activated on the transition from + * 1 to 0, therefore it activates every n+1 clock ticks. If you require a + * period of 100, write 99 to the SysTick Reload Value register. The SysTick + * Reload Value register supports values between 0x1 and 0x00FFFFFF. + * + * If you want to use SysTick to generate an event at a timed interval, for + * example 1ms, you can use the SysTick Calibration Value Register to scale + * your value for the Reload register. The SysTick Calibration Value Register + * is a read-only register that contains the number of pulses for a period of + * 10ms, in the TENMS field, bits[23:0]. + * + * This register also has a SKEW bit. Bit[30] == 1 indicates that the + * calibration for 10ms in the TENMS section is not exactly 10ms due to clock + * frequency. Bit[31] == 1 indicates that the reference clock is not provided. + */ +/* + * SysTick Control and Status Register (CSR). + * Purpose Controls the system timer and provides status data. + * Usage constraints: There are no usage constraints. + * Configurations Always implemented. +*/ +#define SCS_SYST_CSR MMIO32(SCS_BASE + 0x10) + +/* SysTick Reload Value Register (CVR). + * Purpose Reads or clears the current counter value. + * Usage constraints: + * - Any write to the register clears the register to zero. + * - The counter does not provide read-modify-write protection. + * - Unsupported bits are read as zero + * Configurations Always implemented. + */ +#define CM_SCS_SYST_RVR MMIO32(SCS_BASE + 0x14) + +/* SysTick Current Value Register (RVR). + * Purpose Holds the reload value of the SYST_CVR. + * Usage constraints There are no usage constraints. + * Configurations Always implemented. + */ +#define CM_SCS_SYST_CVR MMIO32(SCS_BASE + 0x18) + +/* + * SysTick Calibration value Register(Read Only) (CALIB) + * Purpose Reads the calibration value and parameters for SysTick. + * Usage constraints: There are no usage constraints. + * Configurations Always implemented. + */ +#define CM_SCS_SYST_CALIB MMIO32(SCS_BASE + 0x1C) + +/* --- SCS_SYST_CSR values ----------------------------------------------- */ +/* Counter is operating. */ +#define SCS_SYST_CSR_ENABLE (BIT0) +/* Count to 0 changes the SysTick exception status to pending. */ +#define SCS_SYST_CSR_TICKINT (BIT1) +/* SysTick uses the processor clock. */ +#define SCS_SYST_CSR_CLKSOURCE (BIT2) +/* + * Indicates whether the counter has counted to 0 since the last read of this + * register: + * 0 = Timer has not counted to 0 + * 1 = Timer has counted to 0. + */ +#define SCS_SYST_CSR_COUNTFLAG (BIT16) + +/* --- CM_SCS_SYST_RVR values ---------------------------------------------- */ +/* Bit 0 to 23 => RELOAD The value to load into the SYST_CVR when the counter + * reaches 0. + */ +/* Bit 24 to 31 are Reserved */ + +/* --- CM_SCS_SYST_CVR values ---------------------------------------------- */ +/* Bit0 to 31 => Reads or clears the current counter value. */ + +/* --- CM_SCS_SYST_CALIB values -------------------------------------------- */ +/* + * Bit0 to 23 => TENMS Optionally, holds a reload value to be used for 10ms + * (100Hz) timing, subject to system clock skew errors. If this field is zero, + * the calibration value is not known. + */ +#define SCS_SYST_SYST_CALIB_TENMS_MASK (BIT24-1) + +/* + * Bit30 => SKEW Indicates whether the 10ms calibration value is exact: + * 0 = 10ms calibration value is exact. + * 1 = 10ms calibration value is inexact, because of the clock frequency + */ +#define SCS_SYST_SYST_CALIB_VALUE_INEXACT (BIT30) +/* + * Bit31 => NOREF Indicates whether the IMPLEMENTATION DEFINED reference clock + * is implemented: + * 0 = The reference clock is implemented. + * 1 = The reference clock is not implemented. + * When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to + * 1 and cannot be cleared to 0. + */ +#define SCS_SYST_SYST_CALIB_REF_NOT_IMPLEMENTED (BIT31) + +/* + * System Control Space (SCS) => Data Watchpoint and Trace (DWT). + * See "ARMv7-M Architecture Reference Manual" + * (https://github.com/libopencm3/libopencm3-archive/blob/master/arm/ + * ARMv7-M_ARM.pdf) + * The DWT is an optional debug unit that provides watchpoints, data tracing, + * and system profiling for the processor. + */ +/* + * DWT Control register + * Purpose Provides configuration and status information for the DWT block, and + * used to control features of the block + * Usage constraints: There are no usage constraints. + * Configurations Always implemented. + */ +#define SCS_DWT_CTRL MMIO32(DWT_BASE + 0x00) +/* + * DWT_CYCCNT register + * Cycle Count Register (Shows or sets the value of the processor cycle + * counter, CYCCNT) + * When enabled, CYCCNT increments on each processor clock cycle. On overflow, + * CYCCNT wraps to zero. + * + * Purpose Shows or sets the value of the processor cycle counter, CYCCNT. + * Usage constraints: The DWT unit suspends CYCCNT counting when the processor + * is in Debug state. + * Configurations Implemented: only when DWT_CTRL.NOCYCCNT is RAZ, see Control + * register, DWT_CTRL. + * When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this + * register is UNK/SBZP. +*/ +#define SCS_DWT_CYCCNT MMIO32(DWT_BASE + 0x04) + +/* DWT_CPICNT register + * Purpose Counts additional cycles required to execute multi-cycle + * instructions and instruction fetch stalls. + * Usage constraints: The counter initializes to 0 when software enables its + * counter overflow event by + * setting the DWT_CTRL.CPIEVTENA bit to 1. + * Configurations Implemented: only when DWT_CTRL.NOPRFCNT is RAZ, see Control + * register, DWT_CTRL. + * If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not + * include the profiling counters, this register is UNK/SBZP. + */ +#define SCS_DWT_CPICNT MMIO32(DWT_BASE + 0x08) + +/* DWT_EXCCNT register */ +#define SCS_DWT_EXCCNT MMIO32(DWT_BASE + 0x0C) + +/* DWT_EXCCNT register */ +#define SCS_DWT_SLEEPCNT MMIO32(DWT_BASE + 0x10) + +/* DWT_EXCCNT register */ +#define SCS_DWT_LSUCNT MMIO32(DWT_BASE + 0x14) + +/* DWT_EXCCNT register */ +#define SCS_DWT_FOLDCNT MMIO32(DWT_BASE + 0x18) + +/* DWT_PCSR register */ +#define SCS_DWT_PCSR MMIO32(DWT_BASE + 0x18) + +/* CoreSight Lock Status Register for this peripheral */ +#define SCS_DWT_LSR MMIO32(SCS_DWT_BASE + 0xFB4) +/* CoreSight Lock Access Register for this peripheral */ +#define SCS_DWT_LAR MMIO32(SCS_DWT_BASE + 0xFB0) + +/* --- SCS_DWT_CTRL values ------------------------------------------------- */ +/* + * Enables CYCCNT: + * 0 = Disabled, 1 = Enabled + * This bit is UNK/SBZP if the NOCYCCNT bit is RAO. + */ +#define SCS_DWT_CTRL_CYCCNTENA (BIT0) + +/* CoreSight Lock Status Register lock status bit */ +#define SCS_LSR_SLK (1<<1) +/* CoreSight Lock Status Register lock availability bit */ +#define SCS_LSR_SLI (1<<0) +/* CoreSight Lock Access key, common for all */ +#define SCS_LAR_KEY 0xC5ACCE55 + +/* TODO bit definition values for other DWT_XXX register */ + +/* Macro to be called at startup to enable SCS & Cycle Counter */ +#define SCS_DWT_CYCLE_COUNTER_ENABLED() ((SCS_DEMCR |= SCS_DEMCR_TRCENA)\ + (SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA)) + +#define SCS_SYSTICK_DISABLED() (SCS_SYST_CSR = 0) + +/* Macro to be called at startup to Enable CortexMx SysTick (but IRQ not + * enabled) + */ +#define SCS_SYSTICK_ENABLED() (SCS_SYST_CSR = (SCS_SYST_CSR_ENABLE | \ + SCS_SYST_CSR_CLKSOURCE)) + +/* Macro to be called at startup to Enable CortexMx SysTick and IRQ */ +#define SCS_SYSTICK_AND_IRQ_ENABLED() (SCS_SYST_CSR = (SCS_SYST_CSR_ENABLE | \ + SCS_SYST_CSR_CLKSOURCE | \ + SCS_SYST_CSR_TICKINT)) + +#endif diff --git a/libopencm3/include/libopencm3/cm3/sync.h b/libopencm3/include/libopencm3/cm3/sync.h new file mode 100644 index 0000000..e80e348 --- /dev/null +++ b/libopencm3/include/libopencm3/cm3/sync.h @@ -0,0 +1,54 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Fergus Noble + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CM3_SYNC_H +#define LIBOPENCM3_CM3_SYNC_H + +#include "common.h" + +void __dmb(void); + +/* Implements synchronisation primitives as discussed in the ARM document + * DHT0008A (ID081709) "ARM Synchronization Primitives" and the ARM v7-M + * Architecture Reference Manual. +*/ + +/* --- Exclusive load and store instructions ------------------------------- */ + +/* Those are defined only on CM3 or CM4 */ +#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) + +uint32_t __ldrex(volatile uint32_t *addr); +uint32_t __strex(uint32_t val, volatile uint32_t *addr); + +/* --- Convenience functions ----------------------------------------------- */ + +/* Here we implement some simple synchronisation primitives. */ + +typedef uint32_t mutex_t; + +#define MUTEX_UNLOCKED 0 +#define MUTEX_LOCKED 1 + +void mutex_lock(mutex_t *m); +void mutex_unlock(mutex_t *m); + +#endif + +#endif diff --git a/libopencm3/include/libopencm3/cm3/systick.h b/libopencm3/include/libopencm3/cm3/systick.h new file mode 100644 index 0000000..a355b0f --- /dev/null +++ b/libopencm3/include/libopencm3/cm3/systick.h @@ -0,0 +1,134 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ +/** @defgroup CM3_systick_defines SysTick Defines + * + * @brief libopencm3 Defined Constants and Types for the Cortex SysTick + * + * @ingroup CM3_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2010 Thomas Otto + * + * @date 19 August 2012 + * + * LGPL License Terms @ref lgpl_license + */ + +/** + * @note this file has been not following the register naming scheme, the + * correct names defined, and the old ones stay there for compatibility with + * old software (will be deprecated in the future) + */ + +/**@{*/ + +#ifndef LIBOPENCM3_SYSTICK_H +#define LIBOPENCM3_SYSTICK_H + +#include +#include + +/* --- SYSTICK registers --------------------------------------------------- */ + +/* Control and status register (STK_CTRL) */ +#define STK_CSR MMIO32(SYS_TICK_BASE + 0x00) + +/* reload value register (STK_LOAD) */ +#define STK_RVR MMIO32(SYS_TICK_BASE + 0x04) + +/* current value register (STK_VAL) */ +#define STK_CVR MMIO32(SYS_TICK_BASE + 0x08) + +/* calibration value register (STK_CALIB) */ +#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C) + +/* --- STK_CSR values ------------------------------------------------------ */ +/* Bits [31:17] Reserved, must be kept cleared. */ +/* COUNTFLAG: */ +#define STK_CSR_COUNTFLAG (1 << 16) + +/* Bits [15:3] Reserved, must be kept cleared. */ +/* CLKSOURCE: Clock source selection */ +#define STK_CSR_CLKSOURCE_LSB 2 +#define STK_CSR_CLKSOURCE (1 << STK_CSR_CLKSOURCE_LSB) + +/** @defgroup systick_clksource Clock source selection +@ingroup CM3_systick_defines + +@{*/ +#if defined(__ARM_ARCH_6M__) +#define STK_CSR_CLKSOURCE_EXT (0 << STK_CSR_CLKSOURCE_LSB) +#define STK_CSR_CLKSOURCE_AHB (1 << STK_CSR_CLKSOURCE_LSB) +#else +#define STK_CSR_CLKSOURCE_AHB_DIV8 (0 << STK_CSR_CLKSOURCE_LSB) +#define STK_CSR_CLKSOURCE_AHB (1 << STK_CSR_CLKSOURCE_LSB) +#endif +/**@}*/ + +/* TICKINT: SysTick exception request enable */ +#define STK_CSR_TICKINT (1 << 1) +/* ENABLE: Counter enable */ +#define STK_CSR_ENABLE (1 << 0) + +/* --- STK_RVR values ------------------------------------------------------ */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* RELOAD[23:0]: RELOAD value */ +#define STK_RVR_RELOAD 0x00FFFFFF + + +/* --- STK_CVR values ------------------------------------------------------ */ +/* Bits [31:24] Reserved, must be kept cleared. */ +/* CURRENT[23:0]: Current counter value */ +#define STK_CVR_CURRENT 0x00FFFFFF + + +/* --- STK_CALIB values ---------------------------------------------------- */ +/* NOREF: NOREF flag */ +#define STK_CALIB_NOREF (1 << 31) +/* SKEW: SKEW flag */ +#define STK_CALIB_SKEW (1 << 30) +/* Bits [29:24] Reserved, must be kept cleared. */ +/* TENMS[23:0]: Calibration value */ +#define STK_CALIB_TENMS 0x00FFFFFF + +/* --- Function Prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void systick_set_reload(uint32_t value); +bool systick_set_frequency(uint32_t freq, uint32_t ahb); +uint32_t systick_get_reload(void); +uint32_t systick_get_value(void); +void systick_set_clocksource(uint8_t clocksource); +void systick_interrupt_enable(void); +void systick_interrupt_disable(void); +void systick_counter_enable(void); +void systick_counter_disable(void); +uint8_t systick_get_countflag(void); +void systick_clear(void); + +uint32_t systick_get_calib(void); + +END_DECLS + +#endif +/**@}*/ + diff --git a/libopencm3/include/libopencm3/cm3/tpiu.h b/libopencm3/include/libopencm3/cm3/tpiu.h new file mode 100644 index 0000000..ff21511 --- /dev/null +++ b/libopencm3/include/libopencm3/cm3/tpiu.h @@ -0,0 +1,97 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CM3_TPIU_H +#define LIBOPENCM3_CM3_TPIU_H + +/* Cortex-M3 Trace Port Interface Unit (TPIU) */ + +/* Those defined only on ARMv7 and above */ +#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) +#error "Trace Port Interface Unit not available in CM0" +#endif + +/* --- TPIU registers ------------------------------------------------------ */ + +/* Supported Synchronous Port Size (TPIU_SSPSR) */ +#define TPIU_SSPSR MMIO32(TPIU_BASE + 0x000) + +/* Current Synchronous Port Size (TPIU_CSPSR) */ +#define TPIU_CSPSR MMIO32(TPIU_BASE + 0x004) + +/* Asynchronous Clock Prescaler (TPIU_ACPR) */ +#define TPIU_ACPR MMIO32(TPIU_BASE + 0x010) + +/* Selected Pin Protocol (TPIU_SPPR) */ +#define TPIU_SPPR MMIO32(TPIU_BASE + 0x0F0) + +/* Formatter and Flush Status Register (TPIU_FFSR) */ +#define TPIU_FFSR MMIO32(TPIU_BASE + 0x300) + +/* Formatter and Flush Control Register (TPIU_FFCR) */ +#define TPIU_FFCR MMIO32(TPIU_BASE + 0x304) + +/* (TPIU_DEVID) */ +#define TPIU_DEVID MMIO32(TPIU_BASE + 0xFC8) + +/* CoreSight Lock Status Register for this peripheral */ +#define TPIU_LSR MMIO32(TPIU_BASE + 0xFB4) +/* CoreSight Lock Access Register for this peripheral */ +#define TPIU_LAR MMIO32(TPIU_BASE + 0xFB0) + +/* TODO: PID, CID */ + +/* --- TPIU_ACPR values ---------------------------------------------------- */ + +/* Bits 31:16 - Reserved */ +/* Bits 15:0 - SWO output clock = Asynchronous_Reference_Clock/(value +1) */ + +/* --- TPIU_SPPR values ---------------------------------------------------- */ + +/* Bits 31:2 - Reserved */ +#define TPIU_SPPR_SYNC (0x0) +#define TPIU_SPPR_ASYNC_MANCHESTER (0x1) +#define TPIU_SPPR_ASYNC_NRZ (0x2) + +/* --- TPIU_FFSR values ---------------------------------------------------- */ + +/* Bits 31:4 - Reserved */ +#define TPIU_FFSR_FTNONSTOP (1 << 3) +#define TPIU_FFSR_TCPRESENT (1 << 2) +#define TPIU_FFSR_FTSTOPPED (1 << 1) +#define TPIU_FFSR_FLINPROG (1 << 0) + +/* --- TPIU_FFCR values ---------------------------------------------------- */ + +/* Bits 31:9 - Reserved */ +#define TPIU_FFCR_TRIGIN (1 << 8) +/* Bits 7:2 - Reserved */ +#define TPIU_FFCR_ENFCONT (1 << 1) +/* Bit 0 - Reserved */ + +/* --- TPIU_DEVID values ---------------------------------------------------- */ +/* Bits 31:16 - Reserved */ +/* Bits 15:12 - Implementation defined */ +#define TPUI_DEVID_NRZ_SUPPORTED (1 << 11) +#define TPUI_DEVID_MANCHESTER_SUPPORTED (1 << 10) +/* Bit 9 - RAZ, indicated that trace data and clock are supported */ +#define TPUI_DEVID_FIFO_SIZE_MASK (7 << 6) +/* Bits 5:0 - Implementation defined */ + +#endif diff --git a/libopencm3/include/libopencm3/cm3/vector.h b/libopencm3/include/libopencm3/cm3/vector.h new file mode 100644 index 0000000..17ebb15 --- /dev/null +++ b/libopencm3/include/libopencm3/cm3/vector.h @@ -0,0 +1,64 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/** @file + * + * Definitions for handling vector tables. + * + * This implements d0002_efm32_cortex-m3_reference_manual.pdf's figure 2.2 + * (from the EFM32 documentation at + * http://www.energymicro.com/downloads/datasheets), and was seen analogously + * in other ARM implementations' libopencm3 files. + * + * The structure of the vector table is implemented independently of the system + * vector table starting at memory position 0x0, as it can be relocated to + * other memory locations too. + * + * The exact size of a vector interrupt table depends on the number of + * interrupts IRQ_COUNT, which is defined per family. + */ + +#ifndef LIBOPENCM3_VECTOR_H +#define LIBOPENCM3_VECTOR_H + +#include +#include + +/** Type of an interrupt function. Only used to avoid hard-to-read function + * pointers in the efm32_vector_table_t struct. */ +typedef void (*vector_table_entry_t)(void); + +typedef struct { + unsigned int *initial_sp_value; /**< Initial stack pointer value. */ + vector_table_entry_t reset; + vector_table_entry_t nmi; + vector_table_entry_t hard_fault; + vector_table_entry_t memory_manage_fault; /* not in CM0 */ + vector_table_entry_t bus_fault; /* not in CM0 */ + vector_table_entry_t usage_fault; /* not in CM0 */ + vector_table_entry_t reserved_x001c[4]; + vector_table_entry_t sv_call; + vector_table_entry_t debug_monitor; /* not in CM0 */ + vector_table_entry_t reserved_x0034; + vector_table_entry_t pend_sv; + vector_table_entry_t systick; + vector_table_entry_t irq[NVIC_IRQ_COUNT]; +} vector_table_t; + +#endif diff --git a/libopencm3/include/libopencm3/docmain.dox b/libopencm3/include/libopencm3/docmain.dox new file mode 100644 index 0000000..f85aeb8 --- /dev/null +++ b/libopencm3/include/libopencm3/docmain.dox @@ -0,0 +1,21 @@ +/** @mainpage libopencm3 Developer Documentation + +@version 1.0.0 + +@date 7 September 2012 + + * The libopencm3 project (previously known as libopenstm32) aims to create + * a free/libre/open-source (GPL v3, or later) firmware library for various + * ARM Cortex-M3 microcontrollers, including ST STM32, Toshiba TX03, + * Atmel SAM3U, NXP LPC1000 and others. + * + * @par "" + * + * See the libopencm3 wiki for + * more information. + +LGPL License Terms @ref lgpl_license +*/ + + + diff --git a/libopencm3/include/libopencm3/efm32/efm32g/doc-efm32g.h b/libopencm3/include/libopencm3/efm32/efm32g/doc-efm32g.h new file mode 100644 index 0000000..747cb51 --- /dev/null +++ b/libopencm3/include/libopencm3/efm32/efm32g/doc-efm32g.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 EFM32 Gecko + +@version 1.0.0 + +@date 11 November 2012 + +API documentation for Energy Micro EFM32 Gecko Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup EFM32G EFM32 Gecko +Libraries for Energy Micro EFM32 Gecko series. + +@version 1.0.0 + +@date 11 November 2012 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup EFM32G_defines EFM32 Gecko Defines + +@brief Defined Constants and Types for the Energy Micro EFM32 Gecko series + +@version 1.0.0 + +@date 11 November 2012 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/libopencm3/include/libopencm3/efm32/efm32g/irq.json b/libopencm3/include/libopencm3/efm32/efm32g/irq.json new file mode 100644 index 0000000..59cc38b --- /dev/null +++ b/libopencm3/include/libopencm3/efm32/efm32g/irq.json @@ -0,0 +1,38 @@ +{ + "_source": "The names and sequence are taken from d0001_efm32g_reference_manual.pdf table 4.1.", + "irqs": [ + "dma", + "gpio_even", + "timer0", + "usart0_rx", + "usart0_tx", + "acmp01", + "adc0", + "dac0", + "i2c0", + "gpio_odd", + "timer1", + "timer2", + "usart1_rx", + "usart1_tx", + "usart2_rx", + "usart2_tx", + "uart0_rx", + "uart0_tx", + "leuart0", + "leuart1", + "letimer0", + "pcnt0", + "pcnt1", + "pcnt2", + "rtc", + "cmu", + "vcmp", + "lcd", + "msc", + "aes" + ], + "partname_humanreadable": "EFM32 Gecko series", + "partname_doxygen": "EFM32G", + "includeguard": "LIBOPENCM3_EFM32G_NVIC_H" +} diff --git a/libopencm3/include/libopencm3/efm32/efm32gg/doc-efm32gg.h b/libopencm3/include/libopencm3/efm32/efm32gg/doc-efm32gg.h new file mode 100644 index 0000000..aacb17b --- /dev/null +++ b/libopencm3/include/libopencm3/efm32/efm32gg/doc-efm32gg.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 EFM32 Giant Gecko + +@version 1.0.0 + +@date 11 November 2012 + +API documentation for Energy Micro EFM32 Giant Gecko Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup EFM32GG EFM32 Giant Gecko +Libraries for Energy Micro EFM32 Giant Gecko series. + +@version 1.0.0 + +@date 11 November 2012 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup EFM32GG_defines EFM32 Giant Gecko Defines + +@brief Defined Constants and Types for the Energy Micro EFM32 Giant Gecko series + +@version 1.0.0 + +@date 11 November 2012 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/libopencm3/include/libopencm3/efm32/efm32gg/irq.json b/libopencm3/include/libopencm3/efm32/efm32gg/irq.json new file mode 100644 index 0000000..43e7e8c --- /dev/null +++ b/libopencm3/include/libopencm3/efm32/efm32gg/irq.json @@ -0,0 +1,46 @@ +{ + "_source": "The names and sequence are taken from d0053_efm32gg_refreence_manual.pdf table 4.1.", + "irqs": [ + "dma", + "gpio_even", + "timer0", + "usart0_rx", + "usart0_tx", + "usb", + "acmp01", + "adc0", + "dac0", + "i2c0", + "i2c1", + "gpio_odd", + "timer1", + "timer2", + "timer3", + "usart1_rx", + "usart1_tx", + "lesense", + "usart2_rx", + "usart2_tx", + "uart0_rx", + "uart0_tx", + "uart1_rx", + "uart1_tx", + "leuart0", + "leuart1", + "letimer0", + "pcnt0", + "pcnt1", + "pcnt2", + "rtc", + "burtc", + "cmu", + "vcmp", + "lcd", + "msc", + "aes", + "ebi" + ], + "partname_humanreadable": "EFM32 Giant Gecko series", + "partname_doxygen": "EFM32GG", + "includeguard": "LIBOPENCM3_EFM32GG_NVIC_H" +} diff --git a/libopencm3/include/libopencm3/efm32/efm32lg/doc-efm32lg.h b/libopencm3/include/libopencm3/efm32/efm32lg/doc-efm32lg.h new file mode 100644 index 0000000..7721239 --- /dev/null +++ b/libopencm3/include/libopencm3/efm32/efm32lg/doc-efm32lg.h @@ -0,0 +1,33 @@ +/** @mainpage libopencm3 EFM32 Leopard Gecko + +@version 1.0.0 + +@date 4 March 2013 + +API documentation for Energy Micro EFM32 Leopard Gecko Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup EFM32LG EFM32 LeopardGecko +Libraries for Energy Micro EFM32 Leopard Gecko series. + +@version 1.0.0 + +@date 4 March 2013 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup EFM32LG_defines EFM32 Leopard Gecko Defines + +@brief Defined Constants and Types for the Energy Micro EFM32 Leopard Gecko +series + +@version 1.0.0 + +@date 4 March 2013 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/libopencm3/include/libopencm3/efm32/efm32lg/irq.json b/libopencm3/include/libopencm3/efm32/efm32lg/irq.json new file mode 100644 index 0000000..beb036d --- /dev/null +++ b/libopencm3/include/libopencm3/efm32/efm32lg/irq.json @@ -0,0 +1,46 @@ +{ + "_source": "The names and sequence are taken from d0183_efm32lg_reference_manual.pdf table 4.1.", + "irqs": [ + "dma", + "gpio_even", + "timer0", + "usart0_rx", + "usart0_tx", + "usb", + "acmp01", + "adc0", + "dac0", + "i2c0", + "i2c1", + "gpio_odd", + "timer1", + "timer2", + "timer3", + "usart1_rx", + "usart1_tx", + "lesense", + "usart2_rx", + "usart2_tx", + "uart0_rx", + "uart0_tx", + "uart1_rx", + "uart1_tx", + "leuart0", + "leuart1", + "letimer0", + "pcnt0", + "pcnt1", + "pcnt2", + "rtc", + "burtc", + "cmu", + "vcmp", + "lcd", + "msc", + "aes", + "ebi" + ], + "partname_humanreadable": "EFM32 Leopard Gecko series", + "partname_doxygen": "EFM32LG", + "includeguard": "LIBOPENCM3_EFM32LG_NVIC_H" +} diff --git a/libopencm3/include/libopencm3/efm32/efm32tg/doc-efm32tg.h b/libopencm3/include/libopencm3/efm32/efm32tg/doc-efm32tg.h new file mode 100644 index 0000000..799048c --- /dev/null +++ b/libopencm3/include/libopencm3/efm32/efm32tg/doc-efm32tg.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 EFM32 Tiny Gecko + +@version 1.0.0 + +@date 4 March 2013 + +API documentation for Energy Micro EFM32 Tiny Gecko Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup EFM32TG EFM32 TinyGecko +Libraries for Energy Micro EFM32 Tiny Gecko series. + +@version 1.0.0 + +@date 4 March 2013 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup EFM32TG_defines EFM32 Tiny Gecko Defines + +@brief Defined Constants and Types for the Energy Micro EFM32 Tiny Gecko series + +@version 1.0.0 + +@date 4 March 2013 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/libopencm3/include/libopencm3/efm32/efm32tg/irq.json b/libopencm3/include/libopencm3/efm32/efm32tg/irq.json new file mode 100644 index 0000000..95efa85 --- /dev/null +++ b/libopencm3/include/libopencm3/efm32/efm32tg/irq.json @@ -0,0 +1,31 @@ +{ + "_source": "The names and sequence are taken from d0034_efm32tg_reference_manual.pdf table 4.1.", + "irqs": [ + "dma", + "gpio_even", + "timer0", + "usart0_rx", + "usart0_tx", + "acmp01", + "adc0", + "dac0", + "i2c0", + "gpio_odd", + "timer1", + "usart1_rx", + "usart1_tx", + "lesense", + "leuart0", + "letimer0", + "pcnt0", + "rtc", + "cmu", + "vcmp", + "lcd", + "msc", + "aes" + ], + "partname_humanreadable": "EFM32 Tiny Gecko series", + "partname_doxygen": "EFM32TG", + "includeguard": "LIBOPENCM3_EFM32TG_NVIC_H" +} diff --git a/libopencm3/include/libopencm3/efm32/efm32tg/memorymap.h b/libopencm3/include/libopencm3/efm32/efm32tg/memorymap.h new file mode 100644 index 0000000..d17bb60 --- /dev/null +++ b/libopencm3/include/libopencm3/efm32/efm32tg/memorymap.h @@ -0,0 +1,76 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/** @file + * + * Layout of the system address space of Tiny Gecko devices. + * + * This reflects d0034_efm32tg_reference_manual.pdf figure 5.2. + */ + +/* The common cortex-m3 definitions were verified from + * d0034_efm32tg_reference_manual.pdf figure 5.2. The CM3 ROM Table seems to be + * missing there. The details (everything based on SCS_BASE) was verified from + * d0002_efm32_cortex-m3_reference_manual.pdf table 4.1, and seems to fit, but + * there are discrepancies. */ +#include + +#define CODE_BASE (0x00000000U) + +#define SRAM_BASE (0x20000000U) +#define SRAM_BASE_BITBAND (0x22000000U) + +#define PERIPH_BASE (0x40000000U) +#define PERIPH_BASE_BITBAND (0x42000000U) + +/* Details of the "Code" section */ + +#define FLASH_BASE (CODE_BASE + 0x00000000) +#define USERDATA_BASE (CODE_BASE + 0x0fe00000) +#define LOCKBITS_BASE (CODE_BASE + 0x0fe04000) +#define CHIPCONFIG_BASE (CODE_BASE + 0x0fe08000) +#define CODESPACESRAM_BASE (CODE_BASE + 0x10000000) + +/* Tiny Gecko peripherial definitions */ + +#define VCMP_BASE (PERIPH_BASE + 0x00000000) +#define ACMP0_BASE (PERIPH_BASE + 0x00001000) +#define ACMP1_BASE (PERIPH_BASE + 0x00001400) +#define ADC_BASE (PERIPH_BASE + 0x00002000) +#define DAC0_BASE (PERIPH_BASE + 0x00004000) +#define GPIO_BASE (PERIPH_BASE + 0x00006000) /**< @see gpio.h */ +#define I2C0_BASE (PERIPH_BASE + 0x0000a000) +#define USART0_BASE (PERIPH_BASE + 0x0000c000) +#define USART1_BASE (PERIPH_BASE + 0x0000c400) +#define TIMER0_BASE (PERIPH_BASE + 0x00010000) +#define TIMER1_BASE (PERIPH_BASE + 0x00010400) +#define RTC_BASE (PERIPH_BASE + 0x00080000) +#define LETIMER0_BASE (PERIPH_BASE + 0x00082000) +#define LEUART0_BASE (PERIPH_BASE + 0x00084000) +#define PCNT0_BASE (PERIPH_BASE + 0x00086000) +#define WDOG_BASE (PERIPH_BASE + 0x00088000) +#define LCD_BASE (PERIPH_BASE + 0x0008a000) +#define LESENSE_BASE (PERIPH_BASE + 0x0008c000) +#define MSC_BASE (PERIPH_BASE + 0x000c0000) +#define DMA_BASE (PERIPH_BASE + 0x000c2000) +#define EMU_BASE (PERIPH_BASE + 0x000c6000) +#define CMU_BASE (PERIPH_BASE + 0x000c8000) /**< @see cmu.h */ +#define RMU_BASE (PERIPH_BASE + 0x000ca000) +#define PRS_BASE (PERIPH_BASE + 0x000cc000) +#define AES_BASE (PERIPH_BASE + 0x000e0000) diff --git a/libopencm3/include/libopencm3/efm32/memorymap.h b/libopencm3/include/libopencm3/efm32/memorymap.h new file mode 100644 index 0000000..ff0e544 --- /dev/null +++ b/libopencm3/include/libopencm3/efm32/memorymap.h @@ -0,0 +1,37 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 chrysn + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/** @file + * + * Dispatcher for the base address definitions, depending on the particular + * Gecko family. + * + * @see tinygecko/memorymap.h + */ + +#ifndef LIBOPENCM3_EFM32_MEMORYMAP_H +#define LIBOPENCM3_EFM32_MEMORYMAP_H + +#ifdef TINYGECKO +# include +#else +# error "efm32 family not defined." +#endif + +#endif diff --git a/libopencm3/include/libopencm3/ethernet/mac.h b/libopencm3/include/libopencm3/ethernet/mac.h new file mode 100644 index 0000000..b047e4d --- /dev/null +++ b/libopencm3/include/libopencm3/ethernet/mac.h @@ -0,0 +1,46 @@ +/** @defgroup ethernet_mac_defines MAC Generic Defines + * + * @brief Defined Constants and Types for the Ethernet MAC + * + * @ingroup ETH + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2013 Frantisek Burian + * + * @date 1 September 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#if defined(STM32F1) +# include +#elif defined(STM32F4) +# include +#else +# error "stm32 family not defined." +#endif + +/**@}*/ + + diff --git a/libopencm3/include/libopencm3/ethernet/mac_stm32fxx7.h b/libopencm3/include/libopencm3/ethernet/mac_stm32fxx7.h new file mode 100644 index 0000000..a14a911 --- /dev/null +++ b/libopencm3/include/libopencm3/ethernet/mac_stm32fxx7.h @@ -0,0 +1,752 @@ +/** @defgroup ethernet_mac_stm32fxx7_defines MAC STM32Fxx7 Defines + * + * @brief Defined Constants and Types for the Ethernet MAC for STM32Fxx7 + * chips + * + * @ingroup ETH + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2013 Frantisek Burian + * + * @date 1 September 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_ETHERNET_H +#define LIBOPENCM3_ETHERNET_H + +#include +#include + +/**@{*/ + +/* Ethernet MAC registers */ +#define ETH_MACCR MMIO32(ETHERNET_BASE + 0x00) +#define ETH_MACFFR MMIO32(ETHERNET_BASE + 0x04) +#define ETH_MACHTHR MMIO32(ETHERNET_BASE + 0x08) +#define ETH_MACHTLR MMIO32(ETHERNET_BASE + 0x0C) +#define ETH_MACMIIAR MMIO32(ETHERNET_BASE + 0x10) +#define ETH_MACMIIDR MMIO32(ETHERNET_BASE + 0x14) +#define ETH_MACFCR MMIO32(ETHERNET_BASE + 0x18) +#define ETH_MACVLANTR MMIO32(ETHERNET_BASE + 0x1C) +#define ETH_MACRWUFFR MMIO32(ETHERNET_BASE + 0x28) +#define ETH_MACPMTCSR MMIO32(ETHERNET_BASE + 0x2C) +/* not available on F1 ?*/ +#define ETH_MACDBGR MMIO32(ETHERNET_BASE + 0x34) +#define ETH_MACSR MMIO32(ETHERNET_BASE + 0x38) +#define ETH_MACIMR MMIO32(ETHERNET_BASE + 0x3C) + +/* i=[0..3] */ +#define ETH_MACAHR(i) MMIO32(ETHERNET_BASE + 0x40+i*8) +/* i=[0..3] */ +#define ETH_MACALR(i) MMIO32(ETHERNET_BASE + 0x44+i*8) + +/* Ethernet MMC registers */ +#define ETH_MMCCR MMIO32(ETHERNET_BASE + 0x100) +#define ETH_MMCRIR MMIO32(ETHERNET_BASE + 0x104) +#define ETH_MMCTIR MMIO32(ETHERNET_BASE + 0x108) +#define ETH_MMCRIMR MMIO32(ETHERNET_BASE + 0x10C) +#define ETH_MMCTIMR MMIO32(ETHERNET_BASE + 0x110) +#define ETH_MMCTGFSCCR MMIO32(ETHERNET_BASE + 0x14C) +#define ETH_MMCTGFMSCCR MMIO32(ETHERNET_BASE + 0x150) +#define ETH_MMCTGFCR MMIO32(ETHERNET_BASE + 0x168) +#define ETH_MMCRFCECR MMIO32(ETHERNET_BASE + 0x194) +#define ETH_MMCRFAECR MMIO32(ETHERNET_BASE + 0x198) +#define ETH_MMCRGUFCR MMIO32(ETHERNET_BASE + 0x1C4) + +/* Ethrenet IEEE 1588 time stamp registers */ +#define ETH_PTPTSCR MMIO32(ETHERNET_BASE + 0x700) +#define ETH_PTPSSIR MMIO32(ETHERNET_BASE + 0x704) +#define ETH_PTPTSHR MMIO32(ETHERNET_BASE + 0x708) +#define ETH_PTPTSLR MMIO32(ETHERNET_BASE + 0x70C) +#define ETH_PTPTSHUR MMIO32(ETHERNET_BASE + 0x710) +#define ETH_PTPTSLUR MMIO32(ETHERNET_BASE + 0x714) +#define ETH_PTPTSAR MMIO32(ETHERNET_BASE + 0x718) +#define ETH_PTPTTHR MMIO32(ETHERNET_BASE + 0x71C) +#define ETH_PTPTTLR MMIO32(ETHERNET_BASE + 0x720) +/* not available on F1 ?*/ +#define ETH_PTPTSSR MMIO32(ETHERNET_BASE + 0x728) + +/* Ethernet DMA registers */ +#define ETH_DMABMR MMIO32(ETHERNET_BASE + 0x1000) +#define ETH_DMATPDR MMIO32(ETHERNET_BASE + 0x1004) +#define ETH_DMARPDR MMIO32(ETHERNET_BASE + 0x1008) +#define ETH_DMARDLAR MMIO32(ETHERNET_BASE + 0x100C) +#define ETH_DMATDLAR MMIO32(ETHERNET_BASE + 0x1010) +#define ETH_DMASR MMIO32(ETHERNET_BASE + 0x1014) +#define ETH_DMAOMR MMIO32(ETHERNET_BASE + 0x1018) +#define ETH_DMAIER MMIO32(ETHERNET_BASE + 0x101C) +#define ETH_DMAMFBOCR MMIO32(ETHERNET_BASE + 0x1020) +#define ETH_DMACHTDR MMIO32(ETHERNET_BASE + 0x1048) +#define ETH_DMACHRDR MMIO32(ETHERNET_BASE + 0x104C) +#define ETH_DMACHTBAR MMIO32(ETHERNET_BASE + 0x1050) +#define ETH_DMACHRBAR MMIO32(ETHERNET_BASE + 0x1054) + +/* Ethernet Buffer Descriptors */ +#define ETH_DES(n, base) MMIO32((base) + (n)*4) +#define ETH_DES0(base) ETH_DES(0, base) +#define ETH_DES1(base) ETH_DES(1, base) +#define ETH_DES2(base) ETH_DES(2, base) +#define ETH_DES3(base) ETH_DES(3, base) + +/* Ethernet Extended buffer Descriptors */ +#define ETH_DES4(base) ETH_DES(4, base) +#define ETH_DES5(base) ETH_DES(5, base) +#define ETH_DES6(base) ETH_DES(6, base) +#define ETH_DES7(base) ETH_DES(7, base) + +/*---------------------------------------------------------------------------*/ +/* MACCR --------------------------------------------------------------------*/ + +#define ETH_MACCR_RE (1<<2) +#define ETH_MACCR_TE (1<<3) +#define ETH_MACCR_DC (1<<4) + +#define ETH_MACCR_BL_SHIFT 5 +#define ETH_MACCR_BL (3 << ETH_MACCR_BL_SHIFT) +#define ETH_MACCR_BL_MIN10 (0 << ETH_MACCR_BL_SHIFT) +#define ETH_MACCR_BL_MIN8 (1 << ETH_MACCR_BL_SHIFT) +#define ETH_MACCR_BL_MIN4 (2 << ETH_MACCR_BL_SHIFT) +#define ETH_MACCR_BL_MIN1 (3 << ETH_MACCR_BL_SHIFT) + +#define ETH_MACCR_APCS (1<<7) +#define ETH_MACCR_RD (1<<9) +#define ETH_MACCR_IPCO (1<<10) +#define ETH_MACCR_DM (1<<11) +#define ETH_MACCR_LM (1<<12) +#define ETH_MACCR_ROD (1<<13) +#define ETH_MACCR_FES (1<<14) +#define ETH_MACCR_CSD (1<<16) + +#define ETH_MACCR_IFG_SHIFT 17 +#define ETH_MACCR_IFG (7<Defined Constants and Types for the Ethernet PHY + * + * @ingroup ETH + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2013 Frantisek Burian + * + * @date 1 September 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ +#ifndef LIBOPENCM3_PHY_H +#define LIBOPENCM3_PHY_H + +#include + +/**@{*/ + +/* Registers */ + +#define PHY_REG_BCR 0x00 +#define PHY_REG_BSR 0x01 +#define PHY_REG_ID1 0x02 +#define PHY_REG_ID2 0x03 +#define PHY_REG_ANTX 0x04 +#define PHY_REG_ANRX 0x05 +#define PHY_REG_ANEXP 0x06 +#define PHY_REG_ANNPTX 0x07 +#define PHY_REG_ANNPRX 0x08 + +#define PHY_REG_BCR_COLTEST (1<<7) +#define PHY_REG_BCR_FD (1<<8) +#define PHY_REG_BCR_ANRST (1<<9) +#define PHY_REG_BCR_ISOLATE (1<<10) +#define PHY_REG_BCR_POWERDN (1<<11) +#define PHY_REG_BCR_AN (1<<12) +#define PHY_REG_BCR_100M (1<<13) +#define PHY_REG_BCR_LOOPBACK (1<<14) +#define PHY_REG_BCR_RESET (1<<15) + +#define PHY_REG_BSR_JABBER (1<<1) +#define PHY_REG_BSR_UP (1<<2) +#define PHY_REG_BSR_FAULT (1<<4) +#define PHY_REG_BSR_ANDONE (1<<5) + + +enum phy_status { + LINK_DOWN, + LINK_HD_10M, + LINK_HD_100M, + LINK_HD_1000M, + LINK_HD_10000M, + LINK_FD_10M, + LINK_FD_100M, + LINK_FD_1000M, + LINK_FD_10000M, +}; + +void phy_reset(void); +bool phy_link_isup(void); + +enum phy_status phy_link_status(void); + +void phy_autoneg_force(enum phy_status mode); +void phy_autoneg_enable(void); + +/**@}*/ + + +#endif /* LIBOPENCM3_PHY_H__ */ diff --git a/libopencm3/include/libopencm3/ethernet/phy_ksz8051mll.h b/libopencm3/include/libopencm3/ethernet/phy_ksz8051mll.h new file mode 100644 index 0000000..a7f9865 --- /dev/null +++ b/libopencm3/include/libopencm3/ethernet/phy_ksz8051mll.h @@ -0,0 +1,60 @@ +/** @defgroup ethernet_phy_ksz8051mll_defines PHY KSZ8051mll Defines + * + * @brief Defined Constants and Types for the Ethernet PHY KSZ8051mll + * chips + * + * @ingroup ETH + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2013 Frantisek Burian + * + * @date 1 September 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_PHY_KSZ8051MLL_H +#define LIBOPENCM3_PHY_KSZ8051MLL_H + +#include + +/**@{*/ + +/* Registers */ + +#define PHY_REG_AFECTRL 0x11 +#define PHY_REG_RXERCTR 0x15 +#define PHY_REG_STRAPOVRD 0x16 +#define PHY_REG_STRAPSTAT 0x17 +#define PHY_REG_ECR 0x18 + +#define PHY_REG_ICSR 0x1B + +#define PHY_REG_LINKMD 0x1D + +#define PHY_REG_CR1 0x1E +#define PHY_REG_CR2 0x1E + +/**@}*/ + + +#endif /* LIBOPENCM3_PHY_KSZ8051MLL_H__ */ diff --git a/libopencm3/include/libopencm3/license.dox b/libopencm3/include/libopencm3/license.dox new file mode 100644 index 0000000..3aa9331 --- /dev/null +++ b/libopencm3/include/libopencm3/license.dox @@ -0,0 +1,16 @@ +/** @page lgpl_license libopencm3 License + +libopencm3 is free software: you can redistribute it and/or modify +it under the terms of the GNU Lesser General Public License as published by the Free +Software Foundation, either version 3 of the License, or (at your option) any +later version. + +libopencm3 is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A +PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. + +You should have received a copy of the GNU Lesser General Public License along with this +program. If not, see . + +*/ + diff --git a/libopencm3/include/libopencm3/lm3s/doc-lm3s.h b/libopencm3/include/libopencm3/lm3s/doc-lm3s.h new file mode 100644 index 0000000..1a4ecb8 --- /dev/null +++ b/libopencm3/include/libopencm3/lm3s/doc-lm3s.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 LM3S + +@version 1.0.0 + +@date 14 September 2012 + +API documentation for TI Stellaris LM3S Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup LM3Sxx LM3S +Libraries for TI Stellaris LM3S series. + +@version 1.0.0 + +@date 7 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup LM3Sxx_defines LM3S Defines + +@brief Defined Constants and Types for the LM3S series + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/libopencm3/include/libopencm3/lm3s/gpio.h b/libopencm3/include/libopencm3/lm3s/gpio.h new file mode 100644 index 0000000..8b12078 --- /dev/null +++ b/libopencm3/include/libopencm3/lm3s/gpio.h @@ -0,0 +1,99 @@ +/** @defgroup gpio_defines General Purpose I/O Defines + +@brief Defined Constants and Types for the LM3S General Purpose I/O + +@ingroup LM3Sxx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2011 +Gareth McMullin + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LM3S_GPIO_H +#define LM3S_GPIO_H + +/**@{*/ + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* GPIO port base addresses (for convenience) */ +#define GPIOA GPIOA_APB_BASE +#define GPIOB GPIOB_APB_BASE +#define GPIOC GPIOC_APB_BASE +#define GPIOD GPIOD_APB_BASE +#define GPIOE GPIOE_APB_BASE +#define GPIOF GPIOF_APB_BASE +#define GPIOG GPIOG_APB_BASE +#define GPIOH GPIOH_APB_BASE + +/* GPIO number definitions (for convenience) */ +#define GPIO0 (1 << 0) +#define GPIO1 (1 << 1) +#define GPIO2 (1 << 2) +#define GPIO3 (1 << 3) +#define GPIO4 (1 << 4) +#define GPIO5 (1 << 5) +#define GPIO6 (1 << 6) +#define GPIO7 (1 << 7) + +/* --- GPIO registers ------------------------------------------------------ */ + +#define GPIO_DATA(port) (&MMIO32(port + 0x000)) +#define GPIO_DIR(port) MMIO32(port + 0x400) +#define GPIO_IS(port) MMIO32(port + 0x404) +#define GPIO_IBE(port) MMIO32(port + 0x408) +#define GPIO_IEV(port) MMIO32(port + 0x40c) +#define GPIO_IM(port) MMIO32(port + 0x410) +#define GPIO_RIS(port) MMIO32(port + 0x414) +#define GPIO_MIS(port) MMIO32(port + 0x418) +#define GPIO_ICR(port) MMIO32(port + 0x41c) +#define GPIO_AFSEL(port) MMIO32(port + 0x420) +#define GPIO_DR2R(port) MMIO32(port + 0x500) +#define GPIO_DR4R(port) MMIO32(port + 0x504) +#define GPIO_DR8R(port) MMIO32(port + 0x508) +#define GPIO_ODR(port) MMIO32(port + 0x50c) +#define GPIO_PUR(port) MMIO32(port + 0x510) +#define GPIO_PDR(port) MMIO32(port + 0x514) +#define GPIO_SLR(port) MMIO32(port + 0x518) +#define GPIO_DEN(port) MMIO32(port + 0x51c) +#define GPIO_LOCK(port) MMIO32(port + 0x520) +#define GPIO_CR(port) MMIO32(port + 0x524) +#define GPIO_AMSEL(port) MMIO32(port + 0x528) + +BEGIN_DECLS + +void gpio_set(uint32_t gpioport, uint8_t gpios); +void gpio_clear(uint32_t gpioport, uint8_t gpios); + +END_DECLS + +/**@}*/ + +#endif + diff --git a/libopencm3/include/libopencm3/lm3s/irq.json b/libopencm3/include/libopencm3/lm3s/irq.json new file mode 100644 index 0000000..0d8dcfc --- /dev/null +++ b/libopencm3/include/libopencm3/lm3s/irq.json @@ -0,0 +1,126 @@ +{ + "_comment": [ + "Although this says LM3S, the interrupt table applies to the", + "LM4F as well Some interrupt vectores marked as reserved in LM3S are", + "used in LM4F, and some vectors in LM3S are marked reserved for LM4F.", + "However, the common vectors are identical, and we can safely use the", + "same interrupt table. Reserved vectors will never be triggered, so", + "having them is perfectly safe." + ], + "irqs": { + "0": "GPIOA", + "1": "GPIOB", + "2": "GPIOC", + "3": "GPIOD", + "4": "GPIOE", + "5": "UART0", + "6": "UART1", + "7": "SSI0", + "8": "I2C0", + "9": "PWM0_FAULT", + "10": "PWM0_0", + "11": "PWM0_1", + "12": "PWM0_2", + "13": "QEI0", + "14": "ADC0SS0", + "15": "ADC0SS1", + "16": "ADC0SS2", + "17": "ADC0SS3", + "18": "WATCHDOG", + "19": "TIMER0A", + "20": "TIMER0B", + "21": "TIMER1A", + "22": "TIMER1B", + "23": "TIMER2A", + "24": "TIMER2B", + "25": "COMP0", + "26": "COMP1", + "27": "COMP2", + "28": "SYSCTL", + "29": "FLASH", + "30": "GPIOF", + "31": "GPIOG", + "32": "GPIOH", + "33": "UART2", + "34": "SSI1", + "35": "TIMER3A", + "36": "TIMER3B", + "37": "I2C1", + "38": "QEI1", + "39": "CAN0", + "40": "CAN1", + "41": "CAN2", + "42": "ETH", + "43": "HIBERNATE", + "44": "USB0", + "45": "PWM0_3", + "46": "UDMA", + "47": "UDMAERR", + "48": "ADC1SS0", + "49": "ADC1SS1", + "50": "ADC1SS2", + "51": "ADC1SS3", + "52": "I2S0", + "53": "EPI0", + "54": "GPIOJ", + "55": "GPIOK", + "56": "GPIOL", + "57": "SSI2", + "58": "SSI3", + "59": "UART3", + "60": "UART4", + "61": "UART5", + "62": "UART6", + "63": "UART7", + "68": "I2C2", + "69": "I2C3", + "70": "TIMER4A", + "71": "TIMER4B", + "92": "TIMER5A", + "93": "TIMER5B", + "94": "WTIMER0A", + "95": "WTIMER0B", + "96": "WTIMER1A", + "97": "WTIMER1B", + "98": "WTIMER2A", + "99": "WTIMER2B", + "100": "WTIMER3A", + "101": "WTIMER3B", + "102": "WTIMER4A", + "103": "WTIMER4B", + "104": "WTIMER5A", + "105": "WTIMER5B", + "106": "SYSEXC", + "107": "PECI0", + "108": "LPC0", + "109": "I2C4", + "110": "I2C5", + "111": "GPIOM", + "112": "GPION", + "114": "FAN0", + "116": "GPIOP0", + "117": "GPIOP1", + "118": "GPIOP2", + "119": "GPIOP3", + "120": "GPIOP4", + "121": "GPIOP5", + "122": "GPIOP6", + "123": "GPIOP7", + "124": "GPIOQ0", + "125": "GPIOQ1", + "126": "GPIOQ2", + "127": "GPIOQ3", + "128": "GPIOQ4", + "129": "GPIOQ5", + "130": "GPIOQ6", + "131": "GPIOQ7", + "134": "PWM1_0", + "135": "PWM1_1", + "136": "PWM1_2", + "137": "PWM1_3", + "138": "PWM1_FAULT" + }, + "partname_humanreadable": "LM3S series", + "partname_doxygen": "LM3S", + "includeguard": "LIBOPENCM3_LM3S_NVIC_H" +} diff --git a/libopencm3/include/libopencm3/lm3s/memorymap.h b/libopencm3/include/libopencm3/lm3s/memorymap.h new file mode 100644 index 0000000..df5d6e3 --- /dev/null +++ b/libopencm3/include/libopencm3/lm3s/memorymap.h @@ -0,0 +1,47 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LM3S_MEMORYMAP_H +#define LM3S_MEMORYMAP_H + +#include + +/* --- LM3S specific peripheral definitions ----------------------------- */ + +#define GPIOA_APB_BASE (0x40004000U) +#define GPIOB_APB_BASE (0x40005000U) +#define GPIOC_APB_BASE (0x40006000U) +#define GPIOD_APB_BASE (0x40007000U) +#define GPIOE_APB_BASE (0x40024000U) +#define GPIOF_APB_BASE (0x40025000U) +#define GPIOG_APB_BASE (0x40026000U) +#define GPIOH_APB_BASE (0x40027000U) + +#define GPIOA_BASE (0x40058000U) +#define GPIOB_BASE (0x40059000U) +#define GPIOC_BASE (0x4005A000U) +#define GPIOD_BASE (0x4005B000U) +#define GPIOE_BASE (0x4005C000U) +#define GPIOF_BASE (0x4005D000U) +#define GPIOG_BASE (0x4005E000U) +#define GPIOH_BASE (0x4005F000U) + +#define SYSTEMCONTROL_BASE (0x400FE000U) + +#endif diff --git a/libopencm3/include/libopencm3/lm3s/systemcontrol.h b/libopencm3/include/libopencm3/lm3s/systemcontrol.h new file mode 100644 index 0000000..dd02f0f --- /dev/null +++ b/libopencm3/include/libopencm3/lm3s/systemcontrol.h @@ -0,0 +1,81 @@ +/** @defgroup systemcontrol_defines System Control + +@brief Defined Constants and Types for the LM3S System Control + +@ingroup LM3Sxx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2011 +Gareth McMullin + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LM3S_SYSTEMCONTROL_H +#define LM3S_SYSTEMCONTROL_H + +/**@{*/ + +#include + +#define SYSTEMCONTROL_DID0 MMIO32(SYSTEMCONTROL_BASE + 0x000) +#define SYSTEMCONTROL_DID1 MMIO32(SYSTEMCONTROL_BASE + 0x004) +#define SYSTEMCONTROL_DC0 MMIO32(SYSTEMCONTROL_BASE + 0x008) +#define SYSTEMCONTROL_DC1 MMIO32(SYSTEMCONTROL_BASE + 0x010) +#define SYSTEMCONTROL_DC2 MMIO32(SYSTEMCONTROL_BASE + 0x014) +#define SYSTEMCONTROL_DC3 MMIO32(SYSTEMCONTROL_BASE + 0x018) +#define SYSTEMCONTROL_DC4 MMIO32(SYSTEMCONTROL_BASE + 0x01C) +#define SYSTEMCONTROL_DC5 MMIO32(SYSTEMCONTROL_BASE + 0x020) +#define SYSTEMCONTROL_DC6 MMIO32(SYSTEMCONTROL_BASE + 0x024) +#define SYSTEMCONTROL_DC7 MMIO32(SYSTEMCONTROL_BASE + 0x028) +#define SYSTEMCONTROL_PBORCTL MMIO32(SYSTEMCONTROL_BASE + 0x030) +#define SYSTEMCONTROL_LDORCTL MMIO32(SYSTEMCONTROL_BASE + 0x034) +#define SYSTEMCONTROL_SRCR0 MMIO32(SYSTEMCONTROL_BASE + 0x040) +#define SYSTEMCONTROL_SRCR1 MMIO32(SYSTEMCONTROL_BASE + 0x044) +#define SYSTEMCONTROL_SRCR2 MMIO32(SYSTEMCONTROL_BASE + 0x048) +#define SYSTEMCONTROL_RIS MMIO32(SYSTEMCONTROL_BASE + 0x050) +#define SYSTEMCONTROL_IMC MMIO32(SYSTEMCONTROL_BASE + 0x054) +#define SYSTEMCONTROL_MISC MMIO32(SYSTEMCONTROL_BASE + 0x058) +#define SYSTEMCONTROL_RESC MMIO32(SYSTEMCONTROL_BASE + 0x05C) +#define SYSTEMCONTROL_RCC MMIO32(SYSTEMCONTROL_BASE + 0x060) +#define SYSTEMCONTROL_PLLCFG MMIO32(SYSTEMCONTROL_BASE + 0x064) +#define SYSTEMCONTROL_GPIOHBCTL MMIO32(SYSTEMCONTROL_BASE + 0x06C) +#define SYSTEMCONTROL_RCC2 MMIO32(SYSTEMCONTROL_BASE + 0x070) +#define SYSTEMCONTROL_MOSCCTL MMIO32(SYSTEMCONTROL_BASE + 0x07C) +#define SYSTEMCONTROL_RCGC0 MMIO32(SYSTEMCONTROL_BASE + 0x100) +#define SYSTEMCONTROL_RCGC1 MMIO32(SYSTEMCONTROL_BASE + 0x104) +#define SYSTEMCONTROL_RCGC2 MMIO32(SYSTEMCONTROL_BASE + 0x108) +#define SYSTEMCONTROL_SCGC0 MMIO32(SYSTEMCONTROL_BASE + 0x110) +#define SYSTEMCONTROL_SCGC1 MMIO32(SYSTEMCONTROL_BASE + 0x114) +#define SYSTEMCONTROL_SCGC2 MMIO32(SYSTEMCONTROL_BASE + 0x118) +#define SYSTEMCONTROL_DCGC0 MMIO32(SYSTEMCONTROL_BASE + 0x120) +#define SYSTEMCONTROL_DCGC1 MMIO32(SYSTEMCONTROL_BASE + 0x124) +#define SYSTEMCONTROL_DCGC2 MMIO32(SYSTEMCONTROL_BASE + 0x128) +#define SYSTEMCONTROL_DSLPCLKCFG MMIO32(SYSTEMCONTROL_BASE + 0x144) + +/**@}*/ + +#endif + diff --git a/libopencm3/include/libopencm3/lm4f/doc-lm4f.h b/libopencm3/include/libopencm3/lm4f/doc-lm4f.h new file mode 100644 index 0000000..4877721 --- /dev/null +++ b/libopencm3/include/libopencm3/lm4f/doc-lm4f.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 LM4F + +@version 1.0.0 + +@date 22 November 2012 + +API documentation for TI Stellaris LM4F Cortex M4F series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup LM4Fxx LM4F +Libraries for TI Stellaris LM4F series. + +@version 1.0.0 + +@date 22 November 2012 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup LM4Fxx_defines LM4F Defines + +@brief Defined Constants and Types for the LM4F series + +@version 1.0.0 + +@date 22 November 2012 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/libopencm3/include/libopencm3/lm4f/gpio.h b/libopencm3/include/libopencm3/lm4f/gpio.h new file mode 100644 index 0000000..5f90ad3 --- /dev/null +++ b/libopencm3/include/libopencm3/lm4f/gpio.h @@ -0,0 +1,380 @@ +/** @defgroup gpio_defines General Purpose I/O Defines + * + * @brief Defined Constants and Types for the LM4F General Purpose I/O + * + * @ingroup LM4Fxx_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2011 + * Gareth McMullin + * @author @htmlonly © @endhtmlonly 2013 + * Alexandru Gagniuc + * + * @date 16 March 2013 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * Copyright (C) 2013 Alexandru Gagniuc + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LM4F_GPIO_H +#define LM4F_GPIO_H + +/**@{*/ + +#include +#include + +/* ============================================================================= + * Convenience macros + * ---------------------------------------------------------------------------*/ +/** @defgroup gpio_reg_base GPIO register base addresses + * @{*/ +#define GPIOA GPIOA_BASE +#define GPIOB GPIOB_BASE +#define GPIOC GPIOC_BASE +#define GPIOD GPIOD_BASE +#define GPIOE GPIOE_BASE +#define GPIOF GPIOF_BASE +#define GPIOG GPIOG_BASE +#define GPIOH GPIOH_BASE +#define GPIOJ GPIOJ_BASE +#define GPIOK GPIOK_BASE +#define GPIOL GPIOL_BASE +#define GPIOM GPIOM_BASE +#define GPION GPION_BASE +#define GPIOP GPIOP_BASE +#define GPIOQ GPIOQ_BASE +/** @} */ + +/* ============================================================================= + * GPIO number definitions (for convenience) + * + * These are usable across all GPIO registers, + * except GPIO_LOCK and GPIO_PCTL + * ---------------------------------------------------------------------------*/ +/** @defgroup gpio_pin_id GPIO pin identifiers + * @{*/ +#define GPIO0 (1 << 0) +#define GPIO1 (1 << 1) +#define GPIO2 (1 << 2) +#define GPIO3 (1 << 3) +#define GPIO4 (1 << 4) +#define GPIO5 (1 << 5) +#define GPIO6 (1 << 6) +#define GPIO7 (1 << 7) +#define GPIO_ALL 0xff +/** @} */ + +/* ============================================================================= + * GPIO registers + * ---------------------------------------------------------------------------*/ + +/* GPIO Data */ +#define GPIO_DATA(port) (&MMIO32(port + 0x000)) + +/* GPIO Direction */ +#define GPIO_DIR(port) MMIO32(port + 0x400) + +/* GPIO Interrupt Sense */ +#define GPIO_IS(port) MMIO32(port + 0x404) + +/* GPIO Interrupt Both Edges */ +#define GPIO_IBE(port) MMIO32(port + 0x408) + +/* GPIO Interrupt Event */ +#define GPIO_IEV(port) MMIO32(port + 0x40c) + +/* GPIO Interrupt Mask */ +#define GPIO_IM(port) MMIO32(port + 0x410) + +/* GPIO Raw Interrupt Status */ +#define GPIO_RIS(port) MMIO32(port + 0x414) + +/* GPIO Masked Interrupt Status */ +#define GPIO_MIS(port) MMIO32(port + 0x418) + +/* GPIO Interrupt Clear */ +#define GPIO_ICR(port) MMIO32(port + 0x41c) + +/* GPIO Alternate Function Select */ +#define GPIO_AFSEL(port) MMIO32(port + 0x420) + +/* GPIO 2-mA Drive Select */ +#define GPIO_DR2R(port) MMIO32(port + 0x500) + +/* GPIO 4-mA Drive Select */ +#define GPIO_DR4R(port) MMIO32(port + 0x504) + +/* GPIO 8-mA Drive Select */ +#define GPIO_DR8R(port) MMIO32(port + 0x508) + +/* GPIO Open Drain Select */ +#define GPIO_ODR(port) MMIO32(port + 0x50c) + +/* GPIO Pull-Up Select */ +#define GPIO_PUR(port) MMIO32(port + 0x510) + +/* GPIO Pull-Down Select */ +#define GPIO_PDR(port) MMIO32(port + 0x514) + +/* GPIO Slew Rate Control Select */ +#define GPIO_SLR(port) MMIO32(port + 0x518) + +/* GPIO Digital Enable */ +#define GPIO_DEN(port) MMIO32(port + 0x51c) + +/* GPIO Lock */ +#define GPIO_LOCK(port) MMIO32(port + 0x520) + +/* GPIO Commit */ +#define GPIO_CR(port) MMIO32(port + 0x524) + +/* GPIO Analog Mode Select */ +#define GPIO_AMSEL(port) MMIO32(port + 0x528) + +/* GPIO Port Control */ +#define GPIO_PCTL(port) MMIO32(port + 0x52C) + +/* GPIO ADC Control */ +#define GPIO_ADCCTL(port) MMIO32(port + 0x530) + +/* GPIO DMA Control */ +#define GPIO_DMACTL(port) MMIO32(port + 0x534) + +/* GPIO Peripheral Identification */ +#define GPIO_PERIPH_ID4(port) MMIO32(port + 0xFD0) +#define GPIO_PERIPH_ID5(port) MMIO32(port + 0xFD4) +#define GPIO_PERIPH_ID6(port) MMIO32(port + 0xFD8) +#define GPIO_PERIPH_ID7(port) MMIO32(port + 0xFDC) +#define GPIO_PERIPH_ID0(port) MMIO32(port + 0xFE0) +#define GPIO_PERIPH_ID1(port) MMIO32(port + 0xFE4) +#define GPIO_PERIPH_ID2(port) MMIO32(port + 0xFE8) +#define GPIO_PERIPH_ID3(port) MMIO32(port + 0xFEC) + +/* GPIO PrimeCell Identification */ +#define GPIO_PCELL_ID0(port) MMIO32(port + 0xFF0) +#define GPIO_PCELL_ID1(port) MMIO32(port + 0xFF4) +#define GPIO_PCELL_ID2(port) MMIO32(port + 0xFF8) +#define GPIO_PCELL_ID3(port) MMIO32(port + 0xFFC) + +/* ============================================================================= + * Convenience enums + * ---------------------------------------------------------------------------*/ +enum gpio_mode { + GPIO_MODE_OUTPUT, /**< Configure pin as output */ + GPIO_MODE_INPUT, /**< Configure pin as input */ + GPIO_MODE_ANALOG, /**< Configure pin as analog function */ +}; + +enum gpio_pullup { + GPIO_PUPD_NONE, /**< Do not pull the pin high or low */ + GPIO_PUPD_PULLUP, /**< Pull the pin high */ + GPIO_PUPD_PULLDOWN, /**< Pull the pin low */ +}; + +enum gpio_output_type { + GPIO_OTYPE_PP, /**< Push-pull configuration */ + GPIO_OTYPE_OD, /**< Open drain configuration */ +}; + +enum gpio_drive_strength { + GPIO_DRIVE_2MA, /**< 2mA drive */ + GPIO_DRIVE_4MA, /**< 4mA drive */ + GPIO_DRIVE_8MA, /**< 8mA drive */ + GPIO_DRIVE_8MA_SLEW_CTL,/**< 8mA drive with slew rate control */ +}; + +enum gpio_trigger { + GPIO_TRIG_LVL_LOW, /**< Level trigger, signal low */ + GPIO_TRIG_LVL_HIGH, /**< Level trigger, signal high */ + GPIO_TRIG_EDGE_FALL, /**< Falling edge trigger */ + GPIO_TRIG_EDGE_RISE, /**< Rising edge trigger*/ + GPIO_TRIG_EDGE_BOTH, /**< Falling and Rising edges trigger*/ +}; +/* ============================================================================= + * Function prototypes + * ---------------------------------------------------------------------------*/ +BEGIN_DECLS + +void gpio_enable_ahb_aperture(void); +void gpio_mode_setup(uint32_t gpioport, enum gpio_mode mode, + enum gpio_pullup pullup, uint8_t gpios); +void gpio_set_output_config(uint32_t gpioport, enum gpio_output_type otype, + enum gpio_drive_strength drive, uint8_t gpios); +void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint8_t gpios); + +void gpio_toggle(uint32_t gpioport, uint8_t gpios); +void gpio_unlock_commit(uint32_t gpioport, uint8_t gpios); + +/* Let's keep these ones inlined. GPIO control should be fast */ +/** @ingroup gpio_control + * @{ */ + +/** + * \brief Get status of a Group of Pins (atomic) + * + * Reads the level of the given pins. Bit 0 of the returned data corresponds to + * GPIO0 level, bit 1 to GPIO1 level. and so on. Bits corresponding to masked + * pins (corresponding bit of gpios parameter set to zero) are returned as 0. + * + * This is an atomic operation. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified + * by OR'ing then together. + * + * @return The level of the GPIO port. The pins not specified in gpios are + * masked to zero. + */ +static inline uint8_t gpio_read(uint32_t gpioport, uint8_t gpios) +{ + return GPIO_DATA(gpioport)[gpios]; +} + +/** + * \brief Set level of a Group of Pins (atomic) + * + * Sets the level of the given pins. Bit 0 of the data parameter corresponds to + * GPIO0, bit 1 to GPIO1. and so on. Maskedpins (corresponding bit of gpios + * parameter set to zero) are returned not affected. + * + * This is an atomic operation. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified + * by OR'ing then together. + * @param[in] data Level to set pin to. Bit 0 of data corresponds to GPIO0, bit + * 1 to GPIO1. and so on. + */ +static inline void gpio_write(uint32_t gpioport, uint8_t gpios, uint8_t data) +{ + /* ipaddr[9:2] mask the bits to be set, hence the array index */ + GPIO_DATA(gpioport)[gpios] = data; +} + +/** + * \brief Set a Group of Pins (atomic) + * + * Set one or more pins of the given GPIO port. This is an atomic operation. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified + * by OR'ing then together. + */ +static inline void gpio_set(uint32_t gpioport, uint8_t gpios) +{ + gpio_write(gpioport, gpios, 0xff); +} + +/** + * \brief Clear a Group of Pins (atomic) + * + * Clear one or more pins of the given GPIO port. This is an atomic operation. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified + * by OR'ing then together. + */ +static inline void gpio_clear(uint32_t gpioport, uint8_t gpios) +{ + gpio_write(gpioport, gpios, 0); +} + +/** + * \brief Read level of all pins from a port (atomic) + * + * Read the current value of the given GPIO port. This is an atomic operation. + * + * This is functionally identical to @ref gpio_read (gpioport, GPIO_ALL). + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * + * @return The level of all the pins on the GPIO port. + */ +static inline uint8_t gpio_port_read(uint32_t gpioport) +{ + return gpio_read(gpioport, GPIO_ALL); +} + +/** + * \brief Set level of of all pins from a port (atomic) + * + * Set the level of all pins on the given GPIO port. This is an atomic + * operation. + * + * This is functionally identical to @ref gpio_write (gpioport, GPIO_ALL, data). + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified + * by OR'ing then together. + * @param[in] data Level to set pin to. Bit 0 of data corresponds to GPIO0, bit + * 1 to GPIO1. and so on. + */ +static inline void gpio_port_write(uint32_t gpioport, uint8_t data) +{ + gpio_write(gpioport, GPIO_ALL, data); +} +/** @} */ + +void gpio_configure_trigger(uint32_t gpioport, enum gpio_trigger trigger, + uint8_t gpios); +void gpio_enable_interrupts(uint32_t gpioport, uint8_t gpios); +void gpio_disable_interrupts(uint32_t gpioport, uint8_t gpios); + + +/* Let's keep these ones inlined. GPIO. They are designed to be used in ISRs */ +/** @ingroup gpio_irq + * @{ */ +/** \brief Determine if interrupt is generated by the given pin + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] srcpins source pin or group of pins to check. + */ +static inline bool gpio_is_interrupt_source(uint32_t gpioport, uint8_t srcpins) +{ + return GPIO_MIS(gpioport) & srcpins; +} + +/** + * \brief Mark interrupt as serviced + * + * After an interrupt is services, its flag must be cleared. If the flag is not + * cleared, then execution will jump back to the start of the ISR after the ISR + * returns. + * + * @param[in] gpioport GPIO block register address base @ref gpio_reg_base + * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified + * by OR'ing then together. + */ +static inline void gpio_clear_interrupt_flag(uint32_t gpioport, uint8_t gpios) +{ + GPIO_ICR(gpioport) |= gpios; +} + +/** @} */ +END_DECLS + +#endif + +/**@}*/ + diff --git a/libopencm3/include/libopencm3/lm4f/memorymap.h b/libopencm3/include/libopencm3/lm4f/memorymap.h new file mode 100644 index 0000000..9a20f6d --- /dev/null +++ b/libopencm3/include/libopencm3/lm4f/memorymap.h @@ -0,0 +1,71 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LM4F_MEMORYMAP_H +#define LM4F_MEMORYMAP_H + +#include + +/* --- LM4F specific peripheral definitions ----------------------------- */ + +#define GPIOA_APB_BASE (0x40004000U) +#define GPIOB_APB_BASE (0x40005000U) +#define GPIOC_APB_BASE (0x40006000U) +#define GPIOD_APB_BASE (0x40007000U) +#define GPIOE_APB_BASE (0x40024000U) +#define GPIOF_APB_BASE (0x40025000U) +#define GPIOG_APB_BASE (0x40026000U) +#define GPIOH_APB_BASE (0x40027000U) +#define GPIOJ_APB_BASE (0x4003D000U) + +#define GPIOA_BASE (0x40058000U) +#define GPIOB_BASE (0x40059000U) +#define GPIOC_BASE (0x4005A000U) +#define GPIOD_BASE (0x4005B000U) +#define GPIOE_BASE (0x4005C000U) +#define GPIOF_BASE (0x4005D000U) +#define GPIOG_BASE (0x4005E000U) +#define GPIOH_BASE (0x4005F000U) +#define GPIOJ_BASE (0x40060000U) +#define GPIOK_BASE (0x40061000U) +#define GPIOL_BASE (0x40062000U) +#define GPIOM_BASE (0x40063000U) +#define GPION_BASE (0x40064000U) +#define GPIOP_BASE (0x40065000U) +#define GPIOQ_BASE (0x40066000U) + +#define UART0_BASE (0x4000C000U) +#define UART1_BASE (0x4000D000U) +#define UART2_BASE (0x4000E000U) +#define UART3_BASE (0x4000F000U) +#define UART4_BASE (0x40010000U) +#define UART5_BASE (0x40011000U) +#define UART6_BASE (0x40012000U) +#define UART7_BASE (0x40013000U) + +#define SSI0_BASE (0x40008000U) +#define SSI1_BASE (0x40009000U) +#define SSI2_BASE (0x4000A000U) +#define SSI3_BASE (0x4000B000U) + +#define USB_BASE (0x40050000U) + +#define SYSCTL_BASE (0x400FE000U) + +#endif diff --git a/libopencm3/include/libopencm3/lm4f/rcc.h b/libopencm3/include/libopencm3/lm4f/rcc.h new file mode 100644 index 0000000..98a92cf --- /dev/null +++ b/libopencm3/include/libopencm3/lm4f/rcc.h @@ -0,0 +1,133 @@ +/** @defgroup rcc_defines Reset and Clock Control + +@brief Defined Constants and Types for the LM4F Reset and Clock Control + +@ingroup LM4Fxx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 +Alexandru Gagniuc + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Alexandru Gagniuc + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LM4F_RCC_H +#define LM4F_RCC_H + +/**@{*/ + +#include + +/** + * \brief Oscillator source values + * + * Possible values of the oscillator source. + */ +enum osc_src { + OSCSRC_MOSC = SYSCTL_RCC2_OSCSRC2_MOSC, + OSCSRC_PIOSC = SYSCTL_RCC2_OSCSRC2_PIOSC, + OSCSRC_PIOSC_D4 = SYSCTL_RCC2_OSCSRC2_PIOSC_D4, + OSCSRC_30K_INT = SYSCTL_RCC2_OSCSRC2_30K, + OSCSRC_32K_EXT = SYSCTL_RCC2_OSCSRC2_32K768, +}; + +/** + * \brief PWM clock divisor values + * + * Possible values of the binary divisor used to predivide the system clock down + * for use as the timing reference for the PWM module. + */ +enum pwm_clkdiv { + PWMDIV_2 = SYSCTL_RCC_PWMDIV_2, + PWMDIV_4 = SYSCTL_RCC_PWMDIV_4, + PWMDIV_8 = SYSCTL_RCC_PWMDIV_8, + PWMDIV_16 = SYSCTL_RCC_PWMDIV_16, + PWMDIV_32 = SYSCTL_RCC_PWMDIV_32, + PWMDIV_64 = SYSCTL_RCC_PWMDIV_64, +}; + +/** + * \brief Predefined crystal values + * + * Predefined crystal values for the XTAL field in SYSCTL_RCC. + * Using these predefined values in the XTAL field, the SYSCTL_PLLFREQ0 and + * SYSCTL_PLLFREQ1 are automatically adjusted in hardware to provide a PLL clock + * of 400MHz. + */ +enum xtal_t { + XTAL_4M = SYSCTL_RCC_XTAL_4M, + XTAL_4M_096 = SYSCTL_RCC_XTAL_4M_096, + XTAL_4M_9152 = SYSCTL_RCC_XTAL_4M_9152, + XTAL_5M = SYSCTL_RCC_XTAL_5M, + XTAL_5M_12 = SYSCTL_RCC_XTAL_5M_12, + XTAL_6M = SYSCTL_RCC_XTAL_6M, + XTAL_6M_144 = SYSCTL_RCC_XTAL_6M_144, + XTAL_7M_3728 = SYSCTL_RCC_XTAL_7M_3728, + XTAL_8M = SYSCTL_RCC_XTAL_8M, + XTAL_8M_192 = SYSCTL_RCC_XTAL_8M_192, + XTAL_10M = SYSCTL_RCC_XTAL_10M, + XTAL_12M = SYSCTL_RCC_XTAL_12M, + XTAL_12M_288 = SYSCTL_RCC_XTAL_12M_288, + XTAL_13M_56 = SYSCTL_RCC_XTAL_13M_56, + XTAL_14M_31818 = SYSCTL_RCC_XTAL_14M_31818, + XTAL_16M = SYSCTL_RCC_XTAL_16M, + XTAL_16M_384 = SYSCTL_RCC_XTAL_16M_384, + XTAL_18M = SYSCTL_RCC_XTAL_18M, + XTAL_20M = SYSCTL_RCC_XTAL_20M, + XTAL_24M = SYSCTL_RCC_XTAL_24M, + XTAL_25M = SYSCTL_RCC_XTAL_25M, +}; + +/* ============================================================================= + * Function prototypes + * ---------------------------------------------------------------------------*/ +BEGIN_DECLS +/* Low-level clock API */ +void rcc_configure_xtal(enum xtal_t xtal); +void rcc_disable_main_osc(void); +void rcc_disable_interal_osc(void); +void rcc_enable_main_osc(void); +void rcc_enable_interal_osc(void); +void rcc_enable_rcc2(void); +void rcc_pll_off(void); +void rcc_pll_on(void); +void rcc_set_osc_source(enum osc_src src); +void rcc_pll_bypass_disable(void); +void rcc_pll_bypass_enable(void); +void rcc_set_pll_divisor(uint8_t div400); +void rcc_set_pwm_divisor(enum pwm_clkdiv div); +void rcc_usb_pll_off(void); +void rcc_usb_pll_on(void); +void rcc_wait_for_pll_ready(void); +/* High-level clock API */ +void rcc_change_pll_divisor(uint8_t plldiv400); +uint32_t rcc_get_system_clock_frequency(void); +void rcc_sysclk_config(enum osc_src src, enum xtal_t xtal, uint8_t pll_div400); + +END_DECLS + +/**@}*/ + +#endif /* LM4F_RCC_H */ diff --git a/libopencm3/include/libopencm3/lm4f/ssi.h b/libopencm3/include/libopencm3/lm4f/ssi.h new file mode 100644 index 0000000..be9e4a8 --- /dev/null +++ b/libopencm3/include/libopencm3/lm4f/ssi.h @@ -0,0 +1,118 @@ +/** @defgroup ssi_defines Synchronous Serial Interface + * + * @brief Defined Constants and Types for the LM4F Synchronous Serial Interface (SSI) + * + * @ingroup LM4Fxx_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2014 + * Tiago Costa + * + * @date 11 June 2014 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2014 Tiago Costa + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LM4F_SSI_H +#define LM4F_SSI_H + +/**@{*/ + +#include +#include + +/* ============================================================================= + * Convenience macros + * ---------------------------------------------------------------------------*/ +/** @defgroup ssi_base SSI register base addresses + * @{*/ +#define SSI0 SSI0_BASE +#define SSI1 SSI1_BASE +#define SSI2 SSI2_BASE +#define SSI3 SSI3_BASE +/** @} */ + +/* ============================================================================= + * SSI registers + * ---------------------------------------------------------------------------*/ + +/* SSI Control 0 */ +#define SSI_CR0(port) MMIO32(port + 0x000) + +/* SSI Control 1 */ +#define SSI_CR1(port) MMIO32(port + 0x004) + +/* SSI Data */ +#define SSI_DR(port) MMIO32(port + 0x008) + +/* SSI Satus */ +#define SSI_SR(port) MMIO32(port + 0x00C) + +/* SSI Clock Prescale */ +#define SSI_CPSR(port) MMIO32(port + 0x010) + +/* SSI Interrupt Mask */ +#define SSI_IM(port) MMIO32(port + 0x014) + +/* SSI Raw Interrupt Status */ +#define SSI_RIS(port) MMIO32(port + 0x018) + +/* SSI Masked Interrupt Status */ +#define SSI_MIS(port) MMIO32(port + 0x01C) + +/* SSI Interrupt Clear */ +#define SSI_ICR(port) MMIO32(port + 0x020) + +/* SSI DMA Control */ +#define SSI_DMACTL(port) MMIO32(port + 0x024) + +/* SSI Clock Configuration */ +#define SSI_CC(port) MMIO32(port + 0xFC8) + +/* SSI Peripheral Identification */ +#define SSI_PERIPH_ID4(port) MMIO32(port + 0xFD0) +#define SSI_PERIPH_ID5(port) MMIO32(port + 0xFD4) +#define SSI_PERIPH_ID6(port) MMIO32(port + 0xFD8) +#define SSI_PERIPH_ID7(port) MMIO32(port + 0xFDC) +#define SSI_PERIPH_ID0(port) MMIO32(port + 0xFE0) +#define SSI_PERIPH_ID1(port) MMIO32(port + 0xFE4) +#define SSI_PERIPH_ID2(port) MMIO32(port + 0xFE8) +#define SSI_PERIPH_ID3(port) MMIO32(port + 0xFEC) + +/* SSI PrimeCell Identification */ +#define SSI_PCELL_ID0(port) MMIO32(port + 0xFF0) +#define SSI_PCELL_ID1(port) MMIO32(port + 0xFF4) +#define SSI_PCELL_ID2(port) MMIO32(port + 0xFF8) +#define SSI_PCELL_ID3(port) MMIO32(port + 0xFFC) + +/* ============================================================================= + * Function prototypes + * ---------------------------------------------------------------------------*/ +BEGIN_DECLS + +END_DECLS + +/**@}*/ + +#endif /* LM4F_SSI_H */ + \ No newline at end of file diff --git a/libopencm3/include/libopencm3/lm4f/systemcontrol.h b/libopencm3/include/libopencm3/lm4f/systemcontrol.h new file mode 100644 index 0000000..62e2231 --- /dev/null +++ b/libopencm3/include/libopencm3/lm4f/systemcontrol.h @@ -0,0 +1,743 @@ +/** @defgroup systemcontrol_defines System Control + +@brief Defined Constants and Types for the LM4F System Control + +@ingroup LM4Fxx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 +Alexandru Gagniuc + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Alexandru Gagniuc + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LM4F_SYSTEMCONTROL_H +#define LM4F_SYSTEMCONTROL_H + +/**@{*/ + +#include +#include + +#define SYSCTL_DID0 MMIO32(SYSCTL_BASE + 0x000) +#define SYSCTL_DID1 MMIO32(SYSCTL_BASE + 0x004) +#define SYSCTL_PBORCTL MMIO32(SYSCTL_BASE + 0x030) +#define SYSCTL_LDORCTL MMIO32(SYSCTL_BASE + 0x034) +#define SYSCTL_RIS MMIO32(SYSCTL_BASE + 0x050) +#define SYSCTL_IMC MMIO32(SYSCTL_BASE + 0x054) +#define SYSCTL_MISC MMIO32(SYSCTL_BASE + 0x058) +#define SYSCTL_RESC MMIO32(SYSCTL_BASE + 0x05C) +#define SYSCTL_RCC MMIO32(SYSCTL_BASE + 0x060) +#define SYSCTL_PLLCFG MMIO32(SYSCTL_BASE + 0x064) +#define SYSCTL_GPIOHBCTL MMIO32(SYSCTL_BASE + 0x06C) +#define SYSCTL_RCC2 MMIO32(SYSCTL_BASE + 0x070) +#define SYSCTL_MOSCCTL MMIO32(SYSCTL_BASE + 0x07C) +#define SYSCTL_DSLPCLKCFG MMIO32(SYSCTL_BASE + 0x144) +#define SYSCTL_SYSPROP MMIO32(SYSCTL_BASE + 0x14C) +#define SYSCTL_PIOSCCAL MMIO32(SYSCTL_BASE + 0x150) +#define SYSCTL_PIOSCSTAT MMIO32(SYSCTL_BASE + 0x154) +#define SYSCTL_PLLFREQ0 MMIO32(SYSCTL_BASE + 0x160) +#define SYSCTL_PLLFREQ1 MMIO32(SYSCTL_BASE + 0x164) +#define SYSCTL_PLLSTAT MMIO32(SYSCTL_BASE + 0x168) +/* Peripheral present */ +#define SYSCTL_PPWD MMIO32(SYSCTL_BASE + 0x300) +#define SYSCTL_PPTIMER MMIO32(SYSCTL_BASE + 0x304) +#define SYSCTL_PPGPIO MMIO32(SYSCTL_BASE + 0x308) +#define SYSCTL_PPDMA MMIO32(SYSCTL_BASE + 0x30C) +#define SYSCTL_PPHIB MMIO32(SYSCTL_BASE + 0x314) +#define SYSCTL_PPUART MMIO32(SYSCTL_BASE + 0x318) +#define SYSCTL_PPSSI MMIO32(SYSCTL_BASE + 0x31C) +#define SYSCTL_PPI2C MMIO32(SYSCTL_BASE + 0x320) +#define SYSCTL_PPUSB MMIO32(SYSCTL_BASE + 0x328) +#define SYSCTL_PPCAN MMIO32(SYSCTL_BASE + 0x334) +#define SYSCTL_PPADC MMIO32(SYSCTL_BASE + 0x338) +#define SYSCTL_PPACMP MMIO32(SYSCTL_BASE + 0x33C) +#define SYSCTL_PPPWM MMIO32(SYSCTL_BASE + 0x340) +#define SYSCTL_PPQEI MMIO32(SYSCTL_BASE + 0x344) +#define SYSCTL_PPEEPROM MMIO32(SYSCTL_BASE + 0x358) +#define SYSCTL_PPWTIMER MMIO32(SYSCTL_BASE + 0x35C) +/* Peripheral software reset */ +#define SYSCTL_SRWD MMIO32(SYSCTL_BASE + 0x500) +#define SYSCTL_SRTIMER MMIO32(SYSCTL_BASE + 0x504) +#define SYSCTL_SRGPIO MMIO32(SYSCTL_BASE + 0x508) +#define SYSCTL_SRDMA MMIO32(SYSCTL_BASE + 0x50C) +#define SYSCTL_SRHIB MMIO32(SYSCTL_BASE + 0x514) +#define SYSCTL_SRUART MMIO32(SYSCTL_BASE + 0x518) +#define SYSCTL_SRSSI MMIO32(SYSCTL_BASE + 0x51C) +#define SYSCTL_SRI2C MMIO32(SYSCTL_BASE + 0x520) +#define SYSCTL_SRUSB MMIO32(SYSCTL_BASE + 0x528) +#define SYSCTL_SRCAN MMIO32(SYSCTL_BASE + 0x534) +#define SYSCTL_SRADC MMIO32(SYSCTL_BASE + 0x538) +#define SYSCTL_SRACMP MMIO32(SYSCTL_BASE + 0x53C) +#define SYSCTL_SRPWM MMIO32(SYSCTL_BASE + 0x540) +#define SYSCTL_SRQEI MMIO32(SYSCTL_BASE + 0x544) +#define SYSCTL_SREEPROM MMIO32(SYSCTL_BASE + 0x558) +#define SYSCTL_SRWTIMER MMIO32(SYSCTL_BASE + 0x55C) +/* Peripheral run mode clock gating control */ +#define SYSCTL_RCGCWD MMIO32(SYSCTL_BASE + 0x600) +#define SYSCTL_RCGCTIMER MMIO32(SYSCTL_BASE + 0x604) +#define SYSCTL_RCGCGPIO MMIO32(SYSCTL_BASE + 0x608) +#define SYSCTL_RCGCDMA MMIO32(SYSCTL_BASE + 0x60C) +#define SYSCTL_RCGCHIB MMIO32(SYSCTL_BASE + 0x614) +#define SYSCTL_RCGCUART MMIO32(SYSCTL_BASE + 0x618) +#define SYSCTL_RCGCSSI MMIO32(SYSCTL_BASE + 0x61C) +#define SYSCTL_RCGCI2C MMIO32(SYSCTL_BASE + 0x620) +#define SYSCTL_RCGCUSB MMIO32(SYSCTL_BASE + 0x628) +#define SYSCTL_RCGCCAN MMIO32(SYSCTL_BASE + 0x634) +#define SYSCTL_RCGCADC MMIO32(SYSCTL_BASE + 0x638) +#define SYSCTL_RCGCACMP MMIO32(SYSCTL_BASE + 0x63C) +#define SYSCTL_RCGCPWM MMIO32(SYSCTL_BASE + 0x640) +#define SYSCTL_RCGCQEI MMIO32(SYSCTL_BASE + 0x644) +#define SYSCTL_RCGCEEPROM MMIO32(SYSCTL_BASE + 0x658) +#define SYSCTL_RCGCWTIMER MMIO32(SYSCTL_BASE + 0x65C) +/* Peripheral sleep mode clock gating control */ +#define SYSCTL_SCGCWD MMIO32(SYSCTL_BASE + 0x700) +#define SYSCTL_SCGCTIMER MMIO32(SYSCTL_BASE + 0x704) +#define SYSCTL_SCGCGPIO MMIO32(SYSCTL_BASE + 0x708) +#define SYSCTL_SCGCDMA MMIO32(SYSCTL_BASE + 0x70C) +#define SYSCTL_SCGCHIB MMIO32(SYSCTL_BASE + 0x714) +#define SYSCTL_SCGCUART MMIO32(SYSCTL_BASE + 0x718) +#define SYSCTL_SCGCSSI MMIO32(SYSCTL_BASE + 0x71C) +#define SYSCTL_SCGCI2C MMIO32(SYSCTL_BASE + 0x720) +#define SYSCTL_SCGCUSB MMIO32(SYSCTL_BASE + 0x728) +#define SYSCTL_SCGCCAN MMIO32(SYSCTL_BASE + 0x734) +#define SYSCTL_SCGCADC MMIO32(SYSCTL_BASE + 0x738) +#define SYSCTL_SCGCACMP MMIO32(SYSCTL_BASE + 0x73C) +#define SYSCTL_SCGCPWM MMIO32(SYSCTL_BASE + 0x740) +#define SYSCTL_SCGCQEI MMIO32(SYSCTL_BASE + 0x744) +#define SYSCTL_SCGCEEPROM MMIO32(SYSCTL_BASE + 0x758) +#define SYSCTL_SCGCWTIMER MMIO32(SYSCTL_BASE + 0x75C) +/* Peripheral deep-sleep mode clock gating control */ +#define SYSCTL_DCGCWD MMIO32(SYSCTL_BASE + 0x800) +#define SYSCTL_DCGCTIMER MMIO32(SYSCTL_BASE + 0x804) +#define SYSCTL_DCGCGPIO MMIO32(SYSCTL_BASE + 0x808) +#define SYSCTL_DCGCDMA MMIO32(SYSCTL_BASE + 0x80C) +#define SYSCTL_DCGCHIB MMIO32(SYSCTL_BASE + 0x814) +#define SYSCTL_DCGCUART MMIO32(SYSCTL_BASE + 0x818) +#define SYSCTL_DCGCSSI MMIO32(SYSCTL_BASE + 0x81C) +#define SYSCTL_DCGCI2C MMIO32(SYSCTL_BASE + 0x820) +#define SYSCTL_DCGCUSB MMIO32(SYSCTL_BASE + 0x828) +#define SYSCTL_DCGCCAN MMIO32(SYSCTL_BASE + 0x834) +#define SYSCTL_DCGCADC MMIO32(SYSCTL_BASE + 0x838) +#define SYSCTL_DCGCACMP MMIO32(SYSCTL_BASE + 0x83C) +#define SYSCTL_DCGCPWM MMIO32(SYSCTL_BASE + 0x840) +#define SYSCTL_DCGCQEI MMIO32(SYSCTL_BASE + 0x844) +#define SYSCTL_DCGCEEPROM MMIO32(SYSCTL_BASE + 0x858) +#define SYSCTL_DCGCWTIMER MMIO32(SYSCTL_BASE + 0x85C) +/* Peripheral ready */ +#define SYSCTL_PRWD MMIO32(SYSCTL_BASE + 0xA00) +#define SYSCTL_PRTIMER MMIO32(SYSCTL_BASE + 0xA04) +#define SYSCTL_PRGPIO MMIO32(SYSCTL_BASE + 0xA08) +#define SYSCTL_PRDMA MMIO32(SYSCTL_BASE + 0xA0C) +#define SYSCTL_PRHIB MMIO32(SYSCTL_BASE + 0xA14) +#define SYSCTL_PRUART MMIO32(SYSCTL_BASE + 0xA18) +#define SYSCTL_PRSSI MMIO32(SYSCTL_BASE + 0xA1C) +#define SYSCTL_PRI2C MMIO32(SYSCTL_BASE + 0xA20) +#define SYSCTL_PRUSB MMIO32(SYSCTL_BASE + 0xA28) +#define SYSCTL_PRCAN MMIO32(SYSCTL_BASE + 0xA34) +#define SYSCTL_PRADC MMIO32(SYSCTL_BASE + 0xA38) +#define SYSCTL_PRACMP MMIO32(SYSCTL_BASE + 0xA3C) +#define SYSCTL_PRPWM MMIO32(SYSCTL_BASE + 0xA40) +#define SYSCTL_PRQEI MMIO32(SYSCTL_BASE + 0xA44) +#define SYSCTL_PREEPROM MMIO32(SYSCTL_BASE + 0xA58) +#define SYSCTL_PRWTIMER MMIO32(SYSCTL_BASE + 0xA5C) +/* ============================================================================= + * System Control Legacy Registers + * ---------------------------------------------------------------------------*/ +#ifdef LM4F_LEGACY_SYSCTL +#define SYSCTL_DC0 MMIO32(SYSCTL_BASE + 0x008) +#define SYSCTL_DC1 MMIO32(SYSCTL_BASE + 0x010) +#define SYSCTL_DC2 MMIO32(SYSCTL_BASE + 0x014) +#define SYSCTL_DC3 MMIO32(SYSCTL_BASE + 0x018) +#define SYSCTL_DC4 MMIO32(SYSCTL_BASE + 0x01C) +#define SYSCTL_DC5 MMIO32(SYSCTL_BASE + 0x020) +#define SYSCTL_DC6 MMIO32(SYSCTL_BASE + 0x024) +#define SYSCTL_DC7 MMIO32(SYSCTL_BASE + 0x028) +#define SYSCTL_DC8 MMIO32(SYSCTL_BASE + 0x02C) +#define SYSCTL_SRCR0 MMIO32(SYSCTL_BASE + 0x040) +#define SYSCTL_SRCR1 MMIO32(SYSCTL_BASE + 0x044) +#define SYSCTL_SRCR2 MMIO32(SYSCTL_BASE + 0x048) +#define SYSCTL_RCGC0 MMIO32(SYSCTL_BASE + 0x100) +#define SYSCTL_RCGC1 MMIO32(SYSCTL_BASE + 0x104) +#define SYSCTL_RCGC2 MMIO32(SYSCTL_BASE + 0x108) +#define SYSCTL_SCGC0 MMIO32(SYSCTL_BASE + 0x110) +#define SYSCTL_SCGC1 MMIO32(SYSCTL_BASE + 0x114) +#define SYSCTL_SCGC2 MMIO32(SYSCTL_BASE + 0x118) +#define SYSCTL_DCGC0 MMIO32(SYSCTL_BASE + 0x120) +#define SYSCTL_DCGC1 MMIO32(SYSCTL_BASE + 0x124) +#define SYSCTL_DCGC2 MMIO32(SYSCTL_BASE + 0x128) +#define SYSCTL_DC9 MMIO32(SYSCTL_BASE + 0x190) +#define SYSCTL_NVMSTAT MMIO32(SYSCTL_BASE + 0x1A0) +#endif /* LM4F_LEGACY_SYSCTL */ + +/* ============================================================================= + * SYSCTL_DID0 values + * ---------------------------------------------------------------------------*/ +/** DID0 version */ +#define SYSCTL_DID0_VER_MASK (7 << 28) +/** Device class */ +#define SYSCTL_DID0_CLASS_MASK (0xFF << 16) +/** Major revision */ +#define SYSCTL_DID0_MAJOR_MASK (0xFF << 8) +/** Minor revision */ +#define SYSCTL_DID0_MAJOR_MASK (0xFF << 8) + +/* ============================================================================= + * SYSCTL_DID1 values + * ---------------------------------------------------------------------------*/ +/** DID1 version */ +#define SYSCTL_DID1_VER_MASK (0xF << 28) +/** Family */ +#define SYSCTL_DID1_FAM_MASK (0xF << 24) +/** Part number */ +#define SYSCTL_DID1_PARTNO_MASK (0xFF << 16) +/** Pin count */ +#define SYSCTL_DID1_PINCOUNT_MASK (0x7 << 13) +#define SYSCTL_DID1_PINCOUNT_28P (0x0 << 13) +#define SYSCTL_DID1_PINCOUNT_48P (0x1 << 13) +#define SYSCTL_DID1_PINCOUNT_100P (0x2 << 13) +#define SYSCTL_DID1_PINCOUNT_64P (0x3 << 13) +#define SYSCTL_DID1_PINCOUNT_144P (0x4 << 13) +#define SYSCTL_DID1_PINCOUNT_157P (0x5 << 13) +/** Temperature range */ +#define SYSCTL_DID1_TEMP_MASK (0x7 << 5) +#define SYSCTL_DID1_TEMP_0_70 (0x0 << 5) +#define SYSCTL_DID1_TEMP_M40_85 (0x1 << 5) +#define SYSCTL_DID1_TEMP_M40_105 (0x2 << 5) +/** Package */ +#define SYSCTL_DID1_PKG_MASK (0x3 << 5) +#define SYSCTL_DID1_PKG_SOIC (0x0 << 5) +#define SYSCTL_DID1_PKG_LQFP (0x1 << 5) +#define SYSCTL_DID1_PKG_BGA (0x2 << 5) +/** ROHS compliance */ +#define SYSCTL_DID1_ROHS (1 << 2) +/** Qualification status */ +#define SYSCTL_DID1_QUAL_MASK (3 << 0) + +/* ============================================================================= + * SYSCTL_PBORCTL values + * ---------------------------------------------------------------------------*/ +/** BOR interrupt or reset */ +#define SYSCTL_PBORCTL_BORIOR (1 << 1) + +/* ============================================================================= + * SYSCTL_RIS values + * ---------------------------------------------------------------------------*/ +/** MOSC Power Up Raw Interrupt Status */ +#define SYSCTL_RIS_MOSCPUPRIS (1 << 8) +/** USB PLL Lock Raw Interrupt Status */ +#define SYSCTL_RIS_USBPLLLRIS (1 << 7) +/** PLL Lock Raw Interrupt Status */ +#define SYSCTL_RIS_PLLLRIS (1 << 6) +/** Main Oscillator Failure Raw Interrupt Status */ +#define SYSCTL_RIS_MOFRIS (1 << 3) +/** Brown-Out Reset Raw Interrupt Status */ +#define SYSCTL_RIS_BORRIS (1 << 1) + +/* ============================================================================= + * SYSCTL_IMC values + * ---------------------------------------------------------------------------*/ +/** MOSC Power Up Raw Interrupt Status */ +#define SYSCTL_IMC_MOSCPUPIM (1 << 8) +/** USB PLL Lock Raw Interrupt Status */ +#define SYSCTL_IMC_USBPLLLIM (1 << 7) +/** PLL Lock Raw Interrupt Status */ +#define SYSCTL_IMC_PLLLIM (1 << 6) +/** Main Oscillator Failure Raw Interrupt Status */ +#define SYSCTL_IMC_MOFIM (1 << 3) +/** Brown-Out Reset Raw Interrupt Status */ +#define SYSCTL_IMC_BORIM (1 << 1) + +/* ============================================================================= + * SYSCTL_MISC values + * ---------------------------------------------------------------------------*/ +/** MOSC Power Up Raw Interrupt Status */ +#define SYSCTL_MISC_MOSCPUPMIS (1 << 8) +/** USB PLL Lock Raw Interrupt Status */ +#define SYSCTL_MISC_USBPLLLMIS (1 << 7) +/** PLL Lock Raw Interrupt Status */ +#define SYSCTL_MISC_PLLLMIS (1 << 6) +/** Main Oscillator Failure Raw Interrupt Status */ +#define SYSCTL_MISC_MOFMIS (1 << 3) +/** Brown-Out Reset Raw Interrupt Status */ +#define SYSCTL_MISC_BORMIS (1 << 1) + +/* ============================================================================= + * SYSCTL_RESC values + * ---------------------------------------------------------------------------*/ +/** MOSC Failure Reset */ +#define SYSCTL_RESC_MOSCFAIL (1 << 18) +/** Watchdog Timer 1 Reset */ +#define SYSCTL_RESC_WDT1 (1 << 5) +/** Software Reset */ +#define SYSCTL_RESC_SW (1 << 4) +/** Watchdog Timer 0 Reset */ +#define SYSCTL_RESC_WDT0 (1 << 3) +/** Brown-Out Reset */ +#define SYSCTL_RESC_BOR (1 << 2) +/** Power-On Reset */ +#define SYSCTL_RESC_POR (1 << 1) +/** External Reset */ +#define SYSCTL_RESC_EXT (1 << 0) + +/* ============================================================================= + * SYSCTL_RCC values + * ---------------------------------------------------------------------------*/ +/** Auto Clock Gating */ +#define SYSCTL_RCC_ACG (1 << 27) +/** System Clock Divisor */ +#define SYSCTL_RCC_SYSDIV_MASK (0xF << 23) +/** Enable System Clock Divider */ +#define SYSCTL_RCC_USESYSDIV (1 << 22) +/** Enable PWM Clock Divisor */ +#define SYSCTL_RCC_USEPWMDIV (1 << 20) +/** PWM Unit Clock Divisor */ +#define SYSCTL_RCC_PWMDIV_MASK (0xF << 17) +#define SYSCTL_RCC_PWMDIV_2 (0x0 << 17) +#define SYSCTL_RCC_PWMDIV_4 (0x1 << 17) +#define SYSCTL_RCC_PWMDIV_8 (0x2 << 17) +#define SYSCTL_RCC_PWMDIV_16 (0x3 << 17) +#define SYSCTL_RCC_PWMDIV_32 (0x4 << 17) +#define SYSCTL_RCC_PWMDIV_64 (0x5 << 17) +/** PLL Power Down */ +#define SYSCTL_RCC_PWRDN (1 << 13) +/** PLL Bypass */ +#define SYSCTL_RCC_BYPASS (1 << 11) +/** Crystal Value */ +#define SYSCTL_RCC_XTAL_MASK (0x1F << 6) +#define SYSCTL_RCC_XTAL_4M (0x06 << 6) +#define SYSCTL_RCC_XTAL_4M_096 (0x07 << 6) +#define SYSCTL_RCC_XTAL_4M_9152 (0x08 << 6) +#define SYSCTL_RCC_XTAL_5M (0x09 << 6) +#define SYSCTL_RCC_XTAL_5M_12 (0x0A << 6) +#define SYSCTL_RCC_XTAL_6M (0x0B << 6) +#define SYSCTL_RCC_XTAL_6M_144 (0x0C << 6) +#define SYSCTL_RCC_XTAL_7M_3728 (0x0D << 6) +#define SYSCTL_RCC_XTAL_8M (0x0E << 6) +#define SYSCTL_RCC_XTAL_8M_192 (0x0F << 6) +#define SYSCTL_RCC_XTAL_10M (0x10 << 6) +#define SYSCTL_RCC_XTAL_12M (0x11 << 6) +#define SYSCTL_RCC_XTAL_12M_288 (0x12 << 6) +#define SYSCTL_RCC_XTAL_13M_56 (0x13 << 6) +#define SYSCTL_RCC_XTAL_14M_31818 (0x14 << 6) +#define SYSCTL_RCC_XTAL_16M (0x15 << 6) +#define SYSCTL_RCC_XTAL_16M_384 (0x16 << 6) +#define SYSCTL_RCC_XTAL_18M (0x17 << 6) +#define SYSCTL_RCC_XTAL_20M (0x18 << 6) +#define SYSCTL_RCC_XTAL_24M (0x19 << 6) +#define SYSCTL_RCC_XTAL_25M (0x1A << 6) +/** Oscillator Source */ +#define SYSCTL_RCC_OSCSRC_MASK (0x3 << 4) +#define SYSCTL_RCC_OSCSRC_MOSC (0x0 << 4) +#define SYSCTL_RCC_OSCSRC_PIOSC (0x1 << 4) +#define SYSCTL_RCC_OSCSRC_PIOSC_D4 (0x2 << 4) +#define SYSCTL_RCC_OSCSRC_30K (0x3 << 4) +/** Precision Internal Oscillator Disable */ +#define SYSCTL_RCC_IOSCDIS (1 << 1) +/** Main Oscillator Disable */ +#define SYSCTL_RCC_MOSCDIS (1 << 0) + +/* ============================================================================= + * SYSCTL_GPIOHBCTL values + * ---------------------------------------------------------------------------*/ +#define SYSCTL_GPIOHBCTL_PORTQ (1 << 14) +#define SYSCTL_GPIOHBCTL_PORTP (1 << 13) +#define SYSCTL_GPIOHBCTL_PORTN (1 << 12) +#define SYSCTL_GPIOHBCTL_PORTM (1 << 11) +#define SYSCTL_GPIOHBCTL_PORTL (1 << 10) +#define SYSCTL_GPIOHBCTL_PORTK (1 << 9) +#define SYSCTL_GPIOHBCTL_PORTJ (1 << 8) +#define SYSCTL_GPIOHBCTL_PORTH (1 << 7) +#define SYSCTL_GPIOHBCTL_PORTG (1 << 6) +#define SYSCTL_GPIOHBCTL_PORTF (1 << 5) +#define SYSCTL_GPIOHBCTL_PORTE (1 << 4) +#define SYSCTL_GPIOHBCTL_PORTD (1 << 3) +#define SYSCTL_GPIOHBCTL_PORTC (1 << 2) +#define SYSCTL_GPIOHBCTL_PORTB (1 << 1) +#define SYSCTL_GPIOHBCTL_PORTA (1 << 0) + +/* ============================================================================= + * SYSCTL_RCC2 values + * ---------------------------------------------------------------------------*/ +/** RCC2 overides RCC */ +#define SYSCTL_RCC2_USERCC2 (1 << 31) +/** Divide PLL as 400 MHz vs. 200 MHz */ +#define SYSCTL_RCC2_DIV400 (1 << 30) +/** Auto Clock Gating */ +#define SYSCTL_RCC2_ACG (1 << 27) +/** System Clock Divisor 2 */ +#define SYSCTL_RCC2_SYSDIV2_MASK (0x3F << 23) +/** Additional LSB for SYSDIV2 */ +#define SYSCTL_RCC2_SYSDIV2LSB (1 << 22) +/** System clock divisor mask when RCC2_DIV400 is set */ +#define SYSCTL_RCC2_SYSDIV400_MASK (0x7F << 22) +/** Power-Down USB PLL */ +#define SYSCTL_RCC2_USBPWRDN (1 << 14) +/** PLL Power Down 2 */ +#define SYSCTL_RCC2_PWRDN2 (1 << 13) +/** PLL Bypass 2 */ +#define SYSCTL_RCC2_BYPASS2 (1 << 11) +/** Oscillator Source 2 */ +#define SYSCTL_RCC2_OSCSRC2_MASK (0x7 << 4) +#define SYSCTL_RCC2_OSCSRC2_MOSC (0x0 << 4) +#define SYSCTL_RCC2_OSCSRC2_PIOSC (0x1 << 4) +#define SYSCTL_RCC2_OSCSRC2_PIOSC_D4 (0x2 << 4) +#define SYSCTL_RCC2_OSCSRC2_30K (0x3 << 4) +#define SYSCTL_RCC2_OSCSRC2_32K768 (0x7 << 4) + +/* ============================================================================= + * SYSCTL_MOSCCTL values + * ---------------------------------------------------------------------------*/ +/** No Crystal Connected */ +#define SYSCTL_MOSCCTL_NOXTAL (1 << 2) +/** MOSC Failure Action */ +#define SYSCTL_MOSCCTL_MOSCIM (1 << 1) +/** Clock Validation for MOSC */ +#define SYSCTL_MOSCCTL_CVAL (1 << 0) + +/* ============================================================================= + * SYSCTL_DSLPCLKCFG values + * ---------------------------------------------------------------------------*/ +/*TODO*/ + +/* ============================================================================= + * SYSCTL_SYSPROP values + * ---------------------------------------------------------------------------*/ +/** FPU present */ +#define SYSCTL_SYSPROP_FPU (1 << 0) + +/* ============================================================================= + * SYSCTL_PIOSCCAL values + * ---------------------------------------------------------------------------*/ +/** Use User Trim Value */ +#define SYSCTL_PIOSCCAL_UTEN (1 << 31) +/** Start calibration */ +#define SYSCTL_PIOSCCAL_CAL (1 << 9) +/** Update trim */ +#define SYSCTL_PIOSCCAL_UPDATE (1 << 8) +/** User Trim Value */ +#define SYSCTL_PIOSCCAL_UT_MASK (0x7F << 0) + +/* ============================================================================= + * SYSCTL_PIOSCSTAT values + * ---------------------------------------------------------------------------*/ +/** Default Trim Value */ +#define SYSCTL_PIOSCSTAT_DT_MASK (0x7F << 16) +/** Calibration result */ +#define SYSCTL_PIOSCSTAT_RESULT_MASK (0x3 << 8) +/** Calibration Trim Value */ +#define SYSCTL_PIOSCSTAT_CT_MASK (0x7F << 0) +/* ============================================================================= + * SYSCTL_PLLFREQ0 values + * ---------------------------------------------------------------------------*/ +/** PLL M fractional value */ +#define SYSCTL_PLLFREQ0_MFRAC_MASK (0x3FF << 10) +/** PLL M integer value */ +#define SYSCTL_PLLFREQ0_MINT_MASK (0x3FF << 0) + +/* ============================================================================= + * SYSCTL_PLLFREQ1 values + * ---------------------------------------------------------------------------*/ +/** PLL Q value */ +#define SYSCTL_PLLFREQ1_Q_MASK (0x1F << 8) +/** PLL N value */ +#define SYSCTL_PLLFREQ1_N_MASK (0x1F << 0) + +/* ============================================================================= + * SYSCTL_PLLSTAT values + * ---------------------------------------------------------------------------*/ +/** PLL lock */ +#define SYSCTL_PLLSTAT_LOCK (1 << 0) + +/* ============================================================================= + * Convenience definitions for a readable API + * ---------------------------------------------------------------------------*/ +/** + * \brief Clock enable definitions + * + * The definitions are specified in the form + * 31:5 register offset from SYSCTL_BASE for the clock register + * 4:0 bit offset for the given peripheral + * + * The names have the form [clock_type]_[periph_type]_[periph_number] + * Where clock_type is + * RCC for run clock + * SCC for sleep clock + * DCC for deep-sleep clock + */ +enum lm4f_clken { + /* + * Run clock control + */ + RCC_WD0 = ((uint32_t)&SYSCTL_RCGCWD - SYSCTL_BASE) << 5, + RCC_WD1, + + RCC_TIMER0 = ((uint32_t)&SYSCTL_RCGCTIMER - SYSCTL_BASE) << 5, + RCC_TIMER1, + RCC_TIMER2, + RCC_TIMER3, + RCC_TIMER4, + RCC_TIMER5, + + RCC_GPIOA = ((uint32_t)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5, + RCC_GPIOB, + RCC_GPIOC, + RCC_GPIOD, + RCC_GPIOE, + RCC_GPIOF, + RCC_GPIOG, + RCC_GPIOH, + RCC_GPIOJ, + RCC_GPIOK, + RCC_GPIOL, + RCC_GPIOM, + RCC_GPION, + RCC_GPIOP, + RCC_GPIOQ, + + RCC_DMA = ((uint32_t)&SYSCTL_RCGCDMA - SYSCTL_BASE) << 5, + + RCC_HIB = ((uint32_t)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5, + + RCC_UART0 = ((uint32_t)&SYSCTL_RCGCUART - SYSCTL_BASE) << 5, + RCC_UART1, + RCC_UART2, + RCC_UART3, + RCC_UART4, + RCC_UART5, + RCC_UART6, + RCC_UART7, + + RCC_SSI0 = ((uint32_t)&SYSCTL_RCGCSSI - SYSCTL_BASE) << 5, + RCC_SSI1, + RCC_SSI2, + RCC_SSI3, + + RCC_I2C0 = ((uint32_t)&SYSCTL_RCGCI2C - SYSCTL_BASE) << 5, + RCC_I2C1, + RCC_I2C2, + RCC_I2C3, + RCC_I2C4, + RCC_I2C5, + + RCC_USB0 = ((uint32_t)&SYSCTL_RCGCUSB - SYSCTL_BASE) << 5, + + RCC_CAN0 = ((uint32_t)&SYSCTL_RCGCCAN - SYSCTL_BASE) << 5, + RCC_CAN1, + + RCC_ADC0 = ((uint32_t)&SYSCTL_RCGCADC - SYSCTL_BASE) << 5, + RCC_ADC1, + + RCC_ACMP0 = ((uint32_t)&SYSCTL_RCGCACMP - SYSCTL_BASE) << 5, + + RCC_PWM0 = ((uint32_t)&SYSCTL_RCGCPWM - SYSCTL_BASE) << 5, + RCC_PWM1, + + RCC_QEI0 = ((uint32_t)&SYSCTL_RCGCQEI - SYSCTL_BASE) << 5, + RCC_QEI1, + + RCC_EEPROM0 = ((uint32_t)&SYSCTL_RCGCEEPROM - SYSCTL_BASE) << 5, + + RCC_WTIMER0 = ((uint32_t)&SYSCTL_RCGCWTIMER - SYSCTL_BASE) << 5, + RCC_WTIMER1, + RCC_WTIMER2, + RCC_WTIMER3, + RCC_WTIMER4, + RCC_WTIMER5, + + + /* + * Sleep clock control + */ + SCC_WD0 = ((uint32_t)&SYSCTL_SCGCWD - SYSCTL_BASE) << 5, + SCC_WD1, + + SCC_TIMER0 = ((uint32_t)&SYSCTL_SCGCTIMER - SYSCTL_BASE) << 5, + SCC_TIMER1, + SCC_TIMER2, + SCC_TIMER3, + SCC_TIMER4, + SCC_TIMER5, + + SCC_GPIOA = ((uint32_t)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5, + SCC_GPIOB, + SCC_GPIOC, + SCC_GPIOD, + SCC_GPIOE, + SCC_GPIOF, + SCC_GPIOG, + SCC_GPIOH, + SCC_GPIOJ, + SCC_GPIOK, + SCC_GPIOL, + SCC_GPIOM, + SCC_GPION, + SCC_GPIOP, + SCC_GPIOQ, + + SCC_DMA = ((uint32_t)&SYSCTL_SCGCDMA - SYSCTL_BASE) << 5, + + SCC_HIB = ((uint32_t)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5, + + SCC_UART0 = ((uint32_t)&SYSCTL_SCGCUART - SYSCTL_BASE) << 5, + SCC_UART1, + SCC_UART2, + SCC_UART3, + SCC_UART4, + SCC_UART5, + SCC_UART6, + SCC_UART7, + + SCC_SSI0 = ((uint32_t)&SYSCTL_SCGCSSI - SYSCTL_BASE) << 5, + SCC_SSI1, + SCC_SSI2, + SCC_SSI3, + + SCC_I2C0 = ((uint32_t)&SYSCTL_SCGCI2C - SYSCTL_BASE) << 5, + SCC_I2C1, + SCC_I2C2, + SCC_I2C3, + SCC_I2C4, + SCC_I2C5, + + SCC_USB0 = ((uint32_t)&SYSCTL_SCGCUSB - SYSCTL_BASE) << 5, + + SCC_CAN0 = ((uint32_t)&SYSCTL_SCGCCAN - SYSCTL_BASE) << 5, + SCC_CAN1, + + SCC_ADC0 = ((uint32_t)&SYSCTL_SCGCADC - SYSCTL_BASE) << 5, + SCC_ADC1, + + SCC_ACMP0 = ((uint32_t)&SYSCTL_SCGCACMP - SYSCTL_BASE) << 5, + + SCC_PWM0 = ((uint32_t)&SYSCTL_SCGCPWM - SYSCTL_BASE) << 5, + SCC_PWM1, + + SCC_QEI0 = ((uint32_t)&SYSCTL_SCGCQEI - SYSCTL_BASE) << 5, + SCC_QEI1, + + SCC_EEPROM0 = ((uint32_t)&SYSCTL_SCGCEEPROM - SYSCTL_BASE) << 5, + + SCC_WTIMER0 = ((uint32_t)&SYSCTL_SCGCWTIMER - SYSCTL_BASE) << 5, + SCC_WTIMER1, + SCC_WTIMER2, + SCC_WTIMER3, + SCC_WTIMER4, + SCC_WTIMER5, + + /* + * Deep-sleep clock control + */ + DCC_WD0 = ((uint32_t)&SYSCTL_DCGCWD - SYSCTL_BASE) << 5, + DCC_WD1, + + DCC_TIMER0 = ((uint32_t)&SYSCTL_DCGCTIMER - SYSCTL_BASE) << 5, + DCC_TIMER1, + DCC_TIMER2, + DCC_TIMER3, + DCC_TIMER4, + DCC_TIMER5, + + DCC_GPIOA = ((uint32_t)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5, + DCC_GPIOB, + DCC_GPIOC, + DCC_GPIOD, + DCC_GPIOE, + DCC_GPIOF, + DCC_GPIOG, + DCC_GPIOH, + DCC_GPIOJ, + DCC_GPIOK, + DCC_GPIOL, + DCC_GPIOM, + DCC_GPION, + DCC_GPIOP, + DCC_GPIOQ, + + DCC_DMA = ((uint32_t)&SYSCTL_DCGCDMA - SYSCTL_BASE) << 5, + + DCC_HIB = ((uint32_t)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5, + + DCC_UART0 = ((uint32_t)&SYSCTL_DCGCUART - SYSCTL_BASE) << 5, + DCC_UART1, + DCC_UART2, + DCC_UART3, + DCC_UART4, + DCC_UART5, + DCC_UART6, + DCC_UART7, + + DCC_SSI0 = ((uint32_t)&SYSCTL_DCGCSSI - SYSCTL_BASE) << 5, + DCC_SSI1, + DCC_SSI2, + DCC_SSI3, + + DCC_I2C0 = ((uint32_t)&SYSCTL_DCGCI2C - SYSCTL_BASE) << 5, + DCC_I2C1, + DCC_I2C2, + DCC_I2C3, + DCC_I2C4, + DCC_I2C5, + + DCC_USB0 = ((uint32_t)&SYSCTL_DCGCUSB - SYSCTL_BASE) << 5, + + DCC_CAN0 = ((uint32_t)&SYSCTL_DCGCCAN - SYSCTL_BASE) << 5, + DCC_CAN1, + + DCC_ADC0 = ((uint32_t)&SYSCTL_DCGCADC - SYSCTL_BASE) << 5, + DCC_ADC1, + + DCC_ACMP0 = ((uint32_t)&SYSCTL_DCGCACMP - SYSCTL_BASE) << 5, + + DCC_PWM0 = ((uint32_t)&SYSCTL_DCGCPWM - SYSCTL_BASE) << 5, + DCC_PWM1, + + DCC_QEI0 = ((uint32_t)&SYSCTL_DCGCQEI - SYSCTL_BASE) << 5, + DCC_QEI1, + + DCC_EEPROM0 = ((uint32_t)&SYSCTL_DCGCEEPROM - SYSCTL_BASE) << 5, + + DCC_WTIMER0 = ((uint32_t)&SYSCTL_DCGCWTIMER - SYSCTL_BASE) << 5, + DCC_WTIMER1, + DCC_WTIMER2, + DCC_WTIMER3, + DCC_WTIMER4, + DCC_WTIMER5, + +}; + +/* ============================================================================ + * Function prototypes + * --------------------------------------------------------------------------*/ +BEGIN_DECLS + +void periph_clock_enable(enum lm4f_clken periph); +void periph_clock_disable(enum lm4f_clken periph); + +END_DECLS + +/**@}*/ + +#endif /* LM4F_SYSTEMCONTROL_H */ + diff --git a/libopencm3/include/libopencm3/lm4f/uart.h b/libopencm3/include/libopencm3/lm4f/uart.h new file mode 100644 index 0000000..5bd7e37 --- /dev/null +++ b/libopencm3/include/libopencm3/lm4f/uart.h @@ -0,0 +1,550 @@ +/** @defgroup uart_defines UART Control + * + * @brief Defined Constants and Types for the LM4F UART Control + * + * @ingroup LM4Fxx_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2013 + * Alexandru Gagniuc + * + * @date 07 May 2013 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Alexandru Gagniuc + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_LM4F_UART_H +#define LIBOPENCM3_LM4F_UART_H + +/**@{*/ + +#include +#include + +/* ============================================================================= + * Convenience macros + * ---------------------------------------------------------------------------*/ +/** @defgroup uart_reg_base UART register base addresses + * @{*/ +#define UART0 UART0_BASE +#define UART1 UART1_BASE +#define UART2 UART2_BASE +#define UART3 UART3_BASE +#define UART4 UART4_BASE +#define UART5 UART5_BASE +#define UART6 UART6_BASE +#define UART7 UART7_BASE +/** @} */ + +/* ============================================================================= + * UART registers + * ---------------------------------------------------------------------------*/ + +/* UART data register */ +#define UART_DR(uart_base) MMIO32(uart_base + 0x00) + +/* UART Receive Status/Error Clear register */ +#define UART_RSR(uart_base) MMIO32(uart_base + 0x04) +#define UART_ECR(uart_base) MMIO32(uart_base + 0x04) + +/* UART Flag register */ +#define UART_FR(uart_base) MMIO32(uart_base + 0x18) + +/* UART IrDA Low-Power register */ +#define UART_ILPR(uart_base) MMIO32(uart_base + 0x20) + +/* UART Integer baudrate divisor */ +#define UART_IBRD(uart_base) MMIO32(uart_base + 0x24) + +/* UART Fractional baudrate divisor */ +#define UART_FBRD(uart_base) MMIO32(uart_base + 0x28) + +/* UART Line control */ +#define UART_LCRH(uart_base) MMIO32(uart_base + 0x2C) + +/* UART Control */ +#define UART_CTL(uart_base) MMIO32(uart_base + 0x30) + +/* UART Interrupt FIFO level select */ +#define UART_IFLS(uart_base) MMIO32(uart_base + 0x34) + +/* UART Interrupt mask */ +#define UART_IM(uart_base) MMIO32(uart_base + 0x38) + +/* UART Raw interrupt status */ +#define UART_RIS(uart_base) MMIO32(uart_base + 0x3C) + +/* UART Masked Interrupt status */ +#define UART_MIS(uart_base) MMIO32(uart_base + 0x40) + +/* UART Interrupt Clear */ +#define UART_ICR(uart_base) MMIO32(uart_base + 0x44) + +/* UART DMA control */ +#define UART_DMACTL(uart_base) MMIO32(uart_base + 0x48) + +/* UART LIN control */ +#define UART_LCTL(uart_base) MMIO32(uart_base + 0x90) + +/* UART LIN snap shot */ +#define UART_LSS(uart_base) MMIO32(uart_base + 0x94) + +/* UART LIN timer */ +#define UART_LTIM(uart_base) MMIO32(uart_base + 0x98) + +/* UART 9-Bit self address */ +#define UART_9BITADDR(uart_base) MMIO32(uart_base + 0xA4) + +/* UART 9-Bit self address mask */ +#define UART_9BITAMASK(uart_base) MMIO32(uart_base + 0xA8) + +/* UART Peripheral properties */ +#define UART_PP(uart_base) MMIO32(uart_base + 0xFC0) + +/* UART Clock configuration */ +#define UART_CC(uart_base) MMIO32(uart_base + 0xFC8) + +/* UART Peripheral Identification 4 */ +#define UART_PERIPH_ID4(uart_base) MMIO32(uart_base + 0xFD0) + +/* UART Peripheral Identification 5 */ +#define UART_PERIPH_ID5(uart_base) MMIO32(uart_base + 0xFD4) + +/* UART Peripheral Identification 6 */ +#define UART_PERIPH_ID6(uart_base) MMIO32(uart_base + 0xFD8) + +/* UART Peripheral Identification 7 */ +#define UART_PERIPH_ID7(uart_base) MMIO32(uart_base + 0xFDC) + +/* UART Peripheral Identification 0 */ +#define UART_PERIPH_ID0(uart_base) MMIO32(uart_base + 0xFE0) + +/* UART Peripheral Identification 1 */ +#define UART_PERIPH_ID1(uart_base) MMIO32(uart_base + 0xFE4) + +/* UART Peripheral Identification 2 */ +#define UART_PERIPH_ID2(uart_base) MMIO32(uart_base + 0xFE8) + +/* UART Peripheral Identification 3 */ +#define UART_PERIPH_ID3(uart_base) MMIO32(uart_base + 0xFEC) + +/* UART PrimeCell Identification 0 */ +#define UART_PCELL_ID0(uart_base) MMIO32(uart_base + 0xFF0) + +/* UART PrimeCell Identification 1 */ +#define UART_PCELL_ID1(uart_base) MMIO32(uart_base + 0xFF4) + +/* UART PrimeCell Identification 2 */ +#define UART_PCELL_ID2(uart_base) MMIO32(uart_base + 0xFF8) + +/* UART PrimeCell Identification 3 */ +#define UART_PCELL_ID3(uart_base) MMIO32(uart_base + 0xFFC) + + +/* ============================================================================= + * UART_DR values + * ---------------------------------------------------------------------------*/ +/** Overrun Error */ +#define UART_DR_OE (1 << 11) +/** Break Error */ +#define UART_DR_BE (1 << 10) +/** Parity Error */ +#define UART_DR_PE (1 << 9) +/** Framing Error */ +#define UART_DR_FE (1 << 8) +/** Data transmitted or received */ +#define UART_DR_DATA_MASK (0xFF << 0) + +/* ============================================================================= + * Readonly UART_RSR values + * ---------------------------------------------------------------------------*/ +/** Overrun Error */ +#define UART_RSR_OE (1 << 3) +/** Break Error */ +#define UART_RSR_BE (1 << 2) +/** Parity Error */ +#define UART_RSR_PE (1 << 1) +/** Framing Error */ +#define UART_RSR_FE (1 << 0) + +/* ============================================================================= + * UART_FR values + * ---------------------------------------------------------------------------*/ +/** Tx FIFO empty */ +#define UART_FR_TXFE (1 << 7) +/** Rx FIFO full */ +#define UART_FR_RXFF (1 << 6) +/** Tx FIFO full */ +#define UART_FR_TXFF (1 << 5) +/** Rx FIFO empty */ +#define UART_FR_RXFE (1 << 4) +/** UART Busy */ +#define UART_FR_BUSY (1 << 3) +/** Clear To Send */ +#define UART_FR_CTS (1 << 0) + +/* ============================================================================= + * UART_LCRH values + * ---------------------------------------------------------------------------*/ +/** Stick parity select */ +#define UART_LCRH_SPS (1 << 7) +/** Word length */ +#define UART_LCRH_WLEN_MASK (3 << 5) +#define UART_LCRH_WLEN_5 (0 << 5) +#define UART_LCRH_WLEN_6 (1 << 5) +#define UART_LCRH_WLEN_7 (2 << 5) +#define UART_LCRH_WLEN_8 (3 << 5) +/** Enable FIFOs */ +#define UART_LCRH_FEN (1 << 4) +/** Two stop bits select */ +#define UART_LCRH_STP2 (1 << 3) +/** Even parity select */ +#define UART_LCRH_EPS (1 << 2) +/** Parity enable */ +#define UART_LCRH_PEN (1 << 1) +/** Send break */ +#define UART_LCRH_BRK (1 << 0) + +/* ============================================================================= + * UART_CTL values + * ---------------------------------------------------------------------------*/ +/** Enable Clear To Send */ +#define UART_CTL_CTSEN (1 << 15) +/** Enable Request To Send */ +#define UART_CTL_RTSEN (1 << 14) +/** Request To Send */ +#define UART_CTL_RTS (1 << 11) +/** Data terminal ready */ +#define UART_CTL_DTR (1 << 10) +/** Rx Enable */ +#define UART_CTL_RXE (1 << 9) +/** Tx Enable */ +#define UART_CTL_TXE (1 << 8) +/** Loop back enable */ +#define UART_CTL_LBE (1 << 7) +/** LIN mode enable */ +#define UART_CTL_LIN (1 << 6) +/** High speed Enable */ +#define UART_CTL_HSE (1 << 5) +/** End of transmission */ +#define UART_CTL_EOT (1 << 4) +/** ISO 7816 Smart Card support */ +#define UART_CTL_SMART (1 << 3) +/** SIR low-power mode */ +#define UART_CTL_SIRLIP (1 << 2) +/** SIR enable */ +#define UART_CTL_SIREN (1 << 1) +/** UART enable */ +#define UART_CTL_UARTEN (1 << 0) + +/* ============================================================================= + * UART_IFLS values + * ---------------------------------------------------------------------------*/ +/** UART Rx interrupt FIFO level select */ +#define UART_IFLS_RXIFLSEL_MASK (7 << 3) +#define UART_IFLS_RXIFLSEL_1_8 (0 << 3) +#define UART_IFLS_RXIFLSEL_1_4 (1 << 3) +#define UART_IFLS_RXIFLSEL_1_2 (2 << 3) +#define UART_IFLS_RXIFLSEL_3_4 (3 << 3) +#define UART_IFLS_RXIFLSEL_7_8 (4 << 3) +/** UART Tx interrupt FIFO level select */ +#define UART_IFLS_TXIFLSEL_MASK (7 << 0) +#define UART_IFLS_TXIFLSEL_7_8 (0 << 0) +#define UART_IFLS_TXIFLSEL_3_4 (1 << 0) +#define UART_IFLS_TXIFLSEL_1_2 (2 << 0) +#define UART_IFLS_TXIFLSEL_1_4 (3 << 0) +#define UART_IFLS_TXIFLSEL_1_8 (4 << 0) + +/* ============================================================================= + * UART interrupt mask values + * + * These are interchangeable across UART_IM, UART_RIS, UART_MIS, and UART_ICR + * registers. + * ---------------------------------------------------------------------------*/ +/** LIN mode edge 5 interrupt mask */ +#define UART_IM_LME5IM (1 << 15) +/** LIN mode edge 1 interrupt mask */ +#define UART_IM_LME1IM (1 << 14) +/** LIN mode sync break interrupt mask */ +#define UART_IM_LMSBIM (1 << 13) +/** 9-bit mode interrupt mask */ +#define UART_IM_9BITIM (1 << 12) +/** Overrun error interrupt mask */ +#define UART_IM_OEIM (1 << 10) +/** Break error interrupt mask */ +#define UART_IM_BEIM (1 << 9) +/** Parity error interrupt mask */ +#define UART_IM_PEIM (1 << 8) +/** Framing error interrupt mask */ +#define UART_IM_FEIM (1 << 7) +/** Receive time-out interrupt mask */ +#define UART_IM_RTIM (1 << 6) +/** Transmit interrupt mask */ +#define UART_IM_TXIM (1 << 5) +/** Receive interrupt mask */ +#define UART_IM_RXIM (1 << 4) +/** Data Set Ready modem interrupt mask */ +#define UART_IM_DSRIM (1 << 3) +/** Data Carrier Detect modem interrupt mask */ +#define UART_IM_DCDIM (1 << 2) +/** Clear To Send modem interrupt mask */ +#define UART_IM_CTSIM (1 << 1) +/** Ring Indicator modem interrupt mask */ +#define UART_IM_RIIM (1 << 0) + +/* ============================================================================= + * UART_DMACTL values + * ---------------------------------------------------------------------------*/ +/** DMA on error */ +#define UART_DMACTL_DMAERR (1 << 2) +/** Transmit DMA enable */ +#define UART_DMACTL_TXDMAE (1 << 1) +/** Recieve DMA enable */ +#define UART_DMACTL_RXDMAE (1 << 0) + +/* ============================================================================= + * UART_LCTL values + * ---------------------------------------------------------------------------*/ +/** Sync break length */ +#define UART_LCTL_BLEN_MASK (3 << 4) +#define UART_LCTL_BLEN_16T (3 << 4) +#define UART_LCTL_BLEN_15T (2 << 4) +#define UART_LCTL_BLEN_14T (1 << 4) +#define UART_LCTL_BLEN_13T (0 << 4) +/** LIN master enable */ +#define UART_LCTL_MASTER (1 << 0) + +/* ============================================================================= + * UART_9BITADDR values + * ---------------------------------------------------------------------------*/ +/** Enable 9-bit mode */ +#define UART_UART_9BITADDR_9BITEN (1 << 15) +/** Self-address for 9-bit mode */ +#define UART_UART_9BITADDR_ADDR_MASK (0xFF << 0) + +/* ============================================================================= + * UART_PP values + * ---------------------------------------------------------------------------*/ +/** 9-bit support */ +#define UART_UART_PP_NB (1 << 1) +/** Smart Card support */ +#define UART_UART_PP_SC (1 << 0) + +/* ============================================================================= + * UART_CC values + * ---------------------------------------------------------------------------*/ +/** UART baud clock source */ +#define UART_CC_CS_MASK (0xF << 0) +#define UART_CC_CS_SYSCLK (0x0 << 0) +#define UART_CC_CS_PIOSC (0x5 << 0) + +/* ============================================================================= + * Convenience enums + * ---------------------------------------------------------------------------*/ +enum uart_parity { + UART_PARITY_NONE, + UART_PARITY_ODD, + UART_PARITY_EVEN, + UART_PARITY_STICK_0, + UART_PARITY_STICK_1, +}; + +enum uart_flowctl { + UART_FLOWCTL_NONE, + UART_FLOWCTL_RTS, + UART_FLOWCTL_CTS, + UART_FLOWCTL_RTS_CTS, +}; + +/** + * \brief UART interrupt masks + * + * These masks can be OR'ed together to specify more than one interrupt. For + * example, (UART_INT_TXIM | UART_INT_TXIM) specifies both Rx and Tx Interrupt. + */ +enum uart_interrupt_flag { + + UART_INT_LME5 = UART_IM_LME5IM, + UART_INT_LME1 = UART_IM_LME1IM, + UART_INT_LMSB = UART_IM_LMSBIM, + UART_INT_9BIT = UART_IM_9BITIM, + UART_INT_OE = UART_IM_OEIM, + UART_INT_BE = UART_IM_BEIM, + UART_INT_PE = UART_IM_PEIM, + UART_INT_FE = UART_IM_FEIM, + UART_INT_RT = UART_IM_RTIM, + UART_INT_TX = UART_IM_TXIM, + UART_INT_RX = UART_IM_RXIM, + UART_INT_DSR = UART_IM_DSRIM, + UART_INT_DCD = UART_IM_DCDIM, + UART_INT_CTS = UART_IM_CTSIM, + UART_INT_RI = UART_IM_RIIM, +}; + +/** + * \brief UART RX FIFO interrupt trigger levels + * + * The levels indicate how full the FIFO should be before an interrupt is + * generated. UART_FIFO_RX_TRIG_3_4 means that an interrupt is triggered when + * the FIFO is 3/4 full. As the FIFO is 8 elements deep, 1/8 is equal to being + * triggered by a single character. + */ +enum uart_fifo_rx_trigger_level { + UART_FIFO_RX_TRIG_1_8 = UART_IFLS_RXIFLSEL_1_8, + UART_FIFO_RX_TRIG_1_4 = UART_IFLS_RXIFLSEL_1_4, + UART_FIFO_RX_TRIG_1_2 = UART_IFLS_RXIFLSEL_1_2, + UART_FIFO_RX_TRIG_3_4 = UART_IFLS_RXIFLSEL_3_4, + UART_FIFO_RX_TRIG_7_8 = UART_IFLS_RXIFLSEL_7_8 +}; + +/** + * \brief UART TX FIFO interrupt trigger levels + * + * The levels indicate how empty the FIFO should be before an interrupt is + * generated. Note that this indicates the emptiness of the FIFO and not the + * fullness. This is somewhat confusing, but it follows the wording of the + * LM4F120H5QR datasheet. + * + * UART_FIFO_TX_TRIG_3_4 means that an interrupt is triggered when the FIFO is + * 3/4 empty. As the FIFO is 8 elements deep, 7/8 is equal to being triggered + * by a single character. + */ +enum uart_fifo_tx_trigger_level { + UART_FIFO_TX_TRIG_7_8 = UART_IFLS_TXIFLSEL_7_8, + UART_FIFO_TX_TRIG_3_4 = UART_IFLS_TXIFLSEL_3_4, + UART_FIFO_TX_TRIG_1_2 = UART_IFLS_TXIFLSEL_1_2, + UART_FIFO_TX_TRIG_1_4 = UART_IFLS_TXIFLSEL_1_4, + UART_FIFO_TX_TRIG_1_8 = UART_IFLS_TXIFLSEL_1_8 +}; + +/* ============================================================================= + * Function prototypes + * ---------------------------------------------------------------------------*/ +BEGIN_DECLS + +void uart_set_baudrate(uint32_t uart, uint32_t baud); +void uart_set_databits(uint32_t uart, uint8_t databits); +void uart_set_stopbits(uint32_t uart, uint8_t stopbits); +void uart_set_parity(uint32_t uart, enum uart_parity parity); +void uart_set_mode(uint32_t uart, uint32_t mode); +void uart_set_flow_control(uint32_t uart, enum uart_flowctl flow); +void uart_enable(uint32_t uart); +void uart_disable(uint32_t uart); +void uart_clock_from_piosc(uint32_t uart); +void uart_clock_from_sysclk(uint32_t uart); + +void uart_send(uint32_t uart, uint16_t data); +uint16_t uart_recv(uint32_t uart); +void uart_wait_send_ready(uint32_t uart); +void uart_wait_recv_ready(uint32_t uart); +void uart_send_blocking(uint32_t uart, uint16_t data); +uint16_t uart_recv_blocking(uint32_t uart); + +void uart_enable_rx_dma(uint32_t uart); +void uart_disable_rx_dma(uint32_t uart); +void uart_enable_tx_dma(uint32_t uart); +void uart_disable_tx_dma(uint32_t uart); + +void uart_enable_fifo(uint32_t uart); +void uart_disable_fifo(uint32_t uart); +void uart_set_fifo_trigger_levels(uint32_t uart, + enum uart_fifo_rx_trigger_level rx_level, + enum uart_fifo_tx_trigger_level tx_level); + +/* We inline FIFO full/empty checks as they are intended to be called from ISRs + * */ +/** @ingroup uart_fifo + * @{ + * \brief Determine if the TX fifo is full + * + * @param[in] uart UART block register address base @ref uart_reg_base + */ +static inline +bool uart_is_tx_fifo_full(uint32_t uart) +{ + return UART_FR(uart) & UART_FR_TXFF; +} + + +/** + * \brief Determine if the TX fifo is empty + * + * @param[in] uart UART block register address base @ref uart_reg_base + */ +static inline +bool uart_is_tx_fifo_empty(uint32_t uart) +{ + return UART_FR(uart) & UART_FR_TXFE; +} + +/** + * \brief Determine if the RX fifo is full + * + * @param[in] uart UART block register address base @ref uart_reg_base + */ +static inline +bool uart_is_rx_fifo_full(uint32_t uart) +{ + return UART_FR(uart) & UART_FR_RXFF; +} + +/** + * \brief Determine if the RX fifo is empty + * + * @param[in] uart UART block register address base @ref uart_reg_base + */ +static inline +bool uart_is_rx_fifo_empty(uint32_t uart) +{ + return UART_FR(uart) & UART_FR_RXFE; +} +/**@}*/ + +void uart_enable_interrupts(uint32_t uart, enum uart_interrupt_flag ints); +void uart_disable_interrupts(uint32_t uart, enum uart_interrupt_flag ints); +void uart_enable_rx_interrupt(uint32_t uart); +void uart_disable_rx_interrupt(uint32_t uart); +void uart_enable_tx_interrupt(uint32_t uart); +void uart_disable_tx_interrupt(uint32_t uart); +void uart_clear_interrupt_flag(uint32_t uart, enum uart_interrupt_flag ints); + +/* Let's keep this one inlined. It's designed to be used in ISRs */ +/** @ingroup uart_irq + * @{ + * \brief Determine if interrupt is generated by the given source + * + * @param[in] uart UART block register address base @ref uart_reg_base + * @param[in] source source to check. + */ +static inline +bool uart_is_interrupt_source(uint32_t uart, enum uart_interrupt_flag source) +{ + return UART_MIS(uart) & source; +} +/**@}*/ + +END_DECLS + +/**@}*/ + +#endif /* LIBOPENCM3_LM4F_UART_H */ diff --git a/libopencm3/include/libopencm3/lm4f/usb.h b/libopencm3/include/libopencm3/lm4f/usb.h new file mode 100644 index 0000000..f22d799 --- /dev/null +++ b/libopencm3/include/libopencm3/lm4f/usb.h @@ -0,0 +1,422 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Alexandru Gagniuc + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/** @defgroup usb_defines USB Controller + * + * @brief Defined Constants and Types for the LM4F USB Controller + * + * @ingroup LM4Fxx_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2013 Alexandru Gagniuc + * + * @date 15 May 2013 + * + * LGPL License Terms @ref lgpl_license + */ + + +#ifndef LIBOPENCM3_LM4F_USB_H +#define LIBOPENCM3_LM4F_USB_H + +/**@{*/ + +#include +#include + +/* ============================================================================ + * USB registers + * --------------------------------------------------------------------------*/ + +/* USB Device Functional Address */ +#define USB_FADDR MMIO8(USB_BASE + 0x00) + +/* USB Power */ +#define USB_POWER MMIO8(USB_BASE + 0x01) + +/* USB Transmit Interrupt Status */ +#define USB_TXIS MMIO16(USB_BASE + 0x02) + +/* USB Receive Interrupt Status */ +#define USB_RXIS MMIO16(USB_BASE + 0x04) + +/* USB Transmit Interrupt Enable */ +#define USB_TXIE MMIO16(USB_BASE + 0x06) + +/* USB Receive Interrupt Enable */ +#define USB_RXIE MMIO16(USB_BASE + 0x08) + +/* USB General Interrupt Status */ +#define USB_IS MMIO8(USB_BASE + 0x0A) + +/* USB Interrupt Enable */ +#define USB_IE MMIO8(USB_BASE + 0x0B) + +/* USB Frame Value */ +#define USB_FRAME MMIO16(USB_BASE + 0x0C) + +/* USB Endpoint Index */ +#define USB_EPIDX MMIO8(USB_BASE + 0x0E) + +/* USB Test Mode */ +#define USB_TEST MMIO8(USB_BASE + 0x0F) + +/* USB FIFO Endpoint [0-7] */ +#define USB_FIFO8(n) MMIO8(USB_BASE + 0x20 + n*0x04) +#define USB_FIFO16(n) MMIO16(USB_BASE + 0x20 + n*0x04) +#define USB_FIFO32(n) MMIO32(USB_BASE + 0x20 + n*0x04) + +/* USB Transmit Dynamic FIFO Sizing */ +#define USB_TXFIFOSZ MMIO8(USB_BASE + 0x62) + +/* USB Receive Dynamic FIFO Sizing */ +#define USB_RXFIFOSZ MMIO8(USB_BASE + 0x63) + +/* USB Transmit FIFO Start Address */ +#define USB_TXFIFOADD MMIO16(USB_BASE + 0x64) + +/* USB Receive FIFO Start Address */ +#define USB_RXFIFOADD MMIO16(USB_BASE + 0x66) + +/* USB Connect Timing */ +#define USB_CONTIM MMIO8(USB_BASE + 0x7A) + +/* USB Full-Speed Last Transaction to End of Frame Timing */ +#define USB_FSEOF MMIO8(USB_BASE + 0x7D) + +/* USB Low-Speed Last Transaction to End of Frame Timing */ +#define USB_LSEOF MMIO8(USB_BASE + 0x7E) + +/* USB Control and Status Endpoint 0 Low */ +#define USB_CSRL0 MMIO8(USB_BASE + 0x102) + +/* USB Control and Status Endpoint 0 High */ +#define USB_CSRH0 MMIO8(USB_BASE + 0x103) + +/* USB Receive Byte Count Endpoint 0 */ +#define USB_COUNT0 MMIO8(USB_BASE + 0x108) + +/* USB Maximum Transmit Data Endpoint [1-7] */ +#define USB_TXMAXP(n) MMIO16(USB_BASE + 0x100 + n*0x10) + +/* USB Transmit Control and Status Endpoint [1-7] Low */ +#define USB_TXCSRL(n) MMIO8(USB_BASE + 0x102 + n*0x10) + +/* USB Transmit Control and Status Endpoint [1-7] High */ +#define USB_TXCSRH(n) MMIO8(USB_BASE + 0x103 + n*0x10) + +/* USB Maximum Receive Data Endpoint [1-7] */ +#define USB_RXMAXP(n) MMIO16(USB_BASE + 0x104 + n*0x10) + +/* USB Receive Control and Status Endpoint [1-7] Low */ +#define USB_RXCSRL(n) MMIO8(USB_BASE + 0x106 + n*0x10) + +/* USB Receive Control and Status Endpoint [1-7] High */ +#define USB_RXCSRH(n) MMIO8(USB_BASE + 0x107 + n*0x10) + +/* USB Receive Byte Count Endpoint [1-7] */ +#define USB_RXCOUNT(n) MMIO16(USB_BASE + 0x108 + n*0x10) + +/* USB Receive Double Packet Buffer Disable */ +#define USB_RXDPKTBUFDIS MMIO16(USB_BASE + 0x340) + +/* USB Transmit Double Packet Buffer Disable */ +#define USB_TXDPKTBUFDIS MMIO16(USB_BASE + 0x342) + +/* USB Device RESUME Raw Interrupt Status */ +#define USB_DRRIS MMIO32(USB_BASE + 0x410) + +/* USB Device RESUME Interrupt Mask */ +#define USB_DRIM MMIO32(USB_BASE + 0x414) + +/* USB Device RESUME Interrupt Status and Clear */ +#define USB_DRISC MMIO32(USB_BASE + 0x418) + +/* USB DMA Select */ +#define USB_DMASEL MMIO32(USB_BASE + 0x450) + +/* USB Peripheral Properties */ +#define USB_PP MMIO32(USB_BASE + 0xFC0) + + +/* ============================================================================= + * USB_FADDR values + * ---------------------------------------------------------------------------*/ +/** Function Address */ +#define USB_FADDR_FUNCADDR_MASK (0x3f << 0) + +/* ============================================================================= + * USB_POWER values + * ---------------------------------------------------------------------------*/ +/** Isochronous Update */ +#define USB_POWER_ISOUP (1 << 7) +/** Soft Connect/Disconnect */ +#define USB_POWER_SOFTCONN (1 << 6) +/** RESET signaling */ +#define USB_POWER_RESET (1 << 3) +/** RESUME signaling */ +#define USB_POWER_RESUME (1 << 2) +/** SUSPEND mode */ +#define USB_POWER_SUSPEND (1 << 1) +/** Power down PHY */ +#define USB_POWER_PWRDNPHY (1 << 0) + +/* ============================================================================= + * Endpoint bitmasks for interrupt status and control registers + * Applies to USB_TXIS, USB_RXIS, USB_TXIE, USB_RXIE, USB_RXDPKTBUFDIS, + * USB_TXDPKTBUFDIS + * ---------------------------------------------------------------------------*/ +#define USB_EP7 (1 << 7) +#define USB_EP6 (1 << 6) +#define USB_EP5 (1 << 5) +#define USB_EP4 (1 << 4) +#define USB_EP3 (1 << 3) +#define USB_EP2 (1 << 2) +#define USB_EP1 (1 << 1) +#define USB_EP0 (1 << 0) + +/* ============================================================================= + * USB interrupt mask values + * + * These are interchangeable across USB_IS, and USB_IE registers. + * ---------------------------------------------------------------------------*/ +/** USB disconnect interrupt */ +#define USB_IM_DISCON (1 << 5) +/** Start of frame */ +#define USB_IM_SOF (1 << 3) +/** RESET signaling detected */ +#define USB_IM_RESET (1 << 2) +/** RESUME signaling detected */ +#define USB_IM_RESUME (1 << 1) +/** SUSPEND signaling detected */ +#define USB_IM_SUSPEND (1 << 0) + +/* ============================================================================= + * USB_FRAME values + * ---------------------------------------------------------------------------*/ +/** Frame number */ +#define USB_FRAME_MASK (0x03FF) + +/* ============================================================================= + * USB_IDX values + * ---------------------------------------------------------------------------*/ +/** Endpoint Index */ +#define USB_EPIDX_MASK (0x0F) + +/* ============================================================================= + * USB_TEST values + * ---------------------------------------------------------------------------*/ +/** FIFO access */ +#define USB_TEST_FIFOACC (1 << 6) +/** Force full-speed mode */ +#define USB_TEST_FORCEFS (1 << 5) + +/* ============================================================================= + * USB_TXFIFOSZ and USB_RXFIFOSZ values + * ---------------------------------------------------------------------------*/ +/** Double packet buffer support */ +#define USB_FIFOSZ_DPB (1 << 4) +/* USB Transmit Dynamic FIFO Sizing */ +#define USB_FIFOSZ_SIZE_MASK (0x0F << 0) +#define USB_FIFOSZ_SIZE_8 (0x00 << 0) +#define USB_FIFOSZ_SIZE_16 (0x01 << 0) +#define USB_FIFOSZ_SIZE_32 (0x02 << 0) +#define USB_FIFOSZ_SIZE_64 (0x03 << 0) +#define USB_FIFOSZ_SIZE_128 (0x04 << 0) +#define USB_FIFOSZ_SIZE_256 (0x05 << 0) +#define USB_FIFOSZ_SIZE_512 (0x06 << 0) +#define USB_FIFOSZ_SIZE_1024 (0x07 << 0) +#define USB_FIFOSZ_SIZE_2048 (0x08 << 0) + + +/* ============================================================================= + * USB_CONTIM values + * ---------------------------------------------------------------------------*/ +/** Connect wait */ +#define USB_CONTIM_WTCON_MASK (0x0F << 4) +/** Wait ID */ +#define USB_CONTIM_WTID_MASK (0x0F << 0) + +/* ============================================================================= + * USB_CSRL0 values + * ---------------------------------------------------------------------------*/ +/** Setup End Clear */ +#define USB_CSRL0_SETENDC (1 << 7) +/** RXRDY Clear */ +#define USB_CSRL0_RXRDYC (1 << 6) +/** Send Stall */ +#define USB_CSRL0_STALL (1 << 5) +/** Setup End */ +#define USB_CSRL0_SETEND (1 << 4) +/** Data End */ +#define USB_CSRL0_DATAEND (1 << 3) +/** Endpoint Stalled */ +#define USB_CSRL0_STALLED (1 << 2) +/** Transmit Packet Ready */ +#define USB_CSRL0_TXRDY (1 << 1) +/** Receive Packet Ready */ +#define USB_CSRL0_RXRDY (1 << 0) + +/* ============================================================================= + * USB_CSRH0 values + * ---------------------------------------------------------------------------*/ +/** Flush FIFO */ +#define USB_CSRH0_FLUSH (1 << 0) + +/* ============================================================================= + * USB_TXCSRLx values + * ---------------------------------------------------------------------------*/ +/** Clear data toggle */ +#define USB_TXCSRL_CLRDT (1 << 6) +/** Endpoint Stalled */ +#define USB_TXCSRL_STALLED (1 << 5) +/** Send Stall */ +#define USB_TXCSRL_STALL (1 << 4) +/** Flush FIFO */ +#define USB_TXCSRL_FLUSH (1 << 3) +/** Underrun */ +#define USB_TXCSRL_UNDRN (1 << 2) +/** FIFO not empty */ +#define USB_TXCSRL_FIFONE (1 << 1) +/** Transmit Packet Ready */ +#define USB_TXCSRL_TXRDY (1 << 0) + +/* ============================================================================= + * USB_TXCSRHx values + * ---------------------------------------------------------------------------*/ +/** Auto set */ +#define USB_TXCSRH_AUTOSET (1 << 7) +/** Isochronous transfers */ +#define USB_TXCSRH_ISO (1 << 6) +/** Mode */ +#define USB_TXCSRH_MODE (1 << 5) +/** DMA request enable */ +#define USB_TXCSRH_DMAEN (1 << 4) +/** Force data toggle */ +#define USB_TXCSRH_FDT (1 << 3) +/** DMA request mode */ +#define USB_TXCSRH_DMAMOD (1 << 2) + +/* ============================================================================= + * USB_RXCSRLx values + * ---------------------------------------------------------------------------*/ +/** Clear data toggle */ +#define USB_RXCSRL_CLRDT (1 << 7) +/** Endpoint Stalled */ +#define USB_RXCSRL_STALLED (1 << 6) +/** Send Stall */ +#define USB_RXCSRL_STALL (1 << 5) +/** Flush FIFO */ +#define USB_RXCSRL_FLUSH (1 << 4) +/** Data error */ +#define USB_RXCSRL_DATAERR (1 << 2) +/** Overrun */ +#define USB_RXCSRL_OVER (1 << 2) +/** FIFO full */ +#define USB_RXCSRL_FULL (1 << 1) +/** Receive Packet Ready */ +#define USB_RXCSRL_RXRDY (1 << 0) + +/* ============================================================================= + * USB_RXCSRHx values + * ---------------------------------------------------------------------------*/ +/** Auto clear */ +#define USB_RXCSRH_AUTOCL (1 << 7) +/** Isochronous transfers */ +#define USB_RXCSRH_ISO (1 << 6) +/** DMA request enable */ +#define USB_RXCSRH_DMAEN (1 << 5) +/** Disable NYET / PID error */ +#define USB_RXCSRH_PIDERR (1 << 4) +/** DMA request mode */ +#define USB_RXCSRH_DMAMOD (1 << 3) + +/* ============================================================================= + * USB_DRRIS values + * ---------------------------------------------------------------------------*/ +/** RESUME interrupt status */ +#define USB_DRRIS_RESUME (1 << 0) + +/* ============================================================================= + * USB_DRIM values + * ---------------------------------------------------------------------------*/ +/** RESUME interrupt mask */ +#define USB_DRIM_RESUME (1 << 0) + +/* ============================================================================= + * USB_DRISC values + * ---------------------------------------------------------------------------*/ +/** RESUME interrupt status and clear */ +#define USB_DRISC_RESUME (1 << 0) + +/* ============================================================================= + * USB_PP values + * ---------------------------------------------------------------------------*/ +/** Endpoint count */ +#define USB_PP_ECNT_MASK (0xFF << 8) +/** USB capability */ +#define USB_PP_USB_MASK (0x03 << 6) +#define USB_PP_USB_NA (0x00 << 6) +#define USB_PP_USB_DEVICE (0x01 << 6) +#define USB_PP_USB_HOST (0x02 << 6) +#define USB_PP_USB_OTG (0x03 << 6) +/** PHY present */ +#define USB_PP_PHY (1 << 4) +/** Controller type */ +#define USB_PP_TYPE_MASK (0x0F << 0) + +/* ============================================================================= + * Convenience enums + * ---------------------------------------------------------------------------*/ +enum usb_interrupt { + USB_INT_DISCON = USB_IM_DISCON, + USB_INT_SOF = USB_IM_SOF, + USB_INT_RESET = USB_IM_RESET, + USB_INT_RESUME = USB_IM_RESUME, + USB_INT_SUSPEND = USB_IM_SUSPEND, +}; + +enum usb_ep_interrupt { + USB_EP0_INT = USB_EP0, + USB_EP1_INT = USB_EP1, + USB_EP2_INT = USB_EP2, + USB_EP3_INT = USB_EP3, + USB_EP4_INT = USB_EP4, + USB_EP5_INT = USB_EP5, + USB_EP6_INT = USB_EP6, + USB_EP7_INT = USB_EP7, +}; +/* ============================================================================= + * Function prototypes + * ---------------------------------------------------------------------------*/ +BEGIN_DECLS + +void usb_enable_interrupts(enum usb_interrupt ints, + enum usb_ep_interrupt rx_ints, + enum usb_ep_interrupt tx_ints); +void usb_disable_interrupts(enum usb_interrupt ints, + enum usb_ep_interrupt rx_ints, + enum usb_ep_interrupt tx_ints); + +END_DECLS + +/**@}*/ + +#endif /* LIBOPENCM3_LM4F_USB_H */ diff --git a/libopencm3/include/libopencm3/lpc13xx/doc-lpc13xx.h b/libopencm3/include/libopencm3/lpc13xx/doc-lpc13xx.h new file mode 100644 index 0000000..5ed7cae --- /dev/null +++ b/libopencm3/include/libopencm3/lpc13xx/doc-lpc13xx.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 LPC13xx + +@version 1.0.0 + +@date 14 September 2012 + +API documentation for NXP Semiconductors LPC13xx Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup LPC13xx LPC13xx +Libraries for NXP Semiconductors LPC13xx series. + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup LPC13xx_defines LPC13xx Defines + +@brief Defined Constants and Types for the LPC13xx series + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/libopencm3/include/libopencm3/lpc13xx/gpio.h b/libopencm3/include/libopencm3/lpc13xx/gpio.h new file mode 100644 index 0000000..907533a --- /dev/null +++ b/libopencm3/include/libopencm3/lpc13xx/gpio.h @@ -0,0 +1,124 @@ +/** @defgroup gpio_defines GPIO Defines + +@brief Defined Constants and Types for the LPC13xx General Purpose I/O + +@ingroup LPC13xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2009 Uwe Hermann + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#ifndef LPC13XX_GPIO_H +#define LPC13XX_GPIO_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* GPIO port base addresses (for convenience) */ +#define GPIO0 GPIO_PIO0_BASE +#define GPIO1 GPIO_PIO1_BASE +#define GPIO2 GPIO_PIO2_BASE +#define GPIO3 GPIO_PIO3_BASE + +/* --- GPIO registers ------------------------------------------------------ */ + +/* GPIO data register (GPIOn_DATA) */ +#define GPIO_DATA(port) MMIO32(port + 0x3ffc) +#define GPIO0_DATA GPIO_DATA(GPIO0) +#define GPIO1_DATA GPIO_DATA(GPIO1) +#define GPIO2_DATA GPIO_DATA(GPIO2) +#define GPIO3_DATA GPIO_DATA(GPIO3) + +/* GPIO data direction register (GPIOn_DIR) */ +#define GPIO_DIR(port) MMIO32(port + 0x00) +#define GPIO0_DIR GPIO_DIR(GPIO0) +#define GPIO1_DIR GPIO_DIR(GPIO1) +#define GPIO2_DIR GPIO_DIR(GPIO2) +#define GPIO3_DIR GPIO_DIR(GPIO3) + +/* GPIO interrupt sense register (GPIOn_IS) */ +#define GPIO_IS(port) MMIO32(port + 0x04) +#define GPIO0_IS GPIO_IS(GPIO0) +#define GPIO1_IS GPIO_IS(GPIO1) +#define GPIO2_IS GPIO_IS(GPIO2) +#define GPIO3_IS GPIO_IS(GPIO3) + +/* GPIO interrupt both edges sense register (GPIOn_IBE) */ +#define GPIO_IBE(port) MMIO32(port + 0x08) +#define GPIO0_IBE GPIO_IBE(GPIO0) +#define GPIO1_IBE GPIO_IBE(GPIO1) +#define GPIO2_IBE GPIO_IBE(GPIO2) +#define GPIO3_IBE GPIO_IBE(GPIO3) + +/* GPIO interrupt event register (GPIOn_IEV) */ +#define GPIO_IEV(port) MMIO32(port + 0x0c) +#define GPIO0_IEV GPIO_IEV(GPIO0) +#define GPIO1_IEV GPIO_IEV(GPIO1) +#define GPIO2_IEV GPIO_IEV(GPIO2) +#define GPIO3_IEV GPIO_IEV(GPIO3) + +/* GPIO interrupt mask register (GPIOn_IE) */ +#define GPIO_IE(port) MMIO16(port + 0x10) +#define GPIO0_IE GPIO_IE(GPIO0) +#define GPIO1_IE GPIO_IE(GPIO1) +#define GPIO2_IE GPIO_IE(GPIO2) +#define GPIO3_IE GPIO_IE(GPIO3) + +/* FIXME: IRS or RIS? Datasheet is not consistent here. */ +/* GPIO raw interrupt status register (GPIOn_IRS) */ +#define GPIO_IRS(port) MMIO16(port + 0x14) +#define GPIO0_IRS GPIO_IRS(GPIO0) +#define GPIO1_IRS GPIO_IRS(GPIO1) +#define GPIO2_IRS GPIO_IRS(GPIO2) +#define GPIO3_IRS GPIO_IRS(GPIO3) + +/* GPIO masked interrupt status register (GPIOn_MIS) */ +#define GPIO_MIS(port) MMIO16(port + 0x18) +#define GPIO0_MIS GPIO_MIS(GPIO0) +#define GPIO1_MIS GPIO_MIS(GPIO1) +#define GPIO2_MIS GPIO_MIS(GPIO2) +#define GPIO3_MIS GPIO_MIS(GPIO3) + +/* GPIO interrupt clear register (GPIOn_IC) */ +#define GPIO_IC(port) MMIO16(port + 0x1c) +#define GPIO0_IC GPIO_IC(GPIO0) +#define GPIO1_IC GPIO_IC(GPIO1) +#define GPIO2_IC GPIO_IC(GPIO2) +#define GPIO3_IC GPIO_IC(GPIO3) + +BEGIN_DECLS + +void gpio_set(uint32_t gpioport, uint16_t gpios); + +END_DECLS + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc13xx/irq.json b/libopencm3/include/libopencm3/lpc13xx/irq.json new file mode 100644 index 0000000..d9ac31f --- /dev/null +++ b/libopencm3/include/libopencm3/lpc13xx/irq.json @@ -0,0 +1,63 @@ +{ + "irqs": { + "0": "pio0_0", + "1": "pio0_1", + "2": "pio0_2", + "3": "pio0_3", + "4": "pio0_4", + "5": "pio0_5", + "6": "pio0_6", + "7": "pio0_7", + "8": "pio0_8", + "9": "pio0_9", + "10": "pio0_10", + "11": "pio0_11", + "12": "pio1_0", + "13": "pio1_1", + "14": "pio1_2", + "15": "pio1_3", + "16": "pio1_4", + "17": "pio1_5", + "18": "pio1_6", + "19": "pio1_7", + "20": "pio1_8", + "21": "pio1_9", + "22": "pio1_10", + "23": "pio1_11", + "24": "pio2_0", + "25": "pio2_1", + "26": "pio2_2", + "27": "pio2_3", + "28": "pio2_4", + "29": "pio2_5", + "30": "pio2_6", + "31": "pio2_7", + "32": "pio2_8", + "33": "pio2_9", + "34": "pio2_10", + "35": "pio2_11", + "36": "pio3_0", + "37": "pio3_1", + "38": "pio3_2", + "39": "pio3_3", + "40": "i2c0", + "41": "ct16b0", + "42": "ct16b1", + "43": "ct32b0", + "44": "ct32b1", + "45": "ssp0", + "46": "uart", + "47": "usb", + "48": "usb_fiq", + "49": "adc", + "50": "wdt", + "51": "bod", + "53": "pio3", + "54": "pio2", + "55": "pio1", + "56": "ssp1" + }, + "partname_humanreadable": "LPC 13xx series", + "partname_doxygen": "LPC13xx", + "includeguard": "LIBOPENCM3_LPC13xx_NVIC_H" +} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/lpc13xx/memorymap.h b/libopencm3/include/libopencm3/lpc13xx/memorymap.h new file mode 100644 index 0000000..01b94b2 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc13xx/memorymap.h @@ -0,0 +1,58 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC13XX_MEMORYMAP_H +#define LPC13XX_MEMORYMAP_H + +#include + +/* --- LPC13XX specific peripheral definitions ----------------------------- */ + +/* Memory map for all busses */ +#define PERIPH_BASE_APB (0x40000000U) +#define PERIPH_BASE_AHB (0x50000000U) + +/* Register boundary addresses */ + +/* APB */ +#define I2C_BASE (PERIPH_BASE_APB + 0x00000) +#define WDT_BASE (PERIPH_BASE_APB + 0x04000) +#define UART_BASE (PERIPH_BASE_APB + 0x08000) +#define TIMER0_16BIT_BASE (PERIPH_BASE_APB + 0x0c000) +#define TIMER1_16BIT_BASE (PERIPH_BASE_APB + 0x10000) +#define TIMER0_32BIT_BASE (PERIPH_BASE_APB + 0x14000) +#define TIMER1_32BIT_BASE (PERIPH_BASE_APB + 0x18000) +#define ADC_BASE (PERIPH_BASE_APB + 0x1c000) +#define USB_BASE (PERIPH_BASE_APB + 0x20000) +/* PERIPH_BASE_APB + 0x28000 (0x4002 8000 - 0x4003 7FFF): Reserved */ +#define PMU_BASE (PERIPH_BASE_APB + 0x38000) +#define FLASH_BASE (PERIPH_BASE_APB + 0x3c000) +#define SSP_BASE (PERIPH_BASE_APB + 0x40000) +#define IOCONFIG_BASE (PERIPH_BASE_APB + 0x44000) +#define SYSCTRL_BASE (PERIPH_BASE_APB + 0x48000) +/* PERIPH_BASE_APB + 0x4c000 (0x4004 c000 - 0x4007 FFFF): Reserved */ + +/* AHB */ +#define GPIO_PIO0_BASE (PERIPH_BASE_AHB + 0x00000) +#define GPIO_PIO1_BASE (PERIPH_BASE_AHB + 0x10000) +#define GPIO_PIO2_BASE (PERIPH_BASE_AHB + 0x20000) +#define GPIO_PIO3_BASE (PERIPH_BASE_AHB + 0x30000) +/* PERIPH_BASE_AHB + 0x40000 (0x5004 0000 - 0x501F FFFF): Reserved */ + +#endif diff --git a/libopencm3/include/libopencm3/lpc17xx/doc-lpc17xx.h b/libopencm3/include/libopencm3/lpc17xx/doc-lpc17xx.h new file mode 100644 index 0000000..4bc603d --- /dev/null +++ b/libopencm3/include/libopencm3/lpc17xx/doc-lpc17xx.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 LPC17xx + +@version 1.0.0 + +@date 14 September 2012 + +API documentation for NXP Semiconductors LPC17xx Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup LPC17xx LPC17xx +Libraries for NXP Semiconductors LPC17xx series. + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup LPC17xx_defines LPC17xx Defines + +@brief Defined Constants and Types for the LPC17xx series + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/libopencm3/include/libopencm3/lpc17xx/gpio.h b/libopencm3/include/libopencm3/lpc17xx/gpio.h new file mode 100644 index 0000000..2aecd6b --- /dev/null +++ b/libopencm3/include/libopencm3/lpc17xx/gpio.h @@ -0,0 +1,160 @@ +/** @defgroup gpio_defines GPIO Defines + +@brief Defined Constants and Types for the LPC17xx General Purpose I/O + +@ingroup LPC17xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2009 Uwe Hermann + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC17XX_GPIO_H +#define LPC17XX_GPIO_H + +/**@{*/ + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* GPIO port base addresses (for convenience) */ +#define GPIO0 GPIO_PIO0_BASE +#define GPIO1 GPIO_PIO1_BASE +#define GPIO2 GPIO_PIO2_BASE +#define GPIO3 GPIO_PIO3_BASE +#define GPIO4 GPIO_PIO4_BASE + +/* GPIO number definitions (for convenience) */ +#define GPIOPIN0 (1 << 0) +#define GPIOPIN1 (1 << 1) +#define GPIOPIN2 (1 << 2) +#define GPIOPIN3 (1 << 3) +#define GPIOPIN4 (1 << 4) +#define GPIOPIN5 (1 << 5) +#define GPIOPIN6 (1 << 6) +#define GPIOPIN7 (1 << 7) +#define GPIOPIN8 (1 << 8) +#define GPIOPIN9 (1 << 9) +#define GPIOPIN10 (1 << 10) +#define GPIOPIN11 (1 << 11) +#define GPIOPIN12 (1 << 12) +#define GPIOPIN13 (1 << 13) +#define GPIOPIN14 (1 << 14) +#define GPIOPIN15 (1 << 15) +#define GPIOPIN16 (1 << 16) +#define GPIOPIN17 (1 << 17) +#define GPIOPIN18 (1 << 18) +#define GPIOPIN19 (1 << 19) +#define GPIOPIN20 (1 << 20) +#define GPIOPIN21 (1 << 21) +#define GPIOPIN22 (1 << 22) +#define GPIOPIN23 (1 << 23) +#define GPIOPIN24 (1 << 24) +#define GPIOPIN25 (1 << 25) +#define GPIOPIN26 (1 << 26) +#define GPIOPIN27 (1 << 27) +#define GPIOPIN28 (1 << 28) +#define GPIOPIN29 (1 << 29) +#define GPIOPIN30 (1 << 30) +#define GPIOPIN31 (1 << 31) + +/* --- GPIO registers ------------------------------------------------------ */ + +/* GPIO data direction register (GPIOn_DIR) */ +#define GPIO_DIR(port) MMIO32(port + 0x00) +#define GPIO0_DIR GPIO_DIR(GPIO0) +#define GPIO1_DIR GPIO_DIR(GPIO1) +#define GPIO2_DIR GPIO_DIR(GPIO2) +#define GPIO3_DIR GPIO_DIR(GPIO3) +#define GPIO4_DIR GPIO_DIR(GPIO4) + +/* GPIO fast mask register (GPIOn_DIR) */ +#define GPIO_MASK(port) MMIO32(port + 0x10) +#define GPIO0_MASK GPIO_MASK(GPIO0) +#define GPIO1_MASK GPIO_MASK(GPIO1) +#define GPIO2_MASK GPIO_MASK(GPIO2) +#define GPIO3_MASK GPIO_MASK(GPIO3) +#define GPIO4_MASK GPIO_MASK(GPIO4) + +/* GPIO port pin value register (GPIOn_PIN) */ +#define GPIO_PIN(port) MMIO32(port + 0x14) +#define GPIO0_PIN GPIO_PIN(GPIO0) +#define GPIO1_PIN GPIO_PIN(GPIO1) +#define GPIO2_PIN GPIO_PIN(GPIO2) +#define GPIO3_PIN GPIO_PIN(GPIO3) +#define GPIO4_PIN GPIO_PIN(GPIO4) + +/* GPIO port output set register (GPIOn_SET) */ +#define GPIO_SET(port) MMIO32(port + 0x18) +#define GPIO0_SET GPIO_SET(GPIO0) +#define GPIO1_SET GPIO_SET(GPIO1) +#define GPIO2_SET GPIO_SET(GPIO2) +#define GPIO3_SET GPIO_SET(GPIO3) +#define GPIO4_SET GPIO_SET(GPIO4) + +/* GPIO port output clear register (GPIOn_CLR) */ +#define GPIO_CLR(port) MMIO32(port + 0x1C) +#define GPIO0_CLR GPIO_CLR(GPIO0) +#define GPIO1_CLR GPIO_CLR(GPIO1) +#define GPIO2_CLR GPIO_CLR(GPIO2) +#define GPIO3_CLR GPIO_CLR(GPIO3) +#define GPIO4_CLR GPIO_CLR(GPIO4) + +/* GPIO interrupt register map */ +/* Interrupt enable rising edge */ +#define GPIO0_IER MMIO32(GPIOINTERRUPT_BASE + 0x90) +#define GPIO2_IER MMIO32(GPIOINTERRUPT_BASE + 0xB0) + +/* Interrupt enable falling edge */ +#define GPIO0_IEF MMIO32(GPIOINTERRUPT_BASE + 0x94) +#define GPIO2_IEF MMIO32(GPIOINTERRUPT_BASE + 0xB4) + +/* Interrupt status rising edge */ +#define GPIO0_ISR MMIO32(GPIOINTERRUPT_BASE + 0x84) +#define GPIO2_ISR MMIO32(GPIOINTERRUPT_BASE + 0xA4) + +/* Interrupt status falling edge */ +#define GPIO0_ISF MMIO32(GPIOINTERRUPT_BASE + 0x88) +#define GPIO2_ISF MMIO32(GPIOINTERRUPT_BASE + 0xA8) + +/* Interrupt clear */ +#define GPIO0_IC MMIO32(GPIOINTERRUPT_BASE + 0x8C) +#define GPIO1_IC MMIO32(GPIOINTERRUPT_BASE + 0xAC) + +/* Overall interrupt status */ +#define GPIO_IS MMIO32(GPIOINTERRUPT_BASE + 0x80) + +BEGIN_DECLS + +void gpio_set(uint32_t gpioport, uint32_t gpios); +void gpio_clear(uint32_t gpioport, uint32_t gpios); + +END_DECLS + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc17xx/irq.json b/libopencm3/include/libopencm3/lpc17xx/irq.json new file mode 100644 index 0000000..94eec07 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc17xx/irq.json @@ -0,0 +1,42 @@ +{ + "irqs": { + "0": "wdt", + "1": "timer0", + "2": "timer1", + "3": "timer2", + "4": "timer3", + "5": "uart0", + "6": "uart1", + "7": "uart2", + "8": "uart3", + "9": "pwm", + "10": "i2c0", + "11": "i2c1", + "12": "i2c2", + "13": "spi", + "14": "ssp0", + "15": "ssp1", + "16": "pll0", + "17": "rtc", + "18": "eint0", + "19": "eint1", + "20": "eint2", + "21": "eint3", + "22": "adc", + "23": "bod", + "24": "usb", + "25": "can", + "26": "gpdma", + "27": "i2s", + "28": "ethernet", + "29": "rit", + "30": "motor_pwm", + "31": "qei", + "32": "pll1", + "33": "usb_act", + "34": "can_act" + }, + "partname_humanreadable": "LPC 17xx series", + "partname_doxygen": "LPC17xx", + "includeguard": "LIBOPENCM3_LPC17xx_NVIC_H" +} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/lpc17xx/memorymap.h b/libopencm3/include/libopencm3/lpc17xx/memorymap.h new file mode 100644 index 0000000..b82a51b --- /dev/null +++ b/libopencm3/include/libopencm3/lpc17xx/memorymap.h @@ -0,0 +1,65 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC17XX_MEMORYMAP_H +#define LPC17XX_MEMORYMAP_H + +#include + +/* --- LPC17XX specific peripheral definitions ----------------------------- */ + +/* Memory map for all busses */ +#define PERIPH_BASE_APB0 (0x40000000U) +#define PERIPH_BASE_APB1 (0x40080000U) +#define PERIPH_BASE_AHB (0x20000000U) + +/* Register boundary addresses */ + +/* APB0 */ +#define WDT_BASE (PERIPH_BASE_APB0 + 0x00000) +#define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000) +#define TIMER1_BASE (PERIPH_BASE_APB0 + 0x08000) +#define UART0_BASE (PERIPH_BASE_APB0 + 0x0c000) +#define UART1_BASE (PERIPH_BASE_APB0 + 0x10000) +/* PERIPH_BASE_APB0 + 0X14000 (0x4001 4000 - 0x4001 7FFF): Reserved */ +#define PWM1_BASE (PERIPH_BASE_APB0 + 0x18000) +#define I2C0_BASE (PERIPH_BASE_APB0 + 0x1c000) +#define SPI_BASE (PERIPH_BASE_APB0 + 0x20000) +#define RTC_BASE (PERIPH_BASE_APB0 + 0x24000) +#define GPIOINTERRUPT_BASE (PERIPH_BASE_APB0 + 0x28000) +#define PINCONNECT_BASE (PERIPH_BASE_APB0 + 0x2c000) +#define SSP1_BASE (PERIPH_BASE_APB0 + 0x30000) +#define ADC_BASE (PERIPH_BASE_APB0 + 0x34000) +#define CANAFRAM_BASE (PERIPH_BASE_APB0 + 0x38000) +#define CANAFREG_BASE (PERIPH_BASE_APB0 + 0x3C000) +#define CANCOMMONREG_BASE (PERIPH_BASE_APB0 + 0x40000) +#define CAN1_BASE (PERIPH_BASE_APB0 + 0x44000) +#define CAN2_BASE (PERIPH_BASE_APB0 + 0x48000) +/* PERIPH_BASE_APB0 + 0X4C000 (0x4004 C000 - 0x4005 BFFF): Reserved */ +#define I2C1_BASE (PERIPH_BASE_APB0 + 0x5C000) +/* PERIPH_BASE_APB0 + 0X60000 (0x6000 0000 - 0x4007 BFFF): Reserved */ + +/* AHB */ +#define GPIO_PIO0_BASE (PERIPH_BASE_AHB + 0x9c000) +#define GPIO_PIO1_BASE (PERIPH_BASE_AHB + 0x9c020) +#define GPIO_PIO2_BASE (PERIPH_BASE_AHB + 0x9c040) +#define GPIO_PIO3_BASE (PERIPH_BASE_AHB + 0x9c060) +#define GPIO_PIO4_BASE (PERIPH_BASE_AHB + 0x9c080) + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/adc.h b/libopencm3/include/libopencm3/lpc43xx/adc.h new file mode 100644 index 0000000..c63c1e4 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/adc.h @@ -0,0 +1,113 @@ +/** @defgroup adc_defines ADC Defines + +@brief Defined Constants and Types for the LPC43xx A/D Converter + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC43XX_ADC_H +#define LPC43XX_ADC_H + +/**@{*/ + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* ADC port base addresses (for convenience) */ +#define ADC0 ADC0_BASE +#define ADC1 ADC1_BASE + + +/* --- ADC registers ------------------------------------------------------- */ + +/* A/D Control Register */ +#define ADC_CR(port) MMIO32(port + 0x000) +#define ADC0_CR ADC_CR(ADC0) +#define ADC1_CR ADC_CR(ADC1) + +/* A/D Global Data Register */ +#define ADC_GDR(port) MMIO32(port + 0x004) +#define ADC0_GDR ADC_GDR(ADC0) +#define ADC1_GDR ADC_GDR(ADC1) + +/* A/D Interrupt Enable Register */ +#define ADC_INTEN(port) MMIO32(port + 0x00C) +#define ADC0_INTEN ADC_INTEN(ADC0) +#define ADC1_INTEN ADC_INTEN(ADC1) + +/* A/D Channel 0 Data Register */ +#define ADC_DR0(port) MMIO32(port + 0x010) +#define ADC0_DR0 ADC_DR0(ADC0) +#define ADC1_DR0 ADC_DR0(ADC1) + +/* A/D Channel 1 Data Register */ +#define ADC_DR1(port) MMIO32(port + 0x014) +#define ADC0_DR1 ADC_DR1(ADC0) +#define ADC1_DR1 ADC_DR1(ADC1) + +/* A/D Channel 2 Data Register */ +#define ADC_DR2(port) MMIO32(port + 0x018) +#define ADC0_DR2 ADC_DR2(ADC0) +#define ADC1_DR2 ADC_DR2(ADC1) + +/* A/D Channel 3 Data Register */ +#define ADC_DR3(port) MMIO32(port + 0x01C) +#define ADC0_DR3 ADC_DR3(ADC0) +#define ADC1_DR3 ADC_DR3(ADC1) + +/* A/D Channel 4 Data Register */ +#define ADC_DR4(port) MMIO32(port + 0x020) +#define ADC0_DR4 ADC_DR4(ADC0) +#define ADC1_DR4 ADC_DR4(ADC1) + +/* A/D Channel 5 Data Register */ +#define ADC_DR5(port) MMIO32(port + 0x024) +#define ADC0_DR5 ADC_DR5(ADC0) +#define ADC1_DR5 ADC_DR5(ADC1) + +/* A/D Channel 6 Data Register */ +#define ADC_DR6(port) MMIO32(port + 0x028) +#define ADC0_DR6 ADC_DR6(ADC0) +#define ADC1_DR6 ADC_DR6(ADC1) + +/* A/D Channel 7 Data Register */ +#define ADC_DR7(port) MMIO32(port + 0x02C) +#define ADC0_DR7 ADC_DR7(ADC0) +#define ADC1_DR7 ADC_DR7(ADC1) + +/* A/D Status Register */ +#define ADC_STAT(port) MMIO32(port + 0x030) +#define ADC0_STAT ADC_STAT(ADC0) +#define ADC1_STAT ADC_STAT(ADC1) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/atimer.h b/libopencm3/include/libopencm3/lpc43xx/atimer.h new file mode 100644 index 0000000..cbb70d7 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/atimer.h @@ -0,0 +1,70 @@ +/** @defgroup atimer_defines Alarm Timer Defines + +@brief Defined Constants and Types for the LPC43xx Alarm Timer + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC43XX_ATIMER_H +#define LPC43XX_ATIMER_H + +/**@{*/ + +#include +#include + +/* --- Alarm Timer registers ----------------------------------------------- */ + +/* Downcounter register */ +#define ATIMER_DOWNCOUNTER MMIO32(ATIMER_BASE + 0x000) + +/* Preset value register */ +#define ATIMER_PRESET MMIO32(ATIMER_BASE + 0x004) + +/* Interrupt clear enable register */ +#define ATIMER_CLR_EN MMIO32(ATIMER_BASE + 0xFD8) + +/* Interrupt set enable register */ +#define ATIMER_SET_EN MMIO32(ATIMER_BASE + 0xFDC) + +/* Status register */ +#define ATIMER_STATUS MMIO32(ATIMER_BASE + 0xFE0) + +/* Enable register */ +#define ATIMER_ENABLE MMIO32(ATIMER_BASE + 0xFE4) + +/* Clear register */ +#define ATIMER_CLR_STAT MMIO32(ATIMER_BASE + 0xFE8) + +/* Set register */ +#define ATIMER_SET_STAT MMIO32(ATIMER_BASE + 0xFEC) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/ccu.h b/libopencm3/include/libopencm3/lpc43xx/ccu.h new file mode 100644 index 0000000..d3b1d50 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/ccu.h @@ -0,0 +1,402 @@ +/** @defgroup ccu_defines Clock Control Unit Defines + +@brief Defined Constants and Types for the LPC43xx Clock Control Unit + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC43XX_CCU_H +#define LPC43XX_CCU_H + +/**@{*/ + +#include +#include + +/* --- CCU1 registers ------------------------------------------------------ */ + +/* CCU1 power mode register */ +#define CCU1_PM MMIO32(CCU1_BASE + 0x000) + +/* CCU1 base clock status register */ +#define CCU1_BASE_STAT MMIO32(CCU1_BASE + 0x004) + +/* CLK_APB3_BUS clock configuration register */ +#define CCU1_CLK_APB3_BUS_CFG MMIO32(CCU1_BASE + 0x100) + +/* CLK_APB3_BUS clock status register */ +#define CCU1_CLK_APB3_BUS_STAT MMIO32(CCU1_BASE + 0x104) + +/* CLK_APB3_I2C1 configuration register */ +#define CCU1_CLK_APB3_I2C1_CFG MMIO32(CCU1_BASE + 0x108) + +/* CLK_APB3_I2C1 status register */ +#define CCU1_CLK_APB3_I2C1_STAT MMIO32(CCU1_BASE + 0x10C) + +/* CLK_APB3_DAC configuration register */ +#define CCU1_CLK_APB3_DAC_CFG MMIO32(CCU1_BASE + 0x110) + +/* CLK_APB3_DAC status register */ +#define CCU1_CLK_APB3_DAC_STAT MMIO32(CCU1_BASE + 0x114) + +/* CLK_APB3_ADC0 configuration register */ +#define CCU1_CLK_APB3_ADC0_CFG MMIO32(CCU1_BASE + 0x118) + +/* CLK_APB3_ADC0 status register */ +#define CCU1_CLK_APB3_ADC0_STAT MMIO32(CCU1_BASE + 0x11C) + +/* CLK_APB3_ADC1 configuration register */ +#define CCU1_CLK_APB3_ADC1_CFG MMIO32(CCU1_BASE + 0x120) + +/* CLK_APB3_ADC1 status register */ +#define CCU1_CLK_APB3_ADC1_STAT MMIO32(CCU1_BASE + 0x124) + +/* CLK_APB3_CAN0 configuration register */ +#define CCU1_CLK_APB3_CAN0_CFG MMIO32(CCU1_BASE + 0x128) + +/* CLK_APB3_CAN0 status register */ +#define CCU1_CLK_APB3_CAN0_STAT MMIO32(CCU1_BASE + 0x12C) + +/* CLK_APB1_BUS configuration register */ +#define CCU1_CLK_APB1_BUS_CFG MMIO32(CCU1_BASE + 0x200) + +/* CLK_APB1_BUS status register */ +#define CCU1_CLK_APB1_BUS_STAT MMIO32(CCU1_BASE + 0x204) + +/* CLK_APB1_MOTOCON configuration register */ +#define CCU1_CLK_APB1_MOTOCONPWM_CFG MMIO32(CCU1_BASE + 0x208) + +/* CLK_APB1_MOTOCON status register */ +#define CCU1_CLK_APB1_MOTOCONPWM_STAT MMIO32(CCU1_BASE + 0x20C) + +/* CLK_APB1_I2C0 configuration register */ +#define CCU1_CLK_APB1_I2C0_CFG MMIO32(CCU1_BASE + 0x210) + +/* CLK_APB1_I2C0 status register */ +#define CCU1_CLK_APB1_I2C0_STAT MMIO32(CCU1_BASE + 0x214) + +/* CLK_APB1_I2S configuration register */ +#define CCU1_CLK_APB1_I2S_CFG MMIO32(CCU1_BASE + 0x218) + +/* CLK_APB1_I2S status register */ +#define CCU1_CLK_APB1_I2S_STAT MMIO32(CCU1_BASE + 0x21C) + +/* CLK_APB3_CAN1 configuration register */ +#define CCU1_CLK_APB1_CAN1_CFG MMIO32(CCU1_BASE + 0x220) + +/* CLK_APB3_CAN1 status register */ +#define CCU1_CLK_APB1_CAN1_STAT MMIO32(CCU1_BASE + 0x224) + +/* CLK_SPIFI configuration register */ +#define CCU1_CLK_SPIFI_CFG MMIO32(CCU1_BASE + 0x300) + +/* CLK_SPIFI status register */ +#define CCU1_CLK_SPIFI_STAT MMIO32(CCU1_BASE + 0x304) + +/* CLK_M4_BUS configuration register */ +#define CCU1_CLK_M4_BUS_CFG MMIO32(CCU1_BASE + 0x400) + +/* CLK_M4_BUS status register */ +#define CCU1_CLK_M4_BUS_STAT MMIO32(CCU1_BASE + 0x404) + +/* CLK_M4_SPIFI configuration register */ +#define CCU1_CLK_M4_SPIFI_CFG MMIO32(CCU1_BASE + 0x408) + +/* CLK_M4_SPIFI status register */ +#define CCU1_CLK_M4_SPIFI_STAT MMIO32(CCU1_BASE + 0x40C) + +/* CLK_M4_GPIO configuration register */ +#define CCU1_CLK_M4_GPIO_CFG MMIO32(CCU1_BASE + 0x410) + +/* CLK_M4_GPIO status register */ +#define CCU1_CLK_M4_GPIO_STAT MMIO32(CCU1_BASE + 0x414) + +/* CLK_M4_LCD configuration register */ +#define CCU1_CLK_M4_LCD_CFG MMIO32(CCU1_BASE + 0x418) + +/* CLK_M4_LCD status register */ +#define CCU1_CLK_M4_LCD_STAT MMIO32(CCU1_BASE + 0x41C) + +/* CLK_M4_ETHERNET configuration register */ +#define CCU1_CLK_M4_ETHERNET_CFG MMIO32(CCU1_BASE + 0x420) + +/* CLK_M4_ETHERNET status register */ +#define CCU1_CLK_M4_ETHERNET_STAT MMIO32(CCU1_BASE + 0x424) + +/* CLK_M4_USB0 configuration register */ +#define CCU1_CLK_M4_USB0_CFG MMIO32(CCU1_BASE + 0x428) + +/* CLK_M4_USB0 status register */ +#define CCU1_CLK_M4_USB0_STAT MMIO32(CCU1_BASE + 0x42C) + +/* CLK_M4_EMC configuration register */ +#define CCU1_CLK_M4_EMC_CFG MMIO32(CCU1_BASE + 0x430) + +/* CLK_M4_EMC status register */ +#define CCU1_CLK_M4_EMC_STAT MMIO32(CCU1_BASE + 0x434) + +/* CLK_M4_SDIO configuration register */ +#define CCU1_CLK_M4_SDIO_CFG MMIO32(CCU1_BASE + 0x438) + +/* CLK_M4_SDIO status register */ +#define CCU1_CLK_M4_SDIO_STAT MMIO32(CCU1_BASE + 0x43C) + +/* CLK_M4_DMA configuration register */ +#define CCU1_CLK_M4_DMA_CFG MMIO32(CCU1_BASE + 0x440) + +/* CLK_M4_DMA status register */ +#define CCU1_CLK_M4_DMA_STAT MMIO32(CCU1_BASE + 0x444) + +/* CLK_M4_M4CORE configuration register */ +#define CCU1_CLK_M4_M4CORE_CFG MMIO32(CCU1_BASE + 0x448) + +/* CLK_M4_M4CORE status register */ +#define CCU1_CLK_M4_M4CORE_STAT MMIO32(CCU1_BASE + 0x44C) + +/* CLK_M4_SCT configuration register */ +#define CCU1_CLK_M4_SCT_CFG MMIO32(CCU1_BASE + 0x468) + +/* CLK_M4_SCT status register */ +#define CCU1_CLK_M4_SCT_STAT MMIO32(CCU1_BASE + 0x46C) + +/* CLK_M4_USB1 configuration register */ +#define CCU1_CLK_M4_USB1_CFG MMIO32(CCU1_BASE + 0x470) + +/* CLK_M4_USB1 status register */ +#define CCU1_CLK_M4_USB1_STAT MMIO32(CCU1_BASE + 0x474) + +/* CLK_M4_EMCDIV configuration register */ +#define CCU1_CLK_M4_EMCDIV_CFG MMIO32(CCU1_BASE + 0x478) + +/* CLK_M4_EMCDIV status register */ +#define CCU1_CLK_M4_EMCDIV_STAT MMIO32(CCU1_BASE + 0x47C) + +/* CLK_M4_M0_CFG configuration register */ +#define CCU1_CLK_M4_M0APP_CFG MMIO32(CCU1_BASE + 0x490) + +/* CLK_M4_M0_STAT status register */ +#define CCU1_CLK_M4_M0APP_STAT MMIO32(CCU1_BASE + 0x494) + +/* CLK_M4_VADC_CFG configuration register */ +#define CCU1_CLK_M4_VADC_CFG MMIO32(CCU1_BASE + 0x498) + +/* CLK_M4_VADC_STAT configuration register */ +#define CCU1_CLK_M4_VADC_STAT MMIO32(CCU1_BASE + 0x49C) + +/* CLK_M4_WWDT configuration register */ +#define CCU1_CLK_M4_WWDT_CFG MMIO32(CCU1_BASE + 0x500) + +/* CLK_M4_WWDT status register */ +#define CCU1_CLK_M4_WWDT_STAT MMIO32(CCU1_BASE + 0x504) + +/* CLK_M4_UART0 configuration register */ +#define CCU1_CLK_M4_USART0_CFG MMIO32(CCU1_BASE + 0x508) + +/* CLK_M4_UART0 status register */ +#define CCU1_CLK_M4_USART0_STAT MMIO32(CCU1_BASE + 0x50C) + +/* CLK_M4_UART1 configuration register */ +#define CCU1_CLK_M4_UART1_CFG MMIO32(CCU1_BASE + 0x510) + +/* CLK_M4_UART1 status register */ +#define CCU1_CLK_M4_UART1_STAT MMIO32(CCU1_BASE + 0x514) + +/* CLK_M4_SSP0 configuration register */ +#define CCU1_CLK_M4_SSP0_CFG MMIO32(CCU1_BASE + 0x518) + +/* CLK_M4_SSP0 status register */ +#define CCU1_CLK_M4_SSP0_STAT MMIO32(CCU1_BASE + 0x51C) + +/* CLK_M4_TIMER0 configuration register */ +#define CCU1_CLK_M4_TIMER0_CFG MMIO32(CCU1_BASE + 0x520) + +/* CLK_M4_TIMER0 status register */ +#define CCU1_CLK_M4_TIMER0_STAT MMIO32(CCU1_BASE + 0x524) + +/* CLK_M4_TIMER1 configuration register */ +#define CCU1_CLK_M4_TIMER1_CFG MMIO32(CCU1_BASE + 0x528) + +/* CLK_M4_TIMER1 status register */ +#define CCU1_CLK_M4_TIMER1_STAT MMIO32(CCU1_BASE + 0x52C) + +/* CLK_M4_SCU configuration register */ +#define CCU1_CLK_M4_SCU_CFG MMIO32(CCU1_BASE + 0x530) + +/* CLK_M4_SCU status register */ +#define CCU1_CLK_M4_SCU_STAT MMIO32(CCU1_BASE + 0x534) + +/* CLK_M4_CREG configuration register */ +#define CCU1_CLK_M4_CREG_CFG MMIO32(CCU1_BASE + 0x538) + +/* CLK_M4_CREG status register */ +#define CCU1_CLK_M4_CREG_STAT MMIO32(CCU1_BASE + 0x53C) + +/* CLK_M4_RITIMER configuration register */ +#define CCU1_CLK_M4_RITIMER_CFG MMIO32(CCU1_BASE + 0x600) + +/* CLK_M4_RITIMER status register */ +#define CCU1_CLK_M4_RITIMER_STAT MMIO32(CCU1_BASE + 0x604) + +/* CLK_M4_UART2 configuration register */ +#define CCU1_CLK_M4_USART2_CFG MMIO32(CCU1_BASE + 0x608) + +/* CLK_M4_UART2 status register */ +#define CCU1_CLK_M4_USART2_STAT MMIO32(CCU1_BASE + 0x60C) + +/* CLK_M4_UART3 configuration register */ +#define CCU1_CLK_M4_USART3_CFG MMIO32(CCU1_BASE + 0x610) + +/* CLK_M4_UART3 status register */ +#define CCU1_CLK_M4_USART3_STAT MMIO32(CCU1_BASE + 0x614) + +/* CLK_M4_TIMER2 configuration register */ +#define CCU1_CLK_M4_TIMER2_CFG MMIO32(CCU1_BASE + 0x618) + +/* CLK_M4_TIMER2 status register */ +#define CCU1_CLK_M4_TIMER2_STAT MMIO32(CCU1_BASE + 0x61C) + +/* CLK_M4_TIMER3 configuration register */ +#define CCU1_CLK_M4_TIMER3_CFG MMIO32(CCU1_BASE + 0x620) + +/* CLK_M4_TIMER3 status register */ +#define CCU1_CLK_M4_TIMER3_STAT MMIO32(CCU1_BASE + 0x624) + +/* CLK_M4_SSP1 configuration register */ +#define CCU1_CLK_M4_SSP1_CFG MMIO32(CCU1_BASE + 0x628) + +/* CLK_M4_SSP1 status register */ +#define CCU1_CLK_M4_SSP1_STAT MMIO32(CCU1_BASE + 0x62C) + +/* CLK_M4_QEI configuration register */ +#define CCU1_CLK_M4_QEI_CFG MMIO32(CCU1_BASE + 0x630) + +/* CLK_M4_QEI status register */ +#define CCU1_CLK_M4_QEI_STAT MMIO32(CCU1_BASE + 0x634) + +/* CLK_PERIPH_BUS configuration register */ +#define CCU1_CLK_PERIPH_BUS_CFG MMIO32(CCU1_BASE + 0x700) + +/* CLK_PERIPH_BUS status register */ +#define CCU1_CLK_PERIPH_BUS_STAT MMIO32(CCU1_BASE + 0x704) + +/* CLK_PERIPH_CORE configuration register */ +#define CCU1_CLK_PERIPH_CORE_CFG MMIO32(CCU1_BASE + 0x710) + +/* CLK_PERIPH_CORE status register */ +#define CCU1_CLK_PERIPH_CORE_STAT MMIO32(CCU1_BASE + 0x714) + +/* CLK_PERIPH_SGPIO configuration register */ +#define CCU1_CLK_PERIPH_SGPIO_CFG MMIO32(CCU1_BASE + 0x718) + +/* CLK_PERIPH_SGPIO status register */ +#define CCU1_CLK_PERIPH_SGPIO_STAT MMIO32(CCU1_BASE + 0x71C) + +/* CLK_USB0 configuration register */ +#define CCU1_CLK_USB0_CFG MMIO32(CCU1_BASE + 0x800) + +/* CLK_USB0 status register */ +#define CCU1_CLK_USB0_STAT MMIO32(CCU1_BASE + 0x804) + +/* CLK_USB1 configuration register */ +#define CCU1_CLK_USB1_CFG MMIO32(CCU1_BASE + 0x900) + +/* CLK_USB1 status register */ +#define CCU1_CLK_USB1_STAT MMIO32(CCU1_BASE + 0x904) + +/* CLK_SPI configuration register */ +#define CCU1_CLK_SPI_CFG MMIO32(CCU1_BASE + 0xA00) + +/* CLK_SPI status register */ +#define CCU1_CLK_SPI_STAT MMIO32(CCU1_BASE + 0xA04) + +/* CLK_VADC configuration register */ +#define CCU1_CLK_VADC_CFG MMIO32(CCU1_BASE + 0xB00) + +/* CLK_VADC status register */ +#define CCU1_CLK_VADC_STAT MMIO32(CCU1_BASE + 0xB04) + +/* --- CCU2 registers ------------------------------------------------------ */ + +/* CCU2 power mode register */ +#define CCU2_PM MMIO32(CCU2_BASE + 0x000) + +/* CCU2 base clocks status register */ +#define CCU2_BASE_STAT MMIO32(CCU2_BASE + 0x004) + +/* CLK_APLL configuration register */ +#define CCU2_CLK_APLL_CFG MMIO32(CCU2_BASE + 0x100) + +/* CLK_APLL status register */ +#define CCU2_CLK_APLL_STAT MMIO32(CCU2_BASE + 0x104) + +/* CLK_APB2_UART3 configuration register */ +#define CCU2_CLK_APB2_USART3_CFG MMIO32(CCU2_BASE + 0x200) + +/* CLK_APB2_UART3 status register */ +#define CCU2_CLK_APB2_USART3_STAT MMIO32(CCU2_BASE + 0x204) + +/* CLK_APB2_UART2 configuration register */ +#define CCU2_CLK_APB2_USART2_CFG MMIO32(CCU2_BASE + 0x300) + +/* CLK_APB2_UART2 status register */ +#define CCU2_CLK_APB2_USART2_STAT MMIO32(CCU2_BASE + 0x304) + +/* CLK_APB0_UART1 configuration register */ +#define CCU2_CLK_APB0_UART1_CFG MMIO32(CCU2_BASE + 0x400) + +/* CLK_APB0_UART1 status register */ +#define CCU2_CLK_APB0_UART1_STAT MMIO32(CCU2_BASE + 0x404) + +/* CLK_APB0_UART0 configuration register */ +#define CCU2_CLK_APB0_USART0_CFG MMIO32(CCU2_BASE + 0x500) + +/* CLK_APB0_UART0 status register */ +#define CCU2_CLK_APB0_USART0_STAT MMIO32(CCU2_BASE + 0x504) + +/* CLK_APB2_SSP1 configuration register */ +#define CCU2_CLK_APB2_SSP1_CFG MMIO32(CCU2_BASE + 0x600) + +/* CLK_APB2_SSP1 status register */ +#define CCU2_CLK_APB2_SSP1_STAT MMIO32(CCU2_BASE + 0x604) + +/* CLK_APB0_SSP0 configuration register */ +#define CCU2_CLK_APB0_SSP0_CFG MMIO32(CCU2_BASE + 0x700) + +/* CLK_APB0_SSP0 status register */ +#define CCU2_CLK_APB0_SSP0_STAT MMIO32(CCU2_BASE + 0x704) + +/* CLK_SDIO configuration register (for SD/MMC) */ +#define CCU2_CLK_SDIO_CFG MMIO32(CCU2_BASE + 0x800) + +/* CLK_SDIO status register (for SD/MMC) */ +#define CCU2_CLK_SDIO_STAT MMIO32(CCU2_BASE + 0x804) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/cgu.h b/libopencm3/include/libopencm3/lpc43xx/cgu.h new file mode 100644 index 0000000..0a169fd --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/cgu.h @@ -0,0 +1,964 @@ +/** @defgroup cgu_defines Clock Generation Unit Defines + * + * @brief Defined Constants and Types for the LPC43xx Clock Generation + * Unit + * + * @ingroup LPC43xx_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2012 Michael Ossmann + * + * + * @date 10 March 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC43XX_CGU_H +#define CGU_LPC43XX_CGU_H + +/**@{*/ + +#include +#include + +/* --- CGU registers ------------------------------------------------------- */ + +/* Frequency monitor register */ +#define CGU_FREQ_MON MMIO32(CGU_BASE + 0x014) + +/* Crystal oscillator control register */ +#define CGU_XTAL_OSC_CTRL MMIO32(CGU_BASE + 0x018) + +/* PLL0USB status register */ +#define CGU_PLL0USB_STAT MMIO32(CGU_BASE + 0x01C) + +/* PLL0USB control register */ +#define CGU_PLL0USB_CTRL MMIO32(CGU_BASE + 0x020) + +/* PLL0USB M-divider register */ +#define CGU_PLL0USB_MDIV MMIO32(CGU_BASE + 0x024) + +/* PLL0USB N/P-divider register */ +#define CGU_PLL0USB_NP_DIV MMIO32(CGU_BASE + 0x028) + +/* PLL0AUDIO status register */ +#define CGU_PLL0AUDIO_STAT MMIO32(CGU_BASE + 0x02C) + +/* PLL0AUDIO control register */ +#define CGU_PLL0AUDIO_CTRL MMIO32(CGU_BASE + 0x030) + +/* PLL0AUDIO M-divider register */ +#define CGU_PLL0AUDIO_MDIV MMIO32(CGU_BASE + 0x034) + +/* PLL0AUDIO N/P-divider register */ +#define CGU_PLL0AUDIO_NP_DIV MMIO32(CGU_BASE + 0x038) + +/* PLL0AUDIO fractional divider register */ +#define CGU_PLLAUDIO_FRAC MMIO32(CGU_BASE + 0x03C) + +/* PLL1 status register */ +#define CGU_PLL1_STAT MMIO32(CGU_BASE + 0x040) + +/* PLL1 control register */ +#define CGU_PLL1_CTRL MMIO32(CGU_BASE + 0x044) + +/* Integer divider A control register */ +#define CGU_IDIVA_CTRL MMIO32(CGU_BASE + 0x048) + +/* Integer divider B control register */ +#define CGU_IDIVB_CTRL MMIO32(CGU_BASE + 0x04C) + +/* Integer divider C control register */ +#define CGU_IDIVC_CTRL MMIO32(CGU_BASE + 0x050) + +/* Integer divider D control register */ +#define CGU_IDIVD_CTRL MMIO32(CGU_BASE + 0x054) + +/* Integer divider E control register */ +#define CGU_IDIVE_CTRL MMIO32(CGU_BASE + 0x058) + +/* Output stage 0 control register */ +#define CGU_BASE_SAFE_CLK MMIO32(CGU_BASE + 0x05C) + +/* Output stage 1 control register for base clock */ +#define CGU_BASE_USB0_CLK MMIO32(CGU_BASE + 0x060) + +/* Output stage 2 control register for base clock */ +#define CGU_BASE_PERIPH_CLK MMIO32(CGU_BASE + 0x064) + +/* Output stage 3 control register for base clock */ +#define CGU_BASE_USB1_CLK MMIO32(CGU_BASE + 0x068) + +/* Output stage 4 control register for base clock */ +#define CGU_BASE_M4_CLK MMIO32(CGU_BASE + 0x06C) + +/* Output stage 5 control register for base clock */ +#define CGU_BASE_SPIFI_CLK MMIO32(CGU_BASE + 0x070) + +/* Output stage 6 control register for base clock */ +#define CGU_BASE_SPI_CLK MMIO32(CGU_BASE + 0x074) + +/* Output stage 7 control register for base clock */ +#define CGU_BASE_PHY_RX_CLK MMIO32(CGU_BASE + 0x078) + +/* Output stage 8 control register for base clock */ +#define CGU_BASE_PHY_TX_CLK MMIO32(CGU_BASE + 0x07C) + +/* Output stage 9 control register for base clock */ +#define CGU_BASE_APB1_CLK MMIO32(CGU_BASE + 0x080) + +/* Output stage 10 control register for base clock */ +#define CGU_BASE_APB3_CLK MMIO32(CGU_BASE + 0x084) + +/* Output stage 11 control register for base clock */ +#define CGU_BASE_LCD_CLK MMIO32(CGU_BASE + 0x088) + +/* Output stage 12 control register for base clock */ +#define CGU_BASE_VADC_CLK MMIO32(CGU_BASE + 0x08C) + +/* Output stage 13 control register for base clock */ +#define CGU_BASE_SDIO_CLK MMIO32(CGU_BASE + 0x090) + +/* Output stage 14 control register for base clock */ +#define CGU_BASE_SSP0_CLK MMIO32(CGU_BASE + 0x094) + +/* Output stage 15 control register for base clock */ +#define CGU_BASE_SSP1_CLK MMIO32(CGU_BASE + 0x098) + +/* Output stage 16 control register for base clock */ +#define CGU_BASE_UART0_CLK MMIO32(CGU_BASE + 0x09C) + +/* Output stage 17 control register for base clock */ +#define CGU_BASE_UART1_CLK MMIO32(CGU_BASE + 0x0A0) + +/* Output stage 18 control register for base clock */ +#define CGU_BASE_UART2_CLK MMIO32(CGU_BASE + 0x0A4) + +/* Output stage 19 control register for base clock */ +#define CGU_BASE_UART3_CLK MMIO32(CGU_BASE + 0x0A8) + +/* Output stage 20 control register for base clock */ +#define CGU_BASE_OUT_CLK MMIO32(CGU_BASE + 0x0AC) + +/* Reserved output stage */ +#define CGU_OUTCLK_21_CTRL MMIO32(CGU_BASE + 0x0B0) + +/* Reserved output stage */ +#define CGU_OUTCLK_22_CTRL MMIO32(CGU_BASE + 0x0B4) + +/* Reserved output stage */ +#define CGU_OUTCLK_23_CTRL MMIO32(CGU_BASE + 0x0B8) + +/* Reserved output stage */ +#define CGU_OUTCLK_24_CTRL MMIO32(CGU_BASE + 0x0BC) + +/* Output stage 25 control register for base clock */ +#define CGU_BASE_APLL_CLK MMIO32(CGU_BASE + 0x0C0) + +/* Output stage 26 control CLK register for base clock */ +#define CGU_BASE_CGU_OUT0_CLK MMIO32(CGU_BASE + 0x0C4) + +/* Output stage 27 control CLK register for base clock */ +#define CGU_BASE_CGU_OUT1_CLK MMIO32(CGU_BASE + 0x0C8) + +/* --- CGU_FREQ_MON values -------------------------------------- */ + +/* RCNT: 9-bit reference clock-counter value */ +#define CGU_FREQ_MON_RCNT_SHIFT (0) +#define CGU_FREQ_MON_RCNT_MASK (0x1ff << CGU_FREQ_MON_RCNT_SHIFT) +#define CGU_FREQ_MON_RCNT(x) ((x) << CGU_FREQ_MON_RCNT_SHIFT) + +/* FCNT: 14-bit selected clock-counter value */ +#define CGU_FREQ_MON_FCNT_SHIFT (9) +#define CGU_FREQ_MON_FCNT_MASK (0x3fff << CGU_FREQ_MON_FCNT_SHIFT) +#define CGU_FREQ_MON_FCNT(x) ((x) << CGU_FREQ_MON_FCNT_SHIFT) + +/* MEAS: Measure frequency */ +#define CGU_FREQ_MON_MEAS_SHIFT (23) +#define CGU_FREQ_MON_MEAS (1 << CGU_FREQ_MON_MEAS_SHIFT) + +/* CLK_SEL: Clock-source selection for the clock to be measured */ +#define CGU_FREQ_MON_CLK_SEL_SHIFT (24) +#define CGU_FREQ_MON_CLK_SEL_MASK (0x1f << CGU_FREQ_MON_CLK_SEL_SHIFT) +#define CGU_FREQ_MON_CLK_SEL(x) ((x) << CGU_FREQ_MON_CLK_SEL_SHIFT) + +/* --- CGU_XTAL_OSC_CTRL values --------------------------------- */ + +/* ENABLE: Oscillator-pad enable */ +#define CGU_XTAL_OSC_CTRL_ENABLE_SHIFT (0) +#define CGU_XTAL_OSC_CTRL_ENABLE (1 << CGU_XTAL_OSC_CTRL_ENABLE_SHIFT) + +/* BYPASS: Configure crystal operation or external-clock input pin XTAL1 */ +#define CGU_XTAL_OSC_CTRL_BYPASS_SHIFT (1) +#define CGU_XTAL_OSC_CTRL_BYPASS (1 << CGU_XTAL_OSC_CTRL_BYPASS_SHIFT) + +/* HF: Select frequency range */ +#define CGU_XTAL_OSC_CTRL_HF_SHIFT (2) +#define CGU_XTAL_OSC_CTRL_HF (1 << CGU_XTAL_OSC_CTRL_HF_SHIFT) + +/* --- CGU_PLL0USB_STAT values ---------------------------------- */ + +/* LOCK: PLL0 lock indicator */ +#define CGU_PLL0USB_STAT_LOCK_SHIFT (0) +#define CGU_PLL0USB_STAT_LOCK (1 << CGU_PLL0USB_STAT_LOCK_SHIFT) + +/* FR: PLL0 free running indicator */ +#define CGU_PLL0USB_STAT_FR_SHIFT (1) +#define CGU_PLL0USB_STAT_FR (1 << CGU_PLL0USB_STAT_FR_SHIFT) + +/* --- CGU_PLL0USB_CTRL values ---------------------------------- */ + +/* PD: PLL0 power down */ +#define CGU_PLL0USB_CTRL_PD_SHIFT (0) +#define CGU_PLL0USB_CTRL_PD (1 << CGU_PLL0USB_CTRL_PD_SHIFT) + +/* BYPASS: Input clock bypass control */ +#define CGU_PLL0USB_CTRL_BYPASS_SHIFT (1) +#define CGU_PLL0USB_CTRL_BYPASS (1 << CGU_PLL0USB_CTRL_BYPASS_SHIFT) + +/* DIRECTI: PLL0 direct input */ +#define CGU_PLL0USB_CTRL_DIRECTI_SHIFT (2) +#define CGU_PLL0USB_CTRL_DIRECTI (1 << CGU_PLL0USB_CTRL_DIRECTI_SHIFT) + +/* DIRECTO: PLL0 direct output */ +#define CGU_PLL0USB_CTRL_DIRECTO_SHIFT (3) +#define CGU_PLL0USB_CTRL_DIRECTO (1 << CGU_PLL0USB_CTRL_DIRECTO_SHIFT) + +/* CLKEN: PLL0 clock enable */ +#define CGU_PLL0USB_CTRL_CLKEN_SHIFT (4) +#define CGU_PLL0USB_CTRL_CLKEN (1 << CGU_PLL0USB_CTRL_CLKEN_SHIFT) + +/* FRM: Free running mode */ +#define CGU_PLL0USB_CTRL_FRM_SHIFT (6) +#define CGU_PLL0USB_CTRL_FRM (1 << CGU_PLL0USB_CTRL_FRM_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_PLL0USB_CTRL_AUTOBLOCK (1 << CGU_PLL0USB_CTRL_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_PLL0USB_CTRL_CLK_SEL_SHIFT (24) +#define CGU_PLL0USB_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT) +#define CGU_PLL0USB_CTRL_CLK_SEL(x) ((x) << CGU_PLL0USB_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_PLL0USB_MDIV values ---------------------------------- */ + +/* MDEC: Decoded M-divider coefficient value */ +#define CGU_PLL0USB_MDIV_MDEC_SHIFT (0) +#define CGU_PLL0USB_MDIV_MDEC_MASK (0x1ffff << CGU_PLL0USB_MDIV_MDEC_SHIFT) +#define CGU_PLL0USB_MDIV_MDEC(x) ((x) << CGU_PLL0USB_MDIV_MDEC_SHIFT) + +/* SELP: Bandwidth select P value */ +#define CGU_PLL0USB_MDIV_SELP_SHIFT (17) +#define CGU_PLL0USB_MDIV_SELP_MASK (0x1f << CGU_PLL0USB_MDIV_SELP_SHIFT) +#define CGU_PLL0USB_MDIV_SELP(x) ((x) << CGU_PLL0USB_MDIV_SELP_SHIFT) + +/* SELI: Bandwidth select I value */ +#define CGU_PLL0USB_MDIV_SELI_SHIFT (22) +#define CGU_PLL0USB_MDIV_SELI_MASK (0x3f << CGU_PLL0USB_MDIV_SELI_SHIFT) +#define CGU_PLL0USB_MDIV_SELI(x) ((x) << CGU_PLL0USB_MDIV_SELI_SHIFT) + +/* SELR: Bandwidth select R value */ +#define CGU_PLL0USB_MDIV_SELR_SHIFT (28) +#define CGU_PLL0USB_MDIV_SELR_MASK (0xf << CGU_PLL0USB_MDIV_SELR_SHIFT) +#define CGU_PLL0USB_MDIV_SELR(x) ((x) << CGU_PLL0USB_MDIV_SELR_SHIFT) + +/* --- CGU_PLL0USB_NP_DIV values -------------------------------- */ + +/* PDEC: Decoded P-divider coefficient value */ +#define CGU_PLL0USB_NP_DIV_PDEC_SHIFT (0) +#define CGU_PLL0USB_NP_DIV_PDEC_MASK (0x7f << CGU_PLL0USB_NP_DIV_PDEC_SHIFT) +#define CGU_PLL0USB_NP_DIV_PDEC(x) ((x) << CGU_PLL0USB_NP_DIV_PDEC_SHIFT) + +/* NDEC: Decoded N-divider coefficient value */ +#define CGU_PLL0USB_NP_DIV_NDEC_SHIFT (12) +#define CGU_PLL0USB_NP_DIV_NDEC_MASK (0x3ff << CGU_PLL0USB_NP_DIV_NDEC_SHIFT) +#define CGU_PLL0USB_NP_DIV_NDEC(x) ((x) << CGU_PLL0USB_NP_DIV_NDEC_SHIFT) + +/* --- CGU_PLL0AUDIO_STAT values -------------------------------- */ + +/* LOCK: PLL0 lock indicator */ +#define CGU_PLL0AUDIO_STAT_LOCK_SHIFT (0) +#define CGU_PLL0AUDIO_STAT_LOCK (1 << CGU_PLL0AUDIO_STAT_LOCK_SHIFT) + +/* FR: PLL0 free running indicator */ +#define CGU_PLL0AUDIO_STAT_FR_SHIFT (1) +#define CGU_PLL0AUDIO_STAT_FR (1 << CGU_PLL0AUDIO_STAT_FR_SHIFT) + +/* --- CGU_PLL0AUDIO_CTRL values -------------------------------- */ + +/* PD: PLL0 power down */ +#define CGU_PLL0AUDIO_CTRL_PD_SHIFT (0) +#define CGU_PLL0AUDIO_CTRL_PD (1 << CGU_PLL0AUDIO_CTRL_PD_SHIFT) + +/* BYPASS: Input clock bypass control */ +#define CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT (1) +#define CGU_PLL0AUDIO_CTRL_BYPASS (1 << CGU_PLL0AUDIO_CTRL_BYPASS_SHIFT) + +/* DIRECTI: PLL0 direct input */ +#define CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT (2) +#define CGU_PLL0AUDIO_CTRL_DIRECTI (1 << CGU_PLL0AUDIO_CTRL_DIRECTI_SHIFT) + +/* DIRECTO: PLL0 direct output */ +#define CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT (3) +#define CGU_PLL0AUDIO_CTRL_DIRECTO (1 << CGU_PLL0AUDIO_CTRL_DIRECTO_SHIFT) + +/* CLKEN: PLL0 clock enable */ +#define CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT (4) +#define CGU_PLL0AUDIO_CTRL_CLKEN (1 << CGU_PLL0AUDIO_CTRL_CLKEN_SHIFT) + +/* FRM: Free running mode */ +#define CGU_PLL0AUDIO_CTRL_FRM_SHIFT (6) +#define CGU_PLL0AUDIO_CTRL_FRM (1 << CGU_PLL0AUDIO_CTRL_FRM_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_PLL0AUDIO_CTRL_AUTOBLOCK \ + (1 << CGU_PLL0AUDIO_CTRL_AUTOBLOCK_SHIFT) + +/* PLLFRACT_REQ: Fractional PLL word write request */ +#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT (12) +#define CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ \ + (1 << CGU_PLL0AUDIO_CTRL_PLLFRACT_REQ_SHIFT) + +/* SEL_EXT: Select fractional divider */ +#define CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT (13) +#define CGU_PLL0AUDIO_CTRL_SEL_EXT (1 << CGU_PLL0AUDIO_CTRL_SEL_EXT_SHIFT) + +/* MOD_PD: Sigma-Delta modulator power-down */ +#define CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT (14) +#define CGU_PLL0AUDIO_CTRL_MOD_PD (1 << CGU_PLL0AUDIO_CTRL_MOD_PD_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT (24) +#define CGU_PLL0AUDIO_CTRL_CLK_SEL_MASK \ + (0x1f << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT) +#define CGU_PLL0AUDIO_CTRL_CLK_SEL(x) \ + ((x) << CGU_PLL0AUDIO_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_PLL0AUDIO_MDIV values -------------------------------- */ + +/* MDEC: Decoded M-divider coefficient value */ +#define CGU_PLL0AUDIO_MDIV_MDEC_SHIFT (0) +#define CGU_PLL0AUDIO_MDIV_MDEC_MASK \ + (0x1ffff << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT) +#define CGU_PLL0AUDIO_MDIV_MDEC(x) \ + ((x) << CGU_PLL0AUDIO_MDIV_MDEC_SHIFT) + +/* --- CGU_PLL0AUDIO_NP_DIV values ------------------------------ */ + +/* PDEC: Decoded P-divider coefficient value */ +#define CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT (0) +#define CGU_PLL0AUDIO_NP_DIV_PDEC_MASK \ + (0x7f << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT) +#define CGU_PLL0AUDIO_NP_DIV_PDEC(x) \ + ((x) << CGU_PLL0AUDIO_NP_DIV_PDEC_SHIFT) + +/* NDEC: Decoded N-divider coefficient value */ +#define CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT (12) +#define CGU_PLL0AUDIO_NP_DIV_NDEC_MASK \ + (0x3ff << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT) +#define CGU_PLL0AUDIO_NP_DIV_NDEC(x) \ + ((x) << CGU_PLL0AUDIO_NP_DIV_NDEC_SHIFT) + +/* --- CGU_PLLAUDIO_FRAC values --------------------------------- */ + +/* PLLFRACT_CTRL: PLL fractional divider control word */ +#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT (0) +#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_MASK \ + (0x3fffff << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT) +#define CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL(x) \ + ((x) << CGU_PLLAUDIO_FRAC_PLLFRACT_CTRL_SHIFT) + +/* --- CGU_PLL1_STAT values ------------------------------------- */ + +/* LOCK: PLL1 lock indicator */ +#define CGU_PLL1_STAT_LOCK_SHIFT (0) +#define CGU_PLL1_STAT_LOCK (1 << CGU_PLL1_STAT_LOCK_SHIFT) + +/* --- CGU_PLL1_CTRL values ------------------------------------- */ + +/* PD: PLL1 power down */ +#define CGU_PLL1_CTRL_PD_SHIFT (0) +#define CGU_PLL1_CTRL_PD (1 << CGU_PLL1_CTRL_PD_SHIFT) + +/* BYPASS: Input clock bypass control */ +#define CGU_PLL1_CTRL_BYPASS_SHIFT (1) +#define CGU_PLL1_CTRL_BYPASS (1 << CGU_PLL1_CTRL_BYPASS_SHIFT) + +/* FBSEL: PLL feedback select */ +#define CGU_PLL1_CTRL_FBSEL_SHIFT (6) +#define CGU_PLL1_CTRL_FBSEL (1 << CGU_PLL1_CTRL_FBSEL_SHIFT) + +/* DIRECT: PLL direct CCO output */ +#define CGU_PLL1_CTRL_DIRECT_SHIFT (7) +#define CGU_PLL1_CTRL_DIRECT (1 << CGU_PLL1_CTRL_DIRECT_SHIFT) + +/* PSEL: Post-divider division ratio P */ +#define CGU_PLL1_CTRL_PSEL_SHIFT (8) +#define CGU_PLL1_CTRL_PSEL_MASK (0x3 << CGU_PLL1_CTRL_PSEL_SHIFT) +#define CGU_PLL1_CTRL_PSEL(x) ((x) << CGU_PLL1_CTRL_PSEL_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_PLL1_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_PLL1_CTRL_AUTOBLOCK (1 << CGU_PLL1_CTRL_AUTOBLOCK_SHIFT) + +/* NSEL: Pre-divider division ratio N */ +#define CGU_PLL1_CTRL_NSEL_SHIFT (12) +#define CGU_PLL1_CTRL_NSEL_MASK (0x3 << CGU_PLL1_CTRL_NSEL_SHIFT) +#define CGU_PLL1_CTRL_NSEL(x) ((x) << CGU_PLL1_CTRL_NSEL_SHIFT) + +/* MSEL: Feedback-divider division ratio (M) */ +#define CGU_PLL1_CTRL_MSEL_SHIFT (16) +#define CGU_PLL1_CTRL_MSEL_MASK (0xff << CGU_PLL1_CTRL_MSEL_SHIFT) +#define CGU_PLL1_CTRL_MSEL(x) ((x) << CGU_PLL1_CTRL_MSEL_SHIFT) + +/* CLK_SEL: Clock-source selection */ +#define CGU_PLL1_CTRL_CLK_SEL_SHIFT (24) +#define CGU_PLL1_CTRL_CLK_SEL_MASK (0x1f << CGU_PLL1_CTRL_CLK_SEL_SHIFT) +#define CGU_PLL1_CTRL_CLK_SEL(x) ((x) << CGU_PLL1_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_IDIVA_CTRL values ------------------------------------ */ + +/* PD: Integer divider power down */ +#define CGU_IDIVA_CTRL_PD_SHIFT (0) +#define CGU_IDIVA_CTRL_PD (1 << CGU_IDIVA_CTRL_PD_SHIFT) + +/* IDIV: Integer divider A divider value (1/(IDIV + 1)) */ +#define CGU_IDIVA_CTRL_IDIV_SHIFT (2) +#define CGU_IDIVA_CTRL_IDIV_MASK (0x3 << CGU_IDIVA_CTRL_IDIV_SHIFT) +#define CGU_IDIVA_CTRL_IDIV(x) ((x) << CGU_IDIVA_CTRL_IDIV_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_IDIVA_CTRL_AUTOBLOCK (1 << CGU_IDIVA_CTRL_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_IDIVA_CTRL_CLK_SEL_SHIFT (24) +#define CGU_IDIVA_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVA_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVA_CTRL_CLK_SEL(x) ((x) << CGU_IDIVA_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_IDIVB_CTRL values ------------------------------------ */ + +/* PD: Integer divider power down */ +#define CGU_IDIVB_CTRL_PD_SHIFT (0) +#define CGU_IDIVB_CTRL_PD (1 << CGU_IDIVB_CTRL_PD_SHIFT) + +/* IDIV: Integer divider B divider value (1/(IDIV + 1)) */ +#define CGU_IDIVB_CTRL_IDIV_SHIFT (2) +#define CGU_IDIVB_CTRL_IDIV_MASK (0xf << CGU_IDIVB_CTRL_IDIV_SHIFT) +#define CGU_IDIVB_CTRL_IDIV(x) ((x) << CGU_IDIVB_CTRL_IDIV_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_IDIVB_CTRL_AUTOBLOCK (1 << CGU_IDIVB_CTRL_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_IDIVB_CTRL_CLK_SEL_SHIFT (24) +#define CGU_IDIVB_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVB_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVB_CTRL_CLK_SEL(x) ((x) << CGU_IDIVB_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_IDIVC_CTRL values ------------------------------------ */ + +/* PD: Integer divider power down */ +#define CGU_IDIVC_CTRL_PD_SHIFT (0) +#define CGU_IDIVC_CTRL_PD (1 << CGU_IDIVC_CTRL_PD_SHIFT) + +/* IDIV: Integer divider C divider value (1/(IDIV + 1)) */ +#define CGU_IDIVC_CTRL_IDIV_SHIFT (2) +#define CGU_IDIVC_CTRL_IDIV_MASK (0xf << CGU_IDIVC_CTRL_IDIV_SHIFT) +#define CGU_IDIVC_CTRL_IDIV(x) ((x) << CGU_IDIVC_CTRL_IDIV_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_IDIVC_CTRL_AUTOBLOCK (1 << CGU_IDIVC_CTRL_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_IDIVC_CTRL_CLK_SEL_SHIFT (24) +#define CGU_IDIVC_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVC_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVC_CTRL_CLK_SEL(x) ((x) << CGU_IDIVC_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_IDIVD_CTRL values ------------------------------------ */ + +/* PD: Integer divider power down */ +#define CGU_IDIVD_CTRL_PD_SHIFT (0) +#define CGU_IDIVD_CTRL_PD (1 << CGU_IDIVD_CTRL_PD_SHIFT) + +/* IDIV: Integer divider D divider value (1/(IDIV + 1)) */ +#define CGU_IDIVD_CTRL_IDIV_SHIFT (2) +#define CGU_IDIVD_CTRL_IDIV_MASK (0xf << CGU_IDIVD_CTRL_IDIV_SHIFT) +#define CGU_IDIVD_CTRL_IDIV(x) ((x) << CGU_IDIVD_CTRL_IDIV_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_IDIVD_CTRL_AUTOBLOCK (1 << CGU_IDIVD_CTRL_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_IDIVD_CTRL_CLK_SEL_SHIFT (24) +#define CGU_IDIVD_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVD_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVD_CTRL_CLK_SEL(x) ((x) << CGU_IDIVD_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_IDIVE_CTRL values ------------------------------------ */ + +/* PD: Integer divider power down */ +#define CGU_IDIVE_CTRL_PD_SHIFT (0) +#define CGU_IDIVE_CTRL_PD (1 << CGU_IDIVE_CTRL_PD_SHIFT) + +/* IDIV: Integer divider E divider value (1/(IDIV + 1)) */ +#define CGU_IDIVE_CTRL_IDIV_SHIFT (2) +#define CGU_IDIVE_CTRL_IDIV_MASK (0xff << CGU_IDIVE_CTRL_IDIV_SHIFT) +#define CGU_IDIVE_CTRL_IDIV(x) ((x) << CGU_IDIVE_CTRL_IDIV_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT (11) +#define CGU_IDIVE_CTRL_AUTOBLOCK (1 << CGU_IDIVE_CTRL_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_IDIVE_CTRL_CLK_SEL_SHIFT (24) +#define CGU_IDIVE_CTRL_CLK_SEL_MASK (0x1f << CGU_IDIVE_CTRL_CLK_SEL_SHIFT) +#define CGU_IDIVE_CTRL_CLK_SEL(x) ((x) << CGU_IDIVE_CTRL_CLK_SEL_SHIFT) + +/* --- CGU_BASE_SAFE_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_SAFE_CLK_PD_SHIFT (0) +#define CGU_BASE_SAFE_CLK_PD (1 << CGU_BASE_SAFE_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_SAFE_CLK_AUTOBLOCK (1 << CGU_BASE_SAFE_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_SAFE_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SAFE_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_SAFE_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_USB0_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_USB0_CLK_PD_SHIFT (0) +#define CGU_BASE_USB0_CLK_PD (1 << CGU_BASE_USB0_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_USB0_CLK_AUTOBLOCK (1 << CGU_BASE_USB0_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_USB0_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_USB0_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_USB0_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_USB0_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_PERIPH_CLK values ------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_PERIPH_CLK_PD_SHIFT (0) +#define CGU_BASE_PERIPH_CLK_PD (1 << CGU_BASE_PERIPH_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_PERIPH_CLK_AUTOBLOCK \ + (1 << CGU_BASE_PERIPH_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_PERIPH_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_PERIPH_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_PERIPH_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_USB1_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_USB1_CLK_PD_SHIFT (0) +#define CGU_BASE_USB1_CLK_PD (1 << CGU_BASE_USB1_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_USB1_CLK_AUTOBLOCK (1 << CGU_BASE_USB1_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_USB1_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_USB1_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_USB1_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_USB1_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_M4_CLK values ----------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_M4_CLK_PD_SHIFT (0) +#define CGU_BASE_M4_CLK_PD (1 << CGU_BASE_M4_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_M4_CLK_AUTOBLOCK (1 << CGU_BASE_M4_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_M4_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_M4_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_M4_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_M4_CLK_CLK_SEL(x) ((x) << CGU_BASE_M4_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_SPIFI_CLK values -------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_SPIFI_CLK_PD_SHIFT (0) +#define CGU_BASE_SPIFI_CLK_PD (1 << CGU_BASE_SPIFI_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_SPIFI_CLK_AUTOBLOCK \ + (1 << CGU_BASE_SPIFI_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_SPIFI_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SPIFI_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_SPIFI_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_SPI_CLK values ---------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_SPI_CLK_PD_SHIFT (0) +#define CGU_BASE_SPI_CLK_PD (1 << CGU_BASE_SPI_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_SPI_CLK_AUTOBLOCK (1 << CGU_BASE_SPI_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_SPI_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_SPI_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SPI_CLK_CLK_SEL(x) ((x) << CGU_BASE_SPI_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_PHY_RX_CLK values ------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_PHY_RX_CLK_PD_SHIFT (0) +#define CGU_BASE_PHY_RX_CLK_PD (1 << CGU_BASE_PHY_RX_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_PHY_RX_CLK_AUTOBLOCK \ + (1 << CGU_BASE_PHY_RX_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_PHY_RX_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_PHY_RX_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_PHY_RX_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_PHY_TX_CLK values ------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_PHY_TX_CLK_PD_SHIFT (0) +#define CGU_BASE_PHY_TX_CLK_PD (1 << CGU_BASE_PHY_TX_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_PHY_TX_CLK_AUTOBLOCK \ + (1 << CGU_BASE_PHY_TX_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_PHY_TX_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_PHY_TX_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_PHY_TX_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_APB1_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_APB1_CLK_PD_SHIFT (0) +#define CGU_BASE_APB1_CLK_PD (1 << CGU_BASE_APB1_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_APB1_CLK_AUTOBLOCK (1 << CGU_BASE_APB1_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_APB1_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_APB1_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_APB1_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB1_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_APB3_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_APB3_CLK_PD_SHIFT (0) +#define CGU_BASE_APB3_CLK_PD (1 << CGU_BASE_APB3_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_APB3_CLK_AUTOBLOCK (1 << CGU_BASE_APB3_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_APB3_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_APB3_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_APB3_CLK_CLK_SEL(x) ((x) << CGU_BASE_APB3_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_LCD_CLK values ---------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_LCD_CLK_PD_SHIFT (0) +#define CGU_BASE_LCD_CLK_PD (1 << CGU_BASE_LCD_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_LCD_CLK_AUTOBLOCK (1 << CGU_BASE_LCD_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_LCD_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_LCD_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_LCD_CLK_CLK_SEL(x) ((x) << CGU_BASE_LCD_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_VADC_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_VADC_CLK_PD_SHIFT (0) +#define CGU_BASE_VADC_CLK_PD (1 << CGU_BASE_VADC_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_VADC_CLK_AUTOBLOCK (1 << CGU_BASE_VADC_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_VADC_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_VADC_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_VADC_CLK_CLK_SEL(x) ((x) << CGU_BASE_VADC_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_SDIO_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_SDIO_CLK_PD_SHIFT (0) +#define CGU_BASE_SDIO_CLK_PD (1 << CGU_BASE_SDIO_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_SDIO_CLK_AUTOBLOCK (1 << CGU_BASE_SDIO_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_SDIO_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SDIO_CLK_CLK_SEL(x) ((x) << CGU_BASE_SDIO_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_SSP0_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_SSP0_CLK_PD_SHIFT (0) +#define CGU_BASE_SSP0_CLK_PD (1 << CGU_BASE_SSP0_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_SSP0_CLK_AUTOBLOCK (1 << CGU_BASE_SSP0_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_SSP0_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SSP0_CLK_CLK_SEL(x) ((x) << CGU_BASE_SSP0_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_SSP1_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_SSP1_CLK_PD_SHIFT (0) +#define CGU_BASE_SSP1_CLK_PD (1 << CGU_BASE_SSP1_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_SSP1_CLK_AUTOBLOCK (1 << CGU_BASE_SSP1_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_SSP1_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_SSP1_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_SSP1_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_UART0_CLK values -------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_UART0_CLK_PD_SHIFT (0) +#define CGU_BASE_UART0_CLK_PD (1 << CGU_BASE_UART0_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_UART0_CLK_AUTOBLOCK \ + (1 << CGU_BASE_UART0_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_UART0_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_UART0_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_UART0_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_UART0_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_UART1_CLK values -------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_UART1_CLK_PD_SHIFT (0) +#define CGU_BASE_UART1_CLK_PD (1 << CGU_BASE_UART1_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_UART1_CLK_AUTOBLOCK \ + (1 << CGU_BASE_UART1_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_UART1_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_UART1_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_UART1_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_UART1_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_UART2_CLK values -------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_UART2_CLK_PD_SHIFT (0) +#define CGU_BASE_UART2_CLK_PD (1 << CGU_BASE_UART2_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_UART2_CLK_AUTOBLOCK \ + (1 << CGU_BASE_UART2_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_UART2_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_UART2_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_UART2_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_UART2_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_UART3_CLK values -------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_UART3_CLK_PD_SHIFT (0) +#define CGU_BASE_UART3_CLK_PD (1 << CGU_BASE_UART3_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_UART3_CLK_AUTOBLOCK \ + (1 << CGU_BASE_UART3_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_UART3_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_UART3_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_UART3_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_UART3_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_OUT_CLK values ---------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_OUT_CLK_PD_SHIFT (0) +#define CGU_BASE_OUT_CLK_PD (1 << CGU_BASE_OUT_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_OUT_CLK_AUTOBLOCK (1 << CGU_BASE_OUT_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_OUT_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_OUT_CLK_CLK_SEL_MASK (0x1f << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_OUT_CLK_CLK_SEL(x) ((x) << CGU_BASE_OUT_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_APLL_CLK values --------------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_APLL_CLK_PD_SHIFT (0) +#define CGU_BASE_APLL_CLK_PD (1 << CGU_BASE_APLL_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_APLL_CLK_AUTOBLOCK (1 << CGU_BASE_APLL_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_APLL_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_APLL_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_APLL_CLK_CLK_SEL(x) ((x) << CGU_BASE_APLL_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_CGU_OUT0_CLK values ----------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_CGU_OUT0_CLK_PD_SHIFT (0) +#define CGU_BASE_CGU_OUT0_CLK_PD (1 << CGU_BASE_CGU_OUT0_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK \ + (1 << CGU_BASE_CGU_OUT0_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_CGU_OUT0_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_CGU_OUT0_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_CGU_OUT1_CLK values ----------------------------- */ + +/* PD: Output stage power down */ +#define CGU_BASE_CGU_OUT1_CLK_PD_SHIFT (0) +#define CGU_BASE_CGU_OUT1_CLK_PD (1 << CGU_BASE_CGU_OUT1_CLK_PD_SHIFT) + +/* AUTOBLOCK: Block clock automatically during frequency change */ +#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT (11) +#define CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK \ + (1 << CGU_BASE_CGU_OUT1_CLK_AUTOBLOCK_SHIFT) + +/* CLK_SEL: Clock source selection */ +#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT (24) +#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL_MASK \ + (0x1f << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT) +#define CGU_BASE_CGU_OUT1_CLK_CLK_SEL(x) \ + ((x) << CGU_BASE_CGU_OUT1_CLK_CLK_SEL_SHIFT) + +/* --- CGU_BASE_x_CLK clock sources --------------------------------------- */ + +#define CGU_SRC_32K 0x00 +#define CGU_SRC_IRC 0x01 +#define CGU_SRC_ENET_RX 0x02 +#define CGU_SRC_ENET_TX 0x03 +#define CGU_SRC_GP_CLKIN 0x04 +#define CGU_SRC_XTAL 0x06 +#define CGU_SRC_PLL0USB 0x07 +#define CGU_SRC_PLL0AUDIO 0x08 +#define CGU_SRC_PLL1 0x09 +#define CGU_SRC_IDIVA 0x0C +#define CGU_SRC_IDIVB 0x0D +#define CGU_SRC_IDIVC 0x0E +#define CGU_SRC_IDIVD 0x0F +#define CGU_SRC_IDIVE 0x10 + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/creg.h b/libopencm3/include/libopencm3/lpc43xx/creg.h new file mode 100644 index 0000000..2c69551 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/creg.h @@ -0,0 +1,354 @@ +/** @defgroup creg_defines Configuration Registers Defines + +@brief Defined Constants and Types for the LPC43xx Configuration +Registers + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC43XX_CREG_H +#define LPC43XX_CREG_H + +/**@{*/ + +#include +#include + +/* --- CREG registers ----------------------------------------------------- */ + +/* + * Chip configuration register 32 kHz oscillator output and BOD control + * register + */ +#define CREG_CREG0 MMIO32(CREG_BASE + 0x004) + +/* ARM Cortex-M4 memory mapping */ +#define CREG_M4MEMMAP MMIO32(CREG_BASE + 0x100) + +/* Chip configuration register 1 */ +#define CREG_CREG1 MMIO32(CREG_BASE + 0x108) + +/* Chip configuration register 2 */ +#define CREG_CREG2 MMIO32(CREG_BASE + 0x10C) + +/* Chip configuration register 3 */ +#define CREG_CREG3 MMIO32(CREG_BASE + 0x110) + +/* Chip configuration register 4 */ +#define CREG_CREG4 MMIO32(CREG_BASE + 0x114) + +/* Chip configuration register 5 */ +#define CREG_CREG5 MMIO32(CREG_BASE + 0x118) + +/* DMA muxing control */ +#define CREG_DMAMUX MMIO32(CREG_BASE + 0x11C) + +/* Flash accelerator configuration register for flash bank A */ +#define CREG_FLASHCFGA MMIO32(CREG_BASE + 0x120) + +/* Flash accelerator configuration register for flash bank B */ +#define CREG_FLASHCFGB MMIO32(CREG_BASE + 0x124) + +/* ETB RAM configuration */ +#define CREG_ETBCFG MMIO32(CREG_BASE + 0x128) + +/* + * Chip configuration register 6. Controls multiple functions: Ethernet + * interface, SCT output, I2S0/1 inputs, EMC clock. + */ +#define CREG_CREG6 MMIO32(CREG_BASE + 0x12C) + +/* Cortex-M4 TXEV event clear */ +#define CREG_M4TXEVENT MMIO32(CREG_BASE + 0x130) + +/* Part ID (Boundary scan ID code, read-only) */ +#define CREG_CHIPID MMIO32(CREG_BASE + 0x200) + +/* Cortex-M0 TXEV event clear */ +#define CREG_M0TXEVENT MMIO32(CREG_BASE + 0x400) + +/* ARM Cortex-M0 memory mapping */ +#define CREG_M0APPMEMMAP MMIO32(CREG_BASE + 0x404) + +/* USB0 frame length adjust register */ +#define CREG_USB0FLADJ MMIO32(CREG_BASE + 0x500) + +/* USB1 frame length adjust register */ +#define CREG_USB1FLADJ MMIO32(CREG_BASE + 0x600) + +/* --- CREG_CREG0 values ---------------------------------------- */ + +/* EN1KHZ: Enable 1 kHz output */ +#define CREG_CREG0_EN1KHZ_SHIFT (0) +#define CREG_CREG0_EN1KHZ (1 << CREG_CREG0_EN1KHZ_SHIFT) + +/* EN32KHZ: Enable 32 kHz output */ +#define CREG_CREG0_EN32KHZ_SHIFT (1) +#define CREG_CREG0_EN32KHZ (1 << CREG_CREG0_EN32KHZ_SHIFT) + +/* RESET32KHZ: 32 kHz oscillator reset */ +#define CREG_CREG0_RESET32KHZ_SHIFT (2) +#define CREG_CREG0_RESET32KHZ (1 << CREG_CREG0_RESET32KHZ_SHIFT) + +/* PD32KHZ: 32 kHz power control */ +#define CREG_CREG0_PD32KHZ_SHIFT (3) +#define CREG_CREG0_PD32KHZ (1 << CREG_CREG0_PD32KHZ_SHIFT) + +/* USB0PHY: USB0 PHY power control */ +#define CREG_CREG0_USB0PHY_SHIFT (5) +#define CREG_CREG0_USB0PHY (1 << CREG_CREG0_USB0PHY_SHIFT) + +/* ALARMCTRL: RTC_ALARM pin output control */ +#define CREG_CREG0_ALARMCTRL_SHIFT (6) +#define CREG_CREG0_ALARMCTRL_MASK (0x3 << CREG_CREG0_ALARMCTRL_SHIFT) +#define CREG_CREG0_ALARMCTRL(x) ((x) << CREG_CREG0_ALARMCTRL_SHIFT) + +/* BODLVL1: BOD trip level to generate an interrupt */ +#define CREG_CREG0_BODLVL1_SHIFT (8) +#define CREG_CREG0_BODLVL1_MASK (0x3 << CREG_CREG0_BODLVL1_SHIFT) +#define CREG_CREG0_BODLVL1(x) ((x) << CREG_CREG0_BODLVL1_SHIFT) + +/* BODLVL2: BOD trip level to generate a reset */ +#define CREG_CREG0_BODLVL2_SHIFT (10) +#define CREG_CREG0_BODLVL2_MASK (0x3 << CREG_CREG0_BODLVL2_SHIFT) +#define CREG_CREG0_BODLVL2(x) ((x) << CREG_CREG0_BODLVL2_SHIFT) + +/* SAMPLECTRL: SAMPLE pin input/output control */ +#define CREG_CREG0_SAMPLECTRL_SHIFT (12) +#define CREG_CREG0_SAMPLECTRL_MASK (0x3 << CREG_CREG0_SAMPLECTRL_SHIFT) +#define CREG_CREG0_SAMPLECTRL(x) ((x) << CREG_CREG0_SAMPLECTRL_SHIFT) + +/* WAKEUP0CTRL: WAKEUP0 pin input/output control */ +#define CREG_CREG0_WAKEUP0CTRL_SHIFT (14) +#define CREG_CREG0_WAKEUP0CTRL_MASK (0x3 << CREG_CREG0_WAKEUP0CTRL_SHIFT) +#define CREG_CREG0_WAKEUP0CTRL(x) ((x) << CREG_CREG0_WAKEUP0CTRL_SHIFT) + +/* WAKEUP1CTRL: WAKEUP1 pin input/output control */ +#define CREG_CREG0_WAKEUP1CTRL_SHIFT (16) +#define CREG_CREG0_WAKEUP1CTRL_MASK (0x3 << CREG_CREG0_WAKEUP1CTRL_SHIFT) +#define CREG_CREG0_WAKEUP1CTRL(x) ((x) << CREG_CREG0_WAKEUP1CTRL_SHIFT) + +/* --- CREG_M4MEMMAP values ------------------------------------- */ + +/* M4MAP: Shadow address when accessing memory at address 0x00000000 */ +#define CREG_M4MEMMAP_M4MAP_SHIFT (12) +#define CREG_M4MEMMAP_M4MAP_MASK (0xfffff << CREG_M4MEMMAP_M4MAP_SHIFT) +#define CREG_M4MEMMAP_M4MAP(x) ((x) << CREG_M4MEMMAP_M4MAP_SHIFT) + +/* --- CREG_CREG5 values ---------------------------------------- */ + +/* M4TAPSEL: JTAG debug select for M4 core */ +#define CREG_CREG5_M4TAPSEL_SHIFT (6) +#define CREG_CREG5_M4TAPSEL (1 << CREG_CREG5_M4TAPSEL_SHIFT) + +/* M0APPTAPSEL: JTAG debug select for M0 co-processor */ +#define CREG_CREG5_M0APPTAPSEL_SHIFT (9) +#define CREG_CREG5_M0APPTAPSEL (1 << CREG_CREG5_M0APPTAPSEL_SHIFT) + +/* --- CREG_DMAMUX values --------------------------------------- */ + +/* DMAMUXPER0: Select DMA to peripheral connection for DMA peripheral 0 */ +#define CREG_DMAMUX_DMAMUXPER0_SHIFT (0) +#define CREG_DMAMUX_DMAMUXPER0_MASK (0x3 << CREG_DMAMUX_DMAMUXPER0_SHIFT) +#define CREG_DMAMUX_DMAMUXPER0(x) ((x) << CREG_DMAMUX_DMAMUXPER0_SHIFT) + +/* DMAMUXPER1: Select DMA to peripheral connection for DMA peripheral 1 */ +#define CREG_DMAMUX_DMAMUXPER1_SHIFT (2) +#define CREG_DMAMUX_DMAMUXPER1_MASK (0x3 << CREG_DMAMUX_DMAMUXPER1_SHIFT) +#define CREG_DMAMUX_DMAMUXPER1(x) ((x) << CREG_DMAMUX_DMAMUXPER1_SHIFT) + +/* DMAMUXPER2: Select DMA to peripheral connection for DMA peripheral 2 */ +#define CREG_DMAMUX_DMAMUXPER2_SHIFT (4) +#define CREG_DMAMUX_DMAMUXPER2_MASK (0x3 << CREG_DMAMUX_DMAMUXPER2_SHIFT) +#define CREG_DMAMUX_DMAMUXPER2(x) ((x) << CREG_DMAMUX_DMAMUXPER2_SHIFT) + +/* DMAMUXPER3: Select DMA to peripheral connection for DMA peripheral 3 */ +#define CREG_DMAMUX_DMAMUXPER3_SHIFT (6) +#define CREG_DMAMUX_DMAMUXPER3_MASK (0x3 << CREG_DMAMUX_DMAMUXPER3_SHIFT) +#define CREG_DMAMUX_DMAMUXPER3(x) ((x) << CREG_DMAMUX_DMAMUXPER3_SHIFT) + +/* DMAMUXPER4: Select DMA to peripheral connection for DMA peripheral 4 */ +#define CREG_DMAMUX_DMAMUXPER4_SHIFT (8) +#define CREG_DMAMUX_DMAMUXPER4_MASK (0x3 << CREG_DMAMUX_DMAMUXPER4_SHIFT) +#define CREG_DMAMUX_DMAMUXPER4(x) ((x) << CREG_DMAMUX_DMAMUXPER4_SHIFT) + +/* DMAMUXPER5: Select DMA to peripheral connection for DMA peripheral 5 */ +#define CREG_DMAMUX_DMAMUXPER5_SHIFT (10) +#define CREG_DMAMUX_DMAMUXPER5_MASK (0x3 << CREG_DMAMUX_DMAMUXPER5_SHIFT) +#define CREG_DMAMUX_DMAMUXPER5(x) ((x) << CREG_DMAMUX_DMAMUXPER5_SHIFT) + +/* DMAMUXPER6: Select DMA to peripheral connection for DMA peripheral 6 */ +#define CREG_DMAMUX_DMAMUXPER6_SHIFT (12) +#define CREG_DMAMUX_DMAMUXPER6_MASK (0x3 << CREG_DMAMUX_DMAMUXPER6_SHIFT) +#define CREG_DMAMUX_DMAMUXPER6(x) ((x) << CREG_DMAMUX_DMAMUXPER6_SHIFT) + +/* DMAMUXPER7: Select DMA to peripheral connection for DMA peripheral 7 */ +#define CREG_DMAMUX_DMAMUXPER7_SHIFT (14) +#define CREG_DMAMUX_DMAMUXPER7_MASK (0x3 << CREG_DMAMUX_DMAMUXPER7_SHIFT) +#define CREG_DMAMUX_DMAMUXPER7(x) ((x) << CREG_DMAMUX_DMAMUXPER7_SHIFT) + +/* DMAMUXPER8: Select DMA to peripheral connection for DMA peripheral 8 */ +#define CREG_DMAMUX_DMAMUXPER8_SHIFT (16) +#define CREG_DMAMUX_DMAMUXPER8_MASK (0x3 << CREG_DMAMUX_DMAMUXPER8_SHIFT) +#define CREG_DMAMUX_DMAMUXPER8(x) ((x) << CREG_DMAMUX_DMAMUXPER8_SHIFT) + +/* DMAMUXPER9: Select DMA to peripheral connection for DMA peripheral 9 */ +#define CREG_DMAMUX_DMAMUXPER9_SHIFT (18) +#define CREG_DMAMUX_DMAMUXPER9_MASK (0x3 << CREG_DMAMUX_DMAMUXPER9_SHIFT) +#define CREG_DMAMUX_DMAMUXPER9(x) ((x) << CREG_DMAMUX_DMAMUXPER9_SHIFT) + +/* DMAMUXPER10: Select DMA to peripheral connection for DMA peripheral 10 */ +#define CREG_DMAMUX_DMAMUXPER10_SHIFT (20) +#define CREG_DMAMUX_DMAMUXPER10_MASK (0x3 << CREG_DMAMUX_DMAMUXPER10_SHIFT) +#define CREG_DMAMUX_DMAMUXPER10(x) ((x) << CREG_DMAMUX_DMAMUXPER10_SHIFT) + +/* DMAMUXPER11: Select DMA to peripheral connection for DMA peripheral 11 */ +#define CREG_DMAMUX_DMAMUXPER11_SHIFT (22) +#define CREG_DMAMUX_DMAMUXPER11_MASK (0x3 << CREG_DMAMUX_DMAMUXPER11_SHIFT) +#define CREG_DMAMUX_DMAMUXPER11(x) ((x) << CREG_DMAMUX_DMAMUXPER11_SHIFT) + +/* DMAMUXPER12: Select DMA to peripheral connection for DMA peripheral 12 */ +#define CREG_DMAMUX_DMAMUXPER12_SHIFT (24) +#define CREG_DMAMUX_DMAMUXPER12_MASK (0x3 << CREG_DMAMUX_DMAMUXPER12_SHIFT) +#define CREG_DMAMUX_DMAMUXPER12(x) ((x) << CREG_DMAMUX_DMAMUXPER12_SHIFT) + +/* DMAMUXPER13: Select DMA to peripheral connection for DMA peripheral 13 */ +#define CREG_DMAMUX_DMAMUXPER13_SHIFT (26) +#define CREG_DMAMUX_DMAMUXPER13_MASK (0x3 << CREG_DMAMUX_DMAMUXPER13_SHIFT) +#define CREG_DMAMUX_DMAMUXPER13(x) ((x) << CREG_DMAMUX_DMAMUXPER13_SHIFT) + +/* DMAMUXPER14: Select DMA to peripheral connection for DMA peripheral 14 */ +#define CREG_DMAMUX_DMAMUXPER14_SHIFT (28) +#define CREG_DMAMUX_DMAMUXPER14_MASK (0x3 << CREG_DMAMUX_DMAMUXPER14_SHIFT) +#define CREG_DMAMUX_DMAMUXPER14(x) ((x) << CREG_DMAMUX_DMAMUXPER14_SHIFT) + +/* DMAMUXPER15: Select DMA to peripheral connection for DMA peripheral 15 */ +#define CREG_DMAMUX_DMAMUXPER15_SHIFT (30) +#define CREG_DMAMUX_DMAMUXPER15_MASK (0x3 << CREG_DMAMUX_DMAMUXPER15_SHIFT) +#define CREG_DMAMUX_DMAMUXPER15(x) ((x) << CREG_DMAMUX_DMAMUXPER15_SHIFT) + +/* --- CREG_FLASHCFGA values ------------------------------------ */ + +/* FLASHTIM: Flash access time. The value of this field plus 1 gives the number + * of BASE_M4_CLK clocks used for a flash access */ +#define CREG_FLASHCFGA_FLASHTIM_SHIFT (12) +#define CREG_FLASHCFGA_FLASHTIM_MASK (0xf << CREG_FLASHCFGA_FLASHTIM_SHIFT) +#define CREG_FLASHCFGA_FLASHTIM(x) ((x) << CREG_FLASHCFGA_FLASHTIM_SHIFT) + +/* POW: Flash bank A power control */ +#define CREG_FLASHCFGA_POW_SHIFT (31) +#define CREG_FLASHCFGA_POW (1 << CREG_FLASHCFGA_POW_SHIFT) + +/* --- CREG_FLASHCFGB values ------------------------------------ */ + +/* FLASHTIM: Flash access time. The value of this field plus 1 gives the number + * of BASE_M4_CLK clocks used for a flash access */ +#define CREG_FLASHCFGB_FLASHTIM_SHIFT (12) +#define CREG_FLASHCFGB_FLASHTIM_MASK (0xf << CREG_FLASHCFGB_FLASHTIM_SHIFT) +#define CREG_FLASHCFGB_FLASHTIM(x) ((x) << CREG_FLASHCFGB_FLASHTIM_SHIFT) + +/* POW: Flash bank B power control */ +#define CREG_FLASHCFGB_POW_SHIFT (31) +#define CREG_FLASHCFGB_POW (1 << CREG_FLASHCFGB_POW_SHIFT) + +/* --- CREG_ETBCFG values --------------------------------------- */ + +/* ETB: Select SRAM interface */ +#define CREG_ETBCFG_ETB_SHIFT (0) +#define CREG_ETBCFG_ETB (1 << CREG_ETBCFG_ETB_SHIFT) + +/* --- CREG_CREG6 values ---------------------------------------- */ + +/* ETHMODE: Selects the Ethernet mode. Reset the ethernet after changing the + * PHY interface */ +#define CREG_CREG6_ETHMODE_SHIFT (0) +#define CREG_CREG6_ETHMODE_MASK (0x7 << CREG_CREG6_ETHMODE_SHIFT) +#define CREG_CREG6_ETHMODE(x) ((x) << CREG_CREG6_ETHMODE_SHIFT) + +/* CTOUTCTRL: Selects the functionality of the SCT outputs */ +#define CREG_CREG6_CTOUTCTRL_SHIFT (4) +#define CREG_CREG6_CTOUTCTRL (1 << CREG_CREG6_CTOUTCTRL_SHIFT) + +/* I2S0_TX_SCK_IN_SEL: I2S0_TX_SCK input select */ +#define CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT (12) +#define CREG_CREG6_I2S0_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_TX_SCK_IN_SEL_SHIFT) + +/* I2S0_RX_SCK_IN_SEL: I2S0_RX_SCK input select */ +#define CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT (13) +#define CREG_CREG6_I2S0_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S0_RX_SCK_IN_SEL_SHIFT) + +/* I2S1_TX_SCK_IN_SEL: I2S1_TX_SCK input select */ +#define CREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT (14) +#define CREG_CREG6_I2S1_TX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_TX_SCK_IN_SEL_SHIFT) + +/* I2S1_RX_SCK_IN_SEL: I2S1_RX_SCK input select */ +#define CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT (15) +#define CREG_CREG6_I2S1_RX_SCK_IN_SEL (1 << CREG_CREG6_I2S1_RX_SCK_IN_SEL_SHIFT) + +/* EMC_CLK_SEL: EMC_CLK divided clock select */ +#define CREG_CREG6_EMC_CLK_SEL_SHIFT (16) +#define CREG_CREG6_EMC_CLK_SEL (1 << CREG_CREG6_EMC_CLK_SEL_SHIFT) + +/* --- CREG_M4TXEVENT values ------------------------------------ */ + +/* TXEVCLR: Cortex-M4 TXEV event */ +#define CREG_M4TXEVENT_TXEVCLR_SHIFT (0) +#define CREG_M4TXEVENT_TXEVCLR (1 << CREG_M4TXEVENT_TXEVCLR_SHIFT) + +/* --- CREG_M0TXEVENT values ------------------------------------ */ + +/* TXEVCLR: Cortex-M0 TXEV event */ +#define CREG_M0TXEVENT_TXEVCLR_SHIFT (0) +#define CREG_M0TXEVENT_TXEVCLR (1 << CREG_M0TXEVENT_TXEVCLR_SHIFT) + +/* --- CREG_M0APPMEMMAP values ---------------------------------- */ + +/* M0APPMAP: Shadow address when accessing memory at address 0x00000000 */ +#define CREG_M0APPMEMMAP_M0APPMAP_SHIFT (12) +#define CREG_M0APPMEMMAP_M0APPMAP_MASK \ + (0xfffff << CREG_M0APPMEMMAP_M0APPMAP_SHIFT) +#define CREG_M0APPMEMMAP_M0APPMAP(x) ((x) << CREG_M0APPMEMMAP_M0APPMAP_SHIFT) + +/* --- CREG_USB0FLADJ values ------------------------------------ */ + +/* FLTV: Frame length timing value */ +#define CREG_USB0FLADJ_FLTV_SHIFT (0) +#define CREG_USB0FLADJ_FLTV_MASK (0x3f << CREG_USB0FLADJ_FLTV_SHIFT) +#define CREG_USB0FLADJ_FLTV(x) ((x) << CREG_USB0FLADJ_FLTV_SHIFT) + +/* --- CREG_USB1FLADJ values ------------------------------------ */ + +/* FLTV: Frame length timing value */ +#define CREG_USB1FLADJ_FLTV_SHIFT (0) +#define CREG_USB1FLADJ_FLTV_MASK (0x3f << CREG_USB1FLADJ_FLTV_SHIFT) +#define CREG_USB1FLADJ_FLTV(x) ((x) << CREG_USB1FLADJ_FLTV_SHIFT) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/doc-lpc43xx.h b/libopencm3/include/libopencm3/lpc43xx/doc-lpc43xx.h new file mode 100644 index 0000000..3c21aae --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/doc-lpc43xx.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 LPC43xx + +@version 1.0.0 + +@date 14 September 2012 + +API documentation for NXP Semiconductors LPC43xx Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup LPC43xx LPC43xx +Libraries for NXP Semiconductors LPC43xx series. + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup LPC43xx_defines LPC43xx Defines + +@brief Defined Constants and Types for the LPC43xx series + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/libopencm3/include/libopencm3/lpc43xx/eventrouter.h b/libopencm3/include/libopencm3/lpc43xx/eventrouter.h new file mode 100644 index 0000000..d27c67c --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/eventrouter.h @@ -0,0 +1,70 @@ +/** @defgroup eventrouter_defines Event Router Defines + +@brief Defined Constants and Types for the LPC43xx Event Router + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC43XX_EVENTROUTER_H +#define LPC43XX_EVENTROUTER_H + +/**@{*/ + +#include +#include + +/* --- Event Router registers ---------------------------------------------- */ + +/* Level configuration register */ +#define EVENTROUTER_HILO MMIO32(EVENTROUTER_BASE + 0x000) + +/* Edge configuration */ +#define EVENTROUTER_EDGE MMIO32(EVENTROUTER_BASE + 0x004) + +/* Clear event enable register */ +#define EVENTROUTER_CLR_EN MMIO32(EVENTROUTER_BASE + 0xFD8) + +/* Set event enable register */ +#define EVENTROUTER_SET_EN MMIO32(EVENTROUTER_BASE + 0xFDC) + +/* Event Status register */ +#define EVENTROUTER_STATUS MMIO32(EVENTROUTER_BASE + 0xFE0) + +/* Event Enable register */ +#define EVENTROUTER_ENABLE MMIO32(EVENTROUTER_BASE + 0xFE4) + +/* Clear event status register */ +#define EVENTROUTER_CLR_STAT MMIO32(EVENTROUTER_BASE + 0xFE8) + +/* Set event status register */ +#define EVENTROUTER_SET_STAT MMIO32(EVENTROUTER_BASE + 0xFEC) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/gima.h b/libopencm3/include/libopencm3/lpc43xx/gima.h new file mode 100644 index 0000000..6a36c76 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/gima.h @@ -0,0 +1,137 @@ +/** @defgroup gima_defines Global Input Multiplexer Array Defines + +@brief Defined Constants and Types for the LPC43xx Global Input Multiplexer +Array + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC43XX_GIMA_H +#define LPC43XX_GIMA_H + +/**@{*/ + +#include +#include + +/* --- GIMA registers ----------------------------------------------------- */ + +/* Timer 0 CAP0_0 capture input multiplexer (GIMA output 0) */ +#define GIMA_CAP0_0_IN MMIO32(GIMA_BASE + 0x000) + +/* Timer 0 CAP0_1 capture input multiplexer (GIMA output 1) */ +#define GIMA_CAP0_1_IN MMIO32(GIMA_BASE + 0x004) + +/* Timer 0 CAP0_2 capture input multiplexer (GIMA output 2) */ +#define GIMA_CAP0_2_IN MMIO32(GIMA_BASE + 0x008) + +/* Timer 0 CAP0_3 capture input multiplexer (GIMA output 3) */ +#define GIMA_CAP0_3_IN MMIO32(GIMA_BASE + 0x00C) + +/* Timer 1 CAP1_0 capture input multiplexer (GIMA output 4) */ +#define GIMA_CAP1_0_IN MMIO32(GIMA_BASE + 0x010) + +/* Timer 1 CAP1_1 capture input multiplexer (GIMA output 5) */ +#define GIMA_CAP1_1_IN MMIO32(GIMA_BASE + 0x014) + +/* Timer 1 CAP1_2 capture input multiplexer (GIMA output 6) */ +#define GIMA_CAP1_2_IN MMIO32(GIMA_BASE + 0x018) + +/* Timer 1 CAP1_3 capture input multiplexer (GIMA output 7) */ +#define GIMA_CAP1_3_IN MMIO32(GIMA_BASE + 0x01C) + +/* Timer 2 CAP2_0 capture input multiplexer (GIMA output 8) */ +#define GIMA_CAP2_0_IN MMIO32(GIMA_BASE + 0x020) + +/* Timer 2 CAP2_1 capture input multiplexer (GIMA output 9) */ +#define GIMA_CAP2_1_IN MMIO32(GIMA_BASE + 0x024) + +/* Timer 2 CAP2_2 capture input multiplexer (GIMA output 10) */ +#define GIMA_CAP2_2_IN MMIO32(GIMA_BASE + 0x028) + +/* Timer 2 CAP2_3 capture input multiplexer (GIMA output 11) */ +#define GIMA_CAP2_3_IN MMIO32(GIMA_BASE + 0x02C) + +/* Timer 3 CAP3_0 capture input multiplexer (GIMA output 12) */ +#define GIMA_CAP3_0_IN MMIO32(GIMA_BASE + 0x030) + +/* Timer 3 CAP3_1 capture input multiplexer (GIMA output 13) */ +#define GIMA_CAP3_1_IN MMIO32(GIMA_BASE + 0x034) + +/* Timer 3 CAP3_2 capture input multiplexer (GIMA output 14) */ +#define GIMA_CAP3_2_IN MMIO32(GIMA_BASE + 0x038) + +/* Timer 3 CAP3_3 capture input multiplexer (GIMA output 15) */ +#define GIMA_CAP3_3_IN MMIO32(GIMA_BASE + 0x03C) + +/* SCT CTIN_0 capture input multiplexer (GIMA output 16) */ +#define GIMA_CTIN_0_IN MMIO32(GIMA_BASE + 0x040) + +/* SCT CTIN_1 capture input multiplexer (GIMA output 17) */ +#define GIMA_CTIN_1_IN MMIO32(GIMA_BASE + 0x044) + +/* SCT CTIN_2 capture input multiplexer (GIMA output 18) */ +#define GIMA_CTIN_2_IN MMIO32(GIMA_BASE + 0x048) + +/* SCT CTIN_3 capture input multiplexer (GIMA output 19) */ +#define GIMA_CTIN_3_IN MMIO32(GIMA_BASE + 0x04C) + +/* SCT CTIN_4 capture input multiplexer (GIMA output 20) */ +#define GIMA_CTIN_4_IN MMIO32(GIMA_BASE + 0x050) + +/* SCT CTIN_5 capture input multiplexer (GIMA output 21) */ +#define GIMA_CTIN_5_IN MMIO32(GIMA_BASE + 0x054) + +/* SCT CTIN_6 capture input multiplexer (GIMA output 22) */ +#define GIMA_CTIN_6_IN MMIO32(GIMA_BASE + 0x058) + +/* SCT CTIN_7 capture input multiplexer (GIMA output 23) */ +#define GIMA_CTIN_7_IN MMIO32(GIMA_BASE + 0x05C) + +/* VADC trigger input multiplexer (GIMA output 24) */ +#define GIMA_VADC_TRIGGER_IN MMIO32(GIMA_BASE + 0x060) + +/* Event router input 13 multiplexer (GIMA output 25) */ +#define GIMA_EVENTROUTER_13_IN MMIO32(GIMA_BASE + 0x064) + +/* Event router input 14 multiplexer (GIMA output 26) */ +#define GIMA_EVENTROUTER_14_IN MMIO32(GIMA_BASE + 0x068) + +/* Event router input 16 multiplexer (GIMA output 27) */ +#define GIMA_EVENTROUTER_16_IN MMIO32(GIMA_BASE + 0x06C) + +/* ADC start0 input multiplexer (GIMA output 28) */ +#define GIMA_ADCSTART0_IN MMIO32(GIMA_BASE + 0x070) + +/* ADC start1 input multiplexer (GIMA output 29) */ +#define GIMA_ADCSTART1_IN MMIO32(GIMA_BASE + 0x074) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/gpdma.h b/libopencm3/include/libopencm3/lpc43xx/gpdma.h new file mode 100644 index 0000000..9df6698 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/gpdma.h @@ -0,0 +1,552 @@ +/** @defgroup gpdma_defines General Purpose DMA Defines + * + * @brief Defined Constants and Types for the LPC43xx General Purpose DMA + * + * @ingroup LPC43xx_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2012 Michael Ossmann + * + * @date 10 March 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC43XX_GPDMA_H +#define LPC43XX_GPDMA_H + +/**@{*/ + +#include +#include + +/* --- GPDMA registers ----------------------------------------------------- */ + +/* General registers */ + +/* DMA Interrupt Status Register */ +#define GPDMA_INTSTAT MMIO32(GPDMA_BASE + 0x000) + +/* DMA Interrupt Terminal Count Request Status Register */ +#define GPDMA_INTTCSTAT MMIO32(GPDMA_BASE + 0x004) + +/* DMA Interrupt Terminal Count Request Clear Register */ +#define GPDMA_INTTCCLEAR MMIO32(GPDMA_BASE + 0x008) + +/* DMA Interrupt Error Status Register */ +#define GPDMA_INTERRSTAT MMIO32(GPDMA_BASE + 0x00C) + +/* DMA Interrupt Error Clear Register */ +#define GPDMA_INTERRCLR MMIO32(GPDMA_BASE + 0x010) + +/* DMA Raw Interrupt Terminal Count Status Register */ +#define GPDMA_RAWINTTCSTAT MMIO32(GPDMA_BASE + 0x014) + +/* DMA Raw Error Interrupt Status Register */ +#define GPDMA_RAWINTERRSTAT MMIO32(GPDMA_BASE + 0x018) + +/* DMA Enabled Channel Register */ +#define GPDMA_ENBLDCHNS MMIO32(GPDMA_BASE + 0x01C) + +/* DMA Software Burst Request Register */ +#define GPDMA_SOFTBREQ MMIO32(GPDMA_BASE + 0x020) + +/* DMA Software Single Request Register */ +#define GPDMA_SOFTSREQ MMIO32(GPDMA_BASE + 0x024) + +/* DMA Software Last Burst Request Register */ +#define GPDMA_SOFTLBREQ MMIO32(GPDMA_BASE + 0x028) + +/* DMA Software Last Single Request Register */ +#define GPDMA_SOFTLSREQ MMIO32(GPDMA_BASE + 0x02C) + +/* DMA Configuration Register */ +#define GPDMA_CONFIG MMIO32(GPDMA_BASE + 0x030) + +/* DMA Synchronization Register */ +#define GPDMA_SYNC MMIO32(GPDMA_BASE + 0x034) + + +/* Channel registers */ + +/* Source Address Register */ +#define GPDMA_CSRCADDR(channel) MMIO32(GPDMA_BASE + 0x100 + \ + (channel * 0x20)) +#define GPDMA_C0SRCADDR GPDMA_CSRCADDR(0) +#define GPDMA_C1SRCADDR GPDMA_CSRCADDR(1) +#define GPDMA_C2SRCADDR GPDMA_CSRCADDR(2) +#define GPDMA_C3SRCADDR GPDMA_CSRCADDR(3) +#define GPDMA_C4SRCADDR GPDMA_CSRCADDR(4) +#define GPDMA_C5SRCADDR GPDMA_CSRCADDR(5) +#define GPDMA_C6SRCADDR GPDMA_CSRCADDR(6) +#define GPDMA_C7SRCADDR GPDMA_CSRCADDR(7) + +/* Destination Address Register */ +#define GPDMA_CDESTADDR(channel) MMIO32(GPDMA_BASE + 0x104 + \ + (channel * 0x20)) +#define GPDMA_C0DESTADDR GPDMA_CDESTADDR(0) +#define GPDMA_C1DESTADDR GPDMA_CDESTADDR(1) +#define GPDMA_C2DESTADDR GPDMA_CDESTADDR(2) +#define GPDMA_C3DESTADDR GPDMA_CDESTADDR(3) +#define GPDMA_C4DESTADDR GPDMA_CDESTADDR(4) +#define GPDMA_C5DESTADDR GPDMA_CDESTADDR(5) +#define GPDMA_C6DESTADDR GPDMA_CDESTADDR(6) +#define GPDMA_C7DESTADDR GPDMA_CDESTADDR(7) + +/* Linked List Item Register */ +#define GPDMA_CLLI(channel) MMIO32(GPDMA_BASE + 0x108 + \ + (channel * 0x20)) +#define GPDMA_C0LLI GPDMA_CLLI(0) +#define GPDMA_C1LLI GPDMA_CLLI(1) +#define GPDMA_C2LLI GPDMA_CLLI(2) +#define GPDMA_C3LLI GPDMA_CLLI(3) +#define GPDMA_C4LLI GPDMA_CLLI(4) +#define GPDMA_C5LLI GPDMA_CLLI(5) +#define GPDMA_C6LLI GPDMA_CLLI(6) +#define GPDMA_C7LLI GPDMA_CLLI(7) + +/* Control Register */ +#define GPDMA_CCONTROL(channel) MMIO32(GPDMA_BASE + 0x10C + \ + (channel * 0x20)) +#define GPDMA_C0CONTROL GPDMA_CCONTROL(0) +#define GPDMA_C1CONTROL GPDMA_CCONTROL(1) +#define GPDMA_C2CONTROL GPDMA_CCONTROL(2) +#define GPDMA_C3CONTROL GPDMA_CCONTROL(3) +#define GPDMA_C4CONTROL GPDMA_CCONTROL(4) +#define GPDMA_C5CONTROL GPDMA_CCONTROL(5) +#define GPDMA_C6CONTROL GPDMA_CCONTROL(6) +#define GPDMA_C7CONTROL GPDMA_CCONTROL(7) + +/* Configuration Register */ +#define GPDMA_CCONFIG(channel) MMIO32(GPDMA_BASE + 0x110 + \ + (channel * 0x20)) +#define GPDMA_C0CONFIG GPDMA_CCONFIG(0) +#define GPDMA_C1CONFIG GPDMA_CCONFIG(1) +#define GPDMA_C2CONFIG GPDMA_CCONFIG(2) +#define GPDMA_C3CONFIG GPDMA_CCONFIG(3) +#define GPDMA_C4CONFIG GPDMA_CCONFIG(4) +#define GPDMA_C5CONFIG GPDMA_CCONFIG(5) +#define GPDMA_C6CONFIG GPDMA_CCONFIG(6) +#define GPDMA_C7CONFIG GPDMA_CCONFIG(7) + +/* --- Common fields -------------------------------------------- */ + +#define GPDMA_CSRCADDR_SRCADDR_SHIFT (0) +#define GPDMA_CSRCADDR_SRCADDR_MASK (0xffffffff << GPDMA_CSRCADDR_SRCADDR_SHIFT) +#define GPDMA_CSRCADDR_SRCADDR(x) ((x) << GPDMA_CSRCADDR_SRCADDR_SHIFT) + +#define GPDMA_CDESTADDR_DESTADDR_SHIFT (0) +#define GPDMA_CDESTADDR_DESTADDR_MASK \ + (0xffffffff << GPDMA_CDESTADDR_DESTADDR_SHIFT) +#define GPDMA_CDESTADDR_DESTADDR(x) ((x) << GPDMA_CDESTADDR_DESTADDR_SHIFT) + +#define GPDMA_CLLI_LM_SHIFT (0) +#define GPDMA_CLLI_LM_MASK (0x1 << GPDMA_CLLI_LM_SHIFT) +#define GPDMA_CLLI_LM(x) ((x) << GPDMA_CLLI_LM_SHIFT) + +#define GPDMA_CLLI_LLI_SHIFT (2) +#define GPDMA_CLLI_LLI_MASK (0x3fffffff << GPDMA_CLLI_LLI_SHIFT) +#define GPDMA_CLLI_LLI(x) ((x) << GPDMA_CLLI_LLI_SHIFT) + +#define GPDMA_CCONTROL_TRANSFERSIZE_SHIFT (0) +#define GPDMA_CCONTROL_TRANSFERSIZE_MASK \ + (0xfff << GPDMA_CCONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_CCONTROL_TRANSFERSIZE(x) \ + ((x) << GPDMA_CCONTROL_TRANSFERSIZE_SHIFT) + +#define GPDMA_CCONTROL_SBSIZE_SHIFT (12) +#define GPDMA_CCONTROL_SBSIZE_MASK (0x7 << GPDMA_CCONTROL_SBSIZE_SHIFT) +#define GPDMA_CCONTROL_SBSIZE(x) ((x) << GPDMA_CCONTROL_SBSIZE_SHIFT) + +#define GPDMA_CCONTROL_DBSIZE_SHIFT (15) +#define GPDMA_CCONTROL_DBSIZE_MASK (0x7 << GPDMA_CCONTROL_DBSIZE_SHIFT) +#define GPDMA_CCONTROL_DBSIZE(x) ((x) << GPDMA_CCONTROL_DBSIZE_SHIFT) + +#define GPDMA_CCONTROL_SWIDTH_SHIFT (18) +#define GPDMA_CCONTROL_SWIDTH_MASK (0x7 << GPDMA_CCONTROL_SWIDTH_SHIFT) +#define GPDMA_CCONTROL_SWIDTH(x) ((x) << GPDMA_CCONTROL_SWIDTH_SHIFT) + +#define GPDMA_CCONTROL_DWIDTH_SHIFT (21) +#define GPDMA_CCONTROL_DWIDTH_MASK (0x7 << GPDMA_CCONTROL_DWIDTH_SHIFT) +#define GPDMA_CCONTROL_DWIDTH(x) ((x) << GPDMA_CCONTROL_DWIDTH_SHIFT) + +#define GPDMA_CCONTROL_S_SHIFT (24) +#define GPDMA_CCONTROL_S_MASK (0x1 << GPDMA_CCONTROL_S_SHIFT) +#define GPDMA_CCONTROL_S(x) ((x) << GPDMA_CCONTROL_S_SHIFT) + +#define GPDMA_CCONTROL_D_SHIFT (25) +#define GPDMA_CCONTROL_D_MASK (0x1 << GPDMA_CCONTROL_D_SHIFT) +#define GPDMA_CCONTROL_D(x) ((x) << GPDMA_CCONTROL_D_SHIFT) + +#define GPDMA_CCONTROL_SI_SHIFT (26) +#define GPDMA_CCONTROL_SI_MASK (0x1 << GPDMA_CCONTROL_SI_SHIFT) +#define GPDMA_CCONTROL_SI(x) ((x) << GPDMA_CCONTROL_SI_SHIFT) + +#define GPDMA_CCONTROL_DI_SHIFT (27) +#define GPDMA_CCONTROL_DI_MASK (0x1 << GPDMA_CCONTROL_DI_SHIFT) +#define GPDMA_CCONTROL_DI(x) ((x) << GPDMA_CCONTROL_DI_SHIFT) + +#define GPDMA_CCONTROL_PROT1_SHIFT (28) +#define GPDMA_CCONTROL_PROT1_MASK (0x1 << GPDMA_CCONTROL_PROT1_SHIFT) +#define GPDMA_CCONTROL_PROT1(x) ((x) << GPDMA_CCONTROL_PROT1_SHIFT) + +#define GPDMA_CCONTROL_PROT2_SHIFT (29) +#define GPDMA_CCONTROL_PROT2_MASK (0x1 << GPDMA_CCONTROL_PROT2_SHIFT) +#define GPDMA_CCONTROL_PROT2(x) ((x) << GPDMA_CCONTROL_PROT2_SHIFT) + +#define GPDMA_CCONTROL_PROT3_SHIFT (30) +#define GPDMA_CCONTROL_PROT3_MASK (0x1 << GPDMA_CCONTROL_PROT3_SHIFT) +#define GPDMA_CCONTROL_PROT3(x) ((x) << GPDMA_CCONTROL_PROT3_SHIFT) + +#define GPDMA_CCONTROL_I_SHIFT (31) +#define GPDMA_CCONTROL_I_MASK (0x1 << GPDMA_CCONTROL_I_SHIFT) +#define GPDMA_CCONTROL_I(x) ((x) << GPDMA_CCONTROL_I_SHIFT) + +#define GPDMA_CCONFIG_E_SHIFT (0) +#define GPDMA_CCONFIG_E_MASK (0x1 << GPDMA_CCONFIG_E_SHIFT) +#define GPDMA_CCONFIG_E(x) ((x) << GPDMA_CCONFIG_E_SHIFT) + +#define GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT (1) +#define GPDMA_CCONFIG_SRCPERIPHERAL_MASK \ + (0x1f << GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_CCONFIG_SRCPERIPHERAL(x) \ + ((x) << GPDMA_CCONFIG_SRCPERIPHERAL_SHIFT) + +#define GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT (6) +#define GPDMA_CCONFIG_DESTPERIPHERAL_MASK \ + (0x1f << GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_CCONFIG_DESTPERIPHERAL(x) \ + ((x) << GPDMA_CCONFIG_DESTPERIPHERAL_SHIFT) + +#define GPDMA_CCONFIG_FLOWCNTRL_SHIFT (11) +#define GPDMA_CCONFIG_FLOWCNTRL_MASK (0x7 << GPDMA_CCONFIG_FLOWCNTRL_SHIFT) +#define GPDMA_CCONFIG_FLOWCNTRL(x) ((x) << GPDMA_CCONFIG_FLOWCNTRL_SHIFT) + +#define GPDMA_CCONFIG_IE_SHIFT (14) +#define GPDMA_CCONFIG_IE_MASK (0x1 << GPDMA_CCONFIG_IE_SHIFT) +#define GPDMA_CCONFIG_IE(x) ((x) << GPDMA_CCONFIG_IE_SHIFT) + +#define GPDMA_CCONFIG_ITC_SHIFT (15) +#define GPDMA_CCONFIG_ITC_MASK (0x1 << GPDMA_CCONFIG_ITC_SHIFT) +#define GPDMA_CCONFIG_ITC(x) ((x) << GPDMA_CCONFIG_ITC_SHIFT) + +#define GPDMA_CCONFIG_L_SHIFT (16) +#define GPDMA_CCONFIG_L_MASK (0x1 << GPDMA_CCONFIG_L_SHIFT) +#define GPDMA_CCONFIG_L(x) ((x) << GPDMA_CCONFIG_L_SHIFT) + +#define GPDMA_CCONFIG_A_SHIFT (17) +#define GPDMA_CCONFIG_A_MASK (0x1 << GPDMA_CCONFIG_A_SHIFT) +#define GPDMA_CCONFIG_A(x) ((x) << GPDMA_CCONFIG_A_SHIFT) + +#define GPDMA_CCONFIG_H_SHIFT (18) +#define GPDMA_CCONFIG_H_MASK (0x1 << GPDMA_CCONFIG_H_SHIFT) +#define GPDMA_CCONFIG_H(x) ((x) << GPDMA_CCONFIG_H_SHIFT) + +/* --- AUTO-GENERATED STUFF FOLLOWS ----------------------------- */ + +/* --- GPDMA_NTSTAT values -------------------------------------- */ + +/* INTSTAT: Status of DMA channel interrupts after masking */ +#define GPDMA_NTSTAT_INTSTAT_SHIFT (0) +#define GPDMA_NTSTAT_INTSTAT_MASK (0xff << GPDMA_NTSTAT_INTSTAT_SHIFT) +#define GPDMA_NTSTAT_INTSTAT(x) ((x) << GPDMA_NTSTAT_INTSTAT_SHIFT) + +/* --- GPDMA_INTTCSTAT values ----------------------------------- */ + +/* INTTCSTAT: Terminal count interrupt request status for DMA channels */ +#define GPDMA_INTTCSTAT_INTTCSTAT_SHIFT (0) +#define GPDMA_INTTCSTAT_INTTCSTAT_MASK (0xff << GPDMA_INTTCSTAT_INTTCSTAT_SHIFT) +#define GPDMA_INTTCSTAT_INTTCSTAT(x) ((x) << GPDMA_INTTCSTAT_INTTCSTAT_SHIFT) + +/* --- GPDMA_INTTCCLEAR values ---------------------------------- */ + +/* INTTCCLEAR: Allows clearing the Terminal count interrupt request (IntTCStat) + for DMA channels */ +#define GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT (0) +#define GPDMA_INTTCCLEAR_INTTCCLEAR_MASK \ + (0xff << GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT) +#define GPDMA_INTTCCLEAR_INTTCCLEAR(x) \ + ((x) << GPDMA_INTTCCLEAR_INTTCCLEAR_SHIFT) + +/* --- GPDMA_INTERRSTAT values ---------------------------------- */ + +/* INTERRSTAT: Interrupt error status for DMA channels */ +#define GPDMA_INTERRSTAT_INTERRSTAT_SHIFT (0) +#define GPDMA_INTERRSTAT_INTERRSTAT_MASK \ + (0xff << GPDMA_INTERRSTAT_INTERRSTAT_SHIFT) +#define GPDMA_INTERRSTAT_INTERRSTAT(x) \ + ((x) << GPDMA_INTERRSTAT_INTERRSTAT_SHIFT) + +/* --- GPDMA_INTERRCLR values ----------------------------------- */ + +/* INTERRCLR: Writing a 1 clears the error interrupt request (IntErrStat) + for DMA channels */ +#define GPDMA_INTERRCLR_INTERRCLR_SHIFT (0) +#define GPDMA_INTERRCLR_INTERRCLR_MASK \ + (0xff << GPDMA_INTERRCLR_INTERRCLR_SHIFT) +#define GPDMA_INTERRCLR_INTERRCLR(x) \ + ((x) << GPDMA_INTERRCLR_INTERRCLR_SHIFT) + +/* --- GPDMA_RAWINTTCSTAT values -------------------------------- */ + +/* RAWINTTCSTAT: Status of the terminal count interrupt for DMA channels + prior to masking */ +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT (0) +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_MASK \ + (0xff << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT) +#define GPDMA_RAWINTTCSTAT_RAWINTTCSTAT(x) \ + ((x) << GPDMA_RAWINTTCSTAT_RAWINTTCSTAT_SHIFT) + +/* --- GPDMA_RAWINTERRSTAT values ------------------------------- */ + +/* RAWINTERRSTAT: Status of the error interrupt for DMA channels prior to + masking */ +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT (0) +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_MASK \ + (0xff << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT) +#define GPDMA_RAWINTERRSTAT_RAWINTERRSTAT(x) \ + ((x) << GPDMA_RAWINTERRSTAT_RAWINTERRSTAT_SHIFT) + +/* --- GPDMA_ENBLDCHNS values ----------------------------------- */ + +/* ENABLEDCHANNELS: Enable status for DMA channels */ +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT (0) +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS_MASK \ + (0xff << GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT) +#define GPDMA_ENBLDCHNS_ENABLEDCHANNELS(x) \ + ((x) << GPDMA_ENBLDCHNS_ENABLEDCHANNELS_SHIFT) + +/* --- GPDMA_SOFTBREQ values ------------------------------------ */ + +/* SOFTBREQ: Software burst request flags for each of 16 possible sources */ +#define GPDMA_SOFTBREQ_SOFTBREQ_SHIFT (0) +#define GPDMA_SOFTBREQ_SOFTBREQ_MASK (0xffff << GPDMA_SOFTBREQ_SOFTBREQ_SHIFT) +#define GPDMA_SOFTBREQ_SOFTBREQ(x) ((x) << GPDMA_SOFTBREQ_SOFTBREQ_SHIFT) + +/* --- GPDMA_SOFTSREQ values ------------------------------------ */ + +/* SOFTSREQ: Software single transfer request flags for each of 16 possible + sources */ +#define GPDMA_SOFTSREQ_SOFTSREQ_SHIFT (0) +#define GPDMA_SOFTSREQ_SOFTSREQ_MASK (0xffff << GPDMA_SOFTSREQ_SOFTSREQ_SHIFT) +#define GPDMA_SOFTSREQ_SOFTSREQ(x) ((x) << GPDMA_SOFTSREQ_SOFTSREQ_SHIFT) + +/* --- GPDMA_SOFTLBREQ values ----------------------------------- */ + +/* SOFTLBREQ: Software last burst request flags for each of 16 possible + sources */ +#define GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT (0) +#define GPDMA_SOFTLBREQ_SOFTLBREQ_MASK \ + (0xffff << GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT) +#define GPDMA_SOFTLBREQ_SOFTLBREQ(x) \ + ((x) << GPDMA_SOFTLBREQ_SOFTLBREQ_SHIFT) + +/* --- GPDMA_SOFTLSREQ values ----------------------------------- */ + +/* SOFTLSREQ: Software last single transfer request flags for each of 16 + possible sources */ +#define GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT (0) +#define GPDMA_SOFTLSREQ_SOFTLSREQ_MASK \ + (0xffff << GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT) +#define GPDMA_SOFTLSREQ_SOFTLSREQ(x) \ + ((x) << GPDMA_SOFTLSREQ_SOFTLSREQ_SHIFT) + +/* --- GPDMA_CONFIG values -------------------------------------- */ + +/* E: DMA Controller enable */ +#define GPDMA_CONFIG_E_SHIFT (0) +#define GPDMA_CONFIG_E_MASK (0x1 << GPDMA_CONFIG_E_SHIFT) +#define GPDMA_CONFIG_E(x) ((x) << GPDMA_CONFIG_E_SHIFT) + +/* M0: AHB Master 0 endianness configuration */ +#define GPDMA_CONFIG_M0_SHIFT (1) +#define GPDMA_CONFIG_M0_MASK (0x1 << GPDMA_CONFIG_M0_SHIFT) +#define GPDMA_CONFIG_M0(x) ((x) << GPDMA_CONFIG_M0_SHIFT) + +/* M1: AHB Master 1 endianness configuration */ +#define GPDMA_CONFIG_M1_SHIFT (2) +#define GPDMA_CONFIG_M1_MASK (0x1 << GPDMA_CONFIG_M1_SHIFT) +#define GPDMA_CONFIG_M1(x) ((x) << GPDMA_CONFIG_M1_SHIFT) + +/* --- GPDMA_SYNC values ---------------------------------------- */ + +/* DMACSYNC: Controls the synchronization logic for DMA request signals */ +#define GPDMA_SYNC_DMACSYNC_SHIFT (0) +#define GPDMA_SYNC_DMACSYNC_MASK (0xffff << GPDMA_SYNC_DMACSYNC_SHIFT) +#define GPDMA_SYNC_DMACSYNC(x) ((x) << GPDMA_SYNC_DMACSYNC_SHIFT) + +/* --- GPDMA_C[0..7]SRCADDR values ----------------------------------- */ + +/* SRCADDR: DMA source address */ +#define GPDMA_CxSRCADDR_SRCADDR_SHIFT (0) +#define GPDMA_CxSRCADDR_SRCADDR_MASK \ + (0xffffffff << GPDMA_CxSRCADDR_SRCADDR_SHIFT) +#define GPDMA_CxSRCADDR_SRCADDR(x) ((x) << GPDMA_CxSRCADDR_SRCADDR_SHIFT) + +/* --- GPDMA_C[0..7]DESTADDR values ---------------------------------- */ + +/* DESTADDR: DMA source address */ +#define GPDMA_CxDESTADDR_DESTADDR_SHIFT (0) +#define GPDMA_CxDESTADDR_DESTADDR_MASK \ + (0xffffffff << GPDMA_CxDESTADDR_DESTADDR_SHIFT) +#define GPDMA_CxDESTADDR_DESTADDR(x) ((x) << GPDMA_CxDESTADDR_DESTADDR_SHIFT) + +/* --- GPDMA_C[0..7]LLI values --------------------------------------- */ + +/* LM: AHB master select for loading the next LLI */ +#define GPDMA_CxLLI_LM_SHIFT (0) +#define GPDMA_CxLLI_LM_MASK (0x1 << GPDMA_CxLLI_LM_SHIFT) +#define GPDMA_CxLLI_LM(x) ((x) << GPDMA_CxLLI_LM_SHIFT) + +/* LLI: Linked list item */ +#define GPDMA_CxLLI_LLI_SHIFT (2) +#define GPDMA_CxLLI_LLI_MASK (0x3fffffff << GPDMA_CxLLI_LLI_SHIFT) +#define GPDMA_CxLLI_LLI(x) ((x) << GPDMA_CxLLI_LLI_SHIFT) + +/* --- GPDMA_C[0..7]CONTROL values ----------------------------------- */ + +/* TRANSFERSIZE: Transfer size in number of transfers */ +#define GPDMA_CxCONTROL_TRANSFERSIZE_SHIFT (0) +#define GPDMA_CxCONTROL_TRANSFERSIZE_MASK \ + (0xfff << GPDMA_CxCONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_CxCONTROL_TRANSFERSIZE(x) \ + ((x) << GPDMA_CxCONTROL_TRANSFERSIZE_SHIFT) + +/* SBSIZE: Source burst size */ +#define GPDMA_CxCONTROL_SBSIZE_SHIFT (12) +#define GPDMA_CxCONTROL_SBSIZE_MASK (0x7 << GPDMA_CxCONTROL_SBSIZE_SHIFT) +#define GPDMA_CxCONTROL_SBSIZE(x) ((x) << GPDMA_CxCONTROL_SBSIZE_SHIFT) + +/* DBSIZE: Destination burst size */ +#define GPDMA_CxCONTROL_DBSIZE_SHIFT (15) +#define GPDMA_CxCONTROL_DBSIZE_MASK (0x7 << GPDMA_CxCONTROL_DBSIZE_SHIFT) +#define GPDMA_CxCONTROL_DBSIZE(x) ((x) << GPDMA_CxCONTROL_DBSIZE_SHIFT) + +/* SWIDTH: Source transfer width */ +#define GPDMA_CxCONTROL_SWIDTH_SHIFT (18) +#define GPDMA_CxCONTROL_SWIDTH_MASK (0x7 << GPDMA_CxCONTROL_SWIDTH_SHIFT) +#define GPDMA_CxCONTROL_SWIDTH(x) ((x) << GPDMA_CxCONTROL_SWIDTH_SHIFT) + +/* DWIDTH: Destination transfer width */ +#define GPDMA_CxCONTROL_DWIDTH_SHIFT (21) +#define GPDMA_CxCONTROL_DWIDTH_MASK (0x7 << GPDMA_CxCONTROL_DWIDTH_SHIFT) +#define GPDMA_CxCONTROL_DWIDTH(x) ((x) << GPDMA_CxCONTROL_DWIDTH_SHIFT) + +/* S: Source AHB master select */ +#define GPDMA_CxCONTROL_S_SHIFT (24) +#define GPDMA_CxCONTROL_S_MASK (0x1 << GPDMA_CxCONTROL_S_SHIFT) +#define GPDMA_CxCONTROL_S(x) ((x) << GPDMA_CxCONTROL_S_SHIFT) + +/* D: Destination AHB master select */ +#define GPDMA_CxCONTROL_D_SHIFT (25) +#define GPDMA_CxCONTROL_D_MASK (0x1 << GPDMA_CxCONTROL_D_SHIFT) +#define GPDMA_CxCONTROL_D(x) ((x) << GPDMA_CxCONTROL_D_SHIFT) + +/* SI: Source increment */ +#define GPDMA_CxCONTROL_SI_SHIFT (26) +#define GPDMA_CxCONTROL_SI_MASK (0x1 << GPDMA_CxCONTROL_SI_SHIFT) +#define GPDMA_Cx0CONTROL_SI(x) ((x) << GPDMA_CxCONTROL_SI_SHIFT) + +/* DI: Destination increment */ +#define GPDMA_CxCONTROL_DI_SHIFT (27) +#define GPDMA_CxCONTROL_DI_MASK (0x1 << GPDMA_CxCONTROL_DI_SHIFT) +#define GPDMA_CxCONTROL_DI(x) ((x) << GPDMA_CxCONTROL_DI_SHIFT) + +/* PROT1: This information is provided to the peripheral during a DMA bus + access and indicates that the access is in user mode or privileged mode */ +#define GPDMA_CxCONTROL_PROT1_SHIFT (28) +#define GPDMA_CxCONTROL_PROT1_MASK (0x1 << GPDMA_CxCONTROL_PROT1_SHIFT) +#define GPDMA_CxCONTROL_PROT1(x) ((x) << GPDMA_CxCONTROL_PROT1_SHIFT) + +/* PROT2: This information is provided to the peripheral during a DMA bus + access and indicates to the peripheral that the access is bufferable or not + bufferable */ +#define GPDMA_CxCONTROL_PROT2_SHIFT (29) +#define GPDMA_CxCONTROL_PROT2_MASK (0x1 << GPDMA_CxCONTROL_PROT2_SHIFT) +#define GPDMA_CxCONTROL_PROT2(x) ((x) << GPDMA_CxCONTROL_PROT2_SHIFT) + +/* PROT3: This information is provided to the peripheral during a DMA bus + access and indicates to the peripheral that the access is cacheable or not + cacheable */ +#define GPDMA_CxCONTROL_PROT3_SHIFT (30) +#define GPDMA_CxCONTROL_PROT3_MASK (0x1 << GPDMA_CxCONTROL_PROT3_SHIFT) +#define GPDMA_CxCONTROL_PROT3(x) ((x) << GPDMA_CxCONTROL_PROT3_SHIFT) + +/* I: Terminal count interrupt enable bit */ +#define GPDMA_CxCONTROL_I_SHIFT (31) +#define GPDMA_CxCONTROL_I_MASK (0x1 << GPDMA_CxCONTROL_I_SHIFT) +#define GPDMA_CxCONTROL_I(x) ((x) << GPDMA_CxCONTROL_I_SHIFT) + +/* --- GPDMA_C[0..7]CONFIG values ------------------------------------ */ + +/* E: Channel enable */ +#define GPDMA_CxCONFIG_E_SHIFT (0) +#define GPDMA_CxCONFIG_E_MASK (0x1 << GPDMA_CxCONFIG_E_SHIFT) +#define GPDMA_CxCONFIG_E(x) ((x) << GPDMA_CxCONFIG_E_SHIFT) + +/* SRCPERIPHERAL: Source peripheral */ +#define GPDMA_CxCONFIG_SRCPERIPHERAL_SHIFT (1) +#define GPDMA_CxCONFIG_SRCPERIPHERAL_MASK \ + (0x1f << GPDMA_CxCONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_CxCONFIG_SRCPERIPHERAL(x) \ + ((x) << GPDMA_CxCONFIG_SRCPERIPHERAL_SHIFT) + +/* DESTPERIPHERAL: Destination peripheral */ +#define GPDMA_CxCONFIG_DESTPERIPHERAL_SHIFT (6) +#define GPDMA_CxCONFIG_DESTPERIPHERAL_MASK \ + (0x1f << GPDMA_CxCONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_CxCONFIG_DESTPERIPHERAL(x) \ + ((x) << GPDMA_CxCONFIG_DESTPERIPHERAL_SHIFT) + +/* FLOWCNTRL: Flow control and transfer type */ +#define GPDMA_CxCONFIG_FLOWCNTRL_SHIFT (11) +#define GPDMA_CxCONFIG_FLOWCNTRL_MASK (0x7 << GPDMA_CxCONFIG_FLOWCNTRL_SHIFT) +#define GPDMA_CxCONFIG_FLOWCNTRL(x) ((x) << GPDMA_CxCONFIG_FLOWCNTRL_SHIFT) + +/* IE: Interrupt error mask */ +#define GPDMA_CxCONFIG_IE_SHIFT (14) +#define GPDMA_CxCONFIG_IE_MASK (0x1 << GPDMA_CxCONFIG_IE_SHIFT) +#define GPDMA_CxCONFIG_IE(x) ((x) << GPDMA_CxCONFIG_IE_SHIFT) + +/* ITC: Terminal count interrupt mask */ +#define GPDMA_CxCONFIG_ITC_SHIFT (15) +#define GPDMA_CxCONFIG_ITC_MASK (0x1 << GPDMA_CxCONFIG_ITC_SHIFT) +#define GPDMA_CxCONFIG_ITC(x) ((x) << GPDMA_CxCONFIG_ITC_SHIFT) + +/* L: Lock */ +#define GPDMA_CxCONFIG_L_SHIFT (16) +#define GPDMA_CxCONFIG_L_MASK (0x1 << GPDMA_CxCONFIG_L_SHIFT) +#define GPDMA_CxCONFIG_L(x) ((x) << GPDMA_CxCONFIG_L_SHIFT) + +/* A: Active */ +#define GPDMA_CxCONFIG_A_SHIFT (17) +#define GPDMA_CxCONFIG_A_MASK (0x1 << GPDMA_CxCONFIG_A_SHIFT) +#define GPDMA_CxCONFIG_A(x) ((x) << GPDMA_CxCONFIG_A_SHIFT) + +/* H: Halt */ +#define GPDMA_CxCONFIG_H_SHIFT (18) +#define GPDMA_CxCONFIG_H_MASK (0x1 << GPDMA_CxCONFIG_H_SHIFT) +#define GPDMA_CxCONFIG_H(x) ((x) << GPDMA_CxCONFIG_H_SHIFT) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/gpio.h b/libopencm3/include/libopencm3/lpc43xx/gpio.h new file mode 100644 index 0000000..6747470 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/gpio.h @@ -0,0 +1,784 @@ +/** @defgroup gpio_defines General Purpose I/O Defines + +@brief Defined Constants and Types for the LPC43xx General Purpose I/O + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC43XX_GPIO_H +#define LPC43XX_GPIO_H + +/**@{*/ + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* GPIO port base addresses (for convenience) */ +#define GPIO0 (GPIO_PORT_BASE + 0x2000) +#define GPIO1 (GPIO_PORT_BASE + 0x2004) +#define GPIO2 (GPIO_PORT_BASE + 0x2008) +#define GPIO3 (GPIO_PORT_BASE + 0x200C) +#define GPIO4 (GPIO_PORT_BASE + 0x2010) +#define GPIO5 (GPIO_PORT_BASE + 0x2014) +#define GPIO6 (GPIO_PORT_BASE + 0x2018) +#define GPIO7 (GPIO_PORT_BASE + 0x201C) + +/* GPIO number definitions (for convenience) */ +#define GPIOPIN0 (1 << 0) +#define GPIOPIN1 (1 << 1) +#define GPIOPIN2 (1 << 2) +#define GPIOPIN3 (1 << 3) +#define GPIOPIN4 (1 << 4) +#define GPIOPIN5 (1 << 5) +#define GPIOPIN6 (1 << 6) +#define GPIOPIN7 (1 << 7) +#define GPIOPIN8 (1 << 8) +#define GPIOPIN9 (1 << 9) +#define GPIOPIN10 (1 << 10) +#define GPIOPIN11 (1 << 11) +#define GPIOPIN12 (1 << 12) +#define GPIOPIN13 (1 << 13) +#define GPIOPIN14 (1 << 14) +#define GPIOPIN15 (1 << 15) +#define GPIOPIN16 (1 << 16) +#define GPIOPIN17 (1 << 17) +#define GPIOPIN18 (1 << 18) +#define GPIOPIN19 (1 << 19) +#define GPIOPIN20 (1 << 20) +#define GPIOPIN21 (1 << 21) +#define GPIOPIN22 (1 << 22) +#define GPIOPIN23 (1 << 23) +#define GPIOPIN24 (1 << 24) +#define GPIOPIN25 (1 << 25) +#define GPIOPIN26 (1 << 26) +#define GPIOPIN27 (1 << 27) +#define GPIOPIN28 (1 << 28) +#define GPIOPIN29 (1 << 29) +#define GPIOPIN30 (1 << 30) +#define GPIOPIN31 (1 << 31) + +/* --- GPIO registers ------------------------------------------------------ */ + +/* GPIO pin interrupts */ + +/* Pin Interrupt Mode register */ +#define GPIO_PIN_INTERRUPT_ISEL MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x000) + +/* Pin interrupt level (rising edge) interrupt enable register */ +#define GPIO_PIN_INTERRUPT_IENR MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x004) + +/* Pin interrupt level (rising edge) interrupt set register */ +#define GPIO_PIN_INTERRUPT_SIENR MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x008) + +/* Pin interrupt level (rising edge interrupt) clear register */ +#define GPIO_PIN_INTERRUPT_CIENR MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x00C) + +/* Pin interrupt active level (falling edge) interrupt enable register */ +#define GPIO_PIN_INTERRUPT_IENF MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x010) + +/* Pin interrupt active level (falling edge) interrupt set register */ +#define GPIO_PIN_INTERRUPT_SIENF MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x014) + +/* Pin interrupt active level (falling edge) interrupt clear register */ +#define GPIO_PIN_INTERRUPT_CIENF MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x018) + +/* Pin interrupt rising edge register */ +#define GPIO_PIN_INTERRUPT_RISE MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x01C) + +/* Pin interrupt falling edge register */ +#define GPIO_PIN_INTERRUPT_FALL MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x020) + +/* Pin interrupt status register */ +#define GPIO_PIN_INTERRUPT_IST MMIO32(GPIO_PIN_INTERRUPT_BASE + 0x024) + +/* GPIO GROUP0 interrupt */ + +/* GPIO grouped interrupt control register */ +#define GPIO_GROUP0_INTERRUPT_CTRL \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x000) + +/* GPIO grouped interrupt port [0..7] polarity register */ +#define GPIO_GROUP0_INTERRUPT_PORT_POL(x) \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x020 + ((x)*4)) + +/* GPIO grouped interrupt port [0..7] enable register */ +#define GPIO_GROUP0_INTERRUPT_PORT_ENA(x) \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x040 + ((x)*4)) + +/* GPIO GROUP1 interrupt */ + +/* GPIO grouped interrupt control register */ +#define GPIO_GROUP1_INTERRUPT_CTRL \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x000) + +/* GPIO grouped interrupt port [0..7] polarity register */ +#define GPIO_GROUP1_INTERRUPT_PORT_POL(x) \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x020 + ((x)*4)) + +/* GPIO grouped interrupt port [0..7] enable register */ +#define GPIO_GROUP1_INTERRUPT_PORT_ENA(x) \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x040 + ((x)*4)) + +/* Byte pin registers port 0; pins PIO0_0 to PIO0_31 (R/W) */ +#define GPIO_B0 (GPIO_PORT_BASE + 0x0000) +#define GPIO_B1 (GPIO_PORT_BASE + 0x0001) +#define GPIO_B2 (GPIO_PORT_BASE + 0x0002) +#define GPIO_B3 (GPIO_PORT_BASE + 0x0003) +#define GPIO_B4 (GPIO_PORT_BASE + 0x0004) +#define GPIO_B5 (GPIO_PORT_BASE + 0x0005) +#define GPIO_B6 (GPIO_PORT_BASE + 0x0006) +#define GPIO_B7 (GPIO_PORT_BASE + 0x0007) +#define GPIO_B8 (GPIO_PORT_BASE + 0x0008) +#define GPIO_B9 (GPIO_PORT_BASE + 0x0009) +#define GPIO_B10 (GPIO_PORT_BASE + 0x000A) +#define GPIO_B11 (GPIO_PORT_BASE + 0x000B) +#define GPIO_B12 (GPIO_PORT_BASE + 0x000C) +#define GPIO_B13 (GPIO_PORT_BASE + 0x000D) +#define GPIO_B14 (GPIO_PORT_BASE + 0x000E) +#define GPIO_B15 (GPIO_PORT_BASE + 0x000F) +#define GPIO_B16 (GPIO_PORT_BASE + 0x0010) +#define GPIO_B17 (GPIO_PORT_BASE + 0x0011) +#define GPIO_B18 (GPIO_PORT_BASE + 0x0012) +#define GPIO_B19 (GPIO_PORT_BASE + 0x0013) +#define GPIO_B20 (GPIO_PORT_BASE + 0x0014) +#define GPIO_B21 (GPIO_PORT_BASE + 0x0015) +#define GPIO_B22 (GPIO_PORT_BASE + 0x0016) +#define GPIO_B23 (GPIO_PORT_BASE + 0x0017) +#define GPIO_B24 (GPIO_PORT_BASE + 0x0018) +#define GPIO_B25 (GPIO_PORT_BASE + 0x0019) +#define GPIO_B26 (GPIO_PORT_BASE + 0x001A) +#define GPIO_B27 (GPIO_PORT_BASE + 0x001B) +#define GPIO_B28 (GPIO_PORT_BASE + 0x001C) +#define GPIO_B29 (GPIO_PORT_BASE + 0x001D) +#define GPIO_B30 (GPIO_PORT_BASE + 0x001E) +#define GPIO_B31 (GPIO_PORT_BASE + 0x001F) + +/* Byte pin registers port 1 (R/W) */ +#define GPIO_B32 (GPIO_PORT_BASE + 0x0020) +#define GPIO_B33 (GPIO_PORT_BASE + 0x0021) +#define GPIO_B34 (GPIO_PORT_BASE + 0x0022) +#define GPIO_B35 (GPIO_PORT_BASE + 0x0023) +#define GPIO_B36 (GPIO_PORT_BASE + 0x0024) +#define GPIO_B37 (GPIO_PORT_BASE + 0x0025) +#define GPIO_B38 (GPIO_PORT_BASE + 0x0026) +#define GPIO_B39 (GPIO_PORT_BASE + 0x0027) +#define GPIO_B40 (GPIO_PORT_BASE + 0x0028) +#define GPIO_B41 (GPIO_PORT_BASE + 0x0029) +#define GPIO_B42 (GPIO_PORT_BASE + 0x002A) +#define GPIO_B43 (GPIO_PORT_BASE + 0x002B) +#define GPIO_B44 (GPIO_PORT_BASE + 0x002C) +#define GPIO_B45 (GPIO_PORT_BASE + 0x002D) +#define GPIO_B46 (GPIO_PORT_BASE + 0x002E) +#define GPIO_B47 (GPIO_PORT_BASE + 0x002F) +#define GPIO_B48 (GPIO_PORT_BASE + 0x0030) +#define GPIO_B49 (GPIO_PORT_BASE + 0x0031) +#define GPIO_B50 (GPIO_PORT_BASE + 0x0032) +#define GPIO_B51 (GPIO_PORT_BASE + 0x0033) +#define GPIO_B52 (GPIO_PORT_BASE + 0x0034) +#define GPIO_B53 (GPIO_PORT_BASE + 0x0035) +#define GPIO_B54 (GPIO_PORT_BASE + 0x0036) +#define GPIO_B55 (GPIO_PORT_BASE + 0x0037) +#define GPIO_B56 (GPIO_PORT_BASE + 0x0038) +#define GPIO_B57 (GPIO_PORT_BASE + 0x0039) +#define GPIO_B58 (GPIO_PORT_BASE + 0x003A) +#define GPIO_B59 (GPIO_PORT_BASE + 0x003B) +#define GPIO_B60 (GPIO_PORT_BASE + 0x003C) +#define GPIO_B61 (GPIO_PORT_BASE + 0x003D) +#define GPIO_B62 (GPIO_PORT_BASE + 0x003E) +#define GPIO_B63 (GPIO_PORT_BASE + 0x003F) + +/* Byte pin registers port 2 (R/W) */ +#define GPIO_B64 (GPIO_PORT_BASE + 0x0040) +#define GPIO_B65 (GPIO_PORT_BASE + 0x0041) +#define GPIO_B66 (GPIO_PORT_BASE + 0x0042) +#define GPIO_B67 (GPIO_PORT_BASE + 0x0043) +#define GPIO_B68 (GPIO_PORT_BASE + 0x0044) +#define GPIO_B69 (GPIO_PORT_BASE + 0x0045) +#define GPIO_B70 (GPIO_PORT_BASE + 0x0046) +#define GPIO_B71 (GPIO_PORT_BASE + 0x0047) +#define GPIO_B72 (GPIO_PORT_BASE + 0x0048) +#define GPIO_B73 (GPIO_PORT_BASE + 0x0049) +#define GPIO_B74 (GPIO_PORT_BASE + 0x004A) +#define GPIO_B75 (GPIO_PORT_BASE + 0x004B) +#define GPIO_B76 (GPIO_PORT_BASE + 0x004C) +#define GPIO_B77 (GPIO_PORT_BASE + 0x004D) +#define GPIO_B78 (GPIO_PORT_BASE + 0x004E) +#define GPIO_B79 (GPIO_PORT_BASE + 0x004F) +#define GPIO_B80 (GPIO_PORT_BASE + 0x0050) +#define GPIO_B81 (GPIO_PORT_BASE + 0x0051) +#define GPIO_B82 (GPIO_PORT_BASE + 0x0052) +#define GPIO_B83 (GPIO_PORT_BASE + 0x0053) +#define GPIO_B84 (GPIO_PORT_BASE + 0x0054) +#define GPIO_B85 (GPIO_PORT_BASE + 0x0055) +#define GPIO_B86 (GPIO_PORT_BASE + 0x0056) +#define GPIO_B87 (GPIO_PORT_BASE + 0x0057) +#define GPIO_B88 (GPIO_PORT_BASE + 0x0058) +#define GPIO_B89 (GPIO_PORT_BASE + 0x0059) +#define GPIO_B90 (GPIO_PORT_BASE + 0x005A) +#define GPIO_B91 (GPIO_PORT_BASE + 0x005B) +#define GPIO_B92 (GPIO_PORT_BASE + 0x005C) +#define GPIO_B93 (GPIO_PORT_BASE + 0x005D) +#define GPIO_B94 (GPIO_PORT_BASE + 0x005E) +#define GPIO_B95 (GPIO_PORT_BASE + 0x005F) + +/* Byte pin registers port 3 (R/W) */ +#define GPIO_B96 (GPIO_PORT_BASE + 0x0060) +#define GPIO_B97 (GPIO_PORT_BASE + 0x0061) +#define GPIO_B98 (GPIO_PORT_BASE + 0x0062) +#define GPIO_B99 (GPIO_PORT_BASE + 0x0063) +#define GPIO_B100 (GPIO_PORT_BASE + 0x0064) +#define GPIO_B101 (GPIO_PORT_BASE + 0x0065) +#define GPIO_B102 (GPIO_PORT_BASE + 0x0066) +#define GPIO_B103 (GPIO_PORT_BASE + 0x0067) +#define GPIO_B104 (GPIO_PORT_BASE + 0x0068) +#define GPIO_B105 (GPIO_PORT_BASE + 0x0069) +#define GPIO_B106 (GPIO_PORT_BASE + 0x006A) +#define GPIO_B107 (GPIO_PORT_BASE + 0x006B) +#define GPIO_B108 (GPIO_PORT_BASE + 0x006C) +#define GPIO_B109 (GPIO_PORT_BASE + 0x006D) +#define GPIO_B110 (GPIO_PORT_BASE + 0x006E) +#define GPIO_B111 (GPIO_PORT_BASE + 0x006F) +#define GPIO_B112 (GPIO_PORT_BASE + 0x0070) +#define GPIO_B113 (GPIO_PORT_BASE + 0x0071) +#define GPIO_B114 (GPIO_PORT_BASE + 0x0072) +#define GPIO_B115 (GPIO_PORT_BASE + 0x0073) +#define GPIO_B116 (GPIO_PORT_BASE + 0x0074) +#define GPIO_B117 (GPIO_PORT_BASE + 0x0075) +#define GPIO_B118 (GPIO_PORT_BASE + 0x0076) +#define GPIO_B119 (GPIO_PORT_BASE + 0x0077) +#define GPIO_B120 (GPIO_PORT_BASE + 0x0078) +#define GPIO_B121 (GPIO_PORT_BASE + 0x0079) +#define GPIO_B122 (GPIO_PORT_BASE + 0x007A) +#define GPIO_B123 (GPIO_PORT_BASE + 0x007B) +#define GPIO_B124 (GPIO_PORT_BASE + 0x007C) +#define GPIO_B125 (GPIO_PORT_BASE + 0x007D) +#define GPIO_B126 (GPIO_PORT_BASE + 0x007E) +#define GPIO_B127 (GPIO_PORT_BASE + 0x007F) + +/* Byte pin registers port 4 (R/W) */ +#define GPIO_B128 (GPIO_PORT_BASE + 0x0080) +#define GPIO_B129 (GPIO_PORT_BASE + 0x0081) +#define GPIO_B130 (GPIO_PORT_BASE + 0x0082) +#define GPIO_B131 (GPIO_PORT_BASE + 0x0083) +#define GPIO_B132 (GPIO_PORT_BASE + 0x0084) +#define GPIO_B133 (GPIO_PORT_BASE + 0x0085) +#define GPIO_B134 (GPIO_PORT_BASE + 0x0086) +#define GPIO_B135 (GPIO_PORT_BASE + 0x0087) +#define GPIO_B136 (GPIO_PORT_BASE + 0x0088) +#define GPIO_B137 (GPIO_PORT_BASE + 0x0089) +#define GPIO_B138 (GPIO_PORT_BASE + 0x008A) +#define GPIO_B139 (GPIO_PORT_BASE + 0x008B) +#define GPIO_B140 (GPIO_PORT_BASE + 0x008C) +#define GPIO_B141 (GPIO_PORT_BASE + 0x008D) +#define GPIO_B142 (GPIO_PORT_BASE + 0x008E) +#define GPIO_B143 (GPIO_PORT_BASE + 0x008F) +#define GPIO_B144 (GPIO_PORT_BASE + 0x0090) +#define GPIO_B145 (GPIO_PORT_BASE + 0x0091) +#define GPIO_B146 (GPIO_PORT_BASE + 0x0092) +#define GPIO_B147 (GPIO_PORT_BASE + 0x0093) +#define GPIO_B148 (GPIO_PORT_BASE + 0x0094) +#define GPIO_B149 (GPIO_PORT_BASE + 0x0095) +#define GPIO_B150 (GPIO_PORT_BASE + 0x0096) +#define GPIO_B151 (GPIO_PORT_BASE + 0x0097) +#define GPIO_B152 (GPIO_PORT_BASE + 0x0098) +#define GPIO_B153 (GPIO_PORT_BASE + 0x0099) +#define GPIO_B154 (GPIO_PORT_BASE + 0x009A) +#define GPIO_B155 (GPIO_PORT_BASE + 0x009B) +#define GPIO_B156 (GPIO_PORT_BASE + 0x009C) +#define GPIO_B157 (GPIO_PORT_BASE + 0x009D) +#define GPIO_B158 (GPIO_PORT_BASE + 0x009E) +#define GPIO_B159 (GPIO_PORT_BASE + 0x009F) + +/* Byte pin registers port 5 (R/W) */ +#define GPIO_B160 (GPIO_PORT_BASE + 0x00A0) +#define GPIO_B161 (GPIO_PORT_BASE + 0x00A1) +#define GPIO_B162 (GPIO_PORT_BASE + 0x00A2) +#define GPIO_B163 (GPIO_PORT_BASE + 0x00A3) +#define GPIO_B164 (GPIO_PORT_BASE + 0x00A4) +#define GPIO_B165 (GPIO_PORT_BASE + 0x00A5) +#define GPIO_B166 (GPIO_PORT_BASE + 0x00A6) +#define GPIO_B167 (GPIO_PORT_BASE + 0x00A7) +#define GPIO_B168 (GPIO_PORT_BASE + 0x00A8) +#define GPIO_B169 (GPIO_PORT_BASE + 0x00A9) +#define GPIO_B170 (GPIO_PORT_BASE + 0x00AA) +#define GPIO_B171 (GPIO_PORT_BASE + 0x00AB) +#define GPIO_B172 (GPIO_PORT_BASE + 0x00AC) +#define GPIO_B173 (GPIO_PORT_BASE + 0x00AD) +#define GPIO_B174 (GPIO_PORT_BASE + 0x00AE) +#define GPIO_B175 (GPIO_PORT_BASE + 0x00AF) +#define GPIO_B176 (GPIO_PORT_BASE + 0x00B0) +#define GPIO_B177 (GPIO_PORT_BASE + 0x00B1) +#define GPIO_B178 (GPIO_PORT_BASE + 0x00B2) +#define GPIO_B179 (GPIO_PORT_BASE + 0x00B3) +#define GPIO_B180 (GPIO_PORT_BASE + 0x00B4) +#define GPIO_B181 (GPIO_PORT_BASE + 0x00B5) +#define GPIO_B182 (GPIO_PORT_BASE + 0x00B6) +#define GPIO_B183 (GPIO_PORT_BASE + 0x00B7) +#define GPIO_B184 (GPIO_PORT_BASE + 0x00B8) +#define GPIO_B185 (GPIO_PORT_BASE + 0x00B9) +#define GPIO_B186 (GPIO_PORT_BASE + 0x00BA) +#define GPIO_B187 (GPIO_PORT_BASE + 0x00BB) +#define GPIO_B188 (GPIO_PORT_BASE + 0x00BC) +#define GPIO_B189 (GPIO_PORT_BASE + 0x00BD) +#define GPIO_B190 (GPIO_PORT_BASE + 0x00BE) +#define GPIO_B191 (GPIO_PORT_BASE + 0x00BF) + +/* Byte pin registers port 6 (R/W) */ +#define GPIO_B192 (GPIO_PORT_BASE + 0x00C0) +#define GPIO_B193 (GPIO_PORT_BASE + 0x00C1) +#define GPIO_B194 (GPIO_PORT_BASE + 0x00C2) +#define GPIO_B195 (GPIO_PORT_BASE + 0x00C3) +#define GPIO_B196 (GPIO_PORT_BASE + 0x00C4) +#define GPIO_B197 (GPIO_PORT_BASE + 0x00C5) +#define GPIO_B198 (GPIO_PORT_BASE + 0x00C6) +#define GPIO_B199 (GPIO_PORT_BASE + 0x00C7) +#define GPIO_B200 (GPIO_PORT_BASE + 0x00C8) +#define GPIO_B201 (GPIO_PORT_BASE + 0x00C9) +#define GPIO_B202 (GPIO_PORT_BASE + 0x00CA) +#define GPIO_B203 (GPIO_PORT_BASE + 0x00CB) +#define GPIO_B204 (GPIO_PORT_BASE + 0x00CC) +#define GPIO_B205 (GPIO_PORT_BASE + 0x00CD) +#define GPIO_B206 (GPIO_PORT_BASE + 0x00CE) +#define GPIO_B207 (GPIO_PORT_BASE + 0x00CF) +#define GPIO_B208 (GPIO_PORT_BASE + 0x00D0) +#define GPIO_B209 (GPIO_PORT_BASE + 0x00D1) +#define GPIO_B210 (GPIO_PORT_BASE + 0x00D2) +#define GPIO_B211 (GPIO_PORT_BASE + 0x00D3) +#define GPIO_B212 (GPIO_PORT_BASE + 0x00D4) +#define GPIO_B213 (GPIO_PORT_BASE + 0x00D5) +#define GPIO_B214 (GPIO_PORT_BASE + 0x00D6) +#define GPIO_B215 (GPIO_PORT_BASE + 0x00D7) +#define GPIO_B216 (GPIO_PORT_BASE + 0x00D8) +#define GPIO_B217 (GPIO_PORT_BASE + 0x00D9) +#define GPIO_B218 (GPIO_PORT_BASE + 0x00DA) +#define GPIO_B219 (GPIO_PORT_BASE + 0x00DB) +#define GPIO_B220 (GPIO_PORT_BASE + 0x00DC) +#define GPIO_B221 (GPIO_PORT_BASE + 0x00DD) +#define GPIO_B222 (GPIO_PORT_BASE + 0x00DE) +#define GPIO_B223 (GPIO_PORT_BASE + 0x00DF) + +/* Byte pin registers port 7 (R/W) */ +#define GPIO_B224 (GPIO_PORT_BASE + 0x00E0) +#define GPIO_B225 (GPIO_PORT_BASE + 0x00E1) +#define GPIO_B226 (GPIO_PORT_BASE + 0x00E2) +#define GPIO_B227 (GPIO_PORT_BASE + 0x00E3) +#define GPIO_B228 (GPIO_PORT_BASE + 0x00E4) +#define GPIO_B229 (GPIO_PORT_BASE + 0x00E5) +#define GPIO_B230 (GPIO_PORT_BASE + 0x00E6) +#define GPIO_B231 (GPIO_PORT_BASE + 0x00E7) +#define GPIO_B232 (GPIO_PORT_BASE + 0x00E8) +#define GPIO_B233 (GPIO_PORT_BASE + 0x00E9) +#define GPIO_B234 (GPIO_PORT_BASE + 0x00EA) +#define GPIO_B235 (GPIO_PORT_BASE + 0x00EB) +#define GPIO_B236 (GPIO_PORT_BASE + 0x00EC) +#define GPIO_B237 (GPIO_PORT_BASE + 0x00ED) +#define GPIO_B238 (GPIO_PORT_BASE + 0x00EE) +#define GPIO_B239 (GPIO_PORT_BASE + 0x00EF) +#define GPIO_B240 (GPIO_PORT_BASE + 0x00F0) +#define GPIO_B241 (GPIO_PORT_BASE + 0x00F1) +#define GPIO_B242 (GPIO_PORT_BASE + 0x00F2) +#define GPIO_B243 (GPIO_PORT_BASE + 0x00F3) +#define GPIO_B244 (GPIO_PORT_BASE + 0x00F4) +#define GPIO_B245 (GPIO_PORT_BASE + 0x00F5) +#define GPIO_B246 (GPIO_PORT_BASE + 0x00F6) +#define GPIO_B247 (GPIO_PORT_BASE + 0x00F7) +#define GPIO_B248 (GPIO_PORT_BASE + 0x00F8) +#define GPIO_B249 (GPIO_PORT_BASE + 0x00F9) +#define GPIO_B250 (GPIO_PORT_BASE + 0x00FA) +#define GPIO_B251 (GPIO_PORT_BASE + 0x00FB) +#define GPIO_B252 (GPIO_PORT_BASE + 0x00FC) +#define GPIO_B253 (GPIO_PORT_BASE + 0x00FD) +#define GPIO_B254 (GPIO_PORT_BASE + 0x00FE) +#define GPIO_B255 (GPIO_PORT_BASE + 0x00FF) + +/* Word pin registers port 0 (R/W) */ +#define GPIO_W0 (GPIO_PORT_BASE + 0x1000) +#define GPIO_W1 (GPIO_PORT_BASE + 0x1004) +#define GPIO_W2 (GPIO_PORT_BASE + 0x1008) +#define GPIO_W3 (GPIO_PORT_BASE + 0x100C) +#define GPIO_W4 (GPIO_PORT_BASE + 0x1010) +#define GPIO_W5 (GPIO_PORT_BASE + 0x1014) +#define GPIO_W6 (GPIO_PORT_BASE + 0x1018) +#define GPIO_W7 (GPIO_PORT_BASE + 0x101C) +#define GPIO_W8 (GPIO_PORT_BASE + 0x1020) +#define GPIO_W9 (GPIO_PORT_BASE + 0x1024) +#define GPIO_W10 (GPIO_PORT_BASE + 0x1028) +#define GPIO_W11 (GPIO_PORT_BASE + 0x102C) +#define GPIO_W12 (GPIO_PORT_BASE + 0x1030) +#define GPIO_W13 (GPIO_PORT_BASE + 0x1034) +#define GPIO_W14 (GPIO_PORT_BASE + 0x1038) +#define GPIO_W15 (GPIO_PORT_BASE + 0x103C) +#define GPIO_W16 (GPIO_PORT_BASE + 0x1040) +#define GPIO_W17 (GPIO_PORT_BASE + 0x1044) +#define GPIO_W18 (GPIO_PORT_BASE + 0x1048) +#define GPIO_W19 (GPIO_PORT_BASE + 0x104C) +#define GPIO_W20 (GPIO_PORT_BASE + 0x1050) +#define GPIO_W21 (GPIO_PORT_BASE + 0x1054) +#define GPIO_W22 (GPIO_PORT_BASE + 0x1058) +#define GPIO_W23 (GPIO_PORT_BASE + 0x105C) +#define GPIO_W24 (GPIO_PORT_BASE + 0x1060) +#define GPIO_W25 (GPIO_PORT_BASE + 0x1064) +#define GPIO_W26 (GPIO_PORT_BASE + 0x1068) +#define GPIO_W27 (GPIO_PORT_BASE + 0x106C) +#define GPIO_W28 (GPIO_PORT_BASE + 0x1070) +#define GPIO_W29 (GPIO_PORT_BASE + 0x1074) +#define GPIO_W30 (GPIO_PORT_BASE + 0x1078) +#define GPIO_W31 (GPIO_PORT_BASE + 0x107C) + +/* Word pin registers port 1 (R/W) */ +#define GPIO_W32 (GPIO_PORT_BASE + 0x1080) +#define GPIO_W33 (GPIO_PORT_BASE + 0x1084) +#define GPIO_W34 (GPIO_PORT_BASE + 0x1088) +#define GPIO_W35 (GPIO_PORT_BASE + 0x108C) +#define GPIO_W36 (GPIO_PORT_BASE + 0x1090) +#define GPIO_W37 (GPIO_PORT_BASE + 0x1094) +#define GPIO_W38 (GPIO_PORT_BASE + 0x1098) +#define GPIO_W39 (GPIO_PORT_BASE + 0x109C) +#define GPIO_W40 (GPIO_PORT_BASE + 0x10A0) +#define GPIO_W41 (GPIO_PORT_BASE + 0x10A4) +#define GPIO_W42 (GPIO_PORT_BASE + 0x10A8) +#define GPIO_W43 (GPIO_PORT_BASE + 0x10AC) +#define GPIO_W44 (GPIO_PORT_BASE + 0x10B0) +#define GPIO_W45 (GPIO_PORT_BASE + 0x10B4) +#define GPIO_W46 (GPIO_PORT_BASE + 0x10B8) +#define GPIO_W47 (GPIO_PORT_BASE + 0x10BC) +#define GPIO_W48 (GPIO_PORT_BASE + 0x10C0) +#define GPIO_W49 (GPIO_PORT_BASE + 0x10C4) +#define GPIO_W50 (GPIO_PORT_BASE + 0x10C8) +#define GPIO_W51 (GPIO_PORT_BASE + 0x10CC) +#define GPIO_W52 (GPIO_PORT_BASE + 0x10D0) +#define GPIO_W53 (GPIO_PORT_BASE + 0x10D4) +#define GPIO_W54 (GPIO_PORT_BASE + 0x10D8) +#define GPIO_W55 (GPIO_PORT_BASE + 0x10DC) +#define GPIO_W56 (GPIO_PORT_BASE + 0x10E0) +#define GPIO_W57 (GPIO_PORT_BASE + 0x10E4) +#define GPIO_W58 (GPIO_PORT_BASE + 0x10E8) +#define GPIO_W59 (GPIO_PORT_BASE + 0x10EC) +#define GPIO_W60 (GPIO_PORT_BASE + 0x10F0) +#define GPIO_W61 (GPIO_PORT_BASE + 0x10F4) +#define GPIO_W62 (GPIO_PORT_BASE + 0x10F8) +#define GPIO_W63 (GPIO_PORT_BASE + 0x10FC) + +/* Word pin registers port 2 (R/W) */ +#define GPIO_W64 (GPIO_PORT_BASE + 0x1100) +#define GPIO_W65 (GPIO_PORT_BASE + 0x1104) +#define GPIO_W66 (GPIO_PORT_BASE + 0x1108) +#define GPIO_W67 (GPIO_PORT_BASE + 0x110C) +#define GPIO_W68 (GPIO_PORT_BASE + 0x1110) +#define GPIO_W69 (GPIO_PORT_BASE + 0x1114) +#define GPIO_W70 (GPIO_PORT_BASE + 0x1118) +#define GPIO_W71 (GPIO_PORT_BASE + 0x111C) +#define GPIO_W72 (GPIO_PORT_BASE + 0x1120) +#define GPIO_W73 (GPIO_PORT_BASE + 0x1124) +#define GPIO_W74 (GPIO_PORT_BASE + 0x1128) +#define GPIO_W75 (GPIO_PORT_BASE + 0x112C) +#define GPIO_W76 (GPIO_PORT_BASE + 0x1130) +#define GPIO_W77 (GPIO_PORT_BASE + 0x1134) +#define GPIO_W78 (GPIO_PORT_BASE + 0x1138) +#define GPIO_W79 (GPIO_PORT_BASE + 0x113C) +#define GPIO_W80 (GPIO_PORT_BASE + 0x1140) +#define GPIO_W81 (GPIO_PORT_BASE + 0x1144) +#define GPIO_W82 (GPIO_PORT_BASE + 0x1148) +#define GPIO_W83 (GPIO_PORT_BASE + 0x114C) +#define GPIO_W84 (GPIO_PORT_BASE + 0x1150) +#define GPIO_W85 (GPIO_PORT_BASE + 0x1154) +#define GPIO_W86 (GPIO_PORT_BASE + 0x1158) +#define GPIO_W87 (GPIO_PORT_BASE + 0x115C) +#define GPIO_W88 (GPIO_PORT_BASE + 0x1160) +#define GPIO_W89 (GPIO_PORT_BASE + 0x1164) +#define GPIO_W90 (GPIO_PORT_BASE + 0x1168) +#define GPIO_W91 (GPIO_PORT_BASE + 0x116C) +#define GPIO_W92 (GPIO_PORT_BASE + 0x1170) +#define GPIO_W93 (GPIO_PORT_BASE + 0x1174) +#define GPIO_W94 (GPIO_PORT_BASE + 0x1178) +#define GPIO_W95 (GPIO_PORT_BASE + 0x117C) + +/* Word pin registers port 3 (R/W) */ +#define GPIO_W96 (GPIO_PORT_BASE + 0x1180) +#define GPIO_W97 (GPIO_PORT_BASE + 0x1184) +#define GPIO_W98 (GPIO_PORT_BASE + 0x1188) +#define GPIO_W99 (GPIO_PORT_BASE + 0x118C) +#define GPIO_W100 (GPIO_PORT_BASE + 0x1190) +#define GPIO_W101 (GPIO_PORT_BASE + 0x1194) +#define GPIO_W102 (GPIO_PORT_BASE + 0x1198) +#define GPIO_W103 (GPIO_PORT_BASE + 0x119C) +#define GPIO_W104 (GPIO_PORT_BASE + 0x11A0) +#define GPIO_W105 (GPIO_PORT_BASE + 0x11A4) +#define GPIO_W106 (GPIO_PORT_BASE + 0x11A8) +#define GPIO_W107 (GPIO_PORT_BASE + 0x11AC) +#define GPIO_W108 (GPIO_PORT_BASE + 0x11B0) +#define GPIO_W109 (GPIO_PORT_BASE + 0x11B4) +#define GPIO_W110 (GPIO_PORT_BASE + 0x11B8) +#define GPIO_W111 (GPIO_PORT_BASE + 0x11BC) +#define GPIO_W112 (GPIO_PORT_BASE + 0x11C0) +#define GPIO_W113 (GPIO_PORT_BASE + 0x11C4) +#define GPIO_W114 (GPIO_PORT_BASE + 0x11C8) +#define GPIO_W115 (GPIO_PORT_BASE + 0x11CC) +#define GPIO_W116 (GPIO_PORT_BASE + 0x11D0) +#define GPIO_W117 (GPIO_PORT_BASE + 0x11D4) +#define GPIO_W118 (GPIO_PORT_BASE + 0x11D8) +#define GPIO_W119 (GPIO_PORT_BASE + 0x11DC) +#define GPIO_W120 (GPIO_PORT_BASE + 0x11E0) +#define GPIO_W121 (GPIO_PORT_BASE + 0x11E4) +#define GPIO_W122 (GPIO_PORT_BASE + 0x11E8) +#define GPIO_W123 (GPIO_PORT_BASE + 0x11EC) +#define GPIO_W124 (GPIO_PORT_BASE + 0x11F0) +#define GPIO_W125 (GPIO_PORT_BASE + 0x11F4) +#define GPIO_W126 (GPIO_PORT_BASE + 0x11F8) +#define GPIO_W127 (GPIO_PORT_BASE + 0x11FC) + +/* Word pin registers port 4 (R/W) */ +#define GPIO_W128 (GPIO_PORT_BASE + 0x1200) +#define GPIO_W129 (GPIO_PORT_BASE + 0x1204) +#define GPIO_W130 (GPIO_PORT_BASE + 0x1208) +#define GPIO_W131 (GPIO_PORT_BASE + 0x120C) +#define GPIO_W132 (GPIO_PORT_BASE + 0x1210) +#define GPIO_W133 (GPIO_PORT_BASE + 0x1214) +#define GPIO_W134 (GPIO_PORT_BASE + 0x1218) +#define GPIO_W135 (GPIO_PORT_BASE + 0x121C) +#define GPIO_W136 (GPIO_PORT_BASE + 0x1220) +#define GPIO_W137 (GPIO_PORT_BASE + 0x1224) +#define GPIO_W138 (GPIO_PORT_BASE + 0x1228) +#define GPIO_W139 (GPIO_PORT_BASE + 0x122C) +#define GPIO_W140 (GPIO_PORT_BASE + 0x1230) +#define GPIO_W141 (GPIO_PORT_BASE + 0x1234) +#define GPIO_W142 (GPIO_PORT_BASE + 0x1238) +#define GPIO_W143 (GPIO_PORT_BASE + 0x123C) +#define GPIO_W144 (GPIO_PORT_BASE + 0x1240) +#define GPIO_W145 (GPIO_PORT_BASE + 0x1244) +#define GPIO_W146 (GPIO_PORT_BASE + 0x1248) +#define GPIO_W147 (GPIO_PORT_BASE + 0x124C) +#define GPIO_W148 (GPIO_PORT_BASE + 0x1250) +#define GPIO_W149 (GPIO_PORT_BASE + 0x1254) +#define GPIO_W150 (GPIO_PORT_BASE + 0x1258) +#define GPIO_W151 (GPIO_PORT_BASE + 0x125C) +#define GPIO_W152 (GPIO_PORT_BASE + 0x1260) +#define GPIO_W153 (GPIO_PORT_BASE + 0x1264) +#define GPIO_W154 (GPIO_PORT_BASE + 0x1268) +#define GPIO_W155 (GPIO_PORT_BASE + 0x126C) +#define GPIO_W156 (GPIO_PORT_BASE + 0x1270) +#define GPIO_W157 (GPIO_PORT_BASE + 0x1274) +#define GPIO_W158 (GPIO_PORT_BASE + 0x1278) +#define GPIO_W159 (GPIO_PORT_BASE + 0x127C) + +/* Word pin registers port 5 (R/W) */ +#define GPIO_W160 (GPIO_PORT_BASE + 0x1280) +#define GPIO_W161 (GPIO_PORT_BASE + 0x1284) +#define GPIO_W162 (GPIO_PORT_BASE + 0x1288) +#define GPIO_W163 (GPIO_PORT_BASE + 0x128C) +#define GPIO_W164 (GPIO_PORT_BASE + 0x1290) +#define GPIO_W165 (GPIO_PORT_BASE + 0x1294) +#define GPIO_W166 (GPIO_PORT_BASE + 0x1298) +#define GPIO_W167 (GPIO_PORT_BASE + 0x129C) +#define GPIO_W168 (GPIO_PORT_BASE + 0x12A0) +#define GPIO_W169 (GPIO_PORT_BASE + 0x12A4) +#define GPIO_W170 (GPIO_PORT_BASE + 0x12A8) +#define GPIO_W171 (GPIO_PORT_BASE + 0x12AC) +#define GPIO_W172 (GPIO_PORT_BASE + 0x12B0) +#define GPIO_W173 (GPIO_PORT_BASE + 0x12B4) +#define GPIO_W174 (GPIO_PORT_BASE + 0x12B8) +#define GPIO_W175 (GPIO_PORT_BASE + 0x12BC) +#define GPIO_W176 (GPIO_PORT_BASE + 0x12C0) +#define GPIO_W177 (GPIO_PORT_BASE + 0x12C4) +#define GPIO_W178 (GPIO_PORT_BASE + 0x12C8) +#define GPIO_W179 (GPIO_PORT_BASE + 0x12CC) +#define GPIO_W180 (GPIO_PORT_BASE + 0x12D0) +#define GPIO_W181 (GPIO_PORT_BASE + 0x12D4) +#define GPIO_W182 (GPIO_PORT_BASE + 0x12D8) +#define GPIO_W183 (GPIO_PORT_BASE + 0x12DC) +#define GPIO_W184 (GPIO_PORT_BASE + 0x12E0) +#define GPIO_W185 (GPIO_PORT_BASE + 0x12E4) +#define GPIO_W186 (GPIO_PORT_BASE + 0x12E8) +#define GPIO_W187 (GPIO_PORT_BASE + 0x12EC) +#define GPIO_W188 (GPIO_PORT_BASE + 0x12F0) +#define GPIO_W189 (GPIO_PORT_BASE + 0x12F4) +#define GPIO_W190 (GPIO_PORT_BASE + 0x12F8) +#define GPIO_W191 (GPIO_PORT_BASE + 0x12FC) + +/* Word pin registers port 6 (R/W) */ +#define GPIO_W192 (GPIO_PORT_BASE + 0x1300) +#define GPIO_W193 (GPIO_PORT_BASE + 0x1304) +#define GPIO_W194 (GPIO_PORT_BASE + 0x1308) +#define GPIO_W195 (GPIO_PORT_BASE + 0x130C) +#define GPIO_W196 (GPIO_PORT_BASE + 0x1310) +#define GPIO_W197 (GPIO_PORT_BASE + 0x1314) +#define GPIO_W198 (GPIO_PORT_BASE + 0x1318) +#define GPIO_W199 (GPIO_PORT_BASE + 0x131C) +#define GPIO_W200 (GPIO_PORT_BASE + 0x1320) +#define GPIO_W201 (GPIO_PORT_BASE + 0x1324) +#define GPIO_W202 (GPIO_PORT_BASE + 0x1328) +#define GPIO_W203 (GPIO_PORT_BASE + 0x132C) +#define GPIO_W204 (GPIO_PORT_BASE + 0x1330) +#define GPIO_W205 (GPIO_PORT_BASE + 0x1334) +#define GPIO_W206 (GPIO_PORT_BASE + 0x1338) +#define GPIO_W207 (GPIO_PORT_BASE + 0x133C) +#define GPIO_W208 (GPIO_PORT_BASE + 0x1340) +#define GPIO_W209 (GPIO_PORT_BASE + 0x1344) +#define GPIO_W210 (GPIO_PORT_BASE + 0x1348) +#define GPIO_W211 (GPIO_PORT_BASE + 0x134C) +#define GPIO_W212 (GPIO_PORT_BASE + 0x1350) +#define GPIO_W213 (GPIO_PORT_BASE + 0x1354) +#define GPIO_W214 (GPIO_PORT_BASE + 0x1358) +#define GPIO_W215 (GPIO_PORT_BASE + 0x135C) +#define GPIO_W216 (GPIO_PORT_BASE + 0x1360) +#define GPIO_W217 (GPIO_PORT_BASE + 0x1364) +#define GPIO_W218 (GPIO_PORT_BASE + 0x1368) +#define GPIO_W219 (GPIO_PORT_BASE + 0x136C) +#define GPIO_W220 (GPIO_PORT_BASE + 0x1370) +#define GPIO_W221 (GPIO_PORT_BASE + 0x1374) +#define GPIO_W222 (GPIO_PORT_BASE + 0x1378) +#define GPIO_W223 (GPIO_PORT_BASE + 0x137C) + +/* Word pin registers port 7 (R/W) */ +#define GPIO_W224 (GPIO_PORT_BASE + 0x1380) +#define GPIO_W225 (GPIO_PORT_BASE + 0x1384) +#define GPIO_W226 (GPIO_PORT_BASE + 0x1388) +#define GPIO_W227 (GPIO_PORT_BASE + 0x138C) +#define GPIO_W228 (GPIO_PORT_BASE + 0x1390) +#define GPIO_W229 (GPIO_PORT_BASE + 0x1394) +#define GPIO_W230 (GPIO_PORT_BASE + 0x1398) +#define GPIO_W231 (GPIO_PORT_BASE + 0x139C) +#define GPIO_W232 (GPIO_PORT_BASE + 0x13A0) +#define GPIO_W233 (GPIO_PORT_BASE + 0x13A4) +#define GPIO_W234 (GPIO_PORT_BASE + 0x13A8) +#define GPIO_W235 (GPIO_PORT_BASE + 0x13AC) +#define GPIO_W236 (GPIO_PORT_BASE + 0x13B0) +#define GPIO_W237 (GPIO_PORT_BASE + 0x13B4) +#define GPIO_W238 (GPIO_PORT_BASE + 0x13B8) +#define GPIO_W239 (GPIO_PORT_BASE + 0x13BC) +#define GPIO_W240 (GPIO_PORT_BASE + 0x13C0) +#define GPIO_W241 (GPIO_PORT_BASE + 0x13C4) +#define GPIO_W242 (GPIO_PORT_BASE + 0x13C8) +#define GPIO_W243 (GPIO_PORT_BASE + 0x13CC) +#define GPIO_W244 (GPIO_PORT_BASE + 0x13D0) +#define GPIO_W245 (GPIO_PORT_BASE + 0x13D4) +#define GPIO_W246 (GPIO_PORT_BASE + 0x13D8) +#define GPIO_W247 (GPIO_PORT_BASE + 0x13DC) +#define GPIO_W248 (GPIO_PORT_BASE + 0x13E0) +#define GPIO_W249 (GPIO_PORT_BASE + 0x13E4) +#define GPIO_W250 (GPIO_PORT_BASE + 0x13E8) +#define GPIO_W251 (GPIO_PORT_BASE + 0x13EC) +#define GPIO_W252 (GPIO_PORT_BASE + 0x13F0) +#define GPIO_W253 (GPIO_PORT_BASE + 0x13F4) +#define GPIO_W254 (GPIO_PORT_BASE + 0x13F8) +#define GPIO_W255 (GPIO_PORT_BASE + 0x13FC) + +/* GPIO data direction register (GPIOn_DIR) */ +#define GPIO_DIR(port) MMIO32(port + 0x00) +#define GPIO0_DIR GPIO_DIR(GPIO0) +#define GPIO1_DIR GPIO_DIR(GPIO1) +#define GPIO2_DIR GPIO_DIR(GPIO2) +#define GPIO3_DIR GPIO_DIR(GPIO3) +#define GPIO4_DIR GPIO_DIR(GPIO4) +#define GPIO5_DIR GPIO_DIR(GPIO5) +#define GPIO6_DIR GPIO_DIR(GPIO6) +#define GPIO7_DIR GPIO_DIR(GPIO7) + +/* GPIO fast mask register (GPIOn_MASK) */ +#define GPIO_MASK(port) MMIO32(port + 0x80) +#define GPIO0_MASK GPIO_MASK(GPIO0) +#define GPIO1_MASK GPIO_MASK(GPIO1) +#define GPIO2_MASK GPIO_MASK(GPIO2) +#define GPIO3_MASK GPIO_MASK(GPIO3) +#define GPIO4_MASK GPIO_MASK(GPIO4) +#define GPIO5_MASK GPIO_MASK(GPIO5) +#define GPIO6_MASK GPIO_MASK(GPIO6) +#define GPIO7_MASK GPIO_MASK(GPIO7) + +/* GPIO port pin value register (GPIOn_PIN) */ +#define GPIO_PIN(port) MMIO32(port + 0x100) +#define GPIO0_PIN GPIO_PIN(GPIO0) +#define GPIO1_PIN GPIO_PIN(GPIO1) +#define GPIO2_PIN GPIO_PIN(GPIO2) +#define GPIO3_PIN GPIO_PIN(GPIO3) +#define GPIO4_PIN GPIO_PIN(GPIO4) +#define GPIO5_PIN GPIO_PIN(GPIO5) +#define GPIO6_PIN GPIO_PIN(GPIO6) +#define GPIO7_PIN GPIO_PIN(GPIO7) + +/* GPIO port masked pin value register (GPIOn_MPIN) */ +#define GPIO_MPIN(port) MMIO32(port + 0x180) +#define GPIO0_MPIN GPIO_MPIN(GPIO0) +#define GPIO1_MPIN GPIO_MPIN(GPIO1) +#define GPIO2_MPIN GPIO_MPIN(GPIO2) +#define GPIO3_MPIN GPIO_MPIN(GPIO3) +#define GPIO4_MPIN GPIO_MPIN(GPIO4) +#define GPIO5_MPIN GPIO_MPIN(GPIO5) +#define GPIO6_MPIN GPIO_MPIN(GPIO6) +#define GPIO7_MPIN GPIO_MPIN(GPIO7) + +/* GPIO port output set register (GPIOn_SET) */ +#define GPIO_SET(port) MMIO32(port + 0x200) +#define GPIO0_SET GPIO_SET(GPIO0) +#define GPIO1_SET GPIO_SET(GPIO1) +#define GPIO2_SET GPIO_SET(GPIO2) +#define GPIO3_SET GPIO_SET(GPIO3) +#define GPIO4_SET GPIO_SET(GPIO4) +#define GPIO5_SET GPIO_SET(GPIO5) +#define GPIO6_SET GPIO_SET(GPIO6) +#define GPIO7_SET GPIO_SET(GPIO7) + +/* GPIO port output clear register (GPIOn_CLR) */ +#define GPIO_CLR(port) MMIO32(port + 0x280) +#define GPIO0_CLR GPIO_CLR(GPIO0) +#define GPIO1_CLR GPIO_CLR(GPIO1) +#define GPIO2_CLR GPIO_CLR(GPIO2) +#define GPIO3_CLR GPIO_CLR(GPIO3) +#define GPIO4_CLR GPIO_CLR(GPIO4) +#define GPIO5_CLR GPIO_CLR(GPIO5) +#define GPIO6_CLR GPIO_CLR(GPIO6) +#define GPIO7_CLR GPIO_CLR(GPIO7) + +/* GPIO port toggle register (GPIOn_NOT) */ +#define GPIO_NOT(port) MMIO32(port + 0x300) +#define GPIO0_NOT GPIO_NOT(GPIO0) +#define GPIO1_NOT GPIO_NOT(GPIO1) +#define GPIO2_NOT GPIO_NOT(GPIO2) +#define GPIO3_NOT GPIO_NOT(GPIO3) +#define GPIO4_NOT GPIO_NOT(GPIO4) +#define GPIO5_NOT GPIO_NOT(GPIO5) +#define GPIO6_NOT GPIO_NOT(GPIO6) +#define GPIO7_NOT GPIO_NOT(GPIO7) + +/* TODO interrupts */ + +BEGIN_DECLS + +void gpio_set(uint32_t gpioport, uint32_t gpios); +void gpio_clear(uint32_t gpioport, uint32_t gpios); +void gpio_toggle(uint32_t gpioport, uint32_t gpios); + +END_DECLS + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/i2c.h b/libopencm3/include/libopencm3/lpc43xx/i2c.h new file mode 100644 index 0000000..2bab0b0 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/i2c.h @@ -0,0 +1,164 @@ +/** @defgroup i2c_defines I2C Defines + +@brief Defined Constants and Types for the LPC43xx I2C + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC43XX_I2C_H +#define LPC43XX_I2C_H + +/**@{*/ + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* I2C port base addresses (for convenience) */ +#define I2C0 I2C0_BASE +#define I2C1 I2C1_BASE + +/* --- I2C registers ------------------------------------------------------- */ + +/* I2C Control Set Register */ +#define I2C_CONSET(port) MMIO32(port + 0x000) +#define I2C0_CONSET I2C_CONSET(I2C0) +#define I2C1_CONSET I2C_CONSET(I2C1) + +/* I2C Status Register */ +#define I2C_STAT(port) MMIO32(port + 0x004) +#define I2C0_STAT I2C_STAT(I2C0) +#define I2C1_STAT I2C_STAT(I2C1) + +/* I2C Data Register */ +#define I2C_DAT(port) MMIO32(port + 0x008) +#define I2C0_DAT I2C_DAT(I2C0) +#define I2C1_DAT I2C_DAT(I2C1) + +/* I2C Slave Address Register 0 */ +#define I2C_ADR0(port) MMIO32(port + 0x00C) +#define I2C0_ADR0 I2C_ADR0(I2C0) +#define I2C1_ADR0 I2C_ADR0(I2C1) + +/* SCH Duty Cycle Register High Half Word */ +#define I2C_SCLH(port) MMIO32(port + 0x010) +#define I2C0_SCLH I2C_SCLH(I2C0) +#define I2C1_SCLH I2C_SCLH(I2C1) + +/* SCL Duty Cycle Register Low Half Word */ +#define I2C_SCLL(port) MMIO32(port + 0x014) +#define I2C0_SCLL I2C_SCLL(I2C0) +#define I2C1_SCLL I2C_SCLL(I2C1) + +/* I2C Control Clear Register */ +#define I2C_CONCLR(port) MMIO32(port + 0x018) +#define I2C0_CONCLR I2C_CONCLR(I2C0) +#define I2C1_CONCLR I2C_CONCLR(I2C1) + +/* Monitor mode control register */ +#define I2C_MMCTRL(port) MMIO32(port + 0x01C) +#define I2C0_MMCTRL I2C_MMCTRL(I2C0) +#define I2C1_MMCTRL I2C_MMCTRL(I2C1) + +/* I2C Slave Address Register 1 */ +#define I2C_ADR1(port) MMIO32(port + 0x020) +#define I2C0_ADR1 I2C_ADR1(I2C0) +#define I2C1_ADR1 I2C_ADR1(I2C1) + +/* I2C Slave Address Register 2 */ +#define I2C_ADR2(port) MMIO32(port + 0x024) +#define I2C0_ADR2 I2C_ADR2(I2C0) +#define I2C1_ADR2 I2C_ADR2(I2C1) + +/* I2C Slave Address Register 3 */ +#define I2C_ADR3(port) MMIO32(port + 0x028) +#define I2C0_ADR3 I2C_ADR3(I2C0) +#define I2C1_ADR3 I2C_ADR3(I2C1) + +/* Data buffer register */ +#define I2C_DATA_BUFFER(port) MMIO32(port + 0x02C) +#define I2C0_DATA_BUFFER I2C_DATA_BUFFER(I2C0) +#define I2C1_DATA_BUFFER I2C_DATA_BUFFER(I2C1) + +/* I2C Slave address mask register 0 */ +#define I2C_MASK0(port) MMIO32(port + 0x030) +#define I2C0_MASK0 I2C_MASK0(I2C0) +#define I2C1_MASK0 I2C_MASK0(I2C1) + +/* I2C Slave address mask register 1 */ +#define I2C_MASK1(port) MMIO32(port + 0x034) +#define I2C0_MASK1 I2C_MASK1(I2C0) +#define I2C1_MASK1 I2C_MASK1(I2C1) + +/* I2C Slave address mask register 2 */ +#define I2C_MASK2(port) MMIO32(port + 0x038) +#define I2C0_MASK2 I2C_MASK2(I2C0) +#define I2C1_MASK2 I2C_MASK2(I2C1) + +/* I2C Slave address mask register 3 */ +#define I2C_MASK3(port) MMIO32(port + 0x03C) +#define I2C0_MASK3 I2C_MASK3(I2C0) +#define I2C1_MASK3 I2C_MASK3(I2C1) + +/* --- I2Cx_CONCLR values -------------------------------------------------- */ + +#define I2C_CONCLR_AAC (1 << 2) /* Assert acknowledge Clear */ +#define I2C_CONCLR_SIC (1 << 3) /* I2C interrupt Clear */ +#define I2C_CONCLR_STAC (1 << 5) /* START flag Clear */ +#define I2C_CONCLR_I2ENC (1 << 6) /* I2C interface Disable bit */ + +/* --- I2Cx_CONSET values -------------------------------------------------- */ + +#define I2C_CONSET_AA (1 << 2) /* Assert acknowledge flag */ +#define I2C_CONSET_SI (1 << 3) /* I2C interrupt flag */ +#define I2C_CONSET_STO (1 << 4) /* STOP flag */ +#define I2C_CONSET_STA (1 << 5) /* START flag */ +#define I2C_CONSET_I2EN (1 << 6) /* I2C interface enable */ + +/* --- I2C const definitions ----------------------------------------------- */ + +#define I2C_WRITE 0 +#define I2C_READ 1 + +/* --- I2C function prototypes --------------------------------------------- */ + +BEGIN_DECLS + +void i2c0_init(const uint16_t duty_cycle_count); +void i2c0_tx_start(void); +void i2c0_tx_byte(uint8_t byte); +uint8_t i2c0_rx_byte(void); +void i2c0_stop(void); + +END_DECLS + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/i2s.h b/libopencm3/include/libopencm3/lpc43xx/i2s.h new file mode 100644 index 0000000..63f7afb --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/i2s.h @@ -0,0 +1,122 @@ +/** @defgroup i2s_defines I2S Defines + +@brief Defined Constants and Types for the LPC43xx I2S + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC43XX_I2S_H +#define LPC43XX_I2S_H + +/**@{*/ + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* I2S port base addresses (for convenience) */ +#define I2S0 I2S0_BASE +#define I2S1 I2S1_BASE + +/* --- I2S registers ------------------------------------------------------- */ + +/* I2S Digital Audio Output Register */ +#define I2S_DAO(port) MMIO32(port + 0x000) +#define I2S0_DAO I2S_DAO(I2S0) +#define I2S1_DAO I2S_DAO(I2S1) + +/* I2S Digital Audio Input Register */ +#define I2S_DAI(port) MMIO32(port + 0x004) +#define I2S0_DAI I2S_DAI(I2S0) +#define I2S1_DAI I2S_DAI(I2S1) + +/* I2S Transmit FIFO */ +#define I2S_TXFIFO(port) MMIO32(port + 0x008) +#define I2S0_TXFIFO I2S_TXFIFO(I2S0) +#define I2S1_TXFIFO I2S_TXFIFO(I2S1) + +/* I2S Receive FIFO */ +#define I2S_RXFIFO(port) MMIO32(port + 0x00C) +#define I2S0_RXFIFO I2S_RXFIFO(I2S0) +#define I2S1_RXFIFO I2S_RXFIFO(I2S1) + +/* I2S Status Feedback Register */ +#define I2S_STATE(port) MMIO32(port + 0x010) +#define I2S0_STATE I2S_STATE(I2S0) +#define I2S1_STATE I2S_STATE(I2S1) + +/* I2S DMA Configuration Register 1 */ +#define I2S_DMA1(port) MMIO32(port + 0x014) +#define I2S0_DMA1 I2S_DMA1(I2S0) +#define I2S1_DMA1 I2S_DMA1(I2S1) + +/* I2S DMA Configuration Register 2 */ +#define I2S_DMA2(port) MMIO32(port + 0x018) +#define I2S0_DMA2 I2S_DMA2(I2S0) +#define I2S1_DMA2 I2S_DMA2(I2S1) + +/* I2S Interrupt Request Control Register */ +#define I2S_IRQ(port) MMIO32(port + 0x01C) +#define I2S0_IRQ I2S_IRQ(I2S0) +#define I2S1_IRQ I2S_IRQ(I2S1) + +/* I2S Transmit MCLK divider */ +#define I2S_TXRATE(port) MMIO32(port + 0x020) +#define I2S0_TXRATE I2S_TXRATE(I2S0) +#define I2S1_TXRATE I2S_TXRATE(I2S1) + +/* I2S Receive MCLK divider */ +#define I2S_RXRATE(port) MMIO32(port + 0x024) +#define I2S0_RXRATE I2S_RXRATE(I2S0) +#define I2S1_RXRATE I2S_RXRATE(I2S1) + +/* I2S Transmit bit rate divider */ +#define I2S_TXBITRATE(port) MMIO32(port + 0x028) +#define I2S0_TXBITRATE I2S_TXBITRATE(I2S0) +#define I2S1_TXBITRATE I2S_TXBITRATE(I2S1) + +/* I2S Receive bit rate divider */ +#define I2S_RXBITRATE(port) MMIO32(port + 0x02C) +#define I2S0_RXBITRATE I2S_RXBITRATE(I2S0) +#define I2S1_RXBITRATE I2S_RXBITRATE(I2S1) + +/* I2S Transmit mode control */ +#define I2S_TXMODE(port) MMIO32(port + 0x030) +#define I2S0_TXMODE I2S_TXMODE(I2S0) +#define I2S1_TXMODE I2S_TXMODE(I2S1) + +/* I2S Receive mode control */ +#define I2S_RXMODE(port) MMIO32(port + 0x034) +#define I2S0_RXMODE I2S_RXMODE(I2S0) +#define I2S1_RXMODE I2S_RXMODE(I2S1) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/ipc.h b/libopencm3/include/libopencm3/lpc43xx/ipc.h new file mode 100644 index 0000000..ddd81b8 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/ipc.h @@ -0,0 +1,30 @@ +/* +* This file is part of the libopencm3 project. +* +* Copyright (C) 2012 Benjamin Vernoux +* +* This library is free software: you can redistribute it and/or modify +* it under the terms of the GNU Lesser General Public License as published by +* the Free Software Foundation, either version 3 of the License, or +* (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public License +* along with this library. If not, see . +*/ + +#ifndef LPC43XX_IPC_H +#define LPC43XX_IPC_H + +#include +#include + +void ipc_halt_m0(void); + +void ipc_start_m0(uint32_t cm0_baseaddr); + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/m0/irq.json b/libopencm3/include/libopencm3/lpc43xx/m0/irq.json new file mode 100644 index 0000000..828c1dd --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/m0/irq.json @@ -0,0 +1,36 @@ +{ + "irqs": { + "0": "rtc", + "1": "m4core", + "2": "dma", + "4": "flasheepromat", + "5": "ethernet", + "6": "sdio", + "7": "lcd", + "8": "usb0", + "9": "usb1", + "10": "sct", + "11": "ritimer_or_wwdt", + "12": "timer0", + "13": "gint1", + "14": "pin_int4", + "15": "timer3", + "16": "mcpwm", + "17": "adc0", + "18": "i2c0_or_irc1", + "19": "sgpio", + "20": "spi_or_dac", + "21": "adc1", + "22": "ssp0_or_ssp1", + "23": "eventrouter", + "24": "usart0", + "25": "uart1", + "26": "usart2_or_c_can1", + "27": "usart3", + "28": "i2s0_or_i2s1", + "29": "c_can0" + }, + "partname_humanreadable": "LPC 43xx series M0 core", + "partname_doxygen": "LPC43xx (M0)", + "includeguard": "LIBOPENCM3_LPC43xx_M0_NVIC_H" +} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/lpc43xx/m4/irq.json b/libopencm3/include/libopencm3/lpc43xx/m4/irq.json new file mode 100644 index 0000000..376fab1 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/m4/irq.json @@ -0,0 +1,54 @@ +{ + "irqs": { + "0": "dac", + "1": "m0core", + "2": "dma", + "5": "ethernet", + "6": "sdio", + "7": "lcd", + "8": "usb0", + "9": "usb1", + "10": "sct", + "11": "ritimer", + "12": "timer0", + "13": "timer1", + "14": "timer2", + "15": "timer3", + "16": "mcpwm", + "17": "adc0", + "18": "i2c0", + "19": "i2c1", + "20": "spi", + "21": "adc1", + "22": "ssp0", + "23": "ssp1", + "24": "usart0", + "25": "uart1", + "26": "usart2", + "27": "usart3", + "28": "i2s0", + "29": "i2s1", + "30": "spifi", + "31": "sgpio", + "32": "pin_int0", + "33": "pin_int1", + "34": "pin_int2", + "35": "pin_int3", + "36": "pin_int4", + "37": "pin_int5", + "38": "pin_int6", + "39": "pin_int7", + "40": "gint0", + "41": "gint1", + "42": "eventrouter", + "43": "c_can1", + "46": "atimer", + "47": "rtc", + "49": "wwdt", + "51": "c_can0", + "52": "qei" + }, + "partname_humanreadable": "LPC 43xx series M4 core", + "partname_doxygen": "LPC43xx (M4)", + "includeguard": "LIBOPENCM3_LPC43xx_M4_NVIC_H" +} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/lpc43xx/memorymap.h b/libopencm3/include/libopencm3/lpc43xx/memorymap.h new file mode 100644 index 0000000..5d2bdc4 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/memorymap.h @@ -0,0 +1,138 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC43XX_MEMORYMAP_H +#define LPC43XX_MEMORYMAP_H + +#include + +/* --- LPC43XX specific peripheral definitions ----------------------------- */ + +/* Memory map for all busses */ +#define PERIPH_BASE_AHB (0x40000000U) +#define PERIPH_BASE_APB0 (0x40080000U) +#define PERIPH_BASE_APB1 (0x400A0000U) +#define PERIPH_BASE_APB2 (0x400C0000U) +#define PERIPH_BASE_APB3 (0x400E0000U) + +/* Register boundary addresses */ + +/* AHB (0x4000 0000 - 0x4001 2000) */ +#define SCT_BASE (PERIPH_BASE_AHB + 0x00000) +/* PERIPH_BASE_AHB + 0x01000 (0x4000 1000 - 0x4000 1FFF): Reserved */ +#define GPDMA_BASE (PERIPH_BASE_AHB + 0x02000) +#define SPIFI_BASE (PERIPH_BASE_AHB + 0x03000) +#define SDIO_BASE (PERIPH_BASE_AHB + 0x04000) +#define EMC_BASE (PERIPH_BASE_AHB + 0x05000) +#define USB0_BASE (PERIPH_BASE_AHB + 0x06000) +#define USB1_BASE (PERIPH_BASE_AHB + 0x07000) +#define LCD_BASE (PERIPH_BASE_AHB + 0x08000) +/* PERIPH_BASE_AHB + 0x09000 (0x4000 9000 - 0x4000 FFFF): Reserved */ +#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000) + +/* 0x4001 2000 - 0x4003 FFFF Reserved */ + +/* RTC domain peripherals */ +#define ATIMER_BASE (0x40040000U) +#define BACKUP_REG_BASE (0x40041000U) +#define PMC_BASE (0x40042000U) +#define CREG_BASE (0x40043000U) +#define EVENTROUTER_BASE (0x40044000U) +#define OTP_BASE (0x40045000U) +#define RTC_BASE (0x40046000U) +/* 0x4004 7000 - 0x4004 FFFF Reserved */ + +/* clocking/reset control peripherals */ +#define CGU_BASE (0x40050000U) +#define CCU1_BASE (0x40051000U) +#define CCU2_BASE (0x40052000U) +#define RGU_BASE (0x40053000U) +/* 0x4005 4000 - 0x4005 FFFF Reserved */ + +/* 0x4006 0000 - 0x4007 FFFF Reserved */ + +/* APB0 ( 0x4008 0000 - 0x4008 FFFF) */ +#define WWDT_BASE (PERIPH_BASE_APB0 + 0x00000) +#define USART0_BASE (PERIPH_BASE_APB0 + 0x01000) +#define UART1_BASE (PERIPH_BASE_APB0 + 0x02000) +#define SSP0_BASE (PERIPH_BASE_APB0 + 0x03000) +#define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000) +#define TIMER1_BASE (PERIPH_BASE_APB0 + 0x05000) +#define SCU_BASE (PERIPH_BASE_APB0 + 0x06000) +#define GPIO_PIN_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x07000) +#define GPIO_GROUP0_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x08000) +#define GPIO_GROUP1_INTERRUPT_BASE (PERIPH_BASE_APB0 + 0x09000) +/* 0x4008 A000 - 0x4008 FFFF Reserved */ + +/* 0x4009 0000 - 0x4009 FFFF Reserved */ + +/* APB1 (0x400A 0000 - 0x400A FFFF) */ +#define MCPWM_BASE (PERIPH_BASE_APB1 + 0x00000) +#define I2C0_BASE (PERIPH_BASE_APB1 + 0x01000) +#define I2S0_BASE (PERIPH_BASE_APB1 + 0x02000) +#define I2S1_BASE (PERIPH_BASE_APB1 + 0x03000) +#define C_CCAN1_BASE (PERIPH_BASE_APB1 + 0x04000) +/* 0x400A 5000 - 0x400A FFFF Reserved */ + +/* 0x400B 0000 - 0x400B FFFF Reserved */ + +/* APB2 (0x400C 0000 - 0x400C FFFF) */ +#define RITIMER_BASE (PERIPH_BASE_APB2 + 0x00000) +#define USART2_BASE (PERIPH_BASE_APB2 + 0x01000) +#define USART3_BASE (PERIPH_BASE_APB2 + 0x02000) +#define TIMER2_BASE (PERIPH_BASE_APB2 + 0x03000) +#define TIMER3_BASE (PERIPH_BASE_APB2 + 0x04000) +#define SSP1_BASE (PERIPH_BASE_APB2 + 0x05000) +#define QEI_BASE (PERIPH_BASE_APB2 + 0x06000) +#define GIMA_BASE (PERIPH_BASE_APB2 + 0x07000) +/* 0x400C 8000 - 0x400C FFFF Reserved */ + +/* 0x400D 0000 - 0x400D FFFF Reserved */ + +/* APB3 (0x400E 0000 - 0x400E FFFF) */ +#define I2C1_BASE (PERIPH_BASE_APB3 + 0x00000) +#define DAC_BASE (PERIPH_BASE_APB3 + 0x01000) +#define C_CAN0_BASE (PERIPH_BASE_APB3 + 0x02000) +#define ADC0_BASE (PERIPH_BASE_APB3 + 0x03000) +#define ADC1_BASE (PERIPH_BASE_APB3 + 0x04000) +/* 0x400E 5000 - 0x400E FFFF Reserved */ + +/* 0x400F 0000 - 0x400F 0FFF Reserved */ + +#define AES_BASE (0x400F1000U) + +/* 0x400F 2000 - 0x400F 3FFF Reserved */ + +#define GPIO_PORT_BASE (0x400F4000U) + +/* 0x400F 8000 - 0x400F FFFF Reserved */ + +#define SPI_PORT_BASE (0x40100000U) +#define SGPIO_PORT_BASE (0x40101000U) + +/* 0x4010 2000 - 0x41FF FFFF Reserved */ + +/* 0x4200 0000 - 0x43FF FFFF peripheral bit band alias region */ + +/* 0x4400 0000 - 0x5FFF FFFF Reserved */ + +/* 0x6000 0000 - 0xFFFF FFFF external memories and ARM private bus */ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/rgu.h b/libopencm3/include/libopencm3/lpc43xx/rgu.h new file mode 100644 index 0000000..0ec0146 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/rgu.h @@ -0,0 +1,1206 @@ +/** @defgroup rgu_defines Reset Generation Unit Defines + +@brief Defined Constants and Types for the LPC43xx Reset Generation Unit + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC43XX_RGU_H +#define LPC43XX_RGU_H + +/**@{*/ + +#include +#include + +/* --- RGU registers ------------------------------------------------------- */ + +/* Reset control register 0 */ +#define RESET_CTRL0 MMIO32(RGU_BASE + 0x100) + +/* Reset control register 1 */ +#define RESET_CTRL1 MMIO32(RGU_BASE + 0x104) + +/* Reset status register 0 */ +#define RESET_STATUS0 MMIO32(RGU_BASE + 0x110) + +/* Reset status register 1 */ +#define RESET_STATUS1 MMIO32(RGU_BASE + 0x114) + +/* Reset status register 2 */ +#define RESET_STATUS2 MMIO32(RGU_BASE + 0x118) + +/* Reset status register 3 */ +#define RESET_STATUS3 MMIO32(RGU_BASE + 0x11C) + +/* Reset active status register 0 */ +#define RESET_ACTIVE_STATUS0 MMIO32(RGU_BASE + 0x150) + +/* Reset active status register 1 */ +#define RESET_ACTIVE_STATUS1 MMIO32(RGU_BASE + 0x154) + +/* Reset external status register 0 for CORE_RST */ +#define RESET_EXT_STAT0 MMIO32(RGU_BASE + 0x400) + +/* Reset external status register 1 for PERIPH_RST */ +#define RESET_EXT_STAT1 MMIO32(RGU_BASE + 0x404) + +/* Reset external status register 2 for MASTER_RST */ +#define RESET_EXT_STAT2 MMIO32(RGU_BASE + 0x408) + +/* Reserved */ +#define RESET_EXT_STAT3 MMIO32(RGU_BASE + 0x40C) + +/* Reset external status register 4 for WWDT_RST */ +#define RESET_EXT_STAT4 MMIO32(RGU_BASE + 0x410) + +/* Reset external status register 5 for CREG_RST */ +#define RESET_EXT_STAT5 MMIO32(RGU_BASE + 0x414) + +/* Reserved */ +#define RESET_EXT_STAT6 MMIO32(RGU_BASE + 0x418) + +/* Reserved */ +#define RESET_EXT_STAT7 MMIO32(RGU_BASE + 0x41C) + +/* Reset external status register 8 for BUS_RST */ +#define RESET_EXT_STAT8 MMIO32(RGU_BASE + 0x420) + +/* Reset external status register 9 for SCU_RST */ +#define RESET_EXT_STAT9 MMIO32(RGU_BASE + 0x424) + +/* Reserved */ +#define RESET_EXT_STAT10 MMIO32(RGU_BASE + 0x428) + +/* Reserved */ +#define RESET_EXT_STAT11 MMIO32(RGU_BASE + 0x42C) + +/* Reserved */ +#define RESET_EXT_STAT12 MMIO32(RGU_BASE + 0x430) + +/* Reset external status register 13 for M4_RST */ +#define RESET_EXT_STAT13 MMIO32(RGU_BASE + 0x434) + +/* Reserved */ +#define RESET_EXT_STAT14 MMIO32(RGU_BASE + 0x438) + +/* Reserved */ +#define RESET_EXT_STAT15 MMIO32(RGU_BASE + 0x43C) + +/* Reset external status register 16 for LCD_RST */ +#define RESET_EXT_STAT16 MMIO32(RGU_BASE + 0x440) + +/* Reset external status register 17 for USB0_RST */ +#define RESET_EXT_STAT17 MMIO32(RGU_BASE + 0x444) + +/* Reset external status register 18 for USB1_RST */ +#define RESET_EXT_STAT18 MMIO32(RGU_BASE + 0x448) + +/* Reset external status register 19 for DMA_RST */ +#define RESET_EXT_STAT19 MMIO32(RGU_BASE + 0x44C) + +/* Reset external status register 20 for SDIO_RST */ +#define RESET_EXT_STAT20 MMIO32(RGU_BASE + 0x450) + +/* Reset external status register 21 for EMC_RST */ +#define RESET_EXT_STAT21 MMIO32(RGU_BASE + 0x454) + +/* Reset external status register 22 for ETHERNET_RST */ +#define RESET_EXT_STAT22 MMIO32(RGU_BASE + 0x458) + +/* Reserved */ +#define RESET_EXT_STAT23 MMIO32(RGU_BASE + 0x45C) + +/* Reserved */ +#define RESET_EXT_STAT24 MMIO32(RGU_BASE + 0x460) + +/* Reserved */ +#define RESET_EXT_STAT25 MMIO32(RGU_BASE + 0x464) + +/* Reserved */ +#define RESET_EXT_STAT26 MMIO32(RGU_BASE + 0x468) + +/* Reserved */ +#define RESET_EXT_STAT27 MMIO32(RGU_BASE + 0x46C) + +/* Reset external status register 28 for GPIO_RST */ +#define RESET_EXT_STAT28 MMIO32(RGU_BASE + 0x470) + +/* Reserved */ +#define RESET_EXT_STAT29 MMIO32(RGU_BASE + 0x474) + +/* Reserved */ +#define RESET_EXT_STAT30 MMIO32(RGU_BASE + 0x478) + +/* Reserved */ +#define RESET_EXT_STAT31 MMIO32(RGU_BASE + 0x47C) + +/* Reset external status register 32 for TIMER0_RST */ +#define RESET_EXT_STAT32 MMIO32(RGU_BASE + 0x480) + +/* Reset external status register 33 for TIMER1_RST */ +#define RESET_EXT_STAT33 MMIO32(RGU_BASE + 0x484) + +/* Reset external status register 34 for TIMER2_RST */ +#define RESET_EXT_STAT34 MMIO32(RGU_BASE + 0x488) + +/* Reset external status register 35 for TIMER3_RST */ +#define RESET_EXT_STAT35 MMIO32(RGU_BASE + 0x48C) + +/* Reset external status register 36 for RITIMER_RST */ +#define RESET_EXT_STAT36 MMIO32(RGU_BASE + 0x490) + +/* Reset external status register 37 for SCT_RST */ +#define RESET_EXT_STAT37 MMIO32(RGU_BASE + 0x494) + +/* Reset external status register 38 for MOTOCONPWM_RST */ +#define RESET_EXT_STAT38 MMIO32(RGU_BASE + 0x498) + +/* Reset external status register 39 for QEI_RST */ +#define RESET_EXT_STAT39 MMIO32(RGU_BASE + 0x49C) + +/* Reset external status register 40 for ADC0_RST */ +#define RESET_EXT_STAT40 MMIO32(RGU_BASE + 0x4A0) + +/* Reset external status register 41 for ADC1_RST */ +#define RESET_EXT_STAT41 MMIO32(RGU_BASE + 0x4A4) + +/* Reset external status register 42 for DAC_RST */ +#define RESET_EXT_STAT42 MMIO32(RGU_BASE + 0x4A8) + +/* Reserved */ +#define RESET_EXT_STAT43 MMIO32(RGU_BASE + 0x4AC) + +/* Reset external status register 44 for UART0_RST */ +#define RESET_EXT_STAT44 MMIO32(RGU_BASE + 0x4B0) + +/* Reset external status register 45 for UART1_RST */ +#define RESET_EXT_STAT45 MMIO32(RGU_BASE + 0x4B4) + +/* Reset external status register 46 for UART2_RST */ +#define RESET_EXT_STAT46 MMIO32(RGU_BASE + 0x4B8) + +/* Reset external status register 47 for UART3_RST */ +#define RESET_EXT_STAT47 MMIO32(RGU_BASE + 0x4BC) + +/* Reset external status register 48 for I2C0_RST */ +#define RESET_EXT_STAT48 MMIO32(RGU_BASE + 0x4C0) + +/* Reset external status register 49 for I2C1_RST */ +#define RESET_EXT_STAT49 MMIO32(RGU_BASE + 0x4C4) + +/* Reset external status register 50 for SSP0_RST */ +#define RESET_EXT_STAT50 MMIO32(RGU_BASE + 0x4C8) + +/* Reset external status register 51 for SSP1_RST */ +#define RESET_EXT_STAT51 MMIO32(RGU_BASE + 0x4CC) + +/* Reset external status register 52 for I2S_RST */ +#define RESET_EXT_STAT52 MMIO32(RGU_BASE + 0x4D0) + +/* Reset external status register 53 for SPIFI_RST */ +#define RESET_EXT_STAT53 MMIO32(RGU_BASE + 0x4D4) + +/* Reset external status register 54 for CAN1_RST */ +#define RESET_EXT_STAT54 MMIO32(RGU_BASE + 0x4D8) + +/* Reset external status register 55 for CAN0_RST */ +#define RESET_EXT_STAT55 MMIO32(RGU_BASE + 0x4DC) + +/* Reset external status register 56 for M0APP_RST */ +#define RESET_EXT_STAT56 MMIO32(RGU_BASE + 0x4E0) + +/* Reset external status register 57 for SGPIO_RST */ +#define RESET_EXT_STAT57 MMIO32(RGU_BASE + 0x4E4) + +/* Reset external status register 58 for SPI_RST */ +#define RESET_EXT_STAT58 MMIO32(RGU_BASE + 0x4E8) + +/* Reserved */ +#define RESET_EXT_STAT59 MMIO32(RGU_BASE + 0x4EC) + +/* Reserved */ +#define RESET_EXT_STAT60 MMIO32(RGU_BASE + 0x4F0) + +/* Reserved */ +#define RESET_EXT_STAT61 MMIO32(RGU_BASE + 0x4F4) + +/* Reserved */ +#define RESET_EXT_STAT62 MMIO32(RGU_BASE + 0x4F8) + +/* Reserved */ +#define RESET_EXT_STAT63 MMIO32(RGU_BASE + 0x4FC) + +/* --- RESET_CTRL0 values --------------------------------------- */ + +/* CORE_RST: Writing a one activates the reset */ +#define RESET_CTRL0_CORE_RST_SHIFT (0) +#define RESET_CTRL0_CORE_RST (1 << RESET_CTRL0_CORE_RST_SHIFT) + +/* PERIPH_RST: Writing a one activates the reset */ +#define RESET_CTRL0_PERIPH_RST_SHIFT (1) +#define RESET_CTRL0_PERIPH_RST (1 << RESET_CTRL0_PERIPH_RST_SHIFT) + +/* MASTER_RST: Writing a one activates the reset */ +#define RESET_CTRL0_MASTER_RST_SHIFT (2) +#define RESET_CTRL0_MASTER_RST (1 << RESET_CTRL0_MASTER_RST_SHIFT) + +/* WWDT_RST: Writing a one to this bit has no effect */ +#define RESET_CTRL0_WWDT_RST_SHIFT (4) +#define RESET_CTRL0_WWDT_RST (1 << RESET_CTRL0_WWDT_RST_SHIFT) + +/* CREG_RST: Writing a one to this bit has no effect */ +#define RESET_CTRL0_CREG_RST_SHIFT (5) +#define RESET_CTRL0_CREG_RST (1 << RESET_CTRL0_CREG_RST_SHIFT) + +/* BUS_RST: Writing a one activates the reset */ +#define RESET_CTRL0_BUS_RST_SHIFT (8) +#define RESET_CTRL0_BUS_RST (1 << RESET_CTRL0_BUS_RST_SHIFT) + +/* SCU_RST: Writing a one activates the reset */ +#define RESET_CTRL0_SCU_RST_SHIFT (9) +#define RESET_CTRL0_SCU_RST (1 << RESET_CTRL0_SCU_RST_SHIFT) + +/* M4_RST: Writing a one activates the reset */ +#define RESET_CTRL0_M4_RST_SHIFT (13) +#define RESET_CTRL0_M4_RST (1 << RESET_CTRL0_M4_RST_SHIFT) + +/* LCD_RST: Writing a one activates the reset */ +#define RESET_CTRL0_LCD_RST_SHIFT (16) +#define RESET_CTRL0_LCD_RST (1 << RESET_CTRL0_LCD_RST_SHIFT) + +/* USB0_RST: Writing a one activates the reset */ +#define RESET_CTRL0_USB0_RST_SHIFT (17) +#define RESET_CTRL0_USB0_RST (1 << RESET_CTRL0_USB0_RST_SHIFT) + +/* USB1_RST: Writing a one activates the reset */ +#define RESET_CTRL0_USB1_RST_SHIFT (18) +#define RESET_CTRL0_USB1_RST (1 << RESET_CTRL0_USB1_RST_SHIFT) + +/* DMA_RST: Writing a one activates the reset */ +#define RESET_CTRL0_DMA_RST_SHIFT (19) +#define RESET_CTRL0_DMA_RST (1 << RESET_CTRL0_DMA_RST_SHIFT) + +/* SDIO_RST: Writing a one activates the reset */ +#define RESET_CTRL0_SDIO_RST_SHIFT (20) +#define RESET_CTRL0_SDIO_RST (1 << RESET_CTRL0_SDIO_RST_SHIFT) + +/* EMC_RST: Writing a one activates the reset */ +#define RESET_CTRL0_EMC_RST_SHIFT (21) +#define RESET_CTRL0_EMC_RST (1 << RESET_CTRL0_EMC_RST_SHIFT) + +/* ETHERNET_RST: Writing a one activates the reset */ +#define RESET_CTRL0_ETHERNET_RST_SHIFT (22) +#define RESET_CTRL0_ETHERNET_RST (1 << RESET_CTRL0_ETHERNET_RST_SHIFT) + +/* FLASHA_RST: Writing a one activates the reset */ +#define RESET_CTRL0_FLASHA_RST_SHIFT (25) +#define RESET_CTRL0_FLASHA_RST (1 << RESET_CTRL0_FLASHA_RST_SHIFT) + +/* EEPROM_RST: Writing a one activates the reset */ +#define RESET_CTRL0_EEPROM_RST_SHIFT (27) +#define RESET_CTRL0_EEPROM_RST (1 << RESET_CTRL0_EEPROM_RST_SHIFT) + +/* GPIO_RST: Writing a one activates the reset */ +#define RESET_CTRL0_GPIO_RST_SHIFT (28) +#define RESET_CTRL0_GPIO_RST (1 << RESET_CTRL0_GPIO_RST_SHIFT) + +/* FLASHB_RST: Writing a one activates the reset */ +#define RESET_CTRL0_FLASHB_RST_SHIFT (29) +#define RESET_CTRL0_FLASHB_RST (1 << RESET_CTRL0_FLASHB_RST_SHIFT) + +/* --- RESET_CTRL1 values --------------------------------------- */ + +/* TIMER0_RST: Writing a one activates the reset */ +#define RESET_CTRL1_TIMER0_RST_SHIFT (0) +#define RESET_CTRL1_TIMER0_RST (1 << RESET_CTRL1_TIMER0_RST_SHIFT) + +/* TIMER1_RST: Writing a one activates the reset */ +#define RESET_CTRL1_TIMER1_RST_SHIFT (1) +#define RESET_CTRL1_TIMER1_RST (1 << RESET_CTRL1_TIMER1_RST_SHIFT) + +/* TIMER2_RST: Writing a one activates the reset */ +#define RESET_CTRL1_TIMER2_RST_SHIFT (2) +#define RESET_CTRL1_TIMER2_RST (1 << RESET_CTRL1_TIMER2_RST_SHIFT) + +/* TIMER3_RST: Writing a one activates the reset */ +#define RESET_CTRL1_TIMER3_RST_SHIFT (3) +#define RESET_CTRL1_TIMER3_RST (1 << RESET_CTRL1_TIMER3_RST_SHIFT) + +/* RTIMER_RST: Writing a one activates the reset */ +#define RESET_CTRL1_RTIMER_RST_SHIFT (4) +#define RESET_CTRL1_RTIMER_RST (1 << RESET_CTRL1_RTIMER_RST_SHIFT) + +/* SCT_RST: Writing a one activates the reset */ +#define RESET_CTRL1_SCT_RST_SHIFT (5) +#define RESET_CTRL1_SCT_RST (1 << RESET_CTRL1_SCT_RST_SHIFT) + +/* MOTOCONPWM_RST: Writing a one activates the reset */ +#define RESET_CTRL1_MOTOCONPWM_RST_SHIFT (6) +#define RESET_CTRL1_MOTOCONPWM_RST (1 << RESET_CTRL1_MOTOCONPWM_RST_SHIFT) + +/* QEI_RST: Writing a one activates the reset */ +#define RESET_CTRL1_QEI_RST_SHIFT (7) +#define RESET_CTRL1_QEI_RST (1 << RESET_CTRL1_QEI_RST_SHIFT) + +/* ADC0_RST: Writing a one activates the reset */ +#define RESET_CTRL1_ADC0_RST_SHIFT (8) +#define RESET_CTRL1_ADC0_RST (1 << RESET_CTRL1_ADC0_RST_SHIFT) + +/* ADC1_RST: Writing a one activates the reset */ +#define RESET_CTRL1_ADC1_RST_SHIFT (9) +#define RESET_CTRL1_ADC1_RST (1 << RESET_CTRL1_ADC1_RST_SHIFT) + +/* DAC_RST: Writing a one activates the reset */ +#define RESET_CTRL1_DAC_RST_SHIFT (10) +#define RESET_CTRL1_DAC_RST (1 << RESET_CTRL1_DAC_RST_SHIFT) + +/* UART0_RST: Writing a one activates the reset */ +#define RESET_CTRL1_UART0_RST_SHIFT (12) +#define RESET_CTRL1_UART0_RST (1 << RESET_CTRL1_UART0_RST_SHIFT) + +/* UART1_RST: Writing a one activates the reset */ +#define RESET_CTRL1_UART1_RST_SHIFT (13) +#define RESET_CTRL1_UART1_RST (1 << RESET_CTRL1_UART1_RST_SHIFT) + +/* UART2_RST: Writing a one activates the reset */ +#define RESET_CTRL1_UART2_RST_SHIFT (14) +#define RESET_CTRL1_UART2_RST (1 << RESET_CTRL1_UART2_RST_SHIFT) + +/* UART3_RST: Writing a one activates the reset */ +#define RESET_CTRL1_UART3_RST_SHIFT (15) +#define RESET_CTRL1_UART3_RST (1 << RESET_CTRL1_UART3_RST_SHIFT) + +/* I2C0_RST: Writing a one activates the reset */ +#define RESET_CTRL1_I2C0_RST_SHIFT (16) +#define RESET_CTRL1_I2C0_RST (1 << RESET_CTRL1_I2C0_RST_SHIFT) + +/* I2C1_RST: Writing a one activates the reset */ +#define RESET_CTRL1_I2C1_RST_SHIFT (17) +#define RESET_CTRL1_I2C1_RST (1 << RESET_CTRL1_I2C1_RST_SHIFT) + +/* SSP0_RST: Writing a one activates the reset */ +#define RESET_CTRL1_SSP0_RST_SHIFT (18) +#define RESET_CTRL1_SSP0_RST (1 << RESET_CTRL1_SSP0_RST_SHIFT) + +/* SSP1_RST: Writing a one activates the reset */ +#define RESET_CTRL1_SSP1_RST_SHIFT (19) +#define RESET_CTRL1_SSP1_RST (1 << RESET_CTRL1_SSP1_RST_SHIFT) + +/* I2S_RST: Writing a one activates the reset */ +#define RESET_CTRL1_I2S_RST_SHIFT (20) +#define RESET_CTRL1_I2S_RST (1 << RESET_CTRL1_I2S_RST_SHIFT) + +/* SPIFI_RST: Writing a one activates the reset */ +#define RESET_CTRL1_SPIFI_RST_SHIFT (21) +#define RESET_CTRL1_SPIFI_RST (1 << RESET_CTRL1_SPIFI_RST_SHIFT) + +/* CAN1_RST: Writing a one activates the reset */ +#define RESET_CTRL1_CAN1_RST_SHIFT (22) +#define RESET_CTRL1_CAN1_RST (1 << RESET_CTRL1_CAN1_RST_SHIFT) + +/* CAN0_RST: Writing a one activates the reset */ +#define RESET_CTRL1_CAN0_RST_SHIFT (23) +#define RESET_CTRL1_CAN0_RST (1 << RESET_CTRL1_CAN0_RST_SHIFT) + +/* M0APP_RST: Writing a one activates the reset */ +#define RESET_CTRL1_M0APP_RST_SHIFT (24) +#define RESET_CTRL1_M0APP_RST (1 << RESET_CTRL1_M0APP_RST_SHIFT) + +/* SGPIO_RST: Writing a one activates the reset */ +#define RESET_CTRL1_SGPIO_RST_SHIFT (25) +#define RESET_CTRL1_SGPIO_RST (1 << RESET_CTRL1_SGPIO_RST_SHIFT) + +/* SPI_RST: Writing a one activates the reset */ +#define RESET_CTRL1_SPI_RST_SHIFT (26) +#define RESET_CTRL1_SPI_RST (1 << RESET_CTRL1_SPI_RST_SHIFT) + +/* --- RESET_STATUS0 values ------------------------------------- */ + +/* CORE_RST: Status of the CORE_RST reset generator output */ +#define RESET_STATUS0_CORE_RST_SHIFT (0) +#define RESET_STATUS0_CORE_RST_MASK (0x3 << RESET_STATUS0_CORE_RST_SHIFT) +#define RESET_STATUS0_CORE_RST(x) ((x) << RESET_STATUS0_CORE_RST_SHIFT) + +/* PERIPH_RST: Status of the PERIPH_RST reset generator output */ +#define RESET_STATUS0_PERIPH_RST_SHIFT (2) +#define RESET_STATUS0_PERIPH_RST_MASK (0x3 << RESET_STATUS0_PERIPH_RST_SHIFT) +#define RESET_STATUS0_PERIPH_RST(x) ((x) << RESET_STATUS0_PERIPH_RST_SHIFT) + +/* MASTER_RST: Status of the MASTER_RST reset generator output */ +#define RESET_STATUS0_MASTER_RST_SHIFT (4) +#define RESET_STATUS0_MASTER_RST_MASK (0x3 << RESET_STATUS0_MASTER_RST_SHIFT) +#define RESET_STATUS0_MASTER_RST(x) ((x) << RESET_STATUS0_MASTER_RST_SHIFT) + +/* WWDT_RST: Status of the WWDT_RST reset generator output */ +#define RESET_STATUS0_WWDT_RST_SHIFT (8) +#define RESET_STATUS0_WWDT_RST_MASK (0x3 << RESET_STATUS0_WWDT_RST_SHIFT) +#define RESET_STATUS0_WWDT_RST(x) ((x) << RESET_STATUS0_WWDT_RST_SHIFT) + +/* CREG_RST: Status of the CREG_RST reset generator output */ +#define RESET_STATUS0_CREG_RST_SHIFT (10) +#define RESET_STATUS0_CREG_RST_MASK (0x3 << RESET_STATUS0_CREG_RST_SHIFT) +#define RESET_STATUS0_CREG_RST(x) ((x) << RESET_STATUS0_CREG_RST_SHIFT) + +/* BUS_RST: Status of the BUS_RST reset generator output */ +#define RESET_STATUS0_BUS_RST_SHIFT (16) +#define RESET_STATUS0_BUS_RST_MASK (0x3 << RESET_STATUS0_BUS_RST_SHIFT) +#define RESET_STATUS0_BUS_RST(x) ((x) << RESET_STATUS0_BUS_RST_SHIFT) + +/* SCU_RST: Status of the SCU_RST reset generator output */ +#define RESET_STATUS0_SCU_RST_SHIFT (18) +#define RESET_STATUS0_SCU_RST_MASK (0x3 << RESET_STATUS0_SCU_RST_SHIFT) +#define RESET_STATUS0_SCU_RST(x) ((x) << RESET_STATUS0_SCU_RST_SHIFT) + +/* M4_RST: Status of the M4_RST reset generator output */ +#define RESET_STATUS0_M4_RST_SHIFT (26) +#define RESET_STATUS0_M4_RST_MASK (0x3 << RESET_STATUS0_M4_RST_SHIFT) +#define RESET_STATUS0_M4_RST(x) ((x) << RESET_STATUS0_M4_RST_SHIFT) + +/* --- RESET_STATUS1 values ------------------------------------- */ + +/* LCD_RST: Status of the LCD_RST reset generator output */ +#define RESET_STATUS1_LCD_RST_SHIFT (0) +#define RESET_STATUS1_LCD_RST_MASK (0x3 << RESET_STATUS1_LCD_RST_SHIFT) +#define RESET_STATUS1_LCD_RST(x) ((x) << RESET_STATUS1_LCD_RST_SHIFT) + +/* USB0_RST: Status of the USB0_RST reset generator output */ +#define RESET_STATUS1_USB0_RST_SHIFT (2) +#define RESET_STATUS1_USB0_RST_MASK (0x3 << RESET_STATUS1_USB0_RST_SHIFT) +#define RESET_STATUS1_USB0_RST(x) ((x) << RESET_STATUS1_USB0_RST_SHIFT) + +/* USB1_RST: Status of the USB1_RST reset generator output */ +#define RESET_STATUS1_USB1_RST_SHIFT (4) +#define RESET_STATUS1_USB1_RST_MASK (0x3 << RESET_STATUS1_USB1_RST_SHIFT) +#define RESET_STATUS1_USB1_RST(x) ((x) << RESET_STATUS1_USB1_RST_SHIFT) + +/* DMA_RST: Status of the DMA_RST reset generator output */ +#define RESET_STATUS1_DMA_RST_SHIFT (6) +#define RESET_STATUS1_DMA_RST_MASK (0x3 << RESET_STATUS1_DMA_RST_SHIFT) +#define RESET_STATUS1_DMA_RST(x) ((x) << RESET_STATUS1_DMA_RST_SHIFT) + +/* SDIO_RST: Status of the SDIO_RST reset generator output */ +#define RESET_STATUS1_SDIO_RST_SHIFT (8) +#define RESET_STATUS1_SDIO_RST_MASK (0x3 << RESET_STATUS1_SDIO_RST_SHIFT) +#define RESET_STATUS1_SDIO_RST(x) ((x) << RESET_STATUS1_SDIO_RST_SHIFT) + +/* EMC_RST: Status of the EMC_RST reset generator output */ +#define RESET_STATUS1_EMC_RST_SHIFT (10) +#define RESET_STATUS1_EMC_RST_MASK (0x3 << RESET_STATUS1_EMC_RST_SHIFT) +#define RESET_STATUS1_EMC_RST(x) ((x) << RESET_STATUS1_EMC_RST_SHIFT) + +/* ETHERNET_RST: Status of the ETHERNET_RST reset generator output */ +#define RESET_STATUS1_ETHERNET_RST_SHIFT (12) +#define RESET_STATUS1_ETHERNET_RST_MASK \ + (0x3 << RESET_STATUS1_ETHERNET_RST_SHIFT) +#define RESET_STATUS1_ETHERNET_RST(x) ((x) << RESET_STATUS1_ETHERNET_RST_SHIFT) + +/* FLASHA_RST: Status of the FLASHA_RST reset generator output */ +#define RESET_STATUS1_FLASHA_RST_SHIFT (18) +#define RESET_STATUS1_FLASHA_RST_MASK (0x3 << RESET_STATUS1_FLASHA_RST_SHIFT) +#define RESET_STATUS1_FLASHA_RST(x) ((x) << RESET_STATUS1_FLASHA_RST_SHIFT) + +/* EEPROM_RST: Status of the EEPROM_RST reset generator output */ +#define RESET_STATUS1_EEPROM_RST_SHIFT (22) +#define RESET_STATUS1_EEPROM_RST_MASK (0x3 << RESET_STATUS1_EEPROM_RST_SHIFT) +#define RESET_STATUS1_EEPROM_RST(x) ((x) << RESET_STATUS1_EEPROM_RST_SHIFT) + +/* GPIO_RST: Status of the GPIO_RST reset generator output */ +#define RESET_STATUS1_GPIO_RST_SHIFT (24) +#define RESET_STATUS1_GPIO_RST_MASK (0x3 << RESET_STATUS1_GPIO_RST_SHIFT) +#define RESET_STATUS1_GPIO_RST(x) ((x) << RESET_STATUS1_GPIO_RST_SHIFT) + +/* FLASHB_RST: Status of the FLASHB_RST reset generator output */ +#define RESET_STATUS1_FLASHB_RST_SHIFT (26) +#define RESET_STATUS1_FLASHB_RST_MASK (0x3 << RESET_STATUS1_FLASHB_RST_SHIFT) +#define RESET_STATUS1_FLASHB_RST(x) ((x) << RESET_STATUS1_FLASHB_RST_SHIFT) + +/* --- RESET_STATUS2 values ------------------------------------- */ + +/* TIMER0_RST: Status of the TIMER0_RST reset generator output */ +#define RESET_STATUS2_TIMER0_RST_SHIFT (0) +#define RESET_STATUS2_TIMER0_RST_MASK (0x3 << RESET_STATUS2_TIMER0_RST_SHIFT) +#define RESET_STATUS2_TIMER0_RST(x) ((x) << RESET_STATUS2_TIMER0_RST_SHIFT) + +/* TIMER1_RST: Status of the TIMER1_RST reset generator output */ +#define RESET_STATUS2_TIMER1_RST_SHIFT (2) +#define RESET_STATUS2_TIMER1_RST_MASK (0x3 << RESET_STATUS2_TIMER1_RST_SHIFT) +#define RESET_STATUS2_TIMER1_RST(x) ((x) << RESET_STATUS2_TIMER1_RST_SHIFT) + +/* TIMER2_RST: Status of the TIMER2_RST reset generator output */ +#define RESET_STATUS2_TIMER2_RST_SHIFT (4) +#define RESET_STATUS2_TIMER2_RST_MASK (0x3 << RESET_STATUS2_TIMER2_RST_SHIFT) +#define RESET_STATUS2_TIMER2_RST(x) ((x) << RESET_STATUS2_TIMER2_RST_SHIFT) + +/* TIMER3_RST: Status of the TIMER3_RST reset generator output */ +#define RESET_STATUS2_TIMER3_RST_SHIFT (6) +#define RESET_STATUS2_TIMER3_RST_MASK (0x3 << RESET_STATUS2_TIMER3_RST_SHIFT) +#define RESET_STATUS2_TIMER3_RST(x) ((x) << RESET_STATUS2_TIMER3_RST_SHIFT) + +/* RITIMER_RST: Status of the RITIMER_RST reset generator output */ +#define RESET_STATUS2_RITIMER_RST_SHIFT (8) +#define RESET_STATUS2_RITIMER_RST_MASK (0x3 << RESET_STATUS2_RITIMER_RST_SHIFT) +#define RESET_STATUS2_RITIMER_RST(x) ((x) << RESET_STATUS2_RITIMER_RST_SHIFT) + +/* SCT_RST: Status of the SCT_RST reset generator output */ +#define RESET_STATUS2_SCT_RST_SHIFT (10) +#define RESET_STATUS2_SCT_RST_MASK (0x3 << RESET_STATUS2_SCT_RST_SHIFT) +#define RESET_STATUS2_SCT_RST(x) ((x) << RESET_STATUS2_SCT_RST_SHIFT) + +/* MOTOCONPWM_RST: Status of the MOTOCONPWM_RST reset generator output */ +#define RESET_STATUS2_MOTOCONPWM_RST_SHIFT (12) +#define RESET_STATUS2_MOTOCONPWM_RST_MASK \ + (0x3 << RESET_STATUS2_MOTOCONPWM_RST_SHIFT) +#define RESET_STATUS2_MOTOCONPWM_RST(x) \ + ((x) << RESET_STATUS2_MOTOCONPWM_RST_SHIFT) + +/* QEI_RST: Status of the QEI_RST reset generator output */ +#define RESET_STATUS2_QEI_RST_SHIFT (14) +#define RESET_STATUS2_QEI_RST_MASK (0x3 << RESET_STATUS2_QEI_RST_SHIFT) +#define RESET_STATUS2_QEI_RST(x) ((x) << RESET_STATUS2_QEI_RST_SHIFT) + +/* ADC0_RST: Status of the ADC0_RST reset generator output */ +#define RESET_STATUS2_ADC0_RST_SHIFT (16) +#define RESET_STATUS2_ADC0_RST_MASK (0x3 << RESET_STATUS2_ADC0_RST_SHIFT) +#define RESET_STATUS2_ADC0_RST(x) ((x) << RESET_STATUS2_ADC0_RST_SHIFT) + +/* ADC1_RST: Status of the ADC1_RST reset generator output */ +#define RESET_STATUS2_ADC1_RST_SHIFT (18) +#define RESET_STATUS2_ADC1_RST_MASK (0x3 << RESET_STATUS2_ADC1_RST_SHIFT) +#define RESET_STATUS2_ADC1_RST(x) ((x) << RESET_STATUS2_ADC1_RST_SHIFT) + +/* DAC_RST: Status of the DAC_RST reset generator output */ +#define RESET_STATUS2_DAC_RST_SHIFT (20) +#define RESET_STATUS2_DAC_RST_MASK (0x3 << RESET_STATUS2_DAC_RST_SHIFT) +#define RESET_STATUS2_DAC_RST(x) ((x) << RESET_STATUS2_DAC_RST_SHIFT) + +/* UART0_RST: Status of the UART0_RST reset generator output */ +#define RESET_STATUS2_UART0_RST_SHIFT (24) +#define RESET_STATUS2_UART0_RST_MASK (0x3 << RESET_STATUS2_UART0_RST_SHIFT) +#define RESET_STATUS2_UART0_RST(x) ((x) << RESET_STATUS2_UART0_RST_SHIFT) + +/* UART1_RST: Status of the UART1_RST reset generator output */ +#define RESET_STATUS2_UART1_RST_SHIFT (26) +#define RESET_STATUS2_UART1_RST_MASK (0x3 << RESET_STATUS2_UART1_RST_SHIFT) +#define RESET_STATUS2_UART1_RST(x) ((x) << RESET_STATUS2_UART1_RST_SHIFT) + +/* UART2_RST: Status of the UART2_RST reset generator output */ +#define RESET_STATUS2_UART2_RST_SHIFT (28) +#define RESET_STATUS2_UART2_RST_MASK (0x3 << RESET_STATUS2_UART2_RST_SHIFT) +#define RESET_STATUS2_UART2_RST(x) ((x) << RESET_STATUS2_UART2_RST_SHIFT) + +/* UART3_RST: Status of the UART3_RST reset generator output */ +#define RESET_STATUS2_UART3_RST_SHIFT (30) +#define RESET_STATUS2_UART3_RST_MASK (0x3 << RESET_STATUS2_UART3_RST_SHIFT) +#define RESET_STATUS2_UART3_RST(x) ((x) << RESET_STATUS2_UART3_RST_SHIFT) + +/* --- RESET_STATUS3 values ------------------------------------- */ + +/* I2C0_RST: Status of the I2C0_RST reset generator output */ +#define RESET_STATUS3_I2C0_RST_SHIFT (0) +#define RESET_STATUS3_I2C0_RST_MASK (0x3 << RESET_STATUS3_I2C0_RST_SHIFT) +#define RESET_STATUS3_I2C0_RST(x) ((x) << RESET_STATUS3_I2C0_RST_SHIFT) + +/* I2C1_RST: Status of the I2C1_RST reset generator output */ +#define RESET_STATUS3_I2C1_RST_SHIFT (2) +#define RESET_STATUS3_I2C1_RST_MASK (0x3 << RESET_STATUS3_I2C1_RST_SHIFT) +#define RESET_STATUS3_I2C1_RST(x) ((x) << RESET_STATUS3_I2C1_RST_SHIFT) + +/* SSP0_RST: Status of the SSP0_RST reset generator output */ +#define RESET_STATUS3_SSP0_RST_SHIFT (4) +#define RESET_STATUS3_SSP0_RST_MASK (0x3 << RESET_STATUS3_SSP0_RST_SHIFT) +#define RESET_STATUS3_SSP0_RST(x) ((x) << RESET_STATUS3_SSP0_RST_SHIFT) + +/* SSP1_RST: Status of the SSP1_RST reset generator output */ +#define RESET_STATUS3_SSP1_RST_SHIFT (6) +#define RESET_STATUS3_SSP1_RST_MASK (0x3 << RESET_STATUS3_SSP1_RST_SHIFT) +#define RESET_STATUS3_SSP1_RST(x) ((x) << RESET_STATUS3_SSP1_RST_SHIFT) + +/* I2S_RST: Status of the I2S_RST reset generator output */ +#define RESET_STATUS3_I2S_RST_SHIFT (8) +#define RESET_STATUS3_I2S_RST_MASK (0x3 << RESET_STATUS3_I2S_RST_SHIFT) +#define RESET_STATUS3_I2S_RST(x) ((x) << RESET_STATUS3_I2S_RST_SHIFT) + +/* SPIFI_RST: Status of the SPIFI_RST reset generator output */ +#define RESET_STATUS3_SPIFI_RST_SHIFT (10) +#define RESET_STATUS3_SPIFI_RST_MASK (0x3 << RESET_STATUS3_SPIFI_RST_SHIFT) +#define RESET_STATUS3_SPIFI_RST(x) ((x) << RESET_STATUS3_SPIFI_RST_SHIFT) + +/* CAN1_RST: Status of the CAN1_RST reset generator output */ +#define RESET_STATUS3_CAN1_RST_SHIFT (12) +#define RESET_STATUS3_CAN1_RST_MASK (0x3 << RESET_STATUS3_CAN1_RST_SHIFT) +#define RESET_STATUS3_CAN1_RST(x) ((x) << RESET_STATUS3_CAN1_RST_SHIFT) + +/* CAN0_RST: Status of the CAN0_RST reset generator output */ +#define RESET_STATUS3_CAN0_RST_SHIFT (14) +#define RESET_STATUS3_CAN0_RST_MASK (0x3 << RESET_STATUS3_CAN0_RST_SHIFT) +#define RESET_STATUS3_CAN0_RST(x) ((x) << RESET_STATUS3_CAN0_RST_SHIFT) + +/* M0APP_RST: Status of the M0APP_RST reset generator output */ +#define RESET_STATUS3_M0APP_RST_SHIFT (16) +#define RESET_STATUS3_M0APP_RST_MASK (0x3 << RESET_STATUS3_M0APP_RST_SHIFT) +#define RESET_STATUS3_M0APP_RST(x) ((x) << RESET_STATUS3_M0APP_RST_SHIFT) + +/* SGPIO_RST: Status of the SGPIO_RST reset generator output */ +#define RESET_STATUS3_SGPIO_RST_SHIFT (18) +#define RESET_STATUS3_SGPIO_RST_MASK (0x3 << RESET_STATUS3_SGPIO_RST_SHIFT) +#define RESET_STATUS3_SGPIO_RST(x) ((x) << RESET_STATUS3_SGPIO_RST_SHIFT) + +/* SPI_RST: Status of the SPI_RST reset generator output */ +#define RESET_STATUS3_SPI_RST_SHIFT (20) +#define RESET_STATUS3_SPI_RST_MASK (0x3 << RESET_STATUS3_SPI_RST_SHIFT) +#define RESET_STATUS3_SPI_RST(x) ((x) << RESET_STATUS3_SPI_RST_SHIFT) + +/* --- RESET_ACTIVE_STATUS0 values ------------------------------ */ + +/* CORE_RST: Current status of the CORE_RST */ +#define RESET_ACTIVE_STATUS0_CORE_RST_SHIFT (0) +#define RESET_ACTIVE_STATUS0_CORE_RST (1 << RESET_ACTIVE_STATUS0_CORE_RST_SHIFT) + +/* PERIPH_RST: Current status of the PERIPH_RST */ +#define RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT (1) +#define RESET_ACTIVE_STATUS0_PERIPH_RST \ + (1 << RESET_ACTIVE_STATUS0_PERIPH_RST_SHIFT) + +/* MASTER_RST: Current status of the MASTER_RST */ +#define RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT (2) +#define RESET_ACTIVE_STATUS0_MASTER_RST \ + (1 << RESET_ACTIVE_STATUS0_MASTER_RST_SHIFT) + +/* WWDT_RST: Current status of the WWDT_RST */ +#define RESET_ACTIVE_STATUS0_WWDT_RST_SHIFT (4) +#define RESET_ACTIVE_STATUS0_WWDT_RST (1 << RESET_ACTIVE_STATUS0_WWDT_RST_SHIFT) + +/* CREG_RST: Current status of the CREG_RST */ +#define RESET_ACTIVE_STATUS0_CREG_RST_SHIFT (5) +#define RESET_ACTIVE_STATUS0_CREG_RST (1 << RESET_ACTIVE_STATUS0_CREG_RST_SHIFT) + +/* BUS_RST: Current status of the BUS_RST */ +#define RESET_ACTIVE_STATUS0_BUS_RST_SHIFT (8) +#define RESET_ACTIVE_STATUS0_BUS_RST (1 << RESET_ACTIVE_STATUS0_BUS_RST_SHIFT) + +/* SCU_RST: Current status of the SCU_RST */ +#define RESET_ACTIVE_STATUS0_SCU_RST_SHIFT (9) +#define RESET_ACTIVE_STATUS0_SCU_RST (1 << RESET_ACTIVE_STATUS0_SCU_RST_SHIFT) + +/* M4_RST: Current status of the M4_RST */ +#define RESET_ACTIVE_STATUS0_M4_RST_SHIFT (13) +#define RESET_ACTIVE_STATUS0_M4_RST (1 << RESET_ACTIVE_STATUS0_M4_RST_SHIFT) + +/* LCD_RST: Current status of the LCD_RST */ +#define RESET_ACTIVE_STATUS0_LCD_RST_SHIFT (16) +#define RESET_ACTIVE_STATUS0_LCD_RST (1 << RESET_ACTIVE_STATUS0_LCD_RST_SHIFT) + +/* USB0_RST: Current status of the USB0_RST */ +#define RESET_ACTIVE_STATUS0_USB0_RST_SHIFT (17) +#define RESET_ACTIVE_STATUS0_USB0_RST (1 << RESET_ACTIVE_STATUS0_USB0_RST_SHIFT) + +/* USB1_RST: Current status of the USB1_RST */ +#define RESET_ACTIVE_STATUS0_USB1_RST_SHIFT (18) +#define RESET_ACTIVE_STATUS0_USB1_RST (1 << RESET_ACTIVE_STATUS0_USB1_RST_SHIFT) + +/* DMA_RST: Current status of the DMA_RST */ +#define RESET_ACTIVE_STATUS0_DMA_RST_SHIFT (19) +#define RESET_ACTIVE_STATUS0_DMA_RST (1 << RESET_ACTIVE_STATUS0_DMA_RST_SHIFT) + +/* SDIO_RST: Current status of the SDIO_RST */ +#define RESET_ACTIVE_STATUS0_SDIO_RST_SHIFT (20) +#define RESET_ACTIVE_STATUS0_SDIO_RST (1 << RESET_ACTIVE_STATUS0_SDIO_RST_SHIFT) + +/* EMC_RST: Current status of the EMC_RST */ +#define RESET_ACTIVE_STATUS0_EMC_RST_SHIFT (21) +#define RESET_ACTIVE_STATUS0_EMC_RST (1 << RESET_ACTIVE_STATUS0_EMC_RST_SHIFT) + +/* ETHERNET_RST: Current status of the ETHERNET_RST */ +#define RESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT (22) +#define RESET_ACTIVE_STATUS0_ETHERNET_RST \ + (1 << RESET_ACTIVE_STATUS0_ETHERNET_RST_SHIFT) + +/* FLASHA_RST: Current status of the FLASHA_RST */ +#define RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT (25) +#define RESET_ACTIVE_STATUS0_FLASHA_RST \ + (1 << RESET_ACTIVE_STATUS0_FLASHA_RST_SHIFT) + +/* EEPROM_RST: Current status of the EEPROM_RST */ +#define RESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT (27) +#define RESET_ACTIVE_STATUS0_EEPROM_RST \ + (1 << RESET_ACTIVE_STATUS0_EEPROM_RST_SHIFT) + +/* GPIO_RST: Current status of the GPIO_RST */ +#define RESET_ACTIVE_STATUS0_GPIO_RST_SHIFT (28) +#define RESET_ACTIVE_STATUS0_GPIO_RST (1 << RESET_ACTIVE_STATUS0_GPIO_RST_SHIFT) + +/* FLASHB_RST: Current status of the FLASHB_RST */ +#define RESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT (29) +#define RESET_ACTIVE_STATUS0_FLASHB_RST \ + (1 << RESET_ACTIVE_STATUS0_FLASHB_RST_SHIFT) + +/* --- RESET_ACTIVE_STATUS1 values ------------------------------ */ + +/* TIMER0_RST: Current status of the TIMER0_RST */ +#define RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT (0) +#define RESET_ACTIVE_STATUS1_TIMER0_RST \ + (1 << RESET_ACTIVE_STATUS1_TIMER0_RST_SHIFT) + +/* TIMER1_RST: Current status of the TIMER1_RST */ +#define RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT (1) +#define RESET_ACTIVE_STATUS1_TIMER1_RST \ + (1 << RESET_ACTIVE_STATUS1_TIMER1_RST_SHIFT) + +/* TIMER2_RST: Current status of the TIMER2_RST */ +#define RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT (2) +#define RESET_ACTIVE_STATUS1_TIMER2_RST \ + (1 << RESET_ACTIVE_STATUS1_TIMER2_RST_SHIFT) + +/* TIMER3_RST: Current status of the TIMER3_RST */ +#define RESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT (3) +#define RESET_ACTIVE_STATUS1_TIMER3_RST \ + (1 << RESET_ACTIVE_STATUS1_TIMER3_RST_SHIFT) + +/* RITIMER_RST: Current status of the RITIMER_RST */ +#define RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT (4) +#define RESET_ACTIVE_STATUS1_RITIMER_RST \ + (1 << RESET_ACTIVE_STATUS1_RITIMER_RST_SHIFT) + +/* SCT_RST: Current status of the SCT_RST */ +#define RESET_ACTIVE_STATUS1_SCT_RST_SHIFT (5) +#define RESET_ACTIVE_STATUS1_SCT_RST \ + (1 << RESET_ACTIVE_STATUS1_SCT_RST_SHIFT) + +/* MOTOCONPWM_RST: Current status of the MOTOCONPWM_RST */ +#define RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT (6) +#define RESET_ACTIVE_STATUS1_MOTOCONPWM_RST \ + (1 << RESET_ACTIVE_STATUS1_MOTOCONPWM_RST_SHIFT) + +/* QEI_RST: Current status of the QEI_RST */ +#define RESET_ACTIVE_STATUS1_QEI_RST_SHIFT (7) +#define RESET_ACTIVE_STATUS1_QEI_RST \ + (1 << RESET_ACTIVE_STATUS1_QEI_RST_SHIFT) + +/* ADC0_RST: Current status of the ADC0_RST */ +#define RESET_ACTIVE_STATUS1_ADC0_RST_SHIFT (8) +#define RESET_ACTIVE_STATUS1_ADC0_RST \ + (1 << RESET_ACTIVE_STATUS1_ADC0_RST_SHIFT) + +/* ADC1_RST: Current status of the ADC1_RST */ +#define RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT (9) +#define RESET_ACTIVE_STATUS1_ADC1_RST \ + (1 << RESET_ACTIVE_STATUS1_ADC1_RST_SHIFT) + +/* DAC_RST: Current status of the DAC_RST */ +#define RESET_ACTIVE_STATUS1_DAC_RST_SHIFT (10) +#define RESET_ACTIVE_STATUS1_DAC_RST (1 << RESET_ACTIVE_STATUS1_DAC_RST_SHIFT) + +/* UART0_RST: Current status of the UART0_RST */ +#define RESET_ACTIVE_STATUS1_UART0_RST_SHIFT (12) +#define RESET_ACTIVE_STATUS1_UART0_RST \ + (1 << RESET_ACTIVE_STATUS1_UART0_RST_SHIFT) + +/* UART1_RST: Current status of the UART1_RST */ +#define RESET_ACTIVE_STATUS1_UART1_RST_SHIFT (13) +#define RESET_ACTIVE_STATUS1_UART1_RST \ + (1 << RESET_ACTIVE_STATUS1_UART1_RST_SHIFT) + +/* UART2_RST: Current status of the UART2_RST */ +#define RESET_ACTIVE_STATUS1_UART2_RST_SHIFT (14) +#define RESET_ACTIVE_STATUS1_UART2_RST \ + (1 << RESET_ACTIVE_STATUS1_UART2_RST_SHIFT) + +/* UART3_RST: Current status of the UART3_RST */ +#define RESET_ACTIVE_STATUS1_UART3_RST_SHIFT (15) +#define RESET_ACTIVE_STATUS1_UART3_RST \ + (1 << RESET_ACTIVE_STATUS1_UART3_RST_SHIFT) + +/* I2C0_RST: Current status of the I2C0_RST */ +#define RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT (16) +#define RESET_ACTIVE_STATUS1_I2C0_RST \ + (1 << RESET_ACTIVE_STATUS1_I2C0_RST_SHIFT) + +/* I2C1_RST: Current status of the I2C1_RST */ +#define RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT (17) +#define RESET_ACTIVE_STATUS1_I2C1_RST \ + (1 << RESET_ACTIVE_STATUS1_I2C1_RST_SHIFT) + +/* SSP0_RST: Current status of the SSP0_RST */ +#define RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT (18) +#define RESET_ACTIVE_STATUS1_SSP0_RST \ + (1 << RESET_ACTIVE_STATUS1_SSP0_RST_SHIFT) + +/* SSP1_RST: Current status of the SSP1_RST */ +#define RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT (19) +#define RESET_ACTIVE_STATUS1_SSP1_RST \ + (1 << RESET_ACTIVE_STATUS1_SSP1_RST_SHIFT) + +/* I2S_RST: Current status of the I2S_RST */ +#define RESET_ACTIVE_STATUS1_I2S_RST_SHIFT (20) +#define RESET_ACTIVE_STATUS1_I2S_RST (1 << RESET_ACTIVE_STATUS1_I2S_RST_SHIFT) + +/* SPIFI_RST: Current status of the SPIFI_RST */ +#define RESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT (21) +#define RESET_ACTIVE_STATUS1_SPIFI_RST \ + (1 << RESET_ACTIVE_STATUS1_SPIFI_RST_SHIFT) + +/* CAN1_RST: Current status of the CAN1_RST */ +#define RESET_ACTIVE_STATUS1_CAN1_RST_SHIFT (22) +#define RESET_ACTIVE_STATUS1_CAN1_RST \ + (1 << RESET_ACTIVE_STATUS1_CAN1_RST_SHIFT) + +/* CAN0_RST: Current status of the CAN0_RST */ +#define RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT (23) +#define RESET_ACTIVE_STATUS1_CAN0_RST \ + (1 << RESET_ACTIVE_STATUS1_CAN0_RST_SHIFT) + +/* M0APP_RST: Current status of the M0APP_RST */ +#define RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT (24) +#define RESET_ACTIVE_STATUS1_M0APP_RST \ + (1 << RESET_ACTIVE_STATUS1_M0APP_RST_SHIFT) + +/* SGPIO_RST: Current status of the SGPIO_RST */ +#define RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT (25) +#define RESET_ACTIVE_STATUS1_SGPIO_RST \ + (1 << RESET_ACTIVE_STATUS1_SGPIO_RST_SHIFT) + +/* SPI_RST: Current status of the SPI_RST */ +#define RESET_ACTIVE_STATUS1_SPI_RST_SHIFT (26) +#define RESET_ACTIVE_STATUS1_SPI_RST (1 << RESET_ACTIVE_STATUS1_SPI_RST_SHIFT) + +/* --- RESET_EXT_STAT0 values ----------------------------------- */ + +/* EXT_RESET: Reset activated by external reset from reset pin */ +#define RESET_EXT_STAT0_EXT_RESET_SHIFT (0) +#define RESET_EXT_STAT0_EXT_RESET (1 << RESET_EXT_STAT0_EXT_RESET_SHIFT) + +/* BOD_RESET: Reset activated by BOD reset */ +#define RESET_EXT_STAT0_BOD_RESET_SHIFT (4) +#define RESET_EXT_STAT0_BOD_RESET (1 << RESET_EXT_STAT0_BOD_RESET_SHIFT) + +/* WWDT_RESET: Reset activated by WWDT time-out */ +#define RESET_EXT_STAT0_WWDT_RESET_SHIFT (5) +#define RESET_EXT_STAT0_WWDT_RESET (1 << RESET_EXT_STAT0_WWDT_RESET_SHIFT) + +/* --- RESET_EXT_STAT1 values ----------------------------------- */ + +/* CORE_RESET: Reset activated by CORE_RST output */ +#define RESET_EXT_STAT1_CORE_RESET_SHIFT (1) +#define RESET_EXT_STAT1_CORE_RESET (1 << RESET_EXT_STAT1_CORE_RESET_SHIFT) + +/* --- RESET_EXT_STAT2 values ----------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT2_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT2_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT4 values ----------------------------------- */ + +/* CORE_RESET: Reset activated by CORE_RST output */ +#define RESET_EXT_STAT4_CORE_RESET_SHIFT (1) +#define RESET_EXT_STAT4_CORE_RESET (1 << RESET_EXT_STAT4_CORE_RESET_SHIFT) + +/* --- RESET_EXT_STAT5 values ----------------------------------- */ + +/* CORE_RESET: Reset activated by CORE_RST output */ +#define RESET_EXT_STAT5_CORE_RESET_SHIFT (1) +#define RESET_EXT_STAT5_CORE_RESET (1 << RESET_EXT_STAT5_CORE_RESET_SHIFT) + +/* --- RESET_EXT_STAT8 values ----------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT8_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT8_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT9 values ----------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT9_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT9_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT13 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT13_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT13_MASTER_RESET (1 << RESET_EXT_STAT13_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT16 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT16_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT16_MASTER_RESET (1 << RESET_EXT_STAT16_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT17 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT17_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT17_MASTER_RESET (1 << RESET_EXT_STAT17_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT18 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT18_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT18_MASTER_RESET (1 << RESET_EXT_STAT18_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT19 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT19_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT19_MASTER_RESET (1 << RESET_EXT_STAT19_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT20 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT20_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT20_MASTER_RESET (1 << RESET_EXT_STAT20_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT21 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT21_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT21_MASTER_RESET (1 << RESET_EXT_STAT21_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT22 values ---------------------------------- */ + +/* MASTER_RESET: Reset activated by MASTER_RST output */ +#define RESET_EXT_STAT22_MASTER_RESET_SHIFT (3) +#define RESET_EXT_STAT22_MASTER_RESET (1 << RESET_EXT_STAT22_MASTER_RESET_SHIFT) + +/* --- RESET_EXT_STAT25 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT25_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT25_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT27 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT27_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT27_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT28 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT28_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT28_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT29 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT29_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT29_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT32 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT32_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT32_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT33 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT33_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT33_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT34 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT34_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT34_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT35 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT35_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT35_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT36 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT36_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT36_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT37 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT37_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT37_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT38 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT38_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT38_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT39 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT39_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT39_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT40 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT40_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT40_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT41 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT41_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT41_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT42 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT42_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT42_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT44 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT44_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT44_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT45 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT45_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT45_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT46 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT46_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT46_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT47 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT47_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT47_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT48 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT48_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT48_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT49 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT49_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT49_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT50 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT50_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT50_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT51 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT51_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT51_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT52 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT52_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT52_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT53 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT53_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT53_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT54 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT54_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT54_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT55 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT55_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT55_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT56 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT56_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT56_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT57 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT57_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT57_PERIPHERAL_RESET_SHIFT) + +/* --- RESET_EXT_STAT58 values ---------------------------------- */ + +/* PERIPHERAL_RESET: Reset activated by PERIPHERAL_RST output */ +#define RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT (2) +#define RESET_EXT_STAT58_PERIPHERAL_RESET \ + (1 << RESET_EXT_STAT58_PERIPHERAL_RESET_SHIFT) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/ritimer.h b/libopencm3/include/libopencm3/lpc43xx/ritimer.h new file mode 100644 index 0000000..e736bc3 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/ritimer.h @@ -0,0 +1,59 @@ +/** @defgroup ritimer_defines Repetitive Interrupt Timer Defines + +@brief Defined Constants and Types for the LPC43xx Repetitive Interrupt +Timer + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC43XX_RITIMER_H +#define LPC43XX_RITIMER_H + +/**@{*/ + +#include +#include + +/* --- Repetitive Interrupt Timer registers -------------------------------- */ + +/* Compare register */ +#define RITIMER_COMPVAL MMIO32(RITIMER_BASE + 0x000) + +/* Mask register */ +#define RITIMER_MASK MMIO32(RITIMER_BASE + 0x004) + +/* Control register */ +#define RITIMER_CTRL MMIO32(RITIMER_BASE + 0x008) + +/* 32-bit counter */ +#define RITIMER_COUNTER MMIO32(RITIMER_BASE + 0x00C) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/scu.h b/libopencm3/include/libopencm3/lpc43xx/scu.h new file mode 100644 index 0000000..b869318 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/scu.h @@ -0,0 +1,780 @@ +/** @defgroup scu_defines System Control Unit Defines + +@brief Defined Constants and Types for the LPC43xx System Control Unit + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* +* This file is part of the libopencm3 project. +* +* Copyright (C) 2012 Michael Ossmann +* Copyright (C) 2012 Benjamin Vernoux +* +* This library is free software: you can redistribute it and/or modify +* it under the terms of the GNU Lesser General Public License as published by +* the Free Software Foundation, either version 3 of the License, or +* (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public License +* along with this library. If not, see . +*/ + +#ifndef LPC43XX_SCU_H +#define LPC43XX_SCU_H + +/**@{*/ + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* Pin group base addresses */ +#define PIN_GROUP0 (SCU_BASE + 0x000) +#define PIN_GROUP1 (SCU_BASE + 0x080) +#define PIN_GROUP2 (SCU_BASE + 0x100) +#define PIN_GROUP3 (SCU_BASE + 0x180) +#define PIN_GROUP4 (SCU_BASE + 0x200) +#define PIN_GROUP5 (SCU_BASE + 0x280) +#define PIN_GROUP6 (SCU_BASE + 0x300) +#define PIN_GROUP7 (SCU_BASE + 0x380) +#define PIN_GROUP8 (SCU_BASE + 0x400) +#define PIN_GROUP9 (SCU_BASE + 0x480) +#define PIN_GROUPA (SCU_BASE + 0x500) +#define PIN_GROUPB (SCU_BASE + 0x580) +#define PIN_GROUPC (SCU_BASE + 0x600) +#define PIN_GROUPD (SCU_BASE + 0x680) +#define PIN_GROUPE (SCU_BASE + 0x700) +#define PIN_GROUPF (SCU_BASE + 0x780) + +#define PIN0 0x000 +#define PIN1 0x004 +#define PIN2 0x008 +#define PIN3 0x00C +#define PIN4 0x010 +#define PIN5 0x014 +#define PIN6 0x018 +#define PIN7 0x01C +#define PIN8 0x020 +#define PIN9 0x024 +#define PIN10 0x028 +#define PIN11 0x02C +#define PIN12 0x030 +#define PIN13 0x034 +#define PIN14 0x038 +#define PIN15 0x03C +#define PIN16 0x040 +#define PIN17 0x044 +#define PIN18 0x048 +#define PIN19 0x04C +#define PIN20 0x050 + + +/* --- SCU registers ------------------------------------------------------- */ + +/* Pin configuration registers */ + +#define SCU_SFS(group, pin) MMIO32(group + pin) + +/* Pins P0_n */ +#define SCU_SFSP0_0 SCU_SFS(PIN_GROUP0, PIN0) +#define SCU_SFSP0_1 SCU_SFS(PIN_GROUP0, PIN1) + +/* Pins P1_n */ +#define SCU_SFSP1_0 SCU_SFS(PIN_GROUP1, PIN0) +#define SCU_SFSP1_1 SCU_SFS(PIN_GROUP1, PIN1) +#define SCU_SFSP1_2 SCU_SFS(PIN_GROUP1, PIN2) +#define SCU_SFSP1_3 SCU_SFS(PIN_GROUP1, PIN3) +#define SCU_SFSP1_4 SCU_SFS(PIN_GROUP1, PIN4) +#define SCU_SFSP1_5 SCU_SFS(PIN_GROUP1, PIN5) +#define SCU_SFSP1_6 SCU_SFS(PIN_GROUP1, PIN6) +#define SCU_SFSP1_7 SCU_SFS(PIN_GROUP1, PIN7) +#define SCU_SFSP1_8 SCU_SFS(PIN_GROUP1, PIN8) +#define SCU_SFSP1_9 SCU_SFS(PIN_GROUP1, PIN9) +#define SCU_SFSP1_10 SCU_SFS(PIN_GROUP1, PIN10) +#define SCU_SFSP1_11 SCU_SFS(PIN_GROUP1, PIN11) +#define SCU_SFSP1_12 SCU_SFS(PIN_GROUP1, PIN12) +#define SCU_SFSP1_13 SCU_SFS(PIN_GROUP1, PIN13) +#define SCU_SFSP1_14 SCU_SFS(PIN_GROUP1, PIN14) +#define SCU_SFSP1_15 SCU_SFS(PIN_GROUP1, PIN15) +#define SCU_SFSP1_16 SCU_SFS(PIN_GROUP1, PIN16) +#define SCU_SFSP1_17 SCU_SFS(PIN_GROUP1, PIN17) +#define SCU_SFSP1_18 SCU_SFS(PIN_GROUP1, PIN18) +#define SCU_SFSP1_19 SCU_SFS(PIN_GROUP1, PIN19) +#define SCU_SFSP1_20 SCU_SFS(PIN_GROUP1, PIN20) + +/* Pins P2_n */ +#define SCU_SFSP2_0 SCU_SFS(PIN_GROUP2, PIN0) +#define SCU_SFSP2_1 SCU_SFS(PIN_GROUP2, PIN1) +#define SCU_SFSP2_2 SCU_SFS(PIN_GROUP2, PIN2) +#define SCU_SFSP2_3 SCU_SFS(PIN_GROUP2, PIN3) +#define SCU_SFSP2_4 SCU_SFS(PIN_GROUP2, PIN4) +#define SCU_SFSP2_5 SCU_SFS(PIN_GROUP2, PIN5) +#define SCU_SFSP2_6 SCU_SFS(PIN_GROUP2, PIN6) +#define SCU_SFSP2_7 SCU_SFS(PIN_GROUP2, PIN7) +#define SCU_SFSP2_8 SCU_SFS(PIN_GROUP2, PIN8) +#define SCU_SFSP2_9 SCU_SFS(PIN_GROUP2, PIN9) +#define SCU_SFSP2_10 SCU_SFS(PIN_GROUP2, PIN10) +#define SCU_SFSP2_11 SCU_SFS(PIN_GROUP2, PIN11) +#define SCU_SFSP2_12 SCU_SFS(PIN_GROUP2, PIN12) +#define SCU_SFSP2_13 SCU_SFS(PIN_GROUP2, PIN13) + +/* Pins P3_n */ +#define SCU_SFSP3_0 SCU_SFS(PIN_GROUP3, PIN0) +#define SCU_SFSP3_1 SCU_SFS(PIN_GROUP3, PIN1) +#define SCU_SFSP3_2 SCU_SFS(PIN_GROUP3, PIN2) +#define SCU_SFSP3_3 SCU_SFS(PIN_GROUP3, PIN3) +#define SCU_SFSP3_4 SCU_SFS(PIN_GROUP3, PIN4) +#define SCU_SFSP3_5 SCU_SFS(PIN_GROUP3, PIN5) +#define SCU_SFSP3_6 SCU_SFS(PIN_GROUP3, PIN6) +#define SCU_SFSP3_7 SCU_SFS(PIN_GROUP3, PIN7) +#define SCU_SFSP3_8 SCU_SFS(PIN_GROUP3, PIN8) + +/* Pins P4_n */ +#define SCU_SFSP4_0 SCU_SFS(PIN_GROUP4, PIN0) +#define SCU_SFSP4_1 SCU_SFS(PIN_GROUP4, PIN1) +#define SCU_SFSP4_2 SCU_SFS(PIN_GROUP4, PIN2) +#define SCU_SFSP4_3 SCU_SFS(PIN_GROUP4, PIN3) +#define SCU_SFSP4_4 SCU_SFS(PIN_GROUP4, PIN4) +#define SCU_SFSP4_5 SCU_SFS(PIN_GROUP4, PIN5) +#define SCU_SFSP4_6 SCU_SFS(PIN_GROUP4, PIN6) +#define SCU_SFSP4_7 SCU_SFS(PIN_GROUP4, PIN7) +#define SCU_SFSP4_8 SCU_SFS(PIN_GROUP4, PIN8) +#define SCU_SFSP4_9 SCU_SFS(PIN_GROUP4, PIN9) +#define SCU_SFSP4_10 SCU_SFS(PIN_GROUP4, PIN10) + +/* Pins P5_n */ +#define SCU_SFSP5_0 SCU_SFS(PIN_GROUP5, PIN0) +#define SCU_SFSP5_1 SCU_SFS(PIN_GROUP5, PIN1) +#define SCU_SFSP5_2 SCU_SFS(PIN_GROUP5, PIN2) +#define SCU_SFSP5_3 SCU_SFS(PIN_GROUP5, PIN3) +#define SCU_SFSP5_4 SCU_SFS(PIN_GROUP5, PIN4) +#define SCU_SFSP5_5 SCU_SFS(PIN_GROUP5, PIN5) +#define SCU_SFSP5_6 SCU_SFS(PIN_GROUP5, PIN6) +#define SCU_SFSP5_7 SCU_SFS(PIN_GROUP5, PIN7) + +/* Pins P6_n */ +#define SCU_SFSP6_0 SCU_SFS(PIN_GROUP6, PIN0) +#define SCU_SFSP6_1 SCU_SFS(PIN_GROUP6, PIN1) +#define SCU_SFSP6_2 SCU_SFS(PIN_GROUP6, PIN2) +#define SCU_SFSP6_3 SCU_SFS(PIN_GROUP6, PIN3) +#define SCU_SFSP6_4 SCU_SFS(PIN_GROUP6, PIN4) +#define SCU_SFSP6_5 SCU_SFS(PIN_GROUP6, PIN5) +#define SCU_SFSP6_6 SCU_SFS(PIN_GROUP6, PIN6) +#define SCU_SFSP6_7 SCU_SFS(PIN_GROUP6, PIN7) +#define SCU_SFSP6_8 SCU_SFS(PIN_GROUP6, PIN8) +#define SCU_SFSP6_9 SCU_SFS(PIN_GROUP6, PIN9) +#define SCU_SFSP6_10 SCU_SFS(PIN_GROUP6, PIN10) +#define SCU_SFSP6_11 SCU_SFS(PIN_GROUP6, PIN11) +#define SCU_SFSP6_12 SCU_SFS(PIN_GROUP6, PIN12) + +/* Pins P7_n */ +#define SCU_SFSP7_0 SCU_SFS(PIN_GROUP7, PIN0) +#define SCU_SFSP7_1 SCU_SFS(PIN_GROUP7, PIN1) +#define SCU_SFSP7_2 SCU_SFS(PIN_GROUP7, PIN2) +#define SCU_SFSP7_3 SCU_SFS(PIN_GROUP7, PIN3) +#define SCU_SFSP7_4 SCU_SFS(PIN_GROUP7, PIN4) +#define SCU_SFSP7_5 SCU_SFS(PIN_GROUP7, PIN5) +#define SCU_SFSP7_6 SCU_SFS(PIN_GROUP7, PIN6) +#define SCU_SFSP7_7 SCU_SFS(PIN_GROUP7, PIN7) + +/* Pins P8_n */ +#define SCU_SFSP8_0 SCU_SFS(PIN_GROUP8, PIN0) +#define SCU_SFSP8_1 SCU_SFS(PIN_GROUP8, PIN1) +#define SCU_SFSP8_2 SCU_SFS(PIN_GROUP8, PIN2) +#define SCU_SFSP8_3 SCU_SFS(PIN_GROUP8, PIN3) +#define SCU_SFSP8_4 SCU_SFS(PIN_GROUP8, PIN4) +#define SCU_SFSP8_5 SCU_SFS(PIN_GROUP8, PIN5) +#define SCU_SFSP8_6 SCU_SFS(PIN_GROUP8, PIN6) +#define SCU_SFSP8_7 SCU_SFS(PIN_GROUP8, PIN7) +#define SCU_SFSP8_8 SCU_SFS(PIN_GROUP8, PIN8) + +/* Pins P9_n */ +#define SCU_SFSP9_0 SCU_SFS(PIN_GROUP9, PIN0) +#define SCU_SFSP9_1 SCU_SFS(PIN_GROUP9, PIN1) +#define SCU_SFSP9_2 SCU_SFS(PIN_GROUP9, PIN2) +#define SCU_SFSP9_3 SCU_SFS(PIN_GROUP9, PIN3) +#define SCU_SFSP9_4 SCU_SFS(PIN_GROUP9, PIN4) +#define SCU_SFSP9_5 SCU_SFS(PIN_GROUP9, PIN5) +#define SCU_SFSP9_6 SCU_SFS(PIN_GROUP9, PIN6) + +/* Pins PA_n */ +#define SCU_SFSPA_0 SCU_SFS(PIN_GROUPA, PIN0) +#define SCU_SFSPA_1 SCU_SFS(PIN_GROUPA, PIN1) +#define SCU_SFSPA_2 SCU_SFS(PIN_GROUPA, PIN2) +#define SCU_SFSPA_3 SCU_SFS(PIN_GROUPA, PIN3) +#define SCU_SFSPA_4 SCU_SFS(PIN_GROUPA, PIN4) + +/* Pins PB_n */ +#define SCU_SFSPB_0 SCU_SFS(PIN_GROUPB, PIN0) +#define SCU_SFSPB_1 SCU_SFS(PIN_GROUPB, PIN1) +#define SCU_SFSPB_2 SCU_SFS(PIN_GROUPB, PIN2) +#define SCU_SFSPB_3 SCU_SFS(PIN_GROUPB, PIN3) +#define SCU_SFSPB_4 SCU_SFS(PIN_GROUPB, PIN4) +#define SCU_SFSPB_5 SCU_SFS(PIN_GROUPB, PIN5) +#define SCU_SFSPB_6 SCU_SFS(PIN_GROUPB, PIN6) + +/* Pins PC_n */ +#define SCU_SFSPC_0 SCU_SFS(PIN_GROUPC, PIN0) +#define SCU_SFSPC_1 SCU_SFS(PIN_GROUPC, PIN1) +#define SCU_SFSPC_2 SCU_SFS(PIN_GROUPC, PIN2) +#define SCU_SFSPC_3 SCU_SFS(PIN_GROUPC, PIN3) +#define SCU_SFSPC_4 SCU_SFS(PIN_GROUPC, PIN4) +#define SCU_SFSPC_5 SCU_SFS(PIN_GROUPC, PIN5) +#define SCU_SFSPC_6 SCU_SFS(PIN_GROUPC, PIN6) +#define SCU_SFSPC_7 SCU_SFS(PIN_GROUPC, PIN7) +#define SCU_SFSPC_8 SCU_SFS(PIN_GROUPC, PIN8) +#define SCU_SFSPC_9 SCU_SFS(PIN_GROUPC, PIN9) +#define SCU_SFSPC_10 SCU_SFS(PIN_GROUPC, PIN10) +#define SCU_SFSPC_11 SCU_SFS(PIN_GROUPC, PIN11) +#define SCU_SFSPC_12 SCU_SFS(PIN_GROUPC, PIN12) +#define SCU_SFSPC_13 SCU_SFS(PIN_GROUPC, PIN13) +#define SCU_SFSPC_14 SCU_SFS(PIN_GROUPC, PIN14) + +/* Pins PD_n */ +#define SCU_SFSPD_0 SCU_SFS(PIN_GROUPD, PIN0) +#define SCU_SFSPD_1 SCU_SFS(PIN_GROUPD, PIN1) +#define SCU_SFSPD_2 SCU_SFS(PIN_GROUPD, PIN2) +#define SCU_SFSPD_3 SCU_SFS(PIN_GROUPD, PIN3) +#define SCU_SFSPD_4 SCU_SFS(PIN_GROUPD, PIN4) +#define SCU_SFSPD_5 SCU_SFS(PIN_GROUPD, PIN5) +#define SCU_SFSPD_6 SCU_SFS(PIN_GROUPD, PIN6) +#define SCU_SFSPD_7 SCU_SFS(PIN_GROUPD, PIN7) +#define SCU_SFSPD_8 SCU_SFS(PIN_GROUPD, PIN8) +#define SCU_SFSPD_9 SCU_SFS(PIN_GROUPD, PIN9) +#define SCU_SFSPD_10 SCU_SFS(PIN_GROUPD, PIN10) +#define SCU_SFSPD_11 SCU_SFS(PIN_GROUPD, PIN11) +#define SCU_SFSPD_12 SCU_SFS(PIN_GROUPD, PIN12) +#define SCU_SFSPD_13 SCU_SFS(PIN_GROUPD, PIN13) +#define SCU_SFSPD_14 SCU_SFS(PIN_GROUPD, PIN14) +#define SCU_SFSPD_15 SCU_SFS(PIN_GROUPD, PIN15) +#define SCU_SFSPD_16 SCU_SFS(PIN_GROUPD, PIN16) + +/* Pins PE_n */ +#define SCU_SFSPE_0 SCU_SFS(PIN_GROUPE, PIN0) +#define SCU_SFSPE_1 SCU_SFS(PIN_GROUPE, PIN1) +#define SCU_SFSPE_2 SCU_SFS(PIN_GROUPE, PIN2) +#define SCU_SFSPE_3 SCU_SFS(PIN_GROUPE, PIN3) +#define SCU_SFSPE_4 SCU_SFS(PIN_GROUPE, PIN4) +#define SCU_SFSPE_5 SCU_SFS(PIN_GROUPE, PIN5) +#define SCU_SFSPE_6 SCU_SFS(PIN_GROUPE, PIN6) +#define SCU_SFSPE_7 SCU_SFS(PIN_GROUPE, PIN7) +#define SCU_SFSPE_8 SCU_SFS(PIN_GROUPE, PIN8) +#define SCU_SFSPE_9 SCU_SFS(PIN_GROUPE, PIN9) +#define SCU_SFSPE_10 SCU_SFS(PIN_GROUPE, PIN10) +#define SCU_SFSPE_11 SCU_SFS(PIN_GROUPE, PIN11) +#define SCU_SFSPE_12 SCU_SFS(PIN_GROUPE, PIN12) +#define SCU_SFSPE_13 SCU_SFS(PIN_GROUPE, PIN13) +#define SCU_SFSPE_14 SCU_SFS(PIN_GROUPE, PIN14) +#define SCU_SFSPE_15 SCU_SFS(PIN_GROUPE, PIN15) + +/* Pins PF_n */ +#define SCU_SFSPF_0 SCU_SFS(PIN_GROUPF, PIN0) +#define SCU_SFSPF_1 SCU_SFS(PIN_GROUPF, PIN1) +#define SCU_SFSPF_2 SCU_SFS(PIN_GROUPF, PIN2) +#define SCU_SFSPF_3 SCU_SFS(PIN_GROUPF, PIN3) +#define SCU_SFSPF_4 SCU_SFS(PIN_GROUPF, PIN4) +#define SCU_SFSPF_5 SCU_SFS(PIN_GROUPF, PIN5) +#define SCU_SFSPF_6 SCU_SFS(PIN_GROUPF, PIN6) +#define SCU_SFSPF_7 SCU_SFS(PIN_GROUPF, PIN7) +#define SCU_SFSPF_8 SCU_SFS(PIN_GROUPF, PIN8) +#define SCU_SFSPF_9 SCU_SFS(PIN_GROUPF, PIN9) +#define SCU_SFSPF_10 SCU_SFS(PIN_GROUPF, PIN10) +#define SCU_SFSPF_11 SCU_SFS(PIN_GROUPF, PIN11) + +/* CLKn pins */ +#define SCU_SFSCLK0 MMIO32(SCU_BASE + 0xC00) +#define SCU_SFSCLK1 MMIO32(SCU_BASE + 0xC04) +#define SCU_SFSCLK2 MMIO32(SCU_BASE + 0xC08) +#define SCU_SFSCLK3 MMIO32(SCU_BASE + 0xC0C) + +/* USB1 USB1_DP/USB1_DM pins and I2C-bus open-drain pins */ +#define SCU_SFSUSB MMIO32(SCU_BASE + 0xC80) +#define SCU_SFSI2C0 MMIO32(SCU_BASE + 0xC84) + +/* ADC pin select registers */ + +/* ADC0 function select register */ +#define SCU_ENAIO0 MMIO32(SCU_BASE + 0xC88) + +/* ADC1 function select register */ +#define SCU_ENAIO1 MMIO32(SCU_BASE + 0xC8C) + +/* Analog function select register */ +#define SCU_ENAIO2 MMIO32(SCU_BASE + 0xC90) + +/* EMC clock delay register */ +#define SCU_EMCDELAYCLK MMIO32(SCU_BASE + 0xD00) + +/* Pin interrupt select registers */ + +/* Pin interrupt select register for pin interrupts 0 to 3 */ +#define SCU_PINTSEL0 MMIO32(SCU_BASE + 0xE00) + +/* Pin interrupt select register for pin interrupts 4 to 7 */ +#define SCU_PINTSEL1 MMIO32(SCU_BASE + 0xE04) + +/**************************/ +/* SCU I2C0 Configuration */ +/**************************/ +/* +* Select input glitch filter time constant for the SCL pin. +* 0 = 50 ns glitch filter. +* 1 = 3ns glitch filter. +*/ +#define SCU_SCL_EFP (BIT0) + +/* BIT1 Reserved. Always write a 0 to this bit. */ + +/* +* Select I2C mode for the SCL pin. +* 0 = Standard/Fast mode transmit. +* 1 = Fast-mode Plus transmit. +*/ +#define SCU_SCL_EHD (BIT2) + +/* +* Enable the input receiver for the SCL pin. +* Always write a 1 to this bit when using the +* I2C0. +* 0 = Disabled. +* 1 = Enabled. +*/ +#define SCU_SCL_EZI_EN (BIT3) + +/* BIT4-6 Reserved. */ + +/* +* Enable or disable input glitch filter for the +* SCL pin. The filter time constant is +* determined by bit EFP. +* 0 = Enable input filter. +* 1 = Disable input filter. +*/ +#define SCU_SCL_ZIF_DIS (BIT7) + +/* +* Select input glitch filter time constant for the SDA pin. +* 0 = 50 ns glitch filter. +* 1 = 3ns glitch filter. +*/ +#define SCU_SDA_EFP (BIT8) + +/* BIT9 Reserved. Always write a 0 to this bit. */ + +/* +* Select I2C mode for the SDA pin. +* 0 = Standard/Fast mode transmit. +* 1 = Fast-mode Plus transmit. +*/ +#define SCU_SDA_EHD (BIT10) + +/* +* Enable the input receiver for the SDA pin. +* Always write a 1 to this bit when using the +* I2C0. +* 0 = Disabled. +* 1 = Enabled. +*/ +#define SCU_SDA_EZI_EN (BIT11) + +/* BIT 12-14 - Reserved */ + +/* +* Enable or disable input glitch filter for the +* SDA pin. The filter time constant is +* determined by bit SDA_EFP. +* 0 = Enable input filter. +* 1 = Disable input filter. +*/ +#define SCU_SDA_ZIF_DIS (BIT15) + +/* Standard mode for I2C SCL/SDA Standard/Fast mode */ +#define SCU_I2C0_NOMINAL (SCU_SCL_EZI_EN | SCU_SDA_EZI_EN) + +/* Standard mode for I2C SCL/SDA Fast-mode Plus transmit */ +#define SCU_I2C0_FAST (SCU_SCL_EFP | SCU_SCL_EHD | SCU_SCL_EZI_EN | \ + SCU_SCL_ZIF_DIS | SCU_SDA_EFP | SCU_SDA_EHD | \ + SCU_SDA_EZI_EN) + +/* +* SCU PIN Normal Drive: +* The configuration registers for normal-drive pins control the following pins: +* - P0_0 and P0_1 +* - P1_0 to P1_16 and P1_18 to P1_20 +* - P2_0 to P2_2 and P2_6 to P2_13 +* - P3_0 to P3_2 and P3_4 to P3_8 +* - P4_0 to P4_10 +* - P5_0 to P5_7 +* - P6_0 to P6_12 +* - P7_0 to P7_7 +* - P8_3 to P8_8 +* - P9_0 to P9_6 +* - PA_0 and PA_4 +* - PB_0 to PB_6 +* - PC_0 to PC_14 +* - PE_0 to PE_15 +* - PF_0 to PF_11 +* +* Pin configuration registers for High-Drive pins. +* The configuration registers for high-drive pins control the following pins: +* - P1_17 +* - P2_3 to P2_5 +* - P8_0 to P8_2 +* - PA_1 to PA_3 +* +* Pin configuration registers for High-Speed pins. +* This register controls the following pins: +* - P3_3 and pins CLK0 to CLK3. +*/ +typedef enum { + /* Group Port 0 */ + P0_0 = (PIN_GROUP0+PIN0), + P0_1 = (PIN_GROUP0+PIN1), + + /* Group Port 1 */ + P1_0 = (PIN_GROUP1+PIN0), + P1_1 = (PIN_GROUP1+PIN1), + P1_2 = (PIN_GROUP1+PIN2), + P1_3 = (PIN_GROUP1+PIN3), + P1_4 = (PIN_GROUP1+PIN4), + P1_5 = (PIN_GROUP1+PIN5), + P1_6 = (PIN_GROUP1+PIN6), + P1_7 = (PIN_GROUP1+PIN7), + P1_8 = (PIN_GROUP1+PIN8), + P1_9 = (PIN_GROUP1+PIN9), + P1_10 = (PIN_GROUP1+PIN10), + P1_11 = (PIN_GROUP1+PIN11), + P1_12 = (PIN_GROUP1+PIN12), + P1_13 = (PIN_GROUP1+PIN13), + P1_14 = (PIN_GROUP1+PIN14), + P1_15 = (PIN_GROUP1+PIN15), + P1_16 = (PIN_GROUP1+PIN16), + + /* P1_17 is High-Drive pin */ + P1_17 = (PIN_GROUP1+PIN17), + + P1_18 = (PIN_GROUP1+PIN18), + P1_19 = (PIN_GROUP1+PIN19), + P1_20 = (PIN_GROUP1+PIN20), + + /* Group Port 2 */ + P2_0 = (PIN_GROUP2+PIN0), + P2_1 = (PIN_GROUP2+PIN1), + P2_2 = (PIN_GROUP2+PIN2), + + /* P2_3 to P2_5 are High-Drive pins */ + P2_3 = (PIN_GROUP2+PIN3), + P2_4 = (PIN_GROUP2+PIN4), + P2_5 = (PIN_GROUP2+PIN5), + + P2_6 = (PIN_GROUP2+PIN6), + P2_7 = (PIN_GROUP2+PIN7), + P2_8 = (PIN_GROUP2+PIN8), + P2_9 = (PIN_GROUP2+PIN9), + P2_10 = (PIN_GROUP2+PIN10), + P2_11 = (PIN_GROUP2+PIN11), + P2_12 = (PIN_GROUP2+PIN12), + P2_13 = (PIN_GROUP2+PIN13), + + /* Group Port 3 */ + P3_0 = (PIN_GROUP3+PIN0), + P3_1 = (PIN_GROUP3+PIN1), + P3_2 = (PIN_GROUP3+PIN2), + + /* P3_3 is High-Speed pin */ + P3_3 = (PIN_GROUP3+PIN3), + + P3_4 = (PIN_GROUP3+PIN4), + P3_5 = (PIN_GROUP3+PIN5), + P3_6 = (PIN_GROUP3+PIN6), + P3_7 = (PIN_GROUP3+PIN7), + P3_8 = (PIN_GROUP3+PIN8), + + /* Group Port 4 */ + P4_0 = (PIN_GROUP4+PIN0), + P4_1 = (PIN_GROUP4+PIN1), + P4_2 = (PIN_GROUP4+PIN2), + P4_3 = (PIN_GROUP4+PIN3), + P4_4 = (PIN_GROUP4+PIN4), + P4_5 = (PIN_GROUP4+PIN5), + P4_6 = (PIN_GROUP4+PIN6), + P4_7 = (PIN_GROUP4+PIN7), + P4_8 = (PIN_GROUP4+PIN8), + P4_9 = (PIN_GROUP4+PIN9), + P4_10 = (PIN_GROUP4+PIN10), + + /* Group Port 5 */ + P5_0 = (PIN_GROUP5+PIN0), + P5_1 = (PIN_GROUP5+PIN1), + P5_2 = (PIN_GROUP5+PIN2), + P5_3 = (PIN_GROUP5+PIN3), + P5_4 = (PIN_GROUP5+PIN4), + P5_5 = (PIN_GROUP5+PIN5), + P5_6 = (PIN_GROUP5+PIN6), + P5_7 = (PIN_GROUP5+PIN7), + + /* Group Port 6 */ + P6_0 = (PIN_GROUP6+PIN0), + P6_1 = (PIN_GROUP6+PIN1), + P6_2 = (PIN_GROUP6+PIN2), + P6_3 = (PIN_GROUP6+PIN3), + P6_4 = (PIN_GROUP6+PIN4), + P6_5 = (PIN_GROUP6+PIN5), + P6_6 = (PIN_GROUP6+PIN6), + P6_7 = (PIN_GROUP6+PIN7), + P6_8 = (PIN_GROUP6+PIN8), + P6_9 = (PIN_GROUP6+PIN9), + P6_10 = (PIN_GROUP6+PIN10), + P6_11 = (PIN_GROUP6+PIN11), + P6_12 = (PIN_GROUP6+PIN12), + + /* Group Port 7 */ + P7_0 = (PIN_GROUP7+PIN0), + P7_1 = (PIN_GROUP7+PIN1), + P7_2 = (PIN_GROUP7+PIN2), + P7_3 = (PIN_GROUP7+PIN3), + P7_4 = (PIN_GROUP7+PIN4), + P7_5 = (PIN_GROUP7+PIN5), + P7_6 = (PIN_GROUP7+PIN6), + P7_7 = (PIN_GROUP7+PIN7), + + /* Group Port 8 */ + /* P8_0 to P8_2 are High-Drive pins */ + P8_0 = (PIN_GROUP8+PIN0), + P8_1 = (PIN_GROUP8+PIN1), + P8_2 = (PIN_GROUP8+PIN2), + + P8_3 = (PIN_GROUP8+PIN3), + P8_4 = (PIN_GROUP8+PIN4), + P8_5 = (PIN_GROUP8+PIN5), + P8_6 = (PIN_GROUP8+PIN6), + P8_7 = (PIN_GROUP8+PIN7), + P8_8 = (PIN_GROUP8+PIN8), + + /* Group Port 9 */ + P9_0 = (PIN_GROUP9+PIN0), + P9_1 = (PIN_GROUP9+PIN1), + P9_2 = (PIN_GROUP9+PIN2), + P9_3 = (PIN_GROUP9+PIN3), + P9_4 = (PIN_GROUP9+PIN4), + P9_5 = (PIN_GROUP9+PIN5), + P9_6 = (PIN_GROUP9+PIN6), + + /* Group Port A */ + PA_0 = (PIN_GROUPA+PIN0), + /* PA_1 to PA_3 are Normal & High-Drive Pins */ + PA_1 = (PIN_GROUPA+PIN1), + PA_2 = (PIN_GROUPA+PIN2), + PA_3 = (PIN_GROUPA+PIN3), + PA_4 = (PIN_GROUPA+PIN4), + + /* Group Port B */ + PB_0 = (PIN_GROUPB+PIN0), + PB_1 = (PIN_GROUPB+PIN1), + PB_2 = (PIN_GROUPB+PIN2), + PB_3 = (PIN_GROUPB+PIN3), + PB_4 = (PIN_GROUPB+PIN4), + PB_5 = (PIN_GROUPB+PIN5), + PB_6 = (PIN_GROUPB+PIN6), + + /* Group Port C */ + PC_0 = (PIN_GROUPC+PIN0), + PC_1 = (PIN_GROUPC+PIN1), + PC_2 = (PIN_GROUPC+PIN2), + PC_3 = (PIN_GROUPC+PIN3), + PC_4 = (PIN_GROUPC+PIN4), + PC_5 = (PIN_GROUPC+PIN5), + PC_6 = (PIN_GROUPC+PIN6), + PC_7 = (PIN_GROUPC+PIN7), + PC_8 = (PIN_GROUPC+PIN8), + PC_9 = (PIN_GROUPC+PIN9), + PC_10 = (PIN_GROUPC+PIN10), + PC_11 = (PIN_GROUPC+PIN11), + PC_12 = (PIN_GROUPC+PIN12), + PC_13 = (PIN_GROUPC+PIN13), + PC_14 = (PIN_GROUPC+PIN14), + + /* Group Port D (seems not configurable through SCU, not defined in + * UM10503.pdf Rev.1, keep it here) + */ + PD_0 = (PIN_GROUPD+PIN0), + PD_1 = (PIN_GROUPD+PIN1), + PD_2 = (PIN_GROUPD+PIN2), + PD_3 = (PIN_GROUPD+PIN3), + PD_4 = (PIN_GROUPD+PIN4), + PD_5 = (PIN_GROUPD+PIN5), + PD_6 = (PIN_GROUPD+PIN6), + PD_7 = (PIN_GROUPD+PIN7), + PD_8 = (PIN_GROUPD+PIN8), + PD_9 = (PIN_GROUPD+PIN9), + PD_10 = (PIN_GROUPD+PIN10), + PD_11 = (PIN_GROUPD+PIN11), + PD_12 = (PIN_GROUPD+PIN12), + PD_13 = (PIN_GROUPD+PIN13), + PD_14 = (PIN_GROUPD+PIN14), + PD_15 = (PIN_GROUPD+PIN15), + PD_16 = (PIN_GROUPD+PIN16), + + /* Group Port E */ + PE_0 = (PIN_GROUPE+PIN0), + PE_1 = (PIN_GROUPE+PIN1), + PE_2 = (PIN_GROUPE+PIN2), + PE_3 = (PIN_GROUPE+PIN3), + PE_4 = (PIN_GROUPE+PIN4), + PE_5 = (PIN_GROUPE+PIN5), + PE_6 = (PIN_GROUPE+PIN6), + PE_7 = (PIN_GROUPE+PIN7), + PE_8 = (PIN_GROUPE+PIN8), + PE_9 = (PIN_GROUPE+PIN9), + PE_10 = (PIN_GROUPE+PIN10), + PE_11 = (PIN_GROUPE+PIN11), + PE_12 = (PIN_GROUPE+PIN12), + PE_13 = (PIN_GROUPE+PIN13), + PE_14 = (PIN_GROUPE+PIN14), + PE_15 = (PIN_GROUPE+PIN15), + + /* Group Port F */ + PF_0 = (PIN_GROUPF+PIN0), + PF_1 = (PIN_GROUPF+PIN1), + PF_2 = (PIN_GROUPF+PIN2), + PF_3 = (PIN_GROUPF+PIN3), + PF_4 = (PIN_GROUPF+PIN4), + PF_5 = (PIN_GROUPF+PIN5), + PF_6 = (PIN_GROUPF+PIN6), + PF_7 = (PIN_GROUPF+PIN7), + PF_8 = (PIN_GROUPF+PIN8), + PF_9 = (PIN_GROUPF+PIN9), + PF_10 = (PIN_GROUPF+PIN10), + PF_11 = (PIN_GROUPF+PIN11), + + /* Group Clock 0 to 3 High-Speed pins */ + CLK0 = (SCU_BASE + 0xC00), + CLK1 = (SCU_BASE + 0xC04), + CLK2 = (SCU_BASE + 0xC08), + CLK3 = (SCU_BASE + 0xC0C) + +} scu_grp_pin_t; + +/* +* Pin Configuration to be used for scu_pinmux() parameter scu_conf +* For normal-drive pins, high-drive pins, high-speed pins +*/ +/* +* Function BIT0 to 2. +* Common to normal-drive pins, high-drive pins, high-speed pins. +*/ +#define SCU_CONF_FUNCTION0 (0x0) +#define SCU_CONF_FUNCTION1 (0x1) +#define SCU_CONF_FUNCTION2 (0x2) +#define SCU_CONF_FUNCTION3 (0x3) +#define SCU_CONF_FUNCTION4 (0x4) +#define SCU_CONF_FUNCTION5 (0x5) +#define SCU_CONF_FUNCTION6 (0x6) +#define SCU_CONF_FUNCTION7 (0x7) + +/* +* Enable pull-down resistor at pad +* By default=0 Disable pull-down. +* Available to normal-drive pins, high-drive pins, high-speed pins +*/ +#define SCU_CONF_EPD_EN_PULLDOWN (BIT3) + +/* +* Disable pull-up resistor at pad. +* By default=0 the pull-up resistor is enabled at reset. +* Available to normal-drive pins, high-drive pins, high-speed pins +*/ +#define SCU_CONF_EPUN_DIS_PULLUP (BIT4) + +/* +* Select Slew Rate. +* By Default=0 Slow. +* Available to normal-drive and high-speed pins, reserved for high-drive pins. +*/ +#define SCU_CONF_EHS_FAST (BIT5) + +/* +* Input buffer enable. +* By Default=0 Disable Input Buffer. +* The input buffer is disabled by default at reset and must be enabled for +* receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer +* to the pad(in high-drive pins). +* Available to normal-drive pins, high-drive pins, high-speed pins. +*/ +#define SCU_CONF_EZI_EN_IN_BUFFER (BIT6) + +/* +* Input glitch filter. Disable the input glitch filter for clocking signals +* higher than 30 MHz. +* Available to normal-drive pins, high-drive pins, high-speed pins. +*/ +#define SCU_CONF_ZIF_DIS_IN_GLITCH_FILT (BIT7) + +/* +* Select drive strength. (default=0 Normal-drive: 4 mA drive strength) (BIT8/9). +* Available to high-drive pins, reserved for others. +*/ +#define SCU_CONF_EHD_NORMAL_DRIVE_8MILLIA (0x100) +#define SCU_CONF_EHD_NORMAL_DRIVE_14MILLIA (0x200) +#define SCU_CONF_EHD_NORMAL_DRIVE_20MILLIA (0x300) + +/* BIT10 to 31 are Reserved */ + +/* Configuration for different I/O pins types */ +#define SCU_EMC_IO (SCU_CONF_EPD_EN_PULLDOWN | \ + SCU_CONF_EHS_FAST | \ + SCU_CONF_EZI_EN_IN_BUFFER | \ + SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_LCD (SCU_CONF_EPUN_DIS_PULLUP | \ + SCU_CONF_EHS_FAST | \ + SCU_CONF_EZI_EN_IN_BUFFER | \ + SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_CLK_IN (SCU_CONF_EPD_EN_PULLDOWN | \ + SCU_CONF_EHS_FAST | \ + SCU_CONF_EZI_EN_IN_BUFFER | \ + SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_CLK_OUT (SCU_CONF_EPD_EN_PULLDOWN | \ + SCU_CONF_EHS_FAST | \ + SCU_CONF_EZI_EN_IN_BUFFER | \ + SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_GPIO_PUP (SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_GPIO_PDN (SCU_CONF_EPUN_DIS_PULLUP | \ + SCU_CONF_EPD_EN_PULLDOWN | \ + SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | \ + SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_GPIO_FAST (SCU_CONF_EPUN_DIS_PULLUP | \ + SCU_CONF_EHS_FAST | \ + SCU_CONF_EZI_EN_IN_BUFFER | \ + SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | \ + SCU_CONF_EPD_EN_PULLDOWN | \ + SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_SSP_IO (SCU_CONF_EPUN_DIS_PULLUP | \ + SCU_CONF_EHS_FAST | \ + SCU_CONF_EZI_EN_IN_BUFFER | \ + SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) + +BEGIN_DECLS + +void scu_pinmux(scu_grp_pin_t group_pin, uint32_t scu_conf); + +END_DECLS + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/sdio.h b/libopencm3/include/libopencm3/lpc43xx/sdio.h new file mode 100644 index 0000000..164dda4 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/sdio.h @@ -0,0 +1,151 @@ +/** @defgroup sdio_defines SDIO + +@brief Defined Constants and Types for the LPC43xx SDIO + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC43XX_SDIO_H +#define LPC43XX_SDIO_H + +/**@{*/ + +#include +#include + +/* --- SDIO registers ----------------------------------------------------- */ + +/* Control Register */ +#define SDIO_CTRL MMIO32(SDIO_BASE + 0x000) + +/* Power Enable Register */ +#define SDIO_PWREN MMIO32(SDIO_BASE + 0x004) + +/* Clock Divider Register */ +#define SDIO_CLKDIV MMIO32(SDIO_BASE + 0x008) + +/* SD Clock Source Register */ +#define SDIO_CLKSRC MMIO32(SDIO_BASE + 0x00C) + +/* Clock Enable Register */ +#define SDIO_CLKENA MMIO32(SDIO_BASE + 0x010) + +/* Time-out Register */ +#define SDIO_TMOUT MMIO32(SDIO_BASE + 0x014) + +/* Card Type Register */ +#define SDIO_CTYPE MMIO32(SDIO_BASE + 0x018) + +/* Block Size Register */ +#define SDIO_BLKSIZ MMIO32(SDIO_BASE + 0x01C) + +/* Byte Count Register */ +#define SDIO_BYTCNT MMIO32(SDIO_BASE + 0x020) + +/* Interrupt Mask Register */ +#define SDIO_INTMASK MMIO32(SDIO_BASE + 0x024) + +/* Command Argument Register */ +#define SDIO_CMDARG MMIO32(SDIO_BASE + 0x028) + +/* Command Register */ +#define SDIO_CMD MMIO32(SDIO_BASE + 0x02C) + +/* Response Register 0 */ +#define SDIO_RESP0 MMIO32(SDIO_BASE + 0x030) + +/* Response Register 1 */ +#define SDIO_RESP1 MMIO32(SDIO_BASE + 0x034) + +/* Response Register 2 */ +#define SDIO_RESP2 MMIO32(SDIO_BASE + 0x038) + +/* Response Register 3 */ +#define SDIO_RESP3 MMIO32(SDIO_BASE + 0x03C) + +/* Masked Interrupt Status Register */ +#define SDIO_MINTSTS MMIO32(SDIO_BASE + 0x040) + +/* Raw Interrupt Status Register */ +#define SDIO_RINTSTS MMIO32(SDIO_BASE + 0x044) + +/* Status Register */ +#define SDIO_STATUS MMIO32(SDIO_BASE + 0x048) + +/* FIFO Threshold Watermark Register */ +#define SDIO_FIFOTH MMIO32(SDIO_BASE + 0x04C) + +/* Card Detect Register */ +#define SDIO_CDETECT MMIO32(SDIO_BASE + 0x050) + +/* Write Protect Register */ +#define SDIO_WRTPRT MMIO32(SDIO_BASE + 0x054) + +/* Transferred CIU Card Byte Count Register */ +#define SDIO_TCBCNT MMIO32(SDIO_BASE + 0x05C) + +/* Transferred Host to BIU-FIFO Byte Count Register */ +#define SDIO_TBBCNT MMIO32(SDIO_BASE + 0x060) + +/* Debounce Count Register */ +#define SDIO_DEBNCE MMIO32(SDIO_BASE + 0x064) + +/* UHS-1 Register */ +#define SDIO_UHS_REG MMIO32(SDIO_BASE + 0x074) + +/* Hardware Reset */ +#define SDIO_RST_N MMIO32(SDIO_BASE + 0x078) + +/* Bus Mode Register */ +#define SDIO_BMOD MMIO32(SDIO_BASE + 0x080) + +/* Poll Demand Register */ +#define SDIO_PLDMND MMIO32(SDIO_BASE + 0x084) + +/* Descriptor List Base Address Register */ +#define SDIO_DBADDR MMIO32(SDIO_BASE + 0x088) + +/* Internal DMAC Status Register */ +#define SDIO_IDSTS MMIO32(SDIO_BASE + 0x08C) + +/* Internal DMAC Interrupt Enable Register */ +#define SDIO_IDINTEN MMIO32(SDIO_BASE + 0x090) + +/* Current Host Descriptor Address Register */ +#define SDIO_DSCADDR MMIO32(SDIO_BASE + 0x094) + +/* Current Buffer Descriptor Address Register */ +#define SDIO_BUFADDR MMIO32(SDIO_BASE + 0x098) + +/* Data FIFO read/write */ +#define SDIO_DATA MMIO32(SDIO_BASE + 0x100) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/sgpio.h b/libopencm3/include/libopencm3/lpc43xx/sgpio.h new file mode 100644 index 0000000..4b8d5b6 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/sgpio.h @@ -0,0 +1,691 @@ +/** @defgroup sgpio_defines Serial General Purpose I/O + +@brief Defined Constants and Types for the LPC43xx Serial General Purpose +I/O + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/** @defgroup sdio_defines SDIO + +@brief Defined Constants and Types for the LPC43xx SDIO + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann + * Copyright (C) 2012 Jared Boone + * Copyright (C) 2012 Benjamin Vernoux + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC43XX_SGPIO_H +#define LPC43XX_SGPIO_H + +/**@{*/ + +#include +#include + +/* --- SGPIO registers ----------------------------------------------------- */ + +/* Pin multiplexer configuration registers (OUT_MUX_CFG0 to 15) */ +#define SGPIO_OUT_MUX_CFG(pin) MMIO32(SGPIO_PORT_BASE + (pin * 0x04)) +#define SGPIO_OUT_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x00) +#define SGPIO_OUT_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x04) +#define SGPIO_OUT_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x08) +#define SGPIO_OUT_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x0C) +#define SGPIO_OUT_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x10) +#define SGPIO_OUT_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x14) +#define SGPIO_OUT_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x18) +#define SGPIO_OUT_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x1C) +#define SGPIO_OUT_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0x20) +#define SGPIO_OUT_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0x24) +#define SGPIO_OUT_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0x28) +#define SGPIO_OUT_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0x2C) +#define SGPIO_OUT_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0x30) +#define SGPIO_OUT_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0x34) +#define SGPIO_OUT_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0x38) +#define SGPIO_OUT_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0x3C) + +/* SGPIO multiplexer configuration registers (SGPIO_MUX_CFG0 to 15) */ +#define SGPIO_MUX_CFG(slice) MMIO32(SGPIO_PORT_BASE + 0x40 + \ + (slice * 0x04)) +#define SGPIO_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x40) +#define SGPIO_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x44) +#define SGPIO_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x48) +#define SGPIO_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x4C) +#define SGPIO_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x50) +#define SGPIO_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x54) +#define SGPIO_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x58) +#define SGPIO_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x5C) +#define SGPIO_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0x60) +#define SGPIO_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0x64) +#define SGPIO_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0x68) +#define SGPIO_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0x6C) +#define SGPIO_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0x70) +#define SGPIO_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0x74) +#define SGPIO_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0x78) +#define SGPIO_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0x7C) + +/* Slice multiplexer configuration registers (SLICE_MUX_CFG0 to 15) */ +#define SGPIO_SLICE_MUX_CFG(slice) MMIO32(SGPIO_PORT_BASE + 0x80 + \ + (slice * 0x04)) +#define SGPIO_SLICE_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x80) +#define SGPIO_SLICE_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x84) +#define SGPIO_SLICE_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x88) +#define SGPIO_SLICE_MUX_CFG3 MMIO32(SGPIO_PORT_BASE + 0x8C) +#define SGPIO_SLICE_MUX_CFG4 MMIO32(SGPIO_PORT_BASE + 0x90) +#define SGPIO_SLICE_MUX_CFG5 MMIO32(SGPIO_PORT_BASE + 0x94) +#define SGPIO_SLICE_MUX_CFG6 MMIO32(SGPIO_PORT_BASE + 0x98) +#define SGPIO_SLICE_MUX_CFG7 MMIO32(SGPIO_PORT_BASE + 0x9C) +#define SGPIO_SLICE_MUX_CFG8 MMIO32(SGPIO_PORT_BASE + 0xA0) +#define SGPIO_SLICE_MUX_CFG9 MMIO32(SGPIO_PORT_BASE + 0xA4) +#define SGPIO_SLICE_MUX_CFG10 MMIO32(SGPIO_PORT_BASE + 0xA8) +#define SGPIO_SLICE_MUX_CFG11 MMIO32(SGPIO_PORT_BASE + 0xAC) +#define SGPIO_SLICE_MUX_CFG12 MMIO32(SGPIO_PORT_BASE + 0xB0) +#define SGPIO_SLICE_MUX_CFG13 MMIO32(SGPIO_PORT_BASE + 0xB4) +#define SGPIO_SLICE_MUX_CFG14 MMIO32(SGPIO_PORT_BASE + 0xB8) +#define SGPIO_SLICE_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0xBC) + +/* Slice data registers (REG0 to 15) */ +#define SGPIO_REG(slice) MMIO32(SGPIO_PORT_BASE + 0xC0 + \ + (slice * 0x04)) +#define SGPIO_REG0 MMIO32(SGPIO_PORT_BASE + 0xC0) +#define SGPIO_REG1 MMIO32(SGPIO_PORT_BASE + 0xC4) +#define SGPIO_REG2 MMIO32(SGPIO_PORT_BASE + 0xC8) +#define SGPIO_REG3 MMIO32(SGPIO_PORT_BASE + 0xCC) +#define SGPIO_REG4 MMIO32(SGPIO_PORT_BASE + 0xD0) +#define SGPIO_REG5 MMIO32(SGPIO_PORT_BASE + 0xD4) +#define SGPIO_REG6 MMIO32(SGPIO_PORT_BASE + 0xD8) +#define SGPIO_REG7 MMIO32(SGPIO_PORT_BASE + 0xDC) +#define SGPIO_REG8 MMIO32(SGPIO_PORT_BASE + 0xE0) +#define SGPIO_REG9 MMIO32(SGPIO_PORT_BASE + 0xE4) +#define SGPIO_REG10 MMIO32(SGPIO_PORT_BASE + 0xE8) +#define SGPIO_REG11 MMIO32(SGPIO_PORT_BASE + 0xEC) +#define SGPIO_REG12 MMIO32(SGPIO_PORT_BASE + 0xF0) +#define SGPIO_REG13 MMIO32(SGPIO_PORT_BASE + 0xF4) +#define SGPIO_REG14 MMIO32(SGPIO_PORT_BASE + 0xF8) +#define SGPIO_REG15 MMIO32(SGPIO_PORT_BASE + 0xFC) + +/* Slice data shadow registers (REG_SS0 to 15) */ +#define SGPIO_REG_SS(slice) MMIO32(SGPIO_PORT_BASE + 0x100 + \ + (slice * 0x04)) +#define SGPIO_REG_SS0 MMIO32(SGPIO_PORT_BASE + 0x100) +#define SGPIO_REG_SS1 MMIO32(SGPIO_PORT_BASE + 0x104) +#define SGPIO_REG_SS2 MMIO32(SGPIO_PORT_BASE + 0x108) +#define SGPIO_REG_SS3 MMIO32(SGPIO_PORT_BASE + 0x10C) +#define SGPIO_REG_SS4 MMIO32(SGPIO_PORT_BASE + 0x110) +#define SGPIO_REG_SS5 MMIO32(SGPIO_PORT_BASE + 0x114) +#define SGPIO_REG_SS6 MMIO32(SGPIO_PORT_BASE + 0x118) +#define SGPIO_REG_SS7 MMIO32(SGPIO_PORT_BASE + 0x11C) +#define SGPIO_REG_SS8 MMIO32(SGPIO_PORT_BASE + 0x120) +#define SGPIO_REG_SS9 MMIO32(SGPIO_PORT_BASE + 0x124) +#define SGPIO_REG_SS10 MMIO32(SGPIO_PORT_BASE + 0x128) +#define SGPIO_REG_SS11 MMIO32(SGPIO_PORT_BASE + 0x12C) +#define SGPIO_REG_SS12 MMIO32(SGPIO_PORT_BASE + 0x130) +#define SGPIO_REG_SS13 MMIO32(SGPIO_PORT_BASE + 0x134) +#define SGPIO_REG_SS14 MMIO32(SGPIO_PORT_BASE + 0x138) +#define SGPIO_REG_SS15 MMIO32(SGPIO_PORT_BASE + 0x13C) + +/* Reload registers (PRESET0 to 15) */ +#define SGPIO_PRESET(slice) MMIO32(SGPIO_PORT_BASE + 0x140 + \ + (slice * 0x04)) +#define SGPIO_PRESET0 MMIO32(SGPIO_PORT_BASE + 0x140) +#define SGPIO_PRESET1 MMIO32(SGPIO_PORT_BASE + 0x144) +#define SGPIO_PRESET2 MMIO32(SGPIO_PORT_BASE + 0x148) +#define SGPIO_PRESET3 MMIO32(SGPIO_PORT_BASE + 0x14C) +#define SGPIO_PRESET4 MMIO32(SGPIO_PORT_BASE + 0x150) +#define SGPIO_PRESET5 MMIO32(SGPIO_PORT_BASE + 0x154) +#define SGPIO_PRESET6 MMIO32(SGPIO_PORT_BASE + 0x158) +#define SGPIO_PRESET7 MMIO32(SGPIO_PORT_BASE + 0x15C) +#define SGPIO_PRESET8 MMIO32(SGPIO_PORT_BASE + 0x160) +#define SGPIO_PRESET9 MMIO32(SGPIO_PORT_BASE + 0x164) +#define SGPIO_PRESET10 MMIO32(SGPIO_PORT_BASE + 0x168) +#define SGPIO_PRESET11 MMIO32(SGPIO_PORT_BASE + 0x16C) +#define SGPIO_PRESET12 MMIO32(SGPIO_PORT_BASE + 0x170) +#define SGPIO_PRESET13 MMIO32(SGPIO_PORT_BASE + 0x174) +#define SGPIO_PRESET14 MMIO32(SGPIO_PORT_BASE + 0x178) +#define SGPIO_PRESET15 MMIO32(SGPIO_PORT_BASE + 0x17C) + +/* Down counter registers (COUNT0 to 15) */ +#define SGPIO_COUNT(slice) MMIO32(SGPIO_PORT_BASE + 0x180 + \ + (slice * 0x04)) +#define SGPIO_COUNT0 MMIO32(SGPIO_PORT_BASE + 0x180) +#define SGPIO_COUNT1 MMIO32(SGPIO_PORT_BASE + 0x184) +#define SGPIO_COUNT2 MMIO32(SGPIO_PORT_BASE + 0x188) +#define SGPIO_COUNT3 MMIO32(SGPIO_PORT_BASE + 0x18C) +#define SGPIO_COUNT4 MMIO32(SGPIO_PORT_BASE + 0x190) +#define SGPIO_COUNT5 MMIO32(SGPIO_PORT_BASE + 0x194) +#define SGPIO_COUNT6 MMIO32(SGPIO_PORT_BASE + 0x198) +#define SGPIO_COUNT7 MMIO32(SGPIO_PORT_BASE + 0x19C) +#define SGPIO_COUNT8 MMIO32(SGPIO_PORT_BASE + 0x1A0) +#define SGPIO_COUNT9 MMIO32(SGPIO_PORT_BASE + 0x1A4) +#define SGPIO_COUNT10 MMIO32(SGPIO_PORT_BASE + 0x1A8) +#define SGPIO_COUNT11 MMIO32(SGPIO_PORT_BASE + 0x1AC) +#define SGPIO_COUNT12 MMIO32(SGPIO_PORT_BASE + 0x1B0) +#define SGPIO_COUNT13 MMIO32(SGPIO_PORT_BASE + 0x1B4) +#define SGPIO_COUNT14 MMIO32(SGPIO_PORT_BASE + 0x1B8) +#define SGPIO_COUNT15 MMIO32(SGPIO_PORT_BASE + 0x1BC) + +/* Position registers (POS0 to 15) */ +#define SGPIO_POS(slice) MMIO32(SGPIO_PORT_BASE + 0x1C0 + \ + (slice * 0x04)) +#define SGPIO_POS0 MMIO32(SGPIO_PORT_BASE + 0x1C0) +#define SGPIO_POS1 MMIO32(SGPIO_PORT_BASE + 0x1C4) +#define SGPIO_POS2 MMIO32(SGPIO_PORT_BASE + 0x1C8) +#define SGPIO_POS3 MMIO32(SGPIO_PORT_BASE + 0x1CC) +#define SGPIO_POS4 MMIO32(SGPIO_PORT_BASE + 0x1D0) +#define SGPIO_POS5 MMIO32(SGPIO_PORT_BASE + 0x1D4) +#define SGPIO_POS6 MMIO32(SGPIO_PORT_BASE + 0x1D8) +#define SGPIO_POS7 MMIO32(SGPIO_PORT_BASE + 0x1DC) +#define SGPIO_POS8 MMIO32(SGPIO_PORT_BASE + 0x1E0) +#define SGPIO_POS9 MMIO32(SGPIO_PORT_BASE + 0x1E4) +#define SGPIO_POS10 MMIO32(SGPIO_PORT_BASE + 0x1E8) +#define SGPIO_POS11 MMIO32(SGPIO_PORT_BASE + 0x1EC) +#define SGPIO_POS12 MMIO32(SGPIO_PORT_BASE + 0x1F0) +#define SGPIO_POS13 MMIO32(SGPIO_PORT_BASE + 0x1F4) +#define SGPIO_POS14 MMIO32(SGPIO_PORT_BASE + 0x1F8) +#define SGPIO_POS15 MMIO32(SGPIO_PORT_BASE + 0x1FC) + +/* Slice name to slice index mapping */ +#define SGPIO_SLICE_A 0 +#define SGPIO_SLICE_B 1 +#define SGPIO_SLICE_C 2 +#define SGPIO_SLICE_D 3 +#define SGPIO_SLICE_E 4 +#define SGPIO_SLICE_F 5 +#define SGPIO_SLICE_G 6 +#define SGPIO_SLICE_H 7 +#define SGPIO_SLICE_I 8 +#define SGPIO_SLICE_J 9 +#define SGPIO_SLICE_K 10 +#define SGPIO_SLICE_L 11 +#define SGPIO_SLICE_M 12 +#define SGPIO_SLICE_N 13 +#define SGPIO_SLICE_O 14 +#define SGPIO_SLICE_P 15 + +/* Mask for pattern match function of slice A */ +#define SGPIO_MASK_A MMIO32(SGPIO_PORT_BASE + 0x200) + +/* Mask for pattern match function of slice H */ +#define SGPIO_MASK_H MMIO32(SGPIO_PORT_BASE + 0x204) + +/* Mask for pattern match function of slice I */ +#define SGPIO_MASK_I MMIO32(SGPIO_PORT_BASE + 0x208) + +/* Mask for pattern match function of slice P */ +#define SGPIO_MASK_P MMIO32(SGPIO_PORT_BASE + 0x20C) + +/* GPIO input status register */ +#define SGPIO_GPIO_INREG MMIO32(SGPIO_PORT_BASE + 0x210) + +/* GPIO output control register */ +#define SGPIO_GPIO_OUTREG MMIO32(SGPIO_PORT_BASE + 0x214) + +/* GPIO OE control register */ +#define SGPIO_GPIO_OENREG MMIO32(SGPIO_PORT_BASE + 0x218) + +/* Enables the slice COUNT counter */ +#define SGPIO_CTRL_ENABLE MMIO32(SGPIO_PORT_BASE + 0x21C) + +/* Disables the slice COUNT counter */ +#define SGPIO_CTRL_DISABLE MMIO32(SGPIO_PORT_BASE + 0x220) + +/* Shift clock interrupt clear mask */ +#define SGPIO_CLR_EN_0 MMIO32(SGPIO_PORT_BASE + 0xF00) + +/* Shift clock interrupt set mask */ +#define SGPIO_SET_EN_0 MMIO32(SGPIO_PORT_BASE + 0xF04) + +/* Shift clock interrupt enable */ +#define SGPIO_ENABLE_0 MMIO32(SGPIO_PORT_BASE + 0xF08) + +/* Shift clock interrupt status */ +#define SGPIO_STATUS_0 MMIO32(SGPIO_PORT_BASE + 0xF0C) + +/* Shift clock interrupt clear status */ +#define SGPIO_CLR_STATUS_0 MMIO32(SGPIO_PORT_BASE + 0xF10) + +/* Shift clock interrupt set status */ +#define SGPIO_SET_STATUS_0 MMIO32(SGPIO_PORT_BASE + 0xF14) + +/* Exchange clock interrupt clear mask */ +#define SGPIO_CLR_EN_1 MMIO32(SGPIO_PORT_BASE + 0xF20) + +/* Exchange clock interrupt set mask */ +#define SGPIO_SET_EN_1 MMIO32(SGPIO_PORT_BASE + 0xF24) + +/* Exchange clock interrupt enable */ +#define SGPIO_ENABLE_1 MMIO32(SGPIO_PORT_BASE + 0xF28) + +/* Exchange clock interrupt status */ +#define SGPIO_STATUS_1 MMIO32(SGPIO_PORT_BASE + 0xF2C) + +/* Exchange clock interrupt clear status */ +#define SGPIO_CLR_STATUS_1 MMIO32(SGPIO_PORT_BASE + 0xF30) + +/* Exchange clock interrupt set status */ +#define SGPIO_SET_STATUS_1 MMIO32(SGPIO_PORT_BASE + 0xF34) + +/* Pattern match interrupt clear mask */ +#define SGPIO_CLR_EN_2 MMIO32(SGPIO_PORT_BASE + 0xF40) + +/* Pattern match interrupt set mask */ +#define SGPIO_SET_EN_2 MMIO32(SGPIO_PORT_BASE + 0xF44) + +/* Pattern match interrupt enable */ +#define SGPIO_ENABLE_2 MMIO32(SGPIO_PORT_BASE + 0xF48) + +/* Pattern match interrupt status */ +#define SGPIO_STATUS_2 MMIO32(SGPIO_PORT_BASE + 0xF4C) + +/* Pattern match interrupt clear status */ +#define SGPIO_CLR_STATUS_2 MMIO32(SGPIO_PORT_BASE + 0xF50) + +/* Pattern match interrupt set status */ +#define SGPIO_SET_STATUS_2 MMIO32(SGPIO_PORT_BASE + 0xF54) + +/* Input interrupt clear mask */ +#define SGPIO_CLR_EN_3 MMIO32(SGPIO_PORT_BASE + 0xF60) + +/* Input bit match interrupt set mask */ +#define SGPIO_SET_EN_3 MMIO32(SGPIO_PORT_BASE + 0xF64) + +/* Input bit match interrupt enable */ +#define SGPIO_ENABLE_3 MMIO32(SGPIO_PORT_BASE + 0xF68) + +/* Input bit match interrupt status */ +#define SGPIO_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF6C) + +/* Input bit match interrupt clear status */ +#define SGPIO_CLR_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF70) + +/* Input bit match interrupt set status */ +#define SGPIO_SET_STATUS_3 MMIO32(SGPIO_PORT_BASE + 0xF74) + +/* --- Common register fields ----------------------------------- */ +/* TODO: Generate this stuff with the gen.py script as well! */ + +#define SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFG_P_OUT_CFG_MASK \ + (0xf << SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG_P_OUT_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG_P_OUT_CFG_SHIFT) + +#define SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFG_P_OE_CFG_MASK \ + (0x7 << SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFG_P_OE_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFG_P_OE_CFG_SHIFT) + +#define SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFG_EXT_CLK_ENABLE_MASK \ + (1 << SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT) +#define SGPIO_MUX_CFG_EXT_CLK_ENABLE(x) \ + ((x) << SGPIO_MUX_CFG_EXT_CLK_ENABLE_SHIFT) + +#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE(x) \ + ((x) << SGPIO_MUX_CFG_CLK_SOURCE_PIN_MODE_SHIFT) + +#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE(x) \ + ((x) << SGPIO_MUX_CFG_CLK_SOURCE_SLICE_MODE_SHIFT) + +#define SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFG_QUALIFIER_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFG_QUALIFIER_MODE(x) \ + ((x) << SGPIO_MUX_CFG_QUALIFIER_MODE_SHIFT) + +#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFG_QUALIFIER_PIN_MODE(x) \ + ((x) << SGPIO_MUX_CFG_QUALIFIER_PIN_MODE_SHIFT) + +#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_MASK \ + (0x3 << SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE(x) \ + ((x) << SGPIO_MUX_CFG_QUALIFIER_SLICE_MODE_SHIFT) + +#define SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFG_CONCAT_ENABLE_MASK \ + (1 << SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT) +#define SGPIO_MUX_CFG_CONCAT_ENABLE(x) \ + ((x) << SGPIO_MUX_CFG_CONCAT_ENABLE_SHIFT) + +#define SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFG_CONCAT_ORDER_MASK \ + (0x3 << SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFG_CONCAT_ORDER(x) \ + ((x) << SGPIO_MUX_CFG_CONCAT_ORDER_SHIFT) + +#define SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFG_MATCH_MODE_MASK \ + (1 << SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_MATCH_MODE(x) \ + ((x) << SGPIO_SLICE_MUX_CFG_MATCH_MODE_SHIFT) + +#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_MASK \ + (1 << SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE(x) \ + ((x) << SGPIO_SLICE_MUX_CFG_CLK_CAPTURE_MODE_SHIFT) + +#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_MASK \ + (1 << SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_CLKGEN_MODE(x) \ + ((x) << SGPIO_SLICE_MUX_CFG_CLKGEN_MODE_SHIFT) + +#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_MASK \ + (1 << SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT) +#define SGPIO_SLICE_MUX_CFG_INV_OUT_CLK(x) \ + ((x) << SGPIO_SLICE_MUX_CFG_INV_OUT_CLK_SHIFT) + +#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_MASK \ + (0x3 << SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE(x) \ + ((x) << SGPIO_SLICE_MUX_CFG_DATA_CAPTURE_MODE_SHIFT) + +#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_MASK \ + (0x3 << SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFG_PARALLEL_MODE(x) \ + ((x) << SGPIO_SLICE_MUX_CFG_PARALLEL_MODE_SHIFT) + +#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_MASK \ + (1 << SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT) +#define SGPIO_SLICE_MUX_CFG_INV_QUALIFIER(x) \ + ((x) << SGPIO_SLICE_MUX_CFG_INV_QUALIFIER_SHIFT) + +#define SGPIO_POS_POS_SHIFT (0) +#define SGPIO_POS_POS_MASK (0xff << SGPIO_POS_POS_SHIFT) +#define SGPIO_POS_POS(x) ((x) << SGPIO_POS_POS_SHIFT) + +#define SGPIO_POS_POS_RESET_SHIFT (8) +#define SGPIO_POS_POS_RESET_MASK (0xff << SGPIO_POS_POS_RESET_SHIFT) +#define SGPIO_POS_POS_RESET(x) ((x) << SGPIO_POS_POS_RESET_SHIFT) + +/* --- AUTO-GENERATED STUFF FOLLOWS ----------------------------- */ + +/* --- SGPIO_OUT_MUX_CFG[0..15] values ------------------------------------ */ + +/* P_OUT_CFG: Output control of output SGPIOn */ +#define SGPIO_OUT_MUX_CFGx_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFGx_P_OUT_CFG_MASK \ + (0xf << SGPIO_OUT_MUX_CFGx_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFGx_P_OUT_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFGx_P_OUT_CFG_SHIFT) + +/* P_OE_CFG: Output enable source */ +#define SGPIO_OUT_MUX_CFGx_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFGx_P_OE_CFG_MASK \ + (0x7 << SGPIO_OUT_MUX_CFGx_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFGx_P_OE_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFGx_P_OE_CFG_SHIFT) + +/* --- SGPIO_MUX_CFG[0..15] values ---------------------------------------- */ + +/* EXT_CLK_ENABLE: Select clock signal */ +#define SGPIO_MUX_CFGx_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFGx_EXT_CLK_ENABLE \ + (1 << SGPIO_MUX_CFGx_EXT_CLK_ENABLE_SHIFT) + +/* CLK_SOURCE_PIN_MODE: Select source clock pin */ +#define SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_MASK \ + (0x3 << SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE(x) \ + ((x) << SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_SHIFT) + +/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ +#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_MASK \ + (0x3 << SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE(x) \ + ((x) << SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT) + +/* QUALIFIER_MODE: Select qualifier mode */ +#define SGPIO_MUX_CFGx_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFGx_QUALIFIER_MODE_MASK \ + (0x3 << SGPIO_MUX_CFGx_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFGx_QUALIFIER_MODE(x) \ + ((x) << SGPIO_MUX_CFGx_QUALIFIER_MODE_SHIFT) + +/* QUALIFIER_PIN_MODE: Select qualifier pin */ +#define SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_MASK \ + (0x3 << SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE(x) \ + ((x) << SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_SHIFT) + +/* QUALIFIER_SLICE_MODE: Select qualifier slice */ +#define SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE_MASK \ + (0x3 << SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE(x) \ + ((x) << SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_SHIFT) + +/* CONCAT_ENABLE: Enable concatenation */ +#define SGPIO_MUX_CFGx_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFGx_CONCAT_ENABLE \ + (1 << SGPIO_MUX_CFGx_CONCAT_ENABLE_SHIFT) + +/* CONCAT_ORDER: Select concatenation order */ +#define SGPIO_MUX_CFGx_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFGx_CONCAT_ORDER_MASK \ + (0x3 << SGPIO_MUX_CFGx_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFGx_CONCAT_ORDER(x) \ + ((x) << SGPIO_MUX_CFGx_CONCAT_ORDER_SHIFT) + +/* --- SGPIO_SLICE_MUX_CFG[0..15] values ---------------------------------- */ + +/* MATCH_MODE: Match mode */ +#define SGPIO_SLICE_MUX_CFGx_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFGx_MATCH_MODE \ + (1 << SGPIO_SLICE_MUX_CFG0_MATCH_MODE_SHIFT) + +/* CLK_CAPTURE_MODE: Capture clock mode */ +#define SGPIO_SLICE_MUX_CFGx_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFGx_CLK_CAPTURE_MODE \ + (1 << SGPIO_SLICE_MUX_CFGx_CLK_CAPTURE_MODE_SHIFT) + +/* CLKGEN_MODE: Clock generation mode */ +#define SGPIO_SLICE_MUX_CFGx_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFGx_CLKGEN_MODE \ + (1 << SGPIO_SLICE_MUX_CFGx_CLKGEN_MODE_SHIFT) + +/* INV_OUT_CLK: Invert output clock */ +#define SGPIO_SLICE_MUX_CFGx_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFGx_INV_OUT_CLK \ + (1 << SGPIO_SLICE_MUX_CFGx_INV_OUT_CLK_SHIFT) + +/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ +#define SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_MASK \ + (0x3 << SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE(x) \ + ((x) << SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_SHIFT) + +/* PARALLEL_MODE: Parallel mode */ +#define SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_MASK \ + (0x3 << SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE(x) \ + ((x) << SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_SHIFT) + +/* INV_QUALIFIER: Inversion qualifier */ +#define SGPIO_SLICE_MUX_CFGx_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFGx_INV_QUALIFIER \ + (1 << SGPIO_SLICE_MUX_CFGx_INV_QUALIFIER_SHIFT) + + +/* --- SGPIO_POS[0..15] values -------------------------------------------- */ + +/* POS: Each time COUNT reaches 0x0 POS counts down */ +#define SGPIO_POSx_POS_SHIFT (0) +#define SGPIO_POSx_POS_MASK (0xff << SGPIO_POSx_POS_SHIFT) +#define SGPIO_POSx_POS(x) ((x) << SGPIO_POSx_POS_SHIFT) + +/* POS_RESET: Reload value for POS after POS reaches 0x0 */ +#define SGPIO_POSx_POS_RESET_SHIFT (8) +#define SGPIO_POSx_POS_RESET_MASK (0xff << SGPIO_POSx_POS_RESET_SHIFT) +#define SGPIO_POSx_POS_RESET(x) ((x) << SGPIO_POSx_POS_RESET_SHIFT) + + +/* SGPIO structure for faster/better code generation (especially when optimized + * with -O2/-O3) + */ +/* This structure is compliant with LPC43xx User Manual UM10503 Rev.1.4 - 3 + * September 2012 + */ +typedef struct { + /* Pin multiplexer configuration registers. RW */ + volatile uint32_t OUT_MUX_CFG[16]; + /* SGPIO multiplexer configuration registers. RW */ + volatile uint32_t SGPIO_MUX_CFG[16]; + /* Slice multiplexer configuration registers. RW */ + volatile uint32_t SLICE_MUX_CFG[16]; + /* Slice data registers. RW */ + volatile uint32_t REG[16]; + /* Slice data shadow registers. Each time POS reaches 0x0 the contents + * of REG_SS is exchanged with the content of REG. RW + */ + volatile uint32_t REG_SS[16]; + /* Reload registers. Counter reload value; loaded when COUNT reaches + * 0x0 RW + */ + volatile uint32_t PRESET[16]; + /* Down counter registers, counts down each shift clock cycle. RW */ + volatile uint32_t COUNT[16]; + /* Position registers. POS Each time COUNT reaches 0x0 POS counts down. + * POS_RESET Reload value for POS after POS reaches 0x0. RW + */ + volatile uint32_t POS[16]; + /* Slice A mask register. Mask for pattern match function of slice A. + * RW + */ + volatile uint32_t MASK_A; + /* Slice H mask register. Mask for pattern match function of slice H. + * RW + */ + volatile uint32_t MASK_H; + /* Slice I mask register. Mask for pattern match function of slice I. + * RW + */ + volatile uint32_t MASK_I; + /* Slice P mask register. Mask for pattern match function of slice P. + * RW + */ + volatile uint32_t MASK_P; + /* GPIO input status register. R */ + volatile uint32_t GPIO_INREG; + /* GPIO output control register. RW */ + volatile uint32_t GPIO_OUTREG; + /* GPIO output enable register. RW */ + volatile uint32_t GPIO_OENREG; + /* Slice count enable register. RW */ + volatile uint32_t CTRL_ENABLE; + /* Slice count disable register. RW */ + volatile uint32_t CTRL_DISABLE; + volatile uint32_t RES0[823]; + /* Shift clock interrupt clear mask register. W */ + volatile uint32_t CLR_EN_0; + /* Shift clock interrupt set mask register. W */ + volatile uint32_t SET_EN_0; + /* Shift clock interrupt enable register. R */ + volatile uint32_t ENABLE_0; + /* Shift clock interrupt status register. R */ + volatile uint32_t STATUS_0; + /* Shift clock interrupt clear status register. W */ + volatile uint32_t CLR_STATUS_0; + /* Shift clock interrupt set status register. W */ + volatile uint32_t SET_STATUS_0; + volatile uint32_t RES1[2]; + /* Exchange clock interrupt clear mask register. W */ + volatile uint32_t CLR_EN_1; + /* Exchange clock interrupt set mask register. W */ + volatile uint32_t SET_EN_1; + /* Exchange clock interrupt enable. R */ + volatile uint32_t ENABLE_1; + /* Exchange clock interrupt status register. R */ + volatile uint32_t STATUS_1; + /* Exchange clock interrupt clear status register. W */ + volatile uint32_t CLR_STATUS_1; + /* Exchange clock interrupt set status register. W */ + volatile uint32_t SET_STATUS_1; + volatile uint32_t RES2[2]; + /* Pattern match interrupt clear mask register. W */ + volatile uint32_t CLR_EN_2; + /* Pattern match interrupt set mask register. W */ + volatile uint32_t SET_EN_2; + /* Pattern match interrupt enable register. R */ + volatile uint32_t ENABLE_2; + /* Pattern match interrupt status register. R */ + volatile uint32_t STATUS_2; + /* Pattern match interrupt clear status register. W */ + volatile uint32_t CLR_STATUS_2; + /* Pattern match interrupt set status register. W */ + volatile uint32_t SET_STATUS_2; + volatile uint32_t RES3[2]; + /* Input interrupt clear mask register. W */ + volatile uint32_t CLR_EN_3; + /* Input bit match interrupt set mask register. W */ + volatile uint32_t SET_EN_3; + /* Input bit match interrupt enable register. R */ + volatile uint32_t ENABLE_3; + /* Input bit match interrupt status register. R */ + volatile uint32_t STATUS_3; + /* Input bit match interrupt clear status register. W */ + volatile uint32_t CLR_STATUS_3; + /* Input bit match interrupt set status register. W */ + volatile uint32_t SET_STATUS_3; +} sgpio_t; + +/* Global access to SGPIO structure */ +#define SGPIO ((sgpio_t *)SGPIO_PORT_BASE) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/ssp.h b/libopencm3/include/libopencm3/lpc43xx/ssp.h new file mode 100644 index 0000000..a336652 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/ssp.h @@ -0,0 +1,209 @@ +/** @defgroup ssp_defines Synchronous Serial Port + +@brief Defined Constants and Types for the LPC43xx Synchronous Serial +Port + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* +* This file is part of the libopencm3 project. +* +* Copyright (C) 2012 Michael Ossmann +* +* This library is free software: you can redistribute it and/or modify +* it under the terms of the GNU Lesser General Public License as published by +* the Free Software Foundation, either version 3 of the License, or +* (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public License +* along with this library. If not, see . +*/ + +#ifndef LPC43XX_SSP_H +#define LPC43XX_SSP_H + +/**@{*/ + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* SSP port base addresses (for convenience) */ +#define SSP0 SSP0_BASE +#define SSP1 SSP1_BASE + + +/* --- SSP registers ------------------------------------------------------- */ + +/* Control Register 0 */ +#define SSP_CR0(port) MMIO32(port + 0x000) +#define SSP0_CR0 SSP_CR0(SSP0) +#define SSP1_CR0 SSP_CR0(SSP1) + +/* Control Register 1 */ +#define SSP_CR1(port) MMIO32(port + 0x004) +#define SSP0_CR1 SSP_CR1(SSP0) +#define SSP1_CR1 SSP_CR1(SSP1) + +/* Data Register */ +#define SSP_DR(port) MMIO32(port + 0x008) +#define SSP0_DR SSP_DR(SSP0) +#define SSP1_DR SSP_DR(SSP1) + +/* Status Register */ +#define SSP_SR(port) MMIO32(port + 0x00C) +#define SSP0_SR SSP_SR(SSP0) +#define SSP1_SR SSP_SR(SSP1) + +#define SSP_SR_TFE BIT0 +#define SSP_SR_TNF BIT1 +#define SSP_SR_RNE BIT2 +#define SSP_SR_RFF BIT3 +#define SSP_SR_BSY BIT4 + +/* Clock Prescale Register */ +#define SSP_CPSR(port) MMIO32(port + 0x010) +#define SSP0_CPSR SSP_CPSR(SSP0) +#define SSP1_CPSR SSP_CPSR(SSP1) + +/* Interrupt Mask Set and Clear Register */ +#define SSP_IMSC(port) MMIO32(port + 0x014) +#define SSP0_IMSC SSP_IMSC(SSP0) +#define SSP1_IMSC SSP_IMSC(SSP1) + +/* Raw Interrupt Status Register */ +#define SSP_RIS(port) MMIO32(port + 0x018) +#define SSP0_RIS SSP_RIS(SSP0) +#define SSP1_RIS SSP_RIS(SSP1) + +/* Masked Interrupt Status Register */ +#define SSP_MIS(port) MMIO32(port + 0x01C) +#define SSP0_MIS SSP_MIS(SSP0) +#define SSP1_MIS SSP_MIS(SSP1) + +/* SSPICR Interrupt Clear Register */ +#define SSP_ICR(port) MMIO32(port + 0x020) +#define SSP0_ICR SSP_ICR(SSP0) +#define SSP1_ICR SSP_ICR(SSP1) + +/* SSP1 DMA control register */ +#define SSP_DMACR(port) MMIO32(port + 0x024) +#define SSP0_DMACR SSP_DMACR(SSP0) +#define SSP1_DMACR SSP_DMACR(SSP1) + +/* RXDMAE: Receive DMA enable */ +#define SSP_DMACR_RXDMAE 0x1 + +/* RXDMAE: Transmit DMA enable */ +#define SSP_DMACR_TXDMAE 0x2 + +typedef enum { + SSP0_NUM = 0x0, + SSP1_NUM = 0x1 +} ssp_num_t; + +/* + * SSP Control Register 0 + */ +/* SSP Data Size Bits 0 to 3 */ +typedef enum { + SSP_DATA_4BITS = 0x3, + SSP_DATA_5BITS = 0x4, + SSP_DATA_6BITS = 0x5, + SSP_DATA_7BITS = 0x6, + SSP_DATA_8BITS = 0x7, + SSP_DATA_9BITS = 0x8, + SSP_DATA_10BITS = 0x9, + SSP_DATA_11BITS = 0xA, + SSP_DATA_12BITS = 0xB, + SSP_DATA_13BITS = 0xC, + SSP_DATA_14BITS = 0xD, + SSP_DATA_15BITS = 0xE, + SSP_DATA_16BITS = 0xF +} ssp_datasize_t; + +/* SSP Frame Format/Type Bits 4 & 5 */ +typedef enum { + SSP_FRAME_SPI = 0x00, + SSP_FRAME_TI = BIT4, + SSP_FRAM_MICROWIRE = BIT5 +} ssp_frame_format_t; + +/* Clock Out Polarity / Clock Out Phase Bits Bits 6 & 7 */ +typedef enum { + SSP_CPOL_0_CPHA_0 = 0x0, + SSP_CPOL_1_CPHA_0 = BIT6, + SSP_CPOL_0_CPHA_1 = BIT7, + SSP_CPOL_1_CPHA_1 = (BIT6|BIT7) +} ssp_cpol_cpha_t; + +/* + * SSP Control Register 1 + */ +/* SSP Mode Bit0 */ +typedef enum { + SSP_MODE_NORMAL = 0x0, + SSP_MODE_LOOPBACK = BIT0 +} ssp_mode_t; + +/* SSP Enable Bit1 */ +#define SSP_ENABLE BIT1 + +/* SSP Master/Slave Mode Bit2 */ +typedef enum { + SSP_MASTER = 0x0, + SSP_SLAVE = BIT2 +} ssp_master_slave_t; + +/* +* SSP Slave Output Disable Bit3 +* Slave Output Disable. This bit is relevant only in slave mode +* (MS = 1). If it is 1, this blocks this SSP controller from driving the +* transmit data line (MISO). +*/ +typedef enum { + SSP_SLAVE_OUT_ENABLE = 0x0, + SSP_SLAVE_OUT_DISABLE = BIT3 +} ssp_slave_option_t; /* This option is relevant only in slave mode */ + +BEGIN_DECLS + +void ssp_disable(ssp_num_t ssp_num); + +/* + * SSP Init + * clk_prescale shall be in range 2 to 254 (even number only). + * Clock computation: PCLK / (CPSDVSR * [SCR+1]) => CPSDVSR=clk_prescale, + * SCR=serial_clock_rate + */ +void ssp_init(ssp_num_t ssp_num, + ssp_datasize_t data_size, + ssp_frame_format_t frame_format, + ssp_cpol_cpha_t cpol_cpha_format, + uint8_t serial_clock_rate, + uint8_t clk_prescale, + ssp_mode_t mode, + ssp_master_slave_t master_slave, + ssp_slave_option_t slave_option); + +uint16_t ssp_transfer(ssp_num_t ssp_num, uint16_t data); + +END_DECLS + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/timer.h b/libopencm3/include/libopencm3/lpc43xx/timer.h new file mode 100644 index 0000000..2c691e7 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/timer.h @@ -0,0 +1,270 @@ +/** @defgroup timer_defines Timer + +@brief Defined Constants and Types for the LPC43xx timer + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC43XX_TIMER_H +#define LPC43XX_TIMER_H + +/**@{*/ + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* Timer base addresses */ +#define TIMER0 TIMER0_BASE +#define TIMER1 TIMER1_BASE +#define TIMER2 TIMER2_BASE +#define TIMER3 TIMER3_BASE + + +/* --- Timer registers ----------------------------------------------------- */ + +/* Interrupt Register */ +#define TIMER_IR(timer) MMIO32(timer + 0x000) +#define TIMER0_IR TIMER_IR(TIMER0) +#define TIMER1_IR TIMER_IR(TIMER1) +#define TIMER2_IR TIMER_IR(TIMER2) +#define TIMER3_IR TIMER_IR(TIMER3) + +/* Timer Control Register */ +#define TIMER_TCR(timer) MMIO32(timer + 0x004) +#define TIMER0_TCR TIMER_TCR(TIMER0) +#define TIMER1_TCR TIMER_TCR(TIMER1) +#define TIMER2_TCR TIMER_TCR(TIMER2) +#define TIMER3_TCR TIMER_TCR(TIMER3) + +/* Timer Counter */ +#define TIMER_TC(timer) MMIO32(timer + 0x008) +#define TIMER0_TC TIMER_TC(TIMER0) +#define TIMER1_TC TIMER_TC(TIMER1) +#define TIMER2_TC TIMER_TC(TIMER2) +#define TIMER3_TC TIMER_TC(TIMER3) + +/* Prescale Register */ +#define TIMER_PR(timer) MMIO32(timer + 0x00C) +#define TIMER0_PR TIMER_PR(TIMER0) +#define TIMER1_PR TIMER_PR(TIMER1) +#define TIMER2_PR TIMER_PR(TIMER2) +#define TIMER3_PR TIMER_PR(TIMER3) + +/* Prescale Counter */ +#define TIMER_PC(timer) MMIO32(timer + 0x010) +#define TIMER0_PC TIMER_PC(TIMER0) +#define TIMER1_PC TIMER_PC(TIMER1) +#define TIMER2_PC TIMER_PC(TIMER2) +#define TIMER3_PC TIMER_PC(TIMER3) + +/* Match Control Register */ +#define TIMER_MCR(timer) MMIO32(timer + 0x014) +#define TIMER0_MCR TIMER_MCR(TIMER0) +#define TIMER1_MCR TIMER_MCR(TIMER1) +#define TIMER2_MCR TIMER_MCR(TIMER2) +#define TIMER3_MCR TIMER_MCR(TIMER3) + +/* Match Register 0 */ +#define TIMER_MR0(timer) MMIO32(timer + 0x018) +#define TIMER0_MR0 TIMER_MR0(TIMER0) +#define TIMER1_MR0 TIMER_MR0(TIMER1) +#define TIMER2_MR0 TIMER_MR0(TIMER2) +#define TIMER3_MR0 TIMER_MR0(TIMER3) + +/* Match Register 1 */ +#define TIMER_MR1(timer) MMIO32(timer + 0x01C) +#define TIMER0_MR1 TIMER_MR1(TIMER0) +#define TIMER1_MR1 TIMER_MR1(TIMER1) +#define TIMER2_MR1 TIMER_MR1(TIMER2) +#define TIMER3_MR1 TIMER_MR1(TIMER3) + +/* Match Register 2 */ +#define TIMER_MR2(timer) MMIO32(timer + 0x020) +#define TIMER0_MR2 TIMER_MR2(TIMER0) +#define TIMER1_MR2 TIMER_MR2(TIMER1) +#define TIMER2_MR2 TIMER_MR2(TIMER2) +#define TIMER3_MR2 TIMER_MR2(TIMER3) + +/* Match Register 3 */ +#define TIMER_MR3(timer) MMIO32(timer + 0x024) +#define TIMER0_MR3 TIMER_MR3(TIMER0) +#define TIMER1_MR3 TIMER_MR3(TIMER1) +#define TIMER2_MR3 TIMER_MR3(TIMER2) +#define TIMER3_MR3 TIMER_MR3(TIMER3) + +/* Capture Control Register */ +#define TIMER_CCR(timer) MMIO32(timer + 0x028) +#define TIMER0_CCR TIMER_CCR(TIMER0) +#define TIMER1_CCR TIMER_CCR(TIMER1) +#define TIMER2_CCR TIMER_CCR(TIMER2) +#define TIMER3_CCR TIMER_CCR(TIMER3) + +/* Capture Register 0 */ +#define TIMER_CR0(timer) MMIO32(timer + 0x02C) +#define TIMER0_CR0 TIMER_CR0(TIMER0) +#define TIMER1_CR0 TIMER_CR0(TIMER1) +#define TIMER2_CR0 TIMER_CR0(TIMER2) +#define TIMER3_CR0 TIMER_CR0(TIMER3) + +/* Capture Register 1 */ +#define TIMER_CR1(timer) MMIO32(timer + 0x030) +#define TIMER0_CR1 TIMER_CR1(TIMER0) +#define TIMER1_CR1 TIMER_CR1(TIMER1) +#define TIMER2_CR1 TIMER_CR1(TIMER2) +#define TIMER3_CR1 TIMER_CR1(TIMER3) + +/* Capture Register 2 */ +#define TIMER_CR2(timer) MMIO32(timer + 0x034) +#define TIMER0_CR2 TIMER_CR2(TIMER0) +#define TIMER1_CR2 TIMER_CR2(TIMER1) +#define TIMER2_CR2 TIMER_CR2(TIMER2) +#define TIMER3_CR2 TIMER_CR2(TIMER3) + +/* Capture Register 3 */ +#define TIMER_CR3(timer) MMIO32(timer + 0x038) +#define TIMER0_CR3 TIMER_CR3(TIMER0) +#define TIMER1_CR3 TIMER_CR3(TIMER1) +#define TIMER2_CR3 TIMER_CR3(TIMER2) +#define TIMER3_CR3 TIMER_CR3(TIMER3) + +/* External Match Register */ +#define TIMER_EMR(timer) MMIO32(timer + 0x03C) +#define TIMER0_EMR TIMER_EMR(TIMER0) +#define TIMER1_EMR TIMER_EMR(TIMER1) +#define TIMER2_EMR TIMER_EMR(TIMER2) +#define TIMER3_EMR TIMER_EMR(TIMER3) + +/* Count Control Register */ +#define TIMER_CTCR(timer) MMIO32(timer + 0x070) +#define TIMER0_CTCR TIMER_CTCR(TIMER0) +#define TIMER1_CTCR TIMER_CTCR(TIMER1) +#define TIMER2_CTCR TIMER_CTCR(TIMER2) +#define TIMER3_CTCR TIMER_CTCR(TIMER3) + +/* --- TIMERx_IR values ----------------------------------------------------- */ + +#define TIMER_IR_MR0INT (1 << 0) +#define TIMER_IR_MR1INT (1 << 1) +#define TIMER_IR_MR2INT (1 << 2) +#define TIMER_IR_MR3INT (1 << 3) +#define TIMER_IR_CR0INT (1 << 4) +#define TIMER_IR_CR1INT (1 << 5) +#define TIMER_IR_CR2INT (1 << 6) +#define TIMER_IR_CR3INT (1 << 7) + +/* --- TIMERx_TCR values --------------------------------------------------- */ + +#define TIMER_TCR_CEN (1 << 0) +#define TIMER_TCR_CRST (1 << 1) + +/* --- TIMERx_MCR values --------------------------------------------------- */ + +#define TIMER_MCR_MR0I (1 << 0) +#define TIMER_MCR_MR0R (1 << 1) +#define TIMER_MCR_MR0S (1 << 2) +#define TIMER_MCR_MR1I (1 << 3) +#define TIMER_MCR_MR1R (1 << 4) +#define TIMER_MCR_MR1S (1 << 5) +#define TIMER_MCR_MR2I (1 << 6) +#define TIMER_MCR_MR2R (1 << 7) +#define TIMER_MCR_MR2S (1 << 8) +#define TIMER_MCR_MR3I (1 << 9) +#define TIMER_MCR_MR3R (1 << 10) +#define TIMER_MCR_MR3S (1 << 11) + +/* --- TIMERx_MCR values --------------------------------------------------- */ + +#define TIMER_CCR_CAP0RE (1 << 0) +#define TIMER_CCR_CAP0FE (1 << 1) +#define TIMER_CCR_CAP0I (1 << 2) +#define TIMER_CCR_CAP1RE (1 << 3) +#define TIMER_CCR_CAP1FE (1 << 4) +#define TIMER_CCR_CAP1I (1 << 5) +#define TIMER_CCR_CAP2RE (1 << 6) +#define TIMER_CCR_CAP2FE (1 << 7) +#define TIMER_CCR_CAP2I (1 << 8) +#define TIMER_CCR_CAP3RE (1 << 9) +#define TIMER_CCR_CAP3FE (1 << 10) +#define TIMER_CCR_CAP3I (1 << 11) + +/* --- TIMERx_EMR values --------------------------------------------------- */ + +#define TIMER_EMR_EM0 (1 << 0) +#define TIMER_EMR_EM1 (1 << 1) +#define TIMER_EMR_EM2 (1 << 2) +#define TIMER_EMR_EM3 (1 << 3) +#define TIMER_EMR_EMC0_SHIFT 4 +#define TIMER_EMR_EMC0_MASK (0x3 << TIMER_EMR_EMC0_SHIFT) +#define TIMER_EMR_EMC1_SHIFT 6 +#define TIMER_EMR_EMC1_MASK (0x3 << TIMER_EMR_EMC1_SHIFT) +#define TIMER_EMR_EMC2_SHIFT 8 +#define TIMER_EMR_EMC2_MASK (0x3 << TIMER_EMR_EMC2_SHIFT) +#define TIMER_EMR_EMC3_SHIFT 10 +#define TIMER_EMR_EMC3_MASK (0x3 << TIMER_EMR_EMC3_SHIFT) + +#define TIMER_EMR_EMC_NOTHING 0x0 +#define TIMER_EMR_EMC_CLEAR 0x1 +#define TIMER_EMR_EMC_SET 0x2 +#define TIMER_EMR_EMC_TOGGLE 0x3 + +/* --- TIMERx_CTCR values -------------------------------------------------- */ + +#define TIMER_CTCR_MODE_TIMER (0x0 << 0) +#define TIMER_CTCR_MODE_COUNTER_RISING (0x1 << 0) +#define TIMER_CTCR_MODE_COUNTER_FALLING (0x2 << 0) +#define TIMER_CTCR_MODE_COUNTER_BOTH (0x3 << 0) +#define TIMER_CTCR_MODE_MASK (0x3 << 0) + +#define TIMER_CTCR_CINSEL_CAPN_0 (0x0 << 2) +#define TIMER_CTCR_CINSEL_CAPN_1 (0x1 << 2) +#define TIMER_CTCR_CINSEL_CAPN_2 (0x2 << 2) +#define TIMER_CTCR_CINSEL_CAPN_3 (0x3 << 2) +#define TIMER_CTCR_CINSEL_MASK (0x3 << 2) + +/* --- TIMER function prototypes ------------------------------------------- */ + +BEGIN_DECLS + +void timer_reset(uint32_t timer_peripheral); +void timer_enable_counter(uint32_t timer_peripheral); +void timer_disable_counter(uint32_t timer_peripheral); +uint32_t timer_get_counter(uint32_t timer_peripheral); +void timer_set_counter(uint32_t timer_peripheral, uint32_t count); +uint32_t timer_get_prescaler(uint32_t timer_peripheral); +void timer_set_prescaler(uint32_t timer_peripheral, uint32_t prescaler); +void timer_set_mode(uint32_t timer_peripheral, uint32_t mode); +void timer_set_count_input(uint32_t timer_peripheral, uint32_t input); + +END_DECLS + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/uart.h b/libopencm3/include/libopencm3/lpc43xx/uart.h new file mode 100644 index 0000000..28830e3 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/uart.h @@ -0,0 +1,438 @@ +/* +* This file is part of the libopencm3 project. +* +* Copyright (C) 2012 Benjamin Vernoux +* +* This library is free software: you can redistribute it and/or modify +* it under the terms of the GNU Lesser General Public License as published by +* the Free Software Foundation, either version 3 of the License, or +* (at your option) any later version. +* +* This library is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU Lesser General Public License for more details. +* +* You should have received a copy of the GNU Lesser General Public License +* along with this library. If not, see . +*/ + +#ifndef LPC43XX_UART_H +#define LPC43XX_UART_H + +#include +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* UART port base addresses (for convenience) */ +#define UART0 USART0_BASE /* APB0 */ +#define UART1 UART1_BASE /* APB0 */ +#define UART2 USART2_BASE /* APB2 */ +#define UART3 USART3_BASE /* APB2 */ + +/* --- UART registers ------------------------------------------------------- */ + +/* Receiver Buffer Register (DLAB=0) Read Only */ +#define UART_RBR(port) MMIO32(port + 0x000) /* 8bits */ + +/* Transmitter Holding Register (DLAB=0) Write Only */ +#define UART_THR(port) MMIO32(port + 0x000) /* 8bits */ + +/* Divisor Latch LSB Register (DLAB=1) */ +#define UART_DLL(port) MMIO32(port + 0x000) /* 8bits */ + +/* Divisor Latch MSB Register (DLAB=1) */ +#define UART_DLM(port) MMIO32(port + 0x004) /* 8bits */ + +/* Interrupt Enable Register (DLAB=0) */ +#define UART_IER(port) MMIO32(port + 0x004) + +/* Interrupt ID Register Read Only */ +#define UART_IIR(port) MMIO32(port + 0x008) + +/* FIFO Control Register Write Only */ +#define UART_FCR(port) MMIO32(port + 0x008) + +/* Line Control Register */ +#define UART_LCR(port) MMIO32(port + 0x00C) + +/* MCR only for UART1 */ + +/* Line Status Register */ +#define UART_LSR(port) MMIO32(port + 0x014) + +/* Auto Baud Control Register */ +#define UART_ACR(port) MMIO32(port + 0x020) + +/* IrDA Control Register only for UART0/2/3 */ +#define UART_ICR(port) MMIO32(port + 0x024) + +/* Fractional Divider Register */ +#define UART_FDR(port) MMIO32(port + 0x028) + +/* Oversampling Register only for UART0/2/3 */ +#define UART_OSR(port) MMIO32(port + 0x02C) + +/* Half-Duplex enable Register only for UART0/2/3 */ +#define UART_HDEN(port) MMIO32(port + 0x040) + +/* Smart card Interface Register Only for UART0/2/3 */ +#define UART_SCICTRL(port) MMIO32(port + 0x048) + +/* RS-485/EIA-485 Control Register */ +#define UART_RS485CTRL(port) MMIO32(port + 0x04C) + +/* RS-485/EIA-485 Address Match Register */ +#define UART_RS485ADRMATCH(port) MMIO32(port + 0x050) + +/* RS-485/EIA-485 Direction Control Delay Register */ +#define UART_RS485DLY(port) MMIO32(port + 0x054) + +/* Synchronous Mode Control Register only for UART0/2/3 */ +#define UART_SYNCCTRL(port) MMIO32(port + 0x058) + +/* Transmit Enable Register */ +#define UART_TER(port) MMIO32(port + 0x05C) + +/* --------------------- BIT DEFINITIONS ----------------------------------- */ +/*********************************************************************** +* Macro defines for Macro defines for UARTn Receiver Buffer Register +**********************************************************************/ +/* UART Received Buffer mask bit (8 bits) */ +#define UART_RBR_MASKBIT ((uint8_t)0xFF) + +/*********************************************************************** +* Macro defines for Macro defines for UARTn Transmit Holding Register +**********************************************************************/ +/* UART Transmit Holding mask bit (8 bits) */ +#define UART_THR_MASKBIT ((uint8_t)0xFF) + +/*********************************************************************** +* Macro defines for Macro defines for UARTn Divisor Latch LSB register +**********************************************************************/ +/* Macro for loading least significant halfs of divisors */ +#define UART_LOAD_DLL(div) ((div) & 0xFF) + +/* Divisor latch LSB bit mask */ +#define UART_DLL_MASKBIT ((uint8_t)0xFF) + +/*********************************************************************** +* Macro defines for Macro defines for UARTn Divisor Latch MSB register +**********************************************************************/ +/* Divisor latch MSB bit mask */ +#define UART_DLM_MASKBIT ((uint8_t)0xFF) + +/* Macro for loading most significant halfs of divisors */ +#define UART_LOAD_DLM(div) (((div) >> 8) & 0xFF) + +/*********************************************************************** +* Macro defines for Macro defines for UART interrupt enable register +**********************************************************************/ +/* RBR Interrupt enable*/ +#define UART_IER_RBRINT_EN (1 << 0) +/* THR Interrupt enable*/ +#define UART_IER_THREINT_EN (1 << 1) +/* RX line status interrupt enable*/ +#define UART_IER_RLSINT_EN (1 << 2) +/* Modem status interrupt enable */ +#define UART1_IER_MSINT_EN (1 << 3) +/* CTS1 signal transition interrupt enable */ +#define UART1_IER_CTSINT_EN (1 << 7) +/* Enables the end of auto-baud interrupt */ +#define UART_IER_ABEOINT_EN (1 << 8) +/* Enables the auto-baud time-out interrupt */ +#define UART_IER_ABTOINT_EN (1 << 9) +/* UART interrupt enable register bit mask */ +#define UART_IER_BITMASK ((uint32_t)(0x307)) +/* UART1 interrupt enable register bit mask */ +#define UART1_IER_BITMASK ((uint32_t)(0x38F)) + +/********************************************************************** +* Macro defines for Macro defines for UART interrupt identification register +**********************************************************************/ + +/* Interrupt Status - Active low */ +#define UART_IIR_INTSTAT_PEND (1 << 0) +/* Interrupt identification: Modem interrupt*/ +#define UART1_IIR_INTID_MODEM (0 << 1) +/* Interrupt identification: THRE interrupt*/ +#define UART_IIR_INTID_THRE (1 << 1) +/* Interrupt identification: Receive data available*/ +#define UART_IIR_INTID_RDA (2 << 1) +/* Interrupt identification: Receive line status*/ +#define UART_IIR_INTID_RLS (3 << 1) +/* Interrupt identification: Character time-out indicator*/ +#define UART_IIR_INTID_CTI (6 << 1) +/* Interrupt identification: Interrupt ID mask */ +#define UART_IIR_INTID_MASK (7 << 1) +/* These bits are equivalent to UnFCR[0] */ +#define UART_IIR_FIFO_EN (3 << 6) +/* End of auto-baud interrupt */ +#define UART_IIR_ABEO_INT (1 << 8) +/* Auto-baud time-out interrupt */ +#define UART_IIR_ABTO_INT (1 << 9) +/* UART interrupt identification register bit mask */ +#define UART_IIR_BITMASK ((uint32_t)(0x3CF)) + +/********************************************************************** +* Macro defines for Macro defines for UART FIFO control register +**********************************************************************/ +/* UART FIFO enable */ +#define UART_FCR_FIFO_EN (1 << 0) +/* UART FIFO RX reset */ +#define UART_FCR_RX_RS (1 << 1) +/* UART FIFO TX reset */ +#define UART_FCR_TX_RS (1 << 2) +/* UART DMA mode selection */ +#define UART_FCR_DMAMODE_SEL (1 << 3) +/* UART FIFO trigger level 0: 1 character */ +#define UART_FCR_TRG_LEV0 (0 << 6) +/* UART FIFO trigger level 1: 4 character */ +#define UART_FCR_TRG_LEV1 (1 << 6) +/* UART FIFO trigger level 2: 8 character */ +#define UART_FCR_TRG_LEV2 (2 << 6) +/* UART FIFO trigger level 3: 14 character */ +#define UART_FCR_TRG_LEV3 (3 << 6) +/* UART FIFO control bit mask */ +#define UART_FCR_BITMASK ((uint8_t)(0xCF)) +#define UART_TX_FIFO_SIZE (16) + +/********************************************************************** +* Macro defines for Macro defines for UART line control register +**********************************************************************/ +/* UART 5 bit data mode */ +#define UART_LCR_WLEN5 (0 << 0) +/* UART 6 bit data mode */ +#define UART_LCR_WLEN6 (1 << 0) +/* UART 7 bit data mode */ +#define UART_LCR_WLEN7 (2 << 0) +/* UART 8 bit data mode */ +#define UART_LCR_WLEN8 (3 << 0) +/* UART One Stop Bits */ +#define UART_LCR_ONE_STOPBIT (0 << 2) +/* UART Two Stop Bits */ +#define UART_LCR_TWO_STOPBIT (1 << 2) + +/* UART Parity Disabled / No Parity */ +#define UART_LCR_NO_PARITY (0 << 3) +/* UART Parity Enable */ +#define UART_LCR_PARITY_EN (1 << 3) +/* UART Odd Parity Select */ +#define UART_LCR_PARITY_ODD (0 << 4) +/* UART Even Parity Select */ +#define UART_LCR_PARITY_EVEN (1 << 4) +/* UART force 1 stick parity */ +#define UART_LCR_PARITY_SP_1 (1 << 5) +/* UART force 0 stick parity */ +#define UART_LCR_PARITY_SP_0 ((1 << 5) | (1 << 4)) +/* UART Transmission Break enable */ +#define UART_LCR_BREAK_EN (1 << 6) +/* UART Divisor Latches Access bit enable */ +#define UART_LCR_DLAB_EN (1 << 7) +/* UART line control bit mask */ +#define UART_LCR_BITMASK ((uint8_t)(0xFF)) + +/********************************************************************** +* Macro defines for Macro defines for UART line status register +**********************************************************************/ +/* Line status register: Receive data ready */ +#define UART_LSR_RDR (1 << 0) +/* Line status register: Overrun error */ +#define UART_LSR_OE (1 << 1) +/* Line status register: Parity error */ +#define UART_LSR_PE (1 << 2) +/* Line status register: Framing error */ +#define UART_LSR_FE (1 << 3) +/* Line status register: Break interrupt */ +#define UART_LSR_BI (1 << 4) +/* Line status register: Transmit holding register empty */ +#define UART_LSR_THRE (1 << 5) +/* Line status register: Transmitter empty */ +#define UART_LSR_TEMT (1 << 6) +/* Error in RX FIFO */ +#define UART_LSR_RXFE (1 << 7) +/* UART Line status bit mask */ +#define UART_LSR_BITMASK ((uint8_t)(0xFF)) +#define UART_LSR_ERROR_MASK \ + (UART_LSR_OE | UART_LSR_PE | UART_LSR_FE | UART_LSR_BI | UART_LSR_RXFE) + +/********************************************************************** +* Macro defines for Macro defines for UART Scratch Pad Register +**********************************************************************/ + +/* UART Scratch Pad bit mask */ +#define UART_SCR_BIMASK ((uint8_t)(0xFF)) + +/*********************************************************************** +* Macro defines for Macro defines for UART Auto baudrate control register +**********************************************************************/ + +/* UART Auto-baud start */ +#define UART_ACR_START (1 << 0) +/* UART Auto baudrate Mode 1 */ +#define UART_ACR_MODE (1 << 1) +/* UART Auto baudrate restart */ +#define UART_ACR_AUTO_RESTART (1 << 2) +/* UART End of auto-baud interrupt clear */ +#define UART_ACR_ABEOINT_CLR (1 << 8) +/* UART Auto-baud time-out interrupt clear */ +#define UART_ACR_ABTOINT_CLR (1 << 9) +/* UART Auto Baudrate register bit mask */ +#define UART_ACR_BITMASK ((uint32_t)(0x307)) + +/********************************************************************* +* Macro defines for Macro defines for UART IrDA control register +**********************************************************************/ +/* IrDA mode enable */ +#define UART_ICR_IRDAEN (1 << 0) +/* IrDA serial input inverted */ +#define UART_ICR_IRDAINV (1 << 1) +/* IrDA fixed pulse width mode */ +#define UART_ICR_FIXPULSE_EN (1 << 2) +/* PulseDiv - Configures the pulse when FixPulseEn = 1 */ +#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3)) +/* UART IRDA bit mask */ +#define UART_ICR_BITMASK ((uint32_t)(0x3F)) + +/********************************************************************** +* Macro defines for Macro defines for UART half duplex register +**********************************************************************/ +/* enable half-duplex mode*/ +#define UART_HDEN_HDEN (1 << 0) + +/********************************************************************** +* Macro defines for Macro defines for UART smart card interface control register +**********************************************************************/ +/* enable asynchronous half-duplex smart card interface*/ +#define UART_SCICTRL_SCIEN (1 << 0) +/* NACK response is inhibited*/ +#define UART_SCICTRL_NACKDIS (1 << 1) +/* ISO7816-3 protocol T1 is selected*/ +#define UART_SCICTRL_PROTSEL_T1 (1 << 2) +/* number of retransmission*/ +#define UART_SCICTRL_TXRETRY(n) ((uint32_t)((n&0x07)<<5)) +/* Extra guard time*/ +#define UART_SCICTRL_GUARDTIME(n) ((uint32_t)((n&0xFF)<<8)) + +/********************************************************************* +* Macro defines for Macro defines for UART synchronous control register +**********************************************************************/ +/* enable synchronous mode*/ +#define UART_SYNCCTRL_SYNC (1 << 0) +/* synchronous master mode*/ +#define UART_SYNCCTRL_CSRC_MASTER (1 << 1) +/* sample on falling edge*/ +#define UART_SYNCCTRL_FES (1 << 2) +/* to be defined*/ +#define UART_SYNCCTRL_TSBYPASS (1 << 3) +/* continuous running clock enable (master mode only) */ +#define UART_SYNCCTRL_CSCEN (1 << 4) +/* Do not send start/stop bit */ +#define UART_SYNCCTRL_NOSTARTSTOP (1 << 5) +/* stop continuous clock */ +#define UART_SYNCCTRL_CCCLR (1 << 6) + +/********************************************************************* +* Macro defines for Macro defines for UART Fractional divider register +**********************************************************************/ + +/* Baud-rate generation pre-scaler divisor */ +#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F)) +/* Baud-rate pre-scaler multiplier value */ +#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0)) +/* UART Fractional Divider register bit mask */ +#define UART_FDR_BITMASK ((uint32_t)(0xFF)) + +/********************************************************************* +* Macro defines for Macro defines for UART Tx Enable register +**********************************************************************/ + +#define UART_TER_TXEN (1 << 0) /* Transmit enable bit */ + +/********************************************************************** +* Macro defines for Macro defines for UART FIFO Level register +**********************************************************************/ +/* Reflects the current level of the UART receiver FIFO */ +#define UART_FIFOLVL_RX(n) ((uint32_t)(n&0x0F)) +/* Reflects the current level of the UART transmitter FIFO */ +#define UART_FIFOLVL_TX(n) ((uint32_t)((n>>8)&0x0F)) +/* UART FIFO Level Register bit mask */ +#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F)) + +/********************************************************************* +* UART enum +**********************************************************************/ + +/* +* UART Databit type definitions +*/ +typedef enum { + UART_DATABIT_5 = UART_LCR_WLEN5,/* UART 5 bit data mode */ + UART_DATABIT_6 = UART_LCR_WLEN6,/* UART 6 bit data mode */ + UART_DATABIT_7 = UART_LCR_WLEN7,/* UART 7 bit data mode */ + UART_DATABIT_8 = UART_LCR_WLEN8/* UART 8 bit data mode */ +} uart_databit_t; + +/* +* UART Stop bit type definitions +*/ +typedef enum { + /* UART 1 Stop Bits Select */ + UART_STOPBIT_1 = UART_LCR_ONE_STOPBIT, + /* UART 2 Stop Bits Select */ + UART_STOPBIT_2 = UART_LCR_TWO_STOPBIT +} uart_stopbit_t; + +/* +* UART Parity type definitions +*/ +typedef enum { + /* No parity */ + UART_PARITY_NONE = UART_LCR_NO_PARITY, + /* Odd parity */ + UART_PARITY_ODD = (UART_LCR_PARITY_ODD | UART_LCR_PARITY_EN), + /* Even parity */ + UART_PARITY_EVEN = (UART_LCR_PARITY_EVEN | UART_LCR_PARITY_EN), + /* Forced 1 stick parity */ + UART_PARITY_SP_1 = (UART_LCR_PARITY_SP_1 | UART_LCR_PARITY_EN), + /* Forced 0 stick parity */ + UART_PARITY_SP_0 = (UART_LCR_PARITY_SP_0 | UART_LCR_PARITY_EN) +} uart_parity_t; + +typedef enum { + UART0_NUM = UART0, + UART1_NUM = UART1, + UART2_NUM = UART2, + UART3_NUM = UART3 +} uart_num_t; + +typedef enum { + UART_NO_ERROR = 0, + UART_TIMEOUT_ERROR = 1 +} uart_error_t; + +typedef enum { + UART_RX_NO_DATA = 0, + UART_RX_DATA_READY = 1, + UART_RX_DATA_ERROR = 2 +} uart_rx_data_ready_t; + +/* function prototypes */ + +BEGIN_DECLS + +/* Init UART and set PLL1 as clock source (PCLK) */ +void uart_init(uart_num_t uart_num, uart_databit_t data_nb_bits, + uart_stopbit_t data_nb_stop, uart_parity_t data_parity, + uint16_t uart_divisor, uint8_t uart_divaddval, uint8_t uart_mulval); + +uart_rx_data_ready_t uart_rx_data_ready(uart_num_t uart_num); +uint8_t uart_read(uart_num_t uart_num); +uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles, + uart_error_t *error); +void uart_write(uart_num_t uart_num, uint8_t data); + +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/usb.h b/libopencm3/include/libopencm3/lpc43xx/usb.h new file mode 100644 index 0000000..2f1f156 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/usb.h @@ -0,0 +1,1337 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC43XX_USB_H +#define LPC43XX_USB_H + +#include +#include + +#define BIT_MASK(base_name) \ + (((1 << base_name##_WIDTH) - 1) << base_name##_SHIFT) +#define BIT_ARG(base_name, x) ((x) << base_name##_SHIFT) + +/* USB device data structures */ + +/* "The software must ensure that no interface data structure reachable + * by the Device controller crosses a 4kB-page boundary." + */ + +/* --- Endpoint Transfer Descriptor (dTD) ---------------------------------- */ + +typedef struct usb_transfer_descriptor_t usb_transfer_descriptor_t; +struct usb_transfer_descriptor_t { + volatile usb_transfer_descriptor_t *next_dtd_pointer; + volatile uint32_t total_bytes; + volatile uint32_t buffer_pointer_page[5]; + volatile uint32_t _reserved; +}; + +#define USB_TD_NEXT_DTD_POINTER_TERMINATE_SHIFT (0) +#define USB_TD_NEXT_DTD_POINTER_TERMINATE \ + ((volatile usb_transfer_descriptor_t *) \ + (1 << USB_TD_NEXT_DTD_POINTER_TERMINATE_SHIFT)) + +#define USB_TD_DTD_TOKEN_TOTAL_BYTES_SHIFT (16) +#define USB_TD_DTD_TOKEN_TOTAL_BYTES_WIDTH (15) +#define USB_TD_DTD_TOKEN_TOTAL_BYTES_MASK BIT_MASK(USB_TD_DTD_TOKEN_TOTAL_BYTES) +#define USB_TD_DTD_TOKEN_TOTAL_BYTES(x) BIT_ARG(USB_TD_DTD_TOKEN_TOTAL_BYTES, x) + +#define USB_TD_DTD_TOKEN_IOC_SHIFT (15) +#define USB_TD_DTD_TOKEN_IOC (1 << USB_TD_DTD_TOKEN_IOC_SHIFT) + +#define USB_TD_DTD_TOKEN_MULTO_SHIFT (10) +#define USB_TD_DTD_TOKEN_MULTO_WIDTH (2) +#define USB_TD_DTD_TOKEN_MULTO_MASK BIT_MASK(USB_TD_DTD_TOKEN_MULTO) +#define USB_TD_DTD_TOKEN_MULTO(x) BIT_ARG(USB_TD_DTD_TOKEN_MULTO, x) + +#define USB_TD_DTD_TOKEN_STATUS_ACTIVE_SHIFT (7) +#define USB_TD_DTD_TOKEN_STATUS_ACTIVE \ + (1 << USB_TD_DTD_TOKEN_STATUS_ACTIVE_SHIFT) + +#define USB_TD_DTD_TOKEN_STATUS_HALTED_SHIFT (6) +#define USB_TD_DTD_TOKEN_STATUS_HALTED \ + (1 << USB_TD_DTD_TOKEN_STATUS_HALTED_SHIFT) + +#define USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR_SHIFT (5) +#define USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR \ + (1 << USB_TD_DTD_TOKEN_STATUS_BUFFER_ERROR_SHIFT) + +#define USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR_SHIFT (3) +#define USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR \ + (1 << USB_TD_DTD_TOKEN_STATUS_TRANSACTION_ERROR_SHIFT) + +/* --- Endpoint Queue Head (dQH) ------------------------------------------- */ + +/* - must be aligned on 64-byte boundaries. */ +typedef struct { + volatile uint32_t capabilities; + volatile usb_transfer_descriptor_t *current_dtd_pointer; + volatile usb_transfer_descriptor_t *next_dtd_pointer; + volatile uint32_t total_bytes; + volatile uint32_t buffer_pointer_page[5]; + volatile uint32_t _reserved_0; + volatile uint8_t setup[8]; + volatile uint32_t _reserved_1[4]; +} usb_queue_head_t; + +#define USB_QH_CAPABILITIES_IOS_SHIFT (15) +#define USB_QH_CAPABILITIES_IOS (1 << USB_QH_CAPABILITIES_IOS_SHIFT) + +#define USB_QH_CAPABILITIES_MPL_SHIFT (16) +#define USB_QH_CAPABILITIES_MPL_WIDTH (11) +#define USB_QH_CAPABILITIES_MPL_MASK BIT_MASK(USB_QH_CAPABILITIES_MPL) +#define USB_QH_CAPABILITIES_MPL(x) BIT_ARG(USB_QH_CAPABILITIES_MPL, x) + +#define USB_QH_CAPABILITIES_ZLT_SHIFT (29) +#define USB_QH_CAPABILITIES_ZLT (1 << USB_QH_CAPABILITIES_ZLT_SHIFT) + +#define USB_QH_CAPABILITIES_MULT_SHIFT (30) +#define USB_QH_CAPABILITIES_MULT_WIDTH (2) +#define USB_QH_CAPABILITIES_MULT_MASK BIT_MASK(USB_QH_CAPABILITIES_MULT) +#define USB_QH_CAPABILITIES_MULT(x) BIT_ARG(USB_QH_CAPABILITIES_MULT, x) + +/* --- USB0 registers ------------------------------------------------------ */ + +/* Device/host capability registers */ + +/* Capability register length */ +#define USB0_CAPLENGTH MMIO32(USB0_BASE + 0x100) + +/* Host controller structural parameters */ +#define USB0_HCSPARAMS MMIO32(USB0_BASE + 0x104) + +/* Host controller capability parameters */ +#define USB0_HCCPARAMS MMIO32(USB0_BASE + 0x108) + +/* Device interface version number */ +#define USB0_DCIVERSION MMIO32(USB0_BASE + 0x120) + +/* Device controller capability parameters */ +#define USB0_DCCPARAMS MMIO32(USB0_BASE + 0x124) + + +/* Device/host operational registers */ + +/* USB command (device mode) */ +#define USB0_USBCMD_D MMIO32(USB0_BASE + 0x140) + +/* USB command (host mode) */ +#define USB0_USBCMD_H MMIO32(USB0_BASE + 0x140) + +/* USB status (device mode) */ +#define USB0_USBSTS_D MMIO32(USB0_BASE + 0x144) + +/* USB status (host mode) */ +#define USB0_USBSTS_H MMIO32(USB0_BASE + 0x144) + +/* USB interrupt enable (device mode) */ +#define USB0_USBINTR_D MMIO32(USB0_BASE + 0x148) + +/* USB interrupt enable (host mode) */ +#define USB0_USBINTR_H MMIO32(USB0_BASE + 0x148) + +/* USB frame index (device mode) */ +#define USB0_FRINDEX_D MMIO32(USB0_BASE + 0x14C) + +/* USB frame index (host mode) */ +#define USB0_FRINDEX_H MMIO32(USB0_BASE + 0x14C) + +/* USB device address (device mode) */ +#define USB0_DEVICEADDR MMIO32(USB0_BASE + 0x154) + +/* Frame list base address (host mode) */ +#define USB0_PERIODICLISTBASE MMIO32(USB0_BASE + 0x154) + +/* Address of endpoint list in memory */ +#define USB0_ENDPOINTLISTADDR MMIO32(USB0_BASE + 0x158) + +/* Asynchronous list address */ +#define USB0_ASYNCLISTADDR MMIO32(USB0_BASE + 0x158) + +/* Asynchronous buffer status for embedded TT (host mode) */ +#define USB0_TTCTRL MMIO32(USB0_BASE + 0x15C) + +/* Programmable burst size */ +#define USB0_BURSTSIZE MMIO32(USB0_BASE + 0x160) + +/* Host transmit pre-buffer packet tuning (host mode) */ +#define USB0_TXFILLTUNING MMIO32(USB0_BASE + 0x164) + +/* Length of virtual frame */ +#define USB0_BINTERVAL MMIO32(USB0_BASE + 0x174) + +/* Endpoint NAK (device mode) */ +#define USB0_ENDPTNAK MMIO32(USB0_BASE + 0x178) + +/* Endpoint NAK Enable (device mode) */ +#define USB0_ENDPTNAKEN MMIO32(USB0_BASE + 0x17C) + +/* Port 1 status/control (device mode) */ +#define USB0_PORTSC1_D MMIO32(USB0_BASE + 0x184) + +/* Port 1 status/control (host mode) */ +#define USB0_PORTSC1_H MMIO32(USB0_BASE + 0x184) + +/* OTG status and control */ +#define USB0_OTGSC MMIO32(USB0_BASE + 0x1A4) + +/* USB device mode (device mode) */ +#define USB0_USBMODE_D MMIO32(USB0_BASE + 0x1A8) + +/* USB device mode (host mode) */ +#define USB0_USBMODE_H MMIO32(USB0_BASE + 0x1A8) + + +/* Device endpoint registers */ + +/* Endpoint setup status */ +#define USB0_ENDPTSETUPSTAT MMIO32(USB0_BASE + 0x1AC) + +/* Endpoint initialization */ +#define USB0_ENDPTPRIME MMIO32(USB0_BASE + 0x1B0) + +/* Endpoint de-initialization */ +#define USB0_ENDPTFLUSH MMIO32(USB0_BASE + 0x1B4) + +/* Endpoint status */ +#define USB0_ENDPTSTAT MMIO32(USB0_BASE + 0x1B8) + +/* Endpoint complete */ +#define USB0_ENDPTCOMPLETE MMIO32(USB0_BASE + 0x1BC) + +/* Endpoint control */ +#define USB0_ENDPTCTRL(logical_ep) MMIO32(USB0_BASE + 0x1C0 + \ + (logical_ep * 4)) + +/* Endpoint control 0 */ +#define USB0_ENDPTCTRL0 USB0_ENDPTCTRL(0) + +/* Endpoint control 1 */ +#define USB0_ENDPTCTRL1 USB0_ENDPTCTRL(1) + +/* Endpoint control 2 */ +#define USB0_ENDPTCTRL2 USB0_ENDPTCTRL(2) + +/* Endpoint control 3 */ +#define USB0_ENDPTCTRL3 USB0_ENDPTCTRL(3) + +/* Endpoint control 4 */ +#define USB0_ENDPTCTRL4 USB0_ENDPTCTRL(4) + +/* Endpoint control 5 */ +#define USB0_ENDPTCTRL5 USB0_ENDPTCTRL(5) + +/* --- USB0_CAPLENGTH values ------------------------------------ */ + +/* CAPLENGTH: Indicates offset to add to the register base address at the + beginning of the Operational Register */ +#define USB0_CAPLENGTH_CAPLENGTH_SHIFT (0) +#define USB0_CAPLENGTH_CAPLENGTH_MASK (0xff << USB0_CAPLENGTH_CAPLENGTH_SHIFT) +#define USB0_CAPLENGTH_CAPLENGTH(x) ((x) << USB0_CAPLENGTH_CAPLENGTH_SHIFT) + +/* HCIVERSION: BCD encoding of the EHCI revision number supported by this host + controller */ +#define USB0_CAPLENGTH_HCIVERSION_SHIFT (8) +#define USB0_CAPLENGTH_HCIVERSION_MASK \ + (0xffff << USB0_CAPLENGTH_HCIVERSION_SHIFT) +#define USB0_CAPLENGTH_HCIVERSION(x) ((x) << USB0_CAPLENGTH_HCIVERSION_SHIFT) + +/* --- USB0_HCSPARAMS values ------------------------------------ */ + +/* N_PORTS: Number of downstream ports */ +#define USB0_HCSPARAMS_N_PORTS_SHIFT (0) +#define USB0_HCSPARAMS_N_PORTS_MASK (0xf << USB0_HCSPARAMS_N_PORTS_SHIFT) +#define USB0_HCSPARAMS_N_PORTS(x) ((x) << USB0_HCSPARAMS_N_PORTS_SHIFT) + +/* PPC: Port Power Control */ +#define USB0_HCSPARAMS_PPC_SHIFT (4) +#define USB0_HCSPARAMS_PPC (1 << USB0_HCSPARAMS_PPC_SHIFT) + +/* N_PCC: Number of Ports per Companion Controller */ +#define USB0_HCSPARAMS_N_PCC_SHIFT (8) +#define USB0_HCSPARAMS_N_PCC_MASK (0xf << USB0_HCSPARAMS_N_PCC_SHIFT) +#define USB0_HCSPARAMS_N_PCC(x) ((x) << USB0_HCSPARAMS_N_PCC_SHIFT) + +/* N_CC: Number of Companion Controller */ +#define USB0_HCSPARAMS_N_CC_SHIFT (12) +#define USB0_HCSPARAMS_N_CC_MASK (0xf << USB0_HCSPARAMS_N_CC_SHIFT) +#define USB0_HCSPARAMS_N_CC(x) ((x) << USB0_HCSPARAMS_N_CC_SHIFT) + +/* PI: Port indicators */ +#define USB0_HCSPARAMS_PI_SHIFT (16) +#define USB0_HCSPARAMS_PI (1 << USB0_HCSPARAMS_PI_SHIFT) + +/* N_PTT: Number of Ports per Transaction Translator */ +#define USB0_HCSPARAMS_N_PTT_SHIFT (20) +#define USB0_HCSPARAMS_N_PTT_MASK (0xf << USB0_HCSPARAMS_N_PTT_SHIFT) +#define USB0_HCSPARAMS_N_PTT(x) ((x) << USB0_HCSPARAMS_N_PTT_SHIFT) + +/* N_TT: Number of Transaction Translators */ +#define USB0_HCSPARAMS_N_TT_SHIFT (24) +#define USB0_HCSPARAMS_N_TT_MASK (0xf << USB0_HCSPARAMS_N_TT_SHIFT) +#define USB0_HCSPARAMS_N_TT(x) ((x) << USB0_HCSPARAMS_N_TT_SHIFT) + +/* --- USB0_HCCPARAMS values ------------------------------------ */ + +/* ADC: 64-bit Addressing Capability */ +#define USB0_HCCPARAMS_ADC_SHIFT (0) +#define USB0_HCCPARAMS_ADC (1 << USB0_HCCPARAMS_ADC_SHIFT) + +/* PFL: Programmable Frame List Flag */ +#define USB0_HCCPARAMS_PFL_SHIFT (1) +#define USB0_HCCPARAMS_PFL (1 << USB0_HCCPARAMS_PFL_SHIFT) + +/* ASP: Asynchronous Schedule Park Capability */ +#define USB0_HCCPARAMS_ASP_SHIFT (2) +#define USB0_HCCPARAMS_ASP (1 << USB0_HCCPARAMS_ASP_SHIFT) + +/* IST: Isochronous Scheduling Threshold */ +#define USB0_HCCPARAMS_IST_SHIFT (4) +#define USB0_HCCPARAMS_IST_MASK (0xf << USB0_HCCPARAMS_IST_SHIFT) +#define USB0_HCCPARAMS_IST(x) ((x) << USB0_HCCPARAMS_IST_SHIFT) + +/* EECP: EHCI Extended Capabilities Pointer */ +#define USB0_HCCPARAMS_EECP_SHIFT (8) +#define USB0_HCCPARAMS_EECP_MASK (0xf << USB0_HCCPARAMS_EECP_SHIFT) +#define USB0_HCCPARAMS_EECP(x) ((x) << USB0_HCCPARAMS_EECP_SHIFT) + +/* --- USB0_DCCPARAMS values ------------------------------------ */ + +/* DEN: Device Endpoint Number */ +#define USB0_DCCPARAMS_DEN_SHIFT (0) +#define USB0_DCCPARAMS_DEN_MASK (0x1f << USB0_DCCPARAMS_DEN_SHIFT) +#define USB0_DCCPARAMS_DEN(x) ((x) << USB0_DCCPARAMS_DEN_SHIFT) + +/* DC: Device Capable */ +#define USB0_DCCPARAMS_DC_SHIFT (7) +#define USB0_DCCPARAMS_DC (1 << USB0_DCCPARAMS_DC_SHIFT) + +/* HC: Host Capable */ +#define USB0_DCCPARAMS_HC_SHIFT (8) +#define USB0_DCCPARAMS_HC (1 << USB0_DCCPARAMS_HC_SHIFT) + +/* --- USB0_USBCMD_D values ------------------------------------- */ + +/* RS: Run/Stop */ +#define USB0_USBCMD_D_RS_SHIFT (0) +#define USB0_USBCMD_D_RS (1 << USB0_USBCMD_D_RS_SHIFT) + +/* RST: Controller reset */ +#define USB0_USBCMD_D_RST_SHIFT (1) +#define USB0_USBCMD_D_RST (1 << USB0_USBCMD_D_RST_SHIFT) + +/* SUTW: Setup trip wire */ +#define USB0_USBCMD_D_SUTW_SHIFT (13) +#define USB0_USBCMD_D_SUTW (1 << USB0_USBCMD_D_SUTW_SHIFT) + +/* ATDTW: Add dTD trip wire */ +#define USB0_USBCMD_D_ATDTW_SHIFT (14) +#define USB0_USBCMD_D_ATDTW (1 << USB0_USBCMD_D_ATDTW_SHIFT) + +/* ITC: Interrupt threshold control */ +#define USB0_USBCMD_D_ITC_SHIFT (16) +#define USB0_USBCMD_D_ITC_MASK (0xff << USB0_USBCMD_D_ITC_SHIFT) +#define USB0_USBCMD_D_ITC(x) ((x) << USB0_USBCMD_D_ITC_SHIFT) + +/* --- USB0_USBCMD_H values ------------------------------------- */ + +/* RS: Run/Stop */ +#define USB0_USBCMD_H_RS_SHIFT (0) +#define USB0_USBCMD_H_RS (1 << USB0_USBCMD_H_RS_SHIFT) + +/* RST: Controller reset */ +#define USB0_USBCMD_H_RST_SHIFT (1) +#define USB0_USBCMD_H_RST (1 << USB0_USBCMD_H_RST_SHIFT) + +/* FS0: Bit 0 of the Frame List Size bits */ +#define USB0_USBCMD_H_FS0_SHIFT (2) +#define USB0_USBCMD_H_FS0 (1 << USB0_USBCMD_H_FS0_SHIFT) + +/* FS1: Bit 1 of the Frame List Size bits */ +#define USB0_USBCMD_H_FS1_SHIFT (3) +#define USB0_USBCMD_H_FS1 (1 << USB0_USBCMD_H_FS1_SHIFT) + +/* PSE: This bit controls whether the host controller skips processing the +periodic schedule */ +#define USB0_USBCMD_H_PSE_SHIFT (4) +#define USB0_USBCMD_H_PSE (1 << USB0_USBCMD_H_PSE_SHIFT) + +/* ASE: This bit controls whether the host controller skips processing the +asynchronous schedule */ +#define USB0_USBCMD_H_ASE_SHIFT (5) +#define USB0_USBCMD_H_ASE (1 << USB0_USBCMD_H_ASE_SHIFT) + +/* IAA: This bit is used as a doorbell by software to tell the host controller +to issue an interrupt the next time it advances asynchronous schedule */ +#define USB0_USBCMD_H_IAA_SHIFT (6) +#define USB0_USBCMD_H_IAA (1 << USB0_USBCMD_H_IAA_SHIFT) + +/* ASP1_0: Asynchronous schedule park mode */ +#define USB0_USBCMD_H_ASP1_0_SHIFT (8) +#define USB0_USBCMD_H_ASP1_0_MASK (0x3 << USB0_USBCMD_H_ASP1_0_SHIFT) +#define USB0_USBCMD_H_ASP1_0(x) ((x) << USB0_USBCMD_H_ASP1_0_SHIFT) + +/* ASPE: Asynchronous Schedule Park Mode Enable */ +#define USB0_USBCMD_H_ASPE_SHIFT (11) +#define USB0_USBCMD_H_ASPE (1 << USB0_USBCMD_H_ASPE_SHIFT) + +/* FS2: Bit 2 of the Frame List Size bits */ +#define USB0_USBCMD_H_FS2_SHIFT (15) +#define USB0_USBCMD_H_FS2 (1 << USB0_USBCMD_H_FS2_SHIFT) + +/* ITC: Interrupt threshold control */ +#define USB0_USBCMD_H_ITC_SHIFT (16) +#define USB0_USBCMD_H_ITC_MASK (0xff << USB0_USBCMD_H_ITC_SHIFT) +#define USB0_USBCMD_H_ITC(x) ((x) << USB0_USBCMD_H_ITC_SHIFT) + +/* --- USB0_USBSTS_D values ------------------------------------- */ + +/* UI: USB interrupt */ +#define USB0_USBSTS_D_UI_SHIFT (0) +#define USB0_USBSTS_D_UI (1 << USB0_USBSTS_D_UI_SHIFT) + +/* UEI: USB error interrupt */ +#define USB0_USBSTS_D_UEI_SHIFT (1) +#define USB0_USBSTS_D_UEI (1 << USB0_USBSTS_D_UEI_SHIFT) + +/* PCI: Port change detect */ +#define USB0_USBSTS_D_PCI_SHIFT (2) +#define USB0_USBSTS_D_PCI (1 << USB0_USBSTS_D_PCI_SHIFT) + +/* URI: USB reset received */ +#define USB0_USBSTS_D_URI_SHIFT (6) +#define USB0_USBSTS_D_URI (1 << USB0_USBSTS_D_URI_SHIFT) + +/* SRI: SOF received */ +#define USB0_USBSTS_D_SRI_SHIFT (7) +#define USB0_USBSTS_D_SRI (1 << USB0_USBSTS_D_SRI_SHIFT) + +/* SLI: DCSuspend */ +#define USB0_USBSTS_D_SLI_SHIFT (8) +#define USB0_USBSTS_D_SLI (1 << USB0_USBSTS_D_SLI_SHIFT) + +/* NAKI: NAK interrupt bit */ +#define USB0_USBSTS_D_NAKI_SHIFT (16) +#define USB0_USBSTS_D_NAKI (1 << USB0_USBSTS_D_NAKI_SHIFT) + +/* --- USB0_USBSTS_H values ------------------------------------- */ + +/* UI: USB interrupt */ +#define USB0_USBSTS_H_UI_SHIFT (0) +#define USB0_USBSTS_H_UI (1 << USB0_USBSTS_H_UI_SHIFT) + +/* UEI: USB error interrupt */ +#define USB0_USBSTS_H_UEI_SHIFT (1) +#define USB0_USBSTS_H_UEI (1 << USB0_USBSTS_H_UEI_SHIFT) + +/* PCI: Port change detect */ +#define USB0_USBSTS_H_PCI_SHIFT (2) +#define USB0_USBSTS_H_PCI (1 << USB0_USBSTS_H_PCI_SHIFT) + +/* FRI: Frame list roll-over */ +#define USB0_USBSTS_H_FRI_SHIFT (3) +#define USB0_USBSTS_H_FRI (1 << USB0_USBSTS_H_FRI_SHIFT) + +/* AAI: Interrupt on async advance */ +#define USB0_USBSTS_H_AAI_SHIFT (5) +#define USB0_USBSTS_H_AAI (1 << USB0_USBSTS_H_AAI_SHIFT) + +/* SRI: SOF received */ +#define USB0_USBSTS_H_SRI_SHIFT (7) +#define USB0_USBSTS_H_SRI (1 << USB0_USBSTS_H_SRI_SHIFT) + +/* HCH: HCHalted */ +#define USB0_USBSTS_H_HCH_SHIFT (12) +#define USB0_USBSTS_H_HCH (1 << USB0_USBSTS_H_HCH_SHIFT) + +/* RCL: Reclamation */ +#define USB0_USBSTS_H_RCL_SHIFT (13) +#define USB0_USBSTS_H_RCL (1 << USB0_USBSTS_H_RCL_SHIFT) + +/* PS: Periodic schedule status */ +#define USB0_USBSTS_H_PS_SHIFT (14) +#define USB0_USBSTS_H_PS (1 << USB0_USBSTS_H_PS_SHIFT) + +/* AS: Asynchronous schedule status */ +#define USB0_USBSTS_H_AS_SHIFT (15) +#define USB0_USBSTS_H_AS (1 << USB0_USBSTS_H_AS_SHIFT) + +/* UAI: USB host asynchronous interrupt (USBHSTASYNCINT) */ +#define USB0_USBSTS_H_UAI_SHIFT (18) +#define USB0_USBSTS_H_UAI (1 << USB0_USBSTS_H_UAI_SHIFT) + +/* UPI: USB host periodic interrupt (USBHSTPERINT) */ +#define USB0_USBSTS_H_UPI_SHIFT (19) +#define USB0_USBSTS_H_UPI (1 << USB0_USBSTS_H_UPI_SHIFT) + +/* --- USB0_USBINTR_D values ------------------------------------ */ + +/* UE: USB interrupt enable */ +#define USB0_USBINTR_D_UE_SHIFT (0) +#define USB0_USBINTR_D_UE (1 << USB0_USBINTR_D_UE_SHIFT) + +/* UEE: USB error interrupt enable */ +#define USB0_USBINTR_D_UEE_SHIFT (1) +#define USB0_USBINTR_D_UEE (1 << USB0_USBINTR_D_UEE_SHIFT) + +/* PCE: Port change detect enable */ +#define USB0_USBINTR_D_PCE_SHIFT (2) +#define USB0_USBINTR_D_PCE (1 << USB0_USBINTR_D_PCE_SHIFT) + +/* URE: USB reset enable */ +#define USB0_USBINTR_D_URE_SHIFT (6) +#define USB0_USBINTR_D_URE (1 << USB0_USBINTR_D_URE_SHIFT) + +/* SRE: SOF received enable */ +#define USB0_USBINTR_D_SRE_SHIFT (7) +#define USB0_USBINTR_D_SRE (1 << USB0_USBINTR_D_SRE_SHIFT) + +/* SLE: Sleep enable */ +#define USB0_USBINTR_D_SLE_SHIFT (8) +#define USB0_USBINTR_D_SLE (1 << USB0_USBINTR_D_SLE_SHIFT) + +/* NAKE: NAK interrupt enable */ +#define USB0_USBINTR_D_NAKE_SHIFT (16) +#define USB0_USBINTR_D_NAKE (1 << USB0_USBINTR_D_NAKE_SHIFT) + +/* --- USB0_USBINTR_H values ------------------------------------ */ + +/* UE: USB interrupt enable */ +#define USB0_USBINTR_H_UE_SHIFT (0) +#define USB0_USBINTR_H_UE (1 << USB0_USBINTR_H_UE_SHIFT) + +/* UEE: USB error interrupt enable */ +#define USB0_USBINTR_H_UEE_SHIFT (1) +#define USB0_USBINTR_H_UEE (1 << USB0_USBINTR_H_UEE_SHIFT) + +/* PCE: Port change detect enable */ +#define USB0_USBINTR_H_PCE_SHIFT (2) +#define USB0_USBINTR_H_PCE (1 << USB0_USBINTR_H_PCE_SHIFT) + +/* FRE: Frame list rollover enable */ +#define USB0_USBINTR_H_FRE_SHIFT (3) +#define USB0_USBINTR_H_FRE (1 << USB0_USBINTR_H_FRE_SHIFT) + +/* AAE: Interrupt on asynchronous advance enable */ +#define USB0_USBINTR_H_AAE_SHIFT (5) +#define USB0_USBINTR_H_AAE (1 << USB0_USBINTR_H_AAE_SHIFT) + +/* SRE: SOF received enable */ +#define USB0_USBINTR_H_SRE_SHIFT (7) +#define USB0_USBINTR_H_SRE (1 << USB0_USBINTR_H_SRE_SHIFT) + +/* UAIE: USB host asynchronous interrupt enable */ +#define USB0_USBINTR_H_UAIE_SHIFT (18) +#define USB0_USBINTR_H_UAIE (1 << USB0_USBINTR_H_UAIE_SHIFT) + +/* UPIA: USB host periodic interrupt enable */ +#define USB0_USBINTR_H_UPIA_SHIFT (19) +#define USB0_USBINTR_H_UPIA (1 << USB0_USBINTR_H_UPIA_SHIFT) + +/* --- USB0_FRINDEX_D values ------------------------------------ */ + +/* FRINDEX2_0: Current micro frame number */ +#define USB0_FRINDEX_D_FRINDEX2_0_SHIFT (0) +#define USB0_FRINDEX_D_FRINDEX2_0_MASK (0x7 << USB0_FRINDEX_D_FRINDEX2_0_SHIFT) +#define USB0_FRINDEX_D_FRINDEX2_0(x) ((x) << USB0_FRINDEX_D_FRINDEX2_0_SHIFT) + +/* FRINDEX13_3: Current frame number of the last frame transmitted */ +#define USB0_FRINDEX_D_FRINDEX13_3_SHIFT (3) +#define USB0_FRINDEX_D_FRINDEX13_3_MASK \ + (0x7ff << USB0_FRINDEX_D_FRINDEX13_3_SHIFT) +#define USB0_FRINDEX_D_FRINDEX13_3(x) ((x) << USB0_FRINDEX_D_FRINDEX13_3_SHIFT) + +/* --- USB0_FRINDEX_H values ------------------------------------ */ + +/* FRINDEX2_0: Current micro frame number */ +#define USB0_FRINDEX_H_FRINDEX2_0_SHIFT (0) +#define USB0_FRINDEX_H_FRINDEX2_0_MASK (0x7 << USB0_FRINDEX_H_FRINDEX2_0_SHIFT) +#define USB0_FRINDEX_H_FRINDEX2_0(x) ((x) << USB0_FRINDEX_H_FRINDEX2_0_SHIFT) + +/* FRINDEX12_3: Frame list current index */ +#define USB0_FRINDEX_H_FRINDEX12_3_SHIFT (3) +#define USB0_FRINDEX_H_FRINDEX12_3_MASK \ + (0x3ff << USB0_FRINDEX_H_FRINDEX12_3_SHIFT) +#define USB0_FRINDEX_H_FRINDEX12_3(x) ((x) << USB0_FRINDEX_H_FRINDEX12_3_SHIFT) + +/* --- USB0_DEVICEADDR values ----------------------------------- */ + +/* USBADRA: Device address advance */ +#define USB0_DEVICEADDR_USBADRA_SHIFT (24) +#define USB0_DEVICEADDR_USBADRA (1 << USB0_DEVICEADDR_USBADRA_SHIFT) + +/* USBADR: USB device address */ +#define USB0_DEVICEADDR_USBADR_SHIFT (25) +#define USB0_DEVICEADDR_USBADR_MASK (0x7f << USB0_DEVICEADDR_USBADR_SHIFT) +#define USB0_DEVICEADDR_USBADR(x) ((x) << USB0_DEVICEADDR_USBADR_SHIFT) + +/* --- USB0_PERIODICLISTBASE values ----------------------------- */ + +/* PERBASE31_12: Base Address (Low) */ +#define USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT (12) +#define USB0_PERIODICLISTBASE_PERBASE31_12_MASK \ + (0xfffff << USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT) +#define USB0_PERIODICLISTBASE_PERBASE31_12(x) \ + ((x) << USB0_PERIODICLISTBASE_PERBASE31_12_SHIFT) + +/* --- USB0_ENDPOINTLISTADDR values ----------------------------- */ + +/* EPBASE31_11: Endpoint list pointer (low) */ +#define USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT (11) +#define USB0_ENDPOINTLISTADDR_EPBASE31_11_MASK \ + (0x1fffff << USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT) +#define USB0_ENDPOINTLISTADDR_EPBASE31_11(x) \ + ((x) << USB0_ENDPOINTLISTADDR_EPBASE31_11_SHIFT) + +/* --- USB0_ASYNCLISTADDR values -------------------------------- */ + +/* ASYBASE31_5: Link pointer (Low) LPL */ +#define USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT (5) +#define USB0_ASYNCLISTADDR_ASYBASE31_5_MASK \ + (0x7ffffff << USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT) +#define USB0_ASYNCLISTADDR_ASYBASE31_5(x) \ + ((x) << USB0_ASYNCLISTADDR_ASYBASE31_5_SHIFT) + +/* --- USB0_TTCTRL values --------------------------------------- */ + +/* TTHA: Hub address when FS or LS device are connected directly */ +#define USB0_TTCTRL_TTHA_SHIFT (24) +#define USB0_TTCTRL_TTHA_MASK (0x7f << USB0_TTCTRL_TTHA_SHIFT) +#define USB0_TTCTRL_TTHA(x) ((x) << USB0_TTCTRL_TTHA_SHIFT) + +/* --- USB0_BURSTSIZE values ------------------------------------ */ + +/* RXPBURST: Programmable RX burst length */ +#define USB0_BURSTSIZE_RXPBURST_SHIFT (0) +#define USB0_BURSTSIZE_RXPBURST_MASK (0xff << USB0_BURSTSIZE_RXPBURST_SHIFT) +#define USB0_BURSTSIZE_RXPBURST(x) ((x) << USB0_BURSTSIZE_RXPBURST_SHIFT) + +/* TXPBURST: Programmable TX burst length */ +#define USB0_BURSTSIZE_TXPBURST_SHIFT (8) +#define USB0_BURSTSIZE_TXPBURST_MASK (0xff << USB0_BURSTSIZE_TXPBURST_SHIFT) +#define USB0_BURSTSIZE_TXPBURST(x) ((x) << USB0_BURSTSIZE_TXPBURST_SHIFT) + +/* --- USB0_TXFILLTUNING values --------------------------------- */ + +/* TXSCHOH: FIFO burst threshold */ +#define USB0_TXFILLTUNING_TXSCHOH_SHIFT (0) +#define USB0_TXFILLTUNING_TXSCHOH_MASK (0xff << USB0_TXFILLTUNING_TXSCHOH_SHIFT) +#define USB0_TXFILLTUNING_TXSCHOH(x) ((x) << USB0_TXFILLTUNING_TXSCHOH_SHIFT) + +/* TXSCHEATLTH: Scheduler health counter */ +#define USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT (8) +#define USB0_TXFILLTUNING_TXSCHEATLTH_MASK \ + (0x1f << USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT) +#define USB0_TXFILLTUNING_TXSCHEATLTH(x) \ + ((x) << USB0_TXFILLTUNING_TXSCHEATLTH_SHIFT) + +/* TXFIFOTHRES: Scheduler overhead */ +#define USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT (16) +#define USB0_TXFILLTUNING_TXFIFOTHRES_MASK \ + (0x3f << USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT) +#define USB0_TXFILLTUNING_TXFIFOTHRES(x) \ + ((x) << USB0_TXFILLTUNING_TXFIFOTHRES_SHIFT) + +/* --- USB0_BINTERVAL values ------------------------------------ */ + +/* BINT: bInterval value */ +#define USB0_BINTERVAL_BINT_SHIFT (0) +#define USB0_BINTERVAL_BINT_MASK (0xf << USB0_BINTERVAL_BINT_SHIFT) +#define USB0_BINTERVAL_BINT(x) ((x) << USB0_BINTERVAL_BINT_SHIFT) + +/* --- USB0_ENDPTNAK values ------------------------------------- */ + +/* EPRN: Rx endpoint NAK */ +#define USB0_ENDPTNAK_EPRN_SHIFT (0) +#define USB0_ENDPTNAK_EPRN_MASK (0x3f << USB0_ENDPTNAK_EPRN_SHIFT) +#define USB0_ENDPTNAK_EPRN(x) ((x) << USB0_ENDPTNAK_EPRN_SHIFT) + +/* EPTN: Tx endpoint NAK */ +#define USB0_ENDPTNAK_EPTN_SHIFT (16) +#define USB0_ENDPTNAK_EPTN_MASK (0x3f << USB0_ENDPTNAK_EPTN_SHIFT) +#define USB0_ENDPTNAK_EPTN(x) ((x) << USB0_ENDPTNAK_EPTN_SHIFT) + +/* --- USB0_ENDPTNAKEN values ----------------------------------- */ + +/* EPRNE: Rx endpoint NAK enable */ +#define USB0_ENDPTNAKEN_EPRNE_SHIFT (0) +#define USB0_ENDPTNAKEN_EPRNE_MASK (0x3f << USB0_ENDPTNAKEN_EPRNE_SHIFT) +#define USB0_ENDPTNAKEN_EPRNE(x) ((x) << USB0_ENDPTNAKEN_EPRNE_SHIFT) + +/* EPTNE: Tx endpoint NAK */ +#define USB0_ENDPTNAKEN_EPTNE_SHIFT (16) +#define USB0_ENDPTNAKEN_EPTNE_MASK (0x3f << USB0_ENDPTNAKEN_EPTNE_SHIFT) +#define USB0_ENDPTNAKEN_EPTNE(x) ((x) << USB0_ENDPTNAKEN_EPTNE_SHIFT) + +/* --- USB0_PORTSC1_D values ------------------------------------ */ + +/* CCS: Current connect status */ +#define USB0_PORTSC1_D_CCS_SHIFT (0) +#define USB0_PORTSC1_D_CCS (1 << USB0_PORTSC1_D_CCS_SHIFT) + +/* PE: Port enable */ +#define USB0_PORTSC1_D_PE_SHIFT (2) +#define USB0_PORTSC1_D_PE (1 << USB0_PORTSC1_D_PE_SHIFT) + +/* PEC: Port enable/disable change */ +#define USB0_PORTSC1_D_PEC_SHIFT (3) +#define USB0_PORTSC1_D_PEC (1 << USB0_PORTSC1_D_PEC_SHIFT) + +/* FPR: Force port resume */ +#define USB0_PORTSC1_D_FPR_SHIFT (6) +#define USB0_PORTSC1_D_FPR (1 << USB0_PORTSC1_D_FPR_SHIFT) + +/* SUSP: Suspend */ +#define USB0_PORTSC1_D_SUSP_SHIFT (7) +#define USB0_PORTSC1_D_SUSP (1 << USB0_PORTSC1_D_SUSP_SHIFT) + +/* PR: Port reset */ +#define USB0_PORTSC1_D_PR_SHIFT (8) +#define USB0_PORTSC1_D_PR (1 << USB0_PORTSC1_D_PR_SHIFT) + +/* HSP: High-speed status */ +#define USB0_PORTSC1_D_HSP_SHIFT (9) +#define USB0_PORTSC1_D_HSP (1 << USB0_PORTSC1_D_HSP_SHIFT) + +/* PIC1_0: Port indicator control */ +#define USB0_PORTSC1_D_PIC1_0_SHIFT (14) +#define USB0_PORTSC1_D_PIC1_0_MASK (0x3 << USB0_PORTSC1_D_PIC1_0_SHIFT) +#define USB0_PORTSC1_D_PIC1_0(x) ((x) << USB0_PORTSC1_D_PIC1_0_SHIFT) + +/* PTC3_0: Port test control */ +#define USB0_PORTSC1_D_PTC3_0_SHIFT (16) +#define USB0_PORTSC1_D_PTC3_0_MASK (0xf << USB0_PORTSC1_D_PTC3_0_SHIFT) +#define USB0_PORTSC1_D_PTC3_0(x) ((x) << USB0_PORTSC1_D_PTC3_0_SHIFT) + +/* PHCD: PHY low power suspend - clock disable (PLPSCD) */ +#define USB0_PORTSC1_D_PHCD_SHIFT (23) +#define USB0_PORTSC1_D_PHCD (1 << USB0_PORTSC1_D_PHCD_SHIFT) + +/* PFSC: Port force full speed connect */ +#define USB0_PORTSC1_D_PFSC_SHIFT (24) +#define USB0_PORTSC1_D_PFSC (1 << USB0_PORTSC1_D_PFSC_SHIFT) + +/* PSPD: Port speed */ +#define USB0_PORTSC1_D_PSPD_SHIFT (26) +#define USB0_PORTSC1_D_PSPD_MASK (0x3 << USB0_PORTSC1_D_PSPD_SHIFT) +#define USB0_PORTSC1_D_PSPD(x) ((x) << USB0_PORTSC1_D_PSPD_SHIFT) + +/* --- USB0_PORTSC1_H values ------------------------------------ */ + +/* CCS: Current connect status */ +#define USB0_PORTSC1_H_CCS_SHIFT (0) +#define USB0_PORTSC1_H_CCS (1 << USB0_PORTSC1_H_CCS_SHIFT) + +/* CSC: Connect status change */ +#define USB0_PORTSC1_H_CSC_SHIFT (1) +#define USB0_PORTSC1_H_CSC (1 << USB0_PORTSC1_H_CSC_SHIFT) + +/* PE: Port enable */ +#define USB0_PORTSC1_H_PE_SHIFT (2) +#define USB0_PORTSC1_H_PE (1 << USB0_PORTSC1_H_PE_SHIFT) + +/* PEC: Port disable/enable change */ +#define USB0_PORTSC1_H_PEC_SHIFT (3) +#define USB0_PORTSC1_H_PEC (1 << USB0_PORTSC1_H_PEC_SHIFT) + +/* OCA: Over-current active */ +#define USB0_PORTSC1_H_OCA_SHIFT (4) +#define USB0_PORTSC1_H_OCA (1 << USB0_PORTSC1_H_OCA_SHIFT) + +/* OCC: Over-current change */ +#define USB0_PORTSC1_H_OCC_SHIFT (5) +#define USB0_PORTSC1_H_OCC (1 << USB0_PORTSC1_H_OCC_SHIFT) + +/* FPR: Force port resume */ +#define USB0_PORTSC1_H_FPR_SHIFT (6) +#define USB0_PORTSC1_H_FPR (1 << USB0_PORTSC1_H_FPR_SHIFT) + +/* SUSP: Suspend */ +#define USB0_PORTSC1_H_SUSP_SHIFT (7) +#define USB0_PORTSC1_H_SUSP (1 << USB0_PORTSC1_H_SUSP_SHIFT) + +/* PR: Port reset */ +#define USB0_PORTSC1_H_PR_SHIFT (8) +#define USB0_PORTSC1_H_PR (1 << USB0_PORTSC1_H_PR_SHIFT) + +/* HSP: High-speed status */ +#define USB0_PORTSC1_H_HSP_SHIFT (9) +#define USB0_PORTSC1_H_HSP (1 << USB0_PORTSC1_H_HSP_SHIFT) + +/* LS: Line status */ +#define USB0_PORTSC1_H_LS_SHIFT (10) +#define USB0_PORTSC1_H_LS_MASK (0x3 << USB0_PORTSC1_H_LS_SHIFT) +#define USB0_PORTSC1_H_LS(x) ((x) << USB0_PORTSC1_H_LS_SHIFT) + +/* PP: Port power control */ +#define USB0_PORTSC1_H_PP_SHIFT (12) +#define USB0_PORTSC1_H_PP (1 << USB0_PORTSC1_H_PP_SHIFT) + +/* PIC1_0: Port indicator control */ +#define USB0_PORTSC1_H_PIC1_0_SHIFT (14) +#define USB0_PORTSC1_H_PIC1_0_MASK (0x3 << USB0_PORTSC1_H_PIC1_0_SHIFT) +#define USB0_PORTSC1_H_PIC1_0(x) ((x) << USB0_PORTSC1_H_PIC1_0_SHIFT) + +/* PTC3_0: Port test control */ +#define USB0_PORTSC1_H_PTC3_0_SHIFT (16) +#define USB0_PORTSC1_H_PTC3_0_MASK (0xf << USB0_PORTSC1_H_PTC3_0_SHIFT) +#define USB0_PORTSC1_H_PTC3_0(x) ((x) << USB0_PORTSC1_H_PTC3_0_SHIFT) + +/* WKCN: Wake on connect enable (WKCNNT_E) */ +#define USB0_PORTSC1_H_WKCN_SHIFT (20) +#define USB0_PORTSC1_H_WKCN (1 << USB0_PORTSC1_H_WKCN_SHIFT) + +/* WKDC: Wake on disconnect enable (WKDSCNNT_E) */ +#define USB0_PORTSC1_H_WKDC_SHIFT (21) +#define USB0_PORTSC1_H_WKDC (1 << USB0_PORTSC1_H_WKDC_SHIFT) + +/* WKOC: Wake on over-current enable (WKOC_E) */ +#define USB0_PORTSC1_H_WKOC_SHIFT (22) +#define USB0_PORTSC1_H_WKOC (1 << USB0_PORTSC1_H_WKOC_SHIFT) + +/* PHCD: PHY low power suspend - clock disable (PLPSCD) */ +#define USB0_PORTSC1_H_PHCD_SHIFT (23) +#define USB0_PORTSC1_H_PHCD (1 << USB0_PORTSC1_H_PHCD_SHIFT) + +/* PFSC: Port force full speed connect */ +#define USB0_PORTSC1_H_PFSC_SHIFT (24) +#define USB0_PORTSC1_H_PFSC (1 << USB0_PORTSC1_H_PFSC_SHIFT) + +/* PSPD: Port speed */ +#define USB0_PORTSC1_H_PSPD_SHIFT (26) +#define USB0_PORTSC1_H_PSPD_MASK (0x3 << USB0_PORTSC1_H_PSPD_SHIFT) +#define USB0_PORTSC1_H_PSPD(x) ((x) << USB0_PORTSC1_H_PSPD_SHIFT) + +/* --- USB0_OTGSC values ---------------------------------------- */ + +/* VD: VBUS_Discharge */ +#define USB0_OTGSC_VD_SHIFT (0) +#define USB0_OTGSC_VD (1 << USB0_OTGSC_VD_SHIFT) + +/* VC: VBUS_Charge */ +#define USB0_OTGSC_VC_SHIFT (1) +#define USB0_OTGSC_VC (1 << USB0_OTGSC_VC_SHIFT) + +/* HAAR: Hardware assist auto_reset */ +#define USB0_OTGSC_HAAR_SHIFT (2) +#define USB0_OTGSC_HAAR (1 << USB0_OTGSC_HAAR_SHIFT) + +/* OT: OTG termination */ +#define USB0_OTGSC_OT_SHIFT (3) +#define USB0_OTGSC_OT (1 << USB0_OTGSC_OT_SHIFT) + +/* DP: Data pulsing */ +#define USB0_OTGSC_DP_SHIFT (4) +#define USB0_OTGSC_DP (1 << USB0_OTGSC_DP_SHIFT) + +/* IDPU: ID pull-up */ +#define USB0_OTGSC_IDPU_SHIFT (5) +#define USB0_OTGSC_IDPU (1 << USB0_OTGSC_IDPU_SHIFT) + +/* HADP: Hardware assist data pulse */ +#define USB0_OTGSC_HADP_SHIFT (6) +#define USB0_OTGSC_HADP (1 << USB0_OTGSC_HADP_SHIFT) + +/* HABA: Hardware assist B-disconnect to A-connect */ +#define USB0_OTGSC_HABA_SHIFT (7) +#define USB0_OTGSC_HABA (1 << USB0_OTGSC_HABA_SHIFT) + +/* ID: USB ID */ +#define USB0_OTGSC_ID_SHIFT (8) +#define USB0_OTGSC_ID (1 << USB0_OTGSC_ID_SHIFT) + +/* AVV: A-VBUS valid */ +#define USB0_OTGSC_AVV_SHIFT (9) +#define USB0_OTGSC_AVV (1 << USB0_OTGSC_AVV_SHIFT) + +/* ASV: A-session valid */ +#define USB0_OTGSC_ASV_SHIFT (10) +#define USB0_OTGSC_ASV (1 << USB0_OTGSC_ASV_SHIFT) + +/* BSV: B-session valid */ +#define USB0_OTGSC_BSV_SHIFT (11) +#define USB0_OTGSC_BSV (1 << USB0_OTGSC_BSV_SHIFT) + +/* BSE: B-session end */ +#define USB0_OTGSC_BSE_SHIFT (12) +#define USB0_OTGSC_BSE (1 << USB0_OTGSC_BSE_SHIFT) + +/* MS1T: 1 millisecond timer toggle */ +#define USB0_OTGSC_MS1T_SHIFT (13) +#define USB0_OTGSC_MS1T (1 << USB0_OTGSC_MS1T_SHIFT) + +/* DPS: Data bus pulsing status */ +#define USB0_OTGSC_DPS_SHIFT (14) +#define USB0_OTGSC_DPS (1 << USB0_OTGSC_DPS_SHIFT) + +/* IDIS: USB ID interrupt status */ +#define USB0_OTGSC_IDIS_SHIFT (16) +#define USB0_OTGSC_IDIS (1 << USB0_OTGSC_IDIS_SHIFT) + +/* AVVIS: A-VBUS valid interrupt status */ +#define USB0_OTGSC_AVVIS_SHIFT (17) +#define USB0_OTGSC_AVVIS (1 << USB0_OTGSC_AVVIS_SHIFT) + +/* ASVIS: A-Session valid interrupt status */ +#define USB0_OTGSC_ASVIS_SHIFT (18) +#define USB0_OTGSC_ASVIS (1 << USB0_OTGSC_ASVIS_SHIFT) + +/* BSVIS: B-Session valid interrupt status */ +#define USB0_OTGSC_BSVIS_SHIFT (19) +#define USB0_OTGSC_BSVIS (1 << USB0_OTGSC_BSVIS_SHIFT) + +/* BSEIS: B-Session end interrupt status */ +#define USB0_OTGSC_BSEIS_SHIFT (20) +#define USB0_OTGSC_BSEIS (1 << USB0_OTGSC_BSEIS_SHIFT) + +/* MS1S: 1 millisecond timer interrupt status */ +#define USB0_OTGSC_MS1S_SHIFT (21) +#define USB0_OTGSC_MS1S (1 << USB0_OTGSC_MS1S_SHIFT) + +/* DPIS: Data pulse interrupt status */ +#define USB0_OTGSC_DPIS_SHIFT (22) +#define USB0_OTGSC_DPIS (1 << USB0_OTGSC_DPIS_SHIFT) + +/* IDIE: USB ID interrupt enable */ +#define USB0_OTGSC_IDIE_SHIFT (24) +#define USB0_OTGSC_IDIE (1 << USB0_OTGSC_IDIE_SHIFT) + +/* AVVIE: A-VBUS valid interrupt enable */ +#define USB0_OTGSC_AVVIE_SHIFT (25) +#define USB0_OTGSC_AVVIE (1 << USB0_OTGSC_AVVIE_SHIFT) + +/* ASVIE: A-session valid interrupt enable */ +#define USB0_OTGSC_ASVIE_SHIFT (26) +#define USB0_OTGSC_ASVIE (1 << USB0_OTGSC_ASVIE_SHIFT) + +/* BSVIE: B-session valid interrupt enable */ +#define USB0_OTGSC_BSVIE_SHIFT (27) +#define USB0_OTGSC_BSVIE (1 << USB0_OTGSC_BSVIE_SHIFT) + +/* BSEIE: B-session end interrupt enable */ +#define USB0_OTGSC_BSEIE_SHIFT (28) +#define USB0_OTGSC_BSEIE (1 << USB0_OTGSC_BSEIE_SHIFT) + +/* MS1E: 1 millisecond timer interrupt enable */ +#define USB0_OTGSC_MS1E_SHIFT (29) +#define USB0_OTGSC_MS1E (1 << USB0_OTGSC_MS1E_SHIFT) + +/* DPIE: Data pulse interrupt enable */ +#define USB0_OTGSC_DPIE_SHIFT (30) +#define USB0_OTGSC_DPIE (1 << USB0_OTGSC_DPIE_SHIFT) + +/* --- USB0_USBMODE_D values ------------------------------------ */ + +/* CM1_0: Controller mode */ +#define USB0_USBMODE_D_CM1_0_SHIFT (0) +#define USB0_USBMODE_D_CM1_0_MASK (0x3 << USB0_USBMODE_D_CM1_0_SHIFT) +#define USB0_USBMODE_D_CM1_0(x) ((x) << USB0_USBMODE_D_CM1_0_SHIFT) + +/* ES: Endian select */ +#define USB0_USBMODE_D_ES_SHIFT (2) +#define USB0_USBMODE_D_ES (1 << USB0_USBMODE_D_ES_SHIFT) + +/* SLOM: Setup Lockout mode */ +#define USB0_USBMODE_D_SLOM_SHIFT (3) +#define USB0_USBMODE_D_SLOM (1 << USB0_USBMODE_D_SLOM_SHIFT) + +/* SDIS: Setup Lockout mode */ +#define USB0_USBMODE_D_SDIS_SHIFT (4) +#define USB0_USBMODE_D_SDIS (1 << USB0_USBMODE_D_SDIS_SHIFT) + +/* --- USB0_USBMODE_H values ------------------------------------ */ + +/* CM: Controller mode */ +#define USB0_USBMODE_H_CM_SHIFT (0) +#define USB0_USBMODE_H_CM_MASK (0x3 << USB0_USBMODE_H_CM_SHIFT) +#define USB0_USBMODE_H_CM(x) ((x) << USB0_USBMODE_H_CM_SHIFT) + +/* ES: Endian select */ +#define USB0_USBMODE_H_ES_SHIFT (2) +#define USB0_USBMODE_H_ES (1 << USB0_USBMODE_H_ES_SHIFT) + +/* SDIS: Stream disable mode */ +#define USB0_USBMODE_H_SDIS_SHIFT (4) +#define USB0_USBMODE_H_SDIS (1 << USB0_USBMODE_H_SDIS_SHIFT) + +/* VBPS: VBUS power select */ +#define USB0_USBMODE_H_VBPS_SHIFT (5) +#define USB0_USBMODE_H_VBPS (1 << USB0_USBMODE_H_VBPS_SHIFT) + +/* --- USB0_ENDPTSETUPSTAT values ------------------------------- */ + +/* ENDPSETUPSTAT: Setup endpoint status for logical endpoints 0 to 5 */ +#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0) +#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK \ + (0x3f << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) +#define USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) \ + ((x) << USB0_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT) + +/* --- USB0_ENDPTPRIME values ----------------------------------- */ + +/* PERB: Prime endpoint receive buffer for physical OUT endpoints 5 to 0 */ +#define USB0_ENDPTPRIME_PERB_SHIFT (0) +#define USB0_ENDPTPRIME_PERB_MASK (0x3f << USB0_ENDPTPRIME_PERB_SHIFT) +#define USB0_ENDPTPRIME_PERB(x) ((x) << USB0_ENDPTPRIME_PERB_SHIFT) + +/* PETB: Prime endpoint transmit buffer for physical IN endpoints 5 to 0 */ +#define USB0_ENDPTPRIME_PETB_SHIFT (16) +#define USB0_ENDPTPRIME_PETB_MASK (0x3f << USB0_ENDPTPRIME_PETB_SHIFT) +#define USB0_ENDPTPRIME_PETB(x) ((x) << USB0_ENDPTPRIME_PETB_SHIFT) + +/* --- USB0_ENDPTFLUSH values ----------------------------------- */ + +/* FERB: Flush endpoint receive buffer for physical OUT endpoints 5 to 0 */ +#define USB0_ENDPTFLUSH_FERB_SHIFT (0) +#define USB0_ENDPTFLUSH_FERB_MASK (0x3f << USB0_ENDPTFLUSH_FERB_SHIFT) +#define USB0_ENDPTFLUSH_FERB(x) ((x) << USB0_ENDPTFLUSH_FERB_SHIFT) + +/* FETB: Flush endpoint transmit buffer for physical IN endpoints 5 to 0 */ +#define USB0_ENDPTFLUSH_FETB_SHIFT (16) +#define USB0_ENDPTFLUSH_FETB_MASK (0x3f << USB0_ENDPTFLUSH_FETB_SHIFT) +#define USB0_ENDPTFLUSH_FETB(x) ((x) << USB0_ENDPTFLUSH_FETB_SHIFT) + +/* --- USB0_ENDPTSTAT values ------------------------------------ */ + +/* ERBR: Endpoint receive buffer ready for physical OUT endpoints 5 to 0 */ +#define USB0_ENDPTSTAT_ERBR_SHIFT (0) +#define USB0_ENDPTSTAT_ERBR_MASK (0x3f << USB0_ENDPTSTAT_ERBR_SHIFT) +#define USB0_ENDPTSTAT_ERBR(x) ((x) << USB0_ENDPTSTAT_ERBR_SHIFT) + +/* ETBR: Endpoint transmit buffer ready for physical IN endpoints 3 to 0 */ +#define USB0_ENDPTSTAT_ETBR_SHIFT (16) +#define USB0_ENDPTSTAT_ETBR_MASK (0x3f << USB0_ENDPTSTAT_ETBR_SHIFT) +#define USB0_ENDPTSTAT_ETBR(x) ((x) << USB0_ENDPTSTAT_ETBR_SHIFT) + +/* --- USB0_ENDPTCOMPLETE values -------------------------------- */ + +/* ERCE: Endpoint receive complete event for physical OUT endpoints 5 to 0 */ +#define USB0_ENDPTCOMPLETE_ERCE_SHIFT (0) +#define USB0_ENDPTCOMPLETE_ERCE_MASK (0x3f << USB0_ENDPTCOMPLETE_ERCE_SHIFT) +#define USB0_ENDPTCOMPLETE_ERCE(x) ((x) << USB0_ENDPTCOMPLETE_ERCE_SHIFT) + +/* ETCE: Endpoint transmit complete event for physical IN endpoints 5 to 0 */ +#define USB0_ENDPTCOMPLETE_ETCE_SHIFT (16) +#define USB0_ENDPTCOMPLETE_ETCE_MASK (0x3f << USB0_ENDPTCOMPLETE_ETCE_SHIFT) +#define USB0_ENDPTCOMPLETE_ETCE(x) ((x) << USB0_ENDPTCOMPLETE_ETCE_SHIFT) + +/* --- USB0_ENDPTCTRL0 values ----------------------------------- */ + +/* RXS: Rx endpoint stall */ +#define USB0_ENDPTCTRL0_RXS_SHIFT (0) +#define USB0_ENDPTCTRL0_RXS (1 << USB0_ENDPTCTRL0_RXS_SHIFT) + +/* RXT1_0: Endpoint type */ +#define USB0_ENDPTCTRL0_RXT1_0_SHIFT (2) +#define USB0_ENDPTCTRL0_RXT1_0_MASK (0x3 << USB0_ENDPTCTRL0_RXT1_0_SHIFT) +#define USB0_ENDPTCTRL0_RXT1_0(x) ((x) << USB0_ENDPTCTRL0_RXT1_0_SHIFT) + +/* RXE: Rx endpoint enable */ +#define USB0_ENDPTCTRL0_RXE_SHIFT (7) +#define USB0_ENDPTCTRL0_RXE (1 << USB0_ENDPTCTRL0_RXE_SHIFT) + +/* TXS: Tx endpoint stall */ +#define USB0_ENDPTCTRL0_TXS_SHIFT (16) +#define USB0_ENDPTCTRL0_TXS (1 << USB0_ENDPTCTRL0_TXS_SHIFT) + +/* TXT1_0: Endpoint type */ +#define USB0_ENDPTCTRL0_TXT1_0_SHIFT (18) +#define USB0_ENDPTCTRL0_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL0_TXT1_0_SHIFT) +#define USB0_ENDPTCTRL0_TXT1_0(x) ((x) << USB0_ENDPTCTRL0_TXT1_0_SHIFT) + +/* TXE: Tx endpoint enable */ +#define USB0_ENDPTCTRL0_TXE_SHIFT (23) +#define USB0_ENDPTCTRL0_TXE (1 << USB0_ENDPTCTRL0_TXE_SHIFT) + +/* --- USB0_ENDPTCTRL1 values ----------------------------------- */ + +/* RXS: Rx endpoint stall */ +#define USB0_ENDPTCTRL1_RXS_SHIFT (0) +#define USB0_ENDPTCTRL1_RXS (1 << USB0_ENDPTCTRL1_RXS_SHIFT) + +/* RXT: Endpoint type */ +#define USB0_ENDPTCTRL1_RXT_SHIFT (2) +#define USB0_ENDPTCTRL1_RXT_MASK (0x3 << USB0_ENDPTCTRL1_RXT_SHIFT) +#define USB0_ENDPTCTRL1_RXT(x) ((x) << USB0_ENDPTCTRL1_RXT_SHIFT) + +/* RXI: Rx data toggle inhibit */ +#define USB0_ENDPTCTRL1_RXI_SHIFT (5) +#define USB0_ENDPTCTRL1_RXI (1 << USB0_ENDPTCTRL1_RXI_SHIFT) + +/* RXR: Rx data toggle reset */ +#define USB0_ENDPTCTRL1_RXR_SHIFT (6) +#define USB0_ENDPTCTRL1_RXR (1 << USB0_ENDPTCTRL1_RXR_SHIFT) + +/* RXE: Rx endpoint enable */ +#define USB0_ENDPTCTRL1_RXE_SHIFT (7) +#define USB0_ENDPTCTRL1_RXE (1 << USB0_ENDPTCTRL1_RXE_SHIFT) + +/* TXS: Tx endpoint stall */ +#define USB0_ENDPTCTRL1_TXS_SHIFT (16) +#define USB0_ENDPTCTRL1_TXS (1 << USB0_ENDPTCTRL1_TXS_SHIFT) + +/* TXT1_0: Tx Endpoint type */ +#define USB0_ENDPTCTRL1_TXT1_0_SHIFT (18) +#define USB0_ENDPTCTRL1_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL1_TXT1_0_SHIFT) +#define USB0_ENDPTCTRL1_TXT1_0(x) ((x) << USB0_ENDPTCTRL1_TXT1_0_SHIFT) + +/* TXI: Tx data toggle inhibit */ +#define USB0_ENDPTCTRL1_TXI_SHIFT (21) +#define USB0_ENDPTCTRL1_TXI (1 << USB0_ENDPTCTRL1_TXI_SHIFT) + +/* TXR: Tx data toggle reset */ +#define USB0_ENDPTCTRL1_TXR_SHIFT (22) +#define USB0_ENDPTCTRL1_TXR (1 << USB0_ENDPTCTRL1_TXR_SHIFT) + +/* TXE: Tx endpoint enable */ +#define USB0_ENDPTCTRL1_TXE_SHIFT (23) +#define USB0_ENDPTCTRL1_TXE (1 << USB0_ENDPTCTRL1_TXE_SHIFT) + +/* --- USB0_ENDPTCTRL2 values ----------------------------------- */ + +/* RXS: Rx endpoint stall */ +#define USB0_ENDPTCTRL2_RXS_SHIFT (0) +#define USB0_ENDPTCTRL2_RXS (1 << USB0_ENDPTCTRL2_RXS_SHIFT) + +/* RXT: Endpoint type */ +#define USB0_ENDPTCTRL2_RXT_SHIFT (2) +#define USB0_ENDPTCTRL2_RXT_MASK (0x3 << USB0_ENDPTCTRL2_RXT_SHIFT) +#define USB0_ENDPTCTRL2_RXT(x) ((x) << USB0_ENDPTCTRL2_RXT_SHIFT) + +/* RXI: Rx data toggle inhibit */ +#define USB0_ENDPTCTRL2_RXI_SHIFT (5) +#define USB0_ENDPTCTRL2_RXI (1 << USB0_ENDPTCTRL2_RXI_SHIFT) + +/* RXR: Rx data toggle reset */ +#define USB0_ENDPTCTRL2_RXR_SHIFT (6) +#define USB0_ENDPTCTRL2_RXR (1 << USB0_ENDPTCTRL2_RXR_SHIFT) + +/* RXE: Rx endpoint enable */ +#define USB0_ENDPTCTRL2_RXE_SHIFT (7) +#define USB0_ENDPTCTRL2_RXE (1 << USB0_ENDPTCTRL2_RXE_SHIFT) + +/* TXS: Tx endpoint stall */ +#define USB0_ENDPTCTRL2_TXS_SHIFT (16) +#define USB0_ENDPTCTRL2_TXS (1 << USB0_ENDPTCTRL2_TXS_SHIFT) + +/* TXT1_0: Tx Endpoint type */ +#define USB0_ENDPTCTRL2_TXT1_0_SHIFT (18) +#define USB0_ENDPTCTRL2_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL2_TXT1_0_SHIFT) +#define USB0_ENDPTCTRL2_TXT1_0(x) ((x) << USB0_ENDPTCTRL2_TXT1_0_SHIFT) + +/* TXI: Tx data toggle inhibit */ +#define USB0_ENDPTCTRL2_TXI_SHIFT (21) +#define USB0_ENDPTCTRL2_TXI (1 << USB0_ENDPTCTRL2_TXI_SHIFT) + +/* TXR: Tx data toggle reset */ +#define USB0_ENDPTCTRL2_TXR_SHIFT (22) +#define USB0_ENDPTCTRL2_TXR (1 << USB0_ENDPTCTRL2_TXR_SHIFT) + +/* TXE: Tx endpoint enable */ +#define USB0_ENDPTCTRL2_TXE_SHIFT (23) +#define USB0_ENDPTCTRL2_TXE (1 << USB0_ENDPTCTRL2_TXE_SHIFT) + +/* --- USB0_ENDPTCTRL3 values ----------------------------------- */ + +/* RXS: Rx endpoint stall */ +#define USB0_ENDPTCTRL3_RXS_SHIFT (0) +#define USB0_ENDPTCTRL3_RXS (1 << USB0_ENDPTCTRL3_RXS_SHIFT) + +/* RXT: Endpoint type */ +#define USB0_ENDPTCTRL3_RXT_SHIFT (2) +#define USB0_ENDPTCTRL3_RXT_MASK (0x3 << USB0_ENDPTCTRL3_RXT_SHIFT) +#define USB0_ENDPTCTRL3_RXT(x) ((x) << USB0_ENDPTCTRL3_RXT_SHIFT) + +/* RXI: Rx data toggle inhibit */ +#define USB0_ENDPTCTRL3_RXI_SHIFT (5) +#define USB0_ENDPTCTRL3_RXI (1 << USB0_ENDPTCTRL3_RXI_SHIFT) + +/* RXR: Rx data toggle reset */ +#define USB0_ENDPTCTRL3_RXR_SHIFT (6) +#define USB0_ENDPTCTRL3_RXR (1 << USB0_ENDPTCTRL3_RXR_SHIFT) + +/* RXE: Rx endpoint enable */ +#define USB0_ENDPTCTRL3_RXE_SHIFT (7) +#define USB0_ENDPTCTRL3_RXE (1 << USB0_ENDPTCTRL3_RXE_SHIFT) + +/* TXS: Tx endpoint stall */ +#define USB0_ENDPTCTRL3_TXS_SHIFT (16) +#define USB0_ENDPTCTRL3_TXS (1 << USB0_ENDPTCTRL3_TXS_SHIFT) + +/* TXT1_0: Tx Endpoint type */ +#define USB0_ENDPTCTRL3_TXT1_0_SHIFT (18) +#define USB0_ENDPTCTRL3_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL3_TXT1_0_SHIFT) +#define USB0_ENDPTCTRL3_TXT1_0(x) ((x) << USB0_ENDPTCTRL3_TXT1_0_SHIFT) + +/* TXI: Tx data toggle inhibit */ +#define USB0_ENDPTCTRL3_TXI_SHIFT (21) +#define USB0_ENDPTCTRL3_TXI (1 << USB0_ENDPTCTRL3_TXI_SHIFT) + +/* TXR: Tx data toggle reset */ +#define USB0_ENDPTCTRL3_TXR_SHIFT (22) +#define USB0_ENDPTCTRL3_TXR (1 << USB0_ENDPTCTRL3_TXR_SHIFT) + +/* TXE: Tx endpoint enable */ +#define USB0_ENDPTCTRL3_TXE_SHIFT (23) +#define USB0_ENDPTCTRL3_TXE (1 << USB0_ENDPTCTRL3_TXE_SHIFT) + +/* --- USB0_ENDPTCTRL4 values ----------------------------------- */ + +/* RXS: Rx endpoint stall */ +#define USB0_ENDPTCTRL4_RXS_SHIFT (0) +#define USB0_ENDPTCTRL4_RXS (1 << USB0_ENDPTCTRL4_RXS_SHIFT) + +/* RXT: Endpoint type */ +#define USB0_ENDPTCTRL4_RXT_SHIFT (2) +#define USB0_ENDPTCTRL4_RXT_MASK (0x3 << USB0_ENDPTCTRL4_RXT_SHIFT) +#define USB0_ENDPTCTRL4_RXT(x) ((x) << USB0_ENDPTCTRL4_RXT_SHIFT) + +/* RXI: Rx data toggle inhibit */ +#define USB0_ENDPTCTRL4_RXI_SHIFT (5) +#define USB0_ENDPTCTRL4_RXI (1 << USB0_ENDPTCTRL4_RXI_SHIFT) + +/* RXR: Rx data toggle reset */ +#define USB0_ENDPTCTRL4_RXR_SHIFT (6) +#define USB0_ENDPTCTRL4_RXR (1 << USB0_ENDPTCTRL4_RXR_SHIFT) + +/* RXE: Rx endpoint enable */ +#define USB0_ENDPTCTRL4_RXE_SHIFT (7) +#define USB0_ENDPTCTRL4_RXE (1 << USB0_ENDPTCTRL4_RXE_SHIFT) + +/* TXS: Tx endpoint stall */ +#define USB0_ENDPTCTRL4_TXS_SHIFT (16) +#define USB0_ENDPTCTRL4_TXS (1 << USB0_ENDPTCTRL4_TXS_SHIFT) + +/* TXT1_0: Tx Endpoint type */ +#define USB0_ENDPTCTRL4_TXT1_0_SHIFT (18) +#define USB0_ENDPTCTRL4_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL4_TXT1_0_SHIFT) +#define USB0_ENDPTCTRL4_TXT1_0(x) ((x) << USB0_ENDPTCTRL4_TXT1_0_SHIFT) + +/* TXI: Tx data toggle inhibit */ +#define USB0_ENDPTCTRL4_TXI_SHIFT (21) +#define USB0_ENDPTCTRL4_TXI (1 << USB0_ENDPTCTRL4_TXI_SHIFT) + +/* TXR: Tx data toggle reset */ +#define USB0_ENDPTCTRL4_TXR_SHIFT (22) +#define USB0_ENDPTCTRL4_TXR (1 << USB0_ENDPTCTRL4_TXR_SHIFT) + +/* TXE: Tx endpoint enable */ +#define USB0_ENDPTCTRL4_TXE_SHIFT (23) +#define USB0_ENDPTCTRL4_TXE (1 << USB0_ENDPTCTRL4_TXE_SHIFT) + +/* --- USB0_ENDPTCTRL5 values ----------------------------------- */ + +/* RXS: Rx endpoint stall */ +#define USB0_ENDPTCTRL5_RXS_SHIFT (0) +#define USB0_ENDPTCTRL5_RXS (1 << USB0_ENDPTCTRL5_RXS_SHIFT) + +/* RXT: Endpoint type */ +#define USB0_ENDPTCTRL5_RXT_SHIFT (2) +#define USB0_ENDPTCTRL5_RXT_MASK (0x3 << USB0_ENDPTCTRL5_RXT_SHIFT) +#define USB0_ENDPTCTRL5_RXT(x) ((x) << USB0_ENDPTCTRL5_RXT_SHIFT) + +/* RXI: Rx data toggle inhibit */ +#define USB0_ENDPTCTRL5_RXI_SHIFT (5) +#define USB0_ENDPTCTRL5_RXI (1 << USB0_ENDPTCTRL5_RXI_SHIFT) + +/* RXR: Rx data toggle reset */ +#define USB0_ENDPTCTRL5_RXR_SHIFT (6) +#define USB0_ENDPTCTRL5_RXR (1 << USB0_ENDPTCTRL5_RXR_SHIFT) + +/* RXE: Rx endpoint enable */ +#define USB0_ENDPTCTRL5_RXE_SHIFT (7) +#define USB0_ENDPTCTRL5_RXE (1 << USB0_ENDPTCTRL5_RXE_SHIFT) + +/* TXS: Tx endpoint stall */ +#define USB0_ENDPTCTRL5_TXS_SHIFT (16) +#define USB0_ENDPTCTRL5_TXS (1 << USB0_ENDPTCTRL5_TXS_SHIFT) + +/* TXT1_0: Tx Endpoint type */ +#define USB0_ENDPTCTRL5_TXT1_0_SHIFT (18) +#define USB0_ENDPTCTRL5_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL5_TXT1_0_SHIFT) +#define USB0_ENDPTCTRL5_TXT1_0(x) ((x) << USB0_ENDPTCTRL5_TXT1_0_SHIFT) + +/* TXI: Tx data toggle inhibit */ +#define USB0_ENDPTCTRL5_TXI_SHIFT (21) +#define USB0_ENDPTCTRL5_TXI (1 << USB0_ENDPTCTRL5_TXI_SHIFT) + +/* TXR: Tx data toggle reset */ +#define USB0_ENDPTCTRL5_TXR_SHIFT (22) +#define USB0_ENDPTCTRL5_TXR (1 << USB0_ENDPTCTRL5_TXR_SHIFT) + +/* TXE: Tx endpoint enable */ +#define USB0_ENDPTCTRL5_TXE_SHIFT (23) +#define USB0_ENDPTCTRL5_TXE (1 << USB0_ENDPTCTRL5_TXE_SHIFT) + +/* -------------------------------------------------------------- */ + + +/* --- USB0_ENDPTCTRL common values ----------------------------- */ + +/* RXS: Rx endpoint stall */ +#define USB0_ENDPTCTRL_RXS_SHIFT (0) +#define USB0_ENDPTCTRL_RXS (1 << USB0_ENDPTCTRL_RXS_SHIFT) + +/* RXT: Endpoint type */ +#define USB0_ENDPTCTRL_RXT_SHIFT (2) +#define USB0_ENDPTCTRL_RXT_MASK (0x3 << USB0_ENDPTCTRL_RXT_SHIFT) +#define USB0_ENDPTCTRL_RXT(x) ((x) << USB0_ENDPTCTRL_RXT_SHIFT) + +/* RXI: Rx data toggle inhibit */ +#define USB0_ENDPTCTRL_RXI_SHIFT (5) +#define USB0_ENDPTCTRL_RXI (1 << USB0_ENDPTCTRL_RXI_SHIFT) + +/* RXR: Rx data toggle reset */ +#define USB0_ENDPTCTRL_RXR_SHIFT (6) +#define USB0_ENDPTCTRL_RXR (1 << USB0_ENDPTCTRL_RXR_SHIFT) + +/* RXE: Rx endpoint enable */ +#define USB0_ENDPTCTRL_RXE_SHIFT (7) +#define USB0_ENDPTCTRL_RXE (1 << USB0_ENDPTCTRL_RXE_SHIFT) + +/* TXS: Tx endpoint stall */ +#define USB0_ENDPTCTRL_TXS_SHIFT (16) +#define USB0_ENDPTCTRL_TXS (1 << USB0_ENDPTCTRL_TXS_SHIFT) + +/* TXT1_0: Tx Endpoint type */ +#define USB0_ENDPTCTRL_TXT1_0_SHIFT (18) +#define USB0_ENDPTCTRL_TXT1_0_MASK (0x3 << USB0_ENDPTCTRL_TXT1_0_SHIFT) +#define USB0_ENDPTCTRL_TXT1_0(x) ((x) << USB0_ENDPTCTRL_TXT1_0_SHIFT) + +/* TXI: Tx data toggle inhibit */ +#define USB0_ENDPTCTRL_TXI_SHIFT (21) +#define USB0_ENDPTCTRL_TXI (1 << USB0_ENDPTCTRL_TXI_SHIFT) + +/* TXR: Tx data toggle reset */ +#define USB0_ENDPTCTRL_TXR_SHIFT (22) +#define USB0_ENDPTCTRL_TXR (1 << USB0_ENDPTCTRL_TXR_SHIFT) + +/* TXE: Tx endpoint enable */ +#define USB0_ENDPTCTRL_TXE_SHIFT (23) +#define USB0_ENDPTCTRL_TXE (1 << USB0_ENDPTCTRL_TXE_SHIFT) + + + + + +/* --- USB1 registers ------------------------------------------------------ */ +/* TODO */ + +#endif diff --git a/libopencm3/include/libopencm3/lpc43xx/wwdt.h b/libopencm3/include/libopencm3/lpc43xx/wwdt.h new file mode 100644 index 0000000..30ff6a7 --- /dev/null +++ b/libopencm3/include/libopencm3/lpc43xx/wwdt.h @@ -0,0 +1,65 @@ +/** @defgroup wwdt_defines Windowed Watchdog Timer + +@brief Defined Constants and Types for the LPC43xx Windowed Watchdog +Timer + +@ingroup LPC43xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 Michael Ossmann + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Michael Ossmann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LPC43XX_WWDT_H +#define LPC43XX_WWDT_H + +/**@{*/ + +#include +#include + +/* --- Windowed Watchdog Timer (WWDT) registers ---------------------------- */ + +/* Watchdog mode register */ +#define WWDT_MOD MMIO32(WWDT_BASE + 0x000) + +/* Watchdog timer constant register */ +#define WWDT_TC MMIO32(WWDT_BASE + 0x004) + +/* Watchdog feed sequence register */ +#define WWDT_FEED MMIO32(WWDT_BASE + 0x008) + +/* Watchdog timer value register */ +#define WWDT_TV MMIO32(WWDT_BASE + 0x00C) + +/* Watchdog warning interrupt register */ +#define WWDT_WARNINT MMIO32(WWDT_BASE + 0x014) + +/* Watchdog timer window register */ +#define WWDT_WINDOW MMIO32(WWDT_BASE + 0x018) + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/sam/3a/irq.json b/libopencm3/include/libopencm3/sam/3a/irq.json new file mode 100644 index 0000000..c3d8c10 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/3a/irq.json @@ -0,0 +1,52 @@ +{ + "irqs": [ + "supc", + "rstc", + "rtc", + "rtt", + "wdt", + "pmc", + "eefc0", + "eefc1", + "uart", + "smc_sdramc", + "sdramc", + "pioa", + "piob", + "pioc", + "piod", + "pioe", + "piof", + "usart0", + "usart1", + "usart2", + "usart3", + "hsmci", + "twi0", + "twi1", + "spi0", + "spi1", + "ssc", + "tc0", + "tc1", + "tc2", + "tc3", + "tc4", + "tc5", + "tc6", + "tc7", + "tc8", + "pwm", + "adc", + "dacc", + "dmac", + "uotghs", + "trng", + "reserved0", + "can0", + "can1" + ], + "partname_humanreadable": "Atmel SAM3A series", + "partname_doxygen": "SAM3A", + "includeguard": "LIBOPENCM3_SAM3A_NVIC_H" +} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/sam/3a/memorymap.h b/libopencm3/include/libopencm3/sam/3a/memorymap.h new file mode 100644 index 0000000..90d97c6 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/3a/memorymap.h @@ -0,0 +1,77 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Gareth McMullin + * Copyright (C) 2014 Felix Held + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM3A_MEMORYMAP_H +#define SAM3A_MEMORYMAP_H + +#include + +/* --- SAM3A peripheral space -------------------------------------------- */ +#define HSMCI_BASE (0x40000000U) +#define SSC_BASE (0x40004000U) +#define SPI0_BASE (0x40008000U) +#define SPI1_BASE (0x4000C000U) +#define TC0_BASE (0x40080000U) +#define TC1_BASE (0x40080040U) +#define TC2_BASE (0x40080080U) +#define TC3_BASE (0x40084000U) +#define TC4_BASE (0x40084040U) +#define TC5_BASE (0x40084080U) +#define TC6_BASE (0x40088000U) +#define TC7_BASE (0x40088040U) +#define TC8_BASE (0x40088080U) +#define TWI0_BASE (0x4008C000U) +#define TWI1_BASE (0x40090000U) +#define PWM_BASE (0x40094000U) +#define USART0_BASE (0x40098000U) +#define USART1_BASE (0x4009C000U) +#define USART2_BASE (0x400A0000U) +#define USART3_BASE (0x400A4000U) +#define UOTGHS_BASE (0x400AC000U) +#define CAN0_BASE (0x400B4000U) +#define CAN1_BASE (0x400B8000U) +#define TRNG_BASE (0x400BC000U) +#define ADC_BASE (0x400C0000U) +#define DMAC_BASE (0x400C4000U) +#define DACC_BASE (0x400C8000U) + +/* --- SAM3A system controller space ------------------------------------- */ +#define SMC_BASE (0x400E0000U) +#define SDRAM_BASE (0x400E0200U) +#define MATRIX_BASE (0x400E0400U) +#define PMC_BASE (0x400E0600U) +#define UART_BASE (0x400E0800U) +#define CHIPID_BASE (0x400E0940U) +#define EEFC0_BASE (0x400E0A00U) +#define EEFC1_BASE (0x400E0C00U) +#define PIOA_BASE (0x400E0E00U) +#define PIOB_BASE (0x400E1000U) +#define PIOC_BASE (0x400E1200U) +#define PIOD_BASE (0x400E1400U) +#define PIOE_BASE (0x400E1600U) +#define PIOF_BASE (0x400E1800U) +#define RSTC_BASE (0x400E1A00U) +#define SUPC_BASE (0x400E1A10U) +#define RTT_BASE (0x400E1A30U) +#define WDT_BASE (0x400E1A50U) +#define RTC_BASE (0x400E1A60U) +#define GPBR_BASE (0x400E1A90U) + +#endif diff --git a/libopencm3/include/libopencm3/sam/3n/irq.json b/libopencm3/include/libopencm3/sam/3n/irq.json new file mode 100644 index 0000000..9d1d39e --- /dev/null +++ b/libopencm3/include/libopencm3/sam/3n/irq.json @@ -0,0 +1,39 @@ +{ + "irqs": [ + "supc", + "rstc", + "rtc", + "rtt", + "wdt", + "pmc", + "eefc", + "reserved0", + "uart0", + "uart1", + "reserved1", + "pioa", + "piob", + "pioc", + "usart0", + "usart1", + "reserved2", + "reserved3", + "reserved4", + "twi0", + "twi1", + "spi", + "reserved5", + "tc0", + "tc1", + "tc2", + "tc3", + "tc4", + "tc5", + "adc", + "dacc", + "pwm" + ], + "partname_humanreadable": "Atmel SAM3N series", + "partname_doxygen": "SAM3N", + "includeguard": "LIBOPENCM3_SAM3N_NVIC_H" +} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/sam/3n/memorymap.h b/libopencm3/include/libopencm3/sam/3n/memorymap.h new file mode 100644 index 0000000..34c193f --- /dev/null +++ b/libopencm3/include/libopencm3/sam/3n/memorymap.h @@ -0,0 +1,60 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM3N_MEMORYMAP_H +#define SAM3N_MEMORYMAP_H + +#include + +/* --- SAM3N peripheral space -------------------------------------------- */ + +#define SPI_BASE (0x40008000U) +#define TC0_BASE (0x40010000U) +#define TC1_BASE (0x40010040U) +#define TC2_BASE (0x40010080U) +#define TC3_BASE (0x40014000U) +#define TC4_BASE (0x40014040U) +#define TC5_BASE (0x40014080U) +#define TWI0_BASE (0x40018000U) +#define TWI1_BASE (0x4001C000U) +#define PWM_BASE (0x40020000U) +#define USART0_BASE (0x40024000U) +#define USART1_BASE (0x40028000U) +#define ADC_BASE (0x40038000U) +#define DACC_BASE (0x4003C000U) + +/* --- SAM3N system controller space ------------------------------------- */ +#define SMC_BASE (0x400E0000U) +#define MATRIX_BASE (0x400E0200U) +#define PMC_BASE (0x400E0400U) +#define UART0_BASE (0x400E0600U) +#define CHIPID_BASE (0x400E0740U) +#define UART1_BASE (0x400E0800U) +#define EEFC_BASE (0x400E0A00U) +#define PIOA_BASE (0x400E0E00U) +#define PIOB_BASE (0x400E1000U) +#define PIOC_BASE (0x400E1200U) +#define RSTC_BASE (0x400E1400U) +#define SUPC_BASE (0x400E1410U) +#define RTT_BASE (0x400E1430U) +#define WDT_BASE (0x400E1450U) +#define RTC_BASE (0x400E1460U) +#define GPBR_BASE (0x400E1490U) + +#endif diff --git a/libopencm3/include/libopencm3/sam/3s/irq.json b/libopencm3/include/libopencm3/sam/3s/irq.json new file mode 100644 index 0000000..ddf76f6 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/3s/irq.json @@ -0,0 +1,42 @@ +{ + "irqs": [ + "supc", + "rstc", + "rtc", + "rtt", + "wdt", + "pmc", + "eefc", + "reserved0", + "uart0", + "uart1", + "smc", + "pioa", + "piob", + "pioc", + "usart0", + "usart1", + "usart2", + "reserved1", + "hsmci", + "twi0", + "twi1", + "spi", + "ssc", + "tc0", + "tc1", + "tc2", + "tc3", + "tc4", + "tc5", + "adc", + "dacc", + "pwm", + "crccu", + "acc", + "udp" + ], + "partname_humanreadable": "Atmel SAM3S series", + "partname_doxygen": "SAM3S", + "includeguard": "LIBOPENCM3_SAM3S_NVIC_H" +} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/sam/3s/memorymap.h b/libopencm3/include/libopencm3/sam/3s/memorymap.h new file mode 100644 index 0000000..0ce7200 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/3s/memorymap.h @@ -0,0 +1,66 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Gareth McMullin + * Copyright (C) 2014 Felix Held + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM3S_MEMORYMAP_H +#define SAM3S_MEMORYMAP_H + +#include + +/* --- SAM3S peripheral space -------------------------------------------- */ +#define HSMCI_BASE (0x40000000U) +#define SSC_BASE (0x40004000U) +#define SPI_BASE (0x40008000U) +#define TC0_BASE (0x40010000U) +#define TC1_BASE (0x40010040U) +#define TC2_BASE (0x40010080U) +#define TC3_BASE (0x40014000U) +#define TC4_BASE (0x40014040U) +#define TC5_BASE (0x40014080U) +#define TWI0_BASE (0x40018000U) +#define TWI1_BASE (0x4001C000U) +#define PWM_BASE (0x40020000U) +#define USART0_BASE (0x40024000U) +#define USART1_BASE (0x40028000U) +#define USART2_BASE (0x4002C000U) +#define UDP_BASE (0x40034000U) +#define ADC_BASE (0x40038000U) +#define DACC_BASE (0x4003C000U) +#define ACC_BASE (0x40040000U) +#define CRCCU_BASE (0x40044000U) + +/* --- SAM3S system controller space ------------------------------------- */ +#define SMC_BASE (0x400E0000U) +#define MATRIX_BASE (0x400E0200U) +#define PMC_BASE (0x400E0400U) +#define UART0_BASE (0x400E0600U) +#define CHIPID_BASE (0x400E0740U) +#define UART1_BASE (0x400E0800U) +#define EEFC_BASE (0x400E0A00U) +#define PIOA_BASE (0x400E0E00U) +#define PIOB_BASE (0x400E1000U) +#define PIOC_BASE (0x400E1200U) +#define RSTC_BASE (0x400E1400U) +#define SUPC_BASE (0x400E1410U) +#define RTT_BASE (0x400E1430U) +#define WDT_BASE (0x400E1450U) +#define RTC_BASE (0x400E1460U) +#define GPBR_BASE (0x400E1490U) + +#endif diff --git a/libopencm3/include/libopencm3/sam/3u/irq.json b/libopencm3/include/libopencm3/sam/3u/irq.json new file mode 100644 index 0000000..c52f183 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/3u/irq.json @@ -0,0 +1,37 @@ +{ + "irqs": [ + "supc", + "rstc", + "rtc", + "rtt", + "wdt", + "pmc", + "eefc0", + "eefc1", + "uart", + "smc", + "pioa", + "piob", + "pioc", + "usart0", + "usart1", + "usart2", + "usart3", + "hsmci", + "twi0", + "twi1", + "spi", + "ssc", + "tc0", + "tc1", + "tc2", + "pwm", + "adc12b", + "adc", + "dmac", + "udphs" + ], + "partname_humanreadable": "Atmel SAM3U series", + "partname_doxygen": "SAM3U", + "includeguard": "LIBOPENCM3_SAM3U_NVIC_H" +} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/sam/3u/memorymap.h b/libopencm3/include/libopencm3/sam/3u/memorymap.h new file mode 100644 index 0000000..edd2f29 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/3u/memorymap.h @@ -0,0 +1,63 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Gareth McMullin + * Copyright (C) 2014 Felix Held + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM3U_MEMORYMAP_H +#define SAM3U_MEMORYMAP_H + +#include + +/* --- SAM3U peripheral space -------------------------------------------- */ +#define HSMCI_BASE (0x40000000U) +#define SSC_BASE (0x40004000U) +#define SPI_BASE (0x40008000U) +#define TC0_BASE (0x40080000U) +#define TC1_BASE (0x40080040U) +#define TC2_BASE (0x40080080U) +#define TWI0_BASE (0x40084000U) +#define TWI1_BASE (0x40088000U) +#define PWM_BASE (0x4008C000U) +#define USART0_BASE (0x40090000U) +#define USART1_BASE (0x40094000U) +#define USART2_BASE (0x40098000U) +#define USART3_BASE (0x4009C000U) +#define UDPHS_BASE (0x400A4000U) +#define ADC12B_BASE (0x400A8000U) +#define ADC_BASE (0x400AC000U) +#define DMAC_BASE (0x400B0000U) + +/* --- SAM3U system controller space ------------------------------------- */ +#define SMC_BASE (0x400E0000U) +#define MATRIX_BASE (0x400E0200U) +#define PMC_BASE (0x400E0400U) +#define UART_BASE (0x400E0600U) +#define CHIPID_BASE (0x400E0740U) +#define EEFC0_BASE (0x400E0800U) +#define EEFC1_BASE (0x400E0A00U) +#define PIOA_BASE (0x400E0C00U) +#define PIOB_BASE (0x400E0E00U) +#define PIOC_BASE (0x400E1000U) +#define RSTC_BASE (0x400E1200U) +#define SUPC_BASE (0x400E1210U) +#define RTT_BASE (0x400E1230U) +#define WDT_BASE (0x400E1250U) +#define RTC_BASE (0x400E1260U) +#define GPBR_BASE (0x400E1290U) + +#endif diff --git a/libopencm3/include/libopencm3/sam/3x/irq.json b/libopencm3/include/libopencm3/sam/3x/irq.json new file mode 100644 index 0000000..c53d63c --- /dev/null +++ b/libopencm3/include/libopencm3/sam/3x/irq.json @@ -0,0 +1,52 @@ +{ + "irqs": [ + "supc", + "rstc", + "rtc", + "rtt", + "wdt", + "pmc", + "eefc0", + "eefc1", + "uart", + "smc_sdramc", + "sdramc", + "pioa", + "piob", + "pioc", + "piod", + "pioe", + "piof", + "usart0", + "usart1", + "usart2", + "usart3", + "hsmci", + "twi0", + "twi1", + "spi0", + "spi1", + "ssc", + "tc0", + "tc1", + "tc2", + "tc3", + "tc4", + "tc5", + "tc6", + "tc7", + "tc8", + "pwm", + "adc", + "dacc", + "dmac", + "uotghs", + "trng", + "emac", + "can0", + "can1" + ], + "partname_humanreadable": "Atmel SAM3X series", + "partname_doxygen": "SAM3X", + "includeguard": "LIBOPENCM3_SAM3X_NVIC_H" +} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/sam/3x/memorymap.h b/libopencm3/include/libopencm3/sam/3x/memorymap.h new file mode 100644 index 0000000..dea04bb --- /dev/null +++ b/libopencm3/include/libopencm3/sam/3x/memorymap.h @@ -0,0 +1,78 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM3X_MEMORYMAP_H +#define SAM3X_MEMORYMAP_H + +#include + +/* --- SAM3X peripheral space -------------------------------------------- */ + +#define HSMCI_BASE (0x40000000U) +#define SSC_BASE (0x40004000U) +#define SPI0_BASE (0x40008000U) +#define SPI1_BASE (0x4000C000U) +#define TC0_BASE (0x40080000U) +#define TC1_BASE (0x40080040U) +#define TC2_BASE (0x40080080U) +#define TC3_BASE (0x40084000U) +#define TC4_BASE (0x40084040U) +#define TC5_BASE (0x40084080U) +#define TC6_BASE (0x40088000U) +#define TC7_BASE (0x40088040U) +#define TC8_BASE (0x40088080U) +#define TWI0_BASE (0x4008C000U) +#define TWI1_BASE (0x40090000U) +#define PWM_BASE (0x40094000U) +#define USART0_BASE (0x40098000U) +#define USART1_BASE (0x4009C000U) +#define USART2_BASE (0x400A0000U) +#define USART3_BASE (0x400A4000U) +#define UOTGHS_BASE (0x400AC000U) +#define EMAC_BASE (0x400B0000U) +#define CAN0_BASE (0x400B4000U) +#define CAN1_BASE (0x400B8000U) +#define TRNG_BASE (0x400BC000U) +#define ADC_BASE (0x400C0000U) +#define DMAC_BASE (0x400C4000U) +#define DACC_BASE (0x400C8000U) + +/* --- SAM3X system controller space ------------------------------------- */ +#define SMC_BASE (0x400E0000U) +#define SDRAM_BASE (0x400E0200U) +#define MATRIX_BASE (0x400E0400U) +#define PMC_BASE (0x400E0600U) +#define UART_BASE (0x400E0800U) +#define CHIPID_BASE (0x400E0940U) +#define EEFC0_BASE (0x400E0A00U) +#define EEFC1_BASE (0x400E0C00U) +#define PIOA_BASE (0x400E0E00U) +#define PIOB_BASE (0x400E1000U) +#define PIOC_BASE (0x400E1200U) +#define PIOD_BASE (0x400E1400U) +#define PIOE_BASE (0x400E1600U) +#define PIOF_BASE (0x400E1800U) +#define RSTC_BASE (0x400E1A00U) +#define SUPC_BASE (0x400E1A10U) +#define RTT_BASE (0x400E1A30U) +#define WDT_BASE (0x400E1A50U) +#define RTC_BASE (0x400E1A60U) +#define GPBR_BASE (0x400E1A90U) + +#endif diff --git a/libopencm3/include/libopencm3/sam/eefc.h b/libopencm3/include/libopencm3/sam/eefc.h new file mode 100644 index 0000000..eb6d4d0 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/eefc.h @@ -0,0 +1,83 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM3X_EEFC_H +#define SAM3X_EEFC_H + +#include +#include + +/* --- Convenience macros ------------------------------------------------ */ +#define EEFC EEFC_BASE +#define EEFC0 EEFC0_BASE +#define EEFC1 EEFC1_BASE + +/* --- Enhanced Embedded Flash Controller (EEFC) registers --------------- */ +#define EEFC_FMR(port) MMIO32((port) + 0x00) +#define EEFC_FCR(port) MMIO32((port) + 0x04) +#define EEFC_FSR(port) MMIO32((port) + 0x08) +#define EEFC_FRR(port) MMIO32((port) + 0x0C) +/* 0x0010 - Reserved */ + + +/* EEFC Flash Mode Register (EEFC_FMR) */ +/* Bit [31:25] - Reserved */ +#define EEFC_FMR_FAM (0x01 << 24) +/* Bit [23:12] - Reserved */ +#define EEFC_FMR_FWS_MASK (0x0F << 8) +/* Bit [7:1] - Reserved */ +#define EEFC_FMR_FRDY (0x01 << 0) + +/* EEFC Flash Command Register (EEFC_FCR) */ +#define EEFC_FCR_FKEY (0x5A << 24) +#define EEFC_FCR_FARG_MASK (0xFFFF << 8) +#define EEFC_FCR_FCMD_MASK (0xFF << 0) +#define EEFC_FCR_FCMD_GETD (0x00 << 0) +#define EEFC_FCR_FCMD_WP (0x01 << 0) +#define EEFC_FCR_FCMD_WPL (0x02 << 0) +#define EEFC_FCR_FCMD_EWP (0x03 << 0) +#define EEFC_FCR_FCMD_EWPL (0x04 << 0) +#define EEFC_FCR_FCMD_EA (0x05 << 0) +#define EEFC_FCR_FCMD_SLB (0x08 << 0) +#define EEFC_FCR_FCMD_CLB (0x09 << 0) +#define EEFC_FCR_FCMD_GLB (0x0A << 0) +#define EEFC_FCR_FCMD_SGPB (0x0B << 0) +#define EEFC_FCR_FCMD_CGPB (0x0C << 0) +#define EEFC_FCR_FCMD_GGPB (0x0D << 0) +#define EEFC_FCR_FCMD_STUI (0x0E << 0) +#define EEFC_FCR_FCMD_SPUI (0x0F << 0) + +/* EEFC Flash Status Register (EEFC_FSR) */ +/* Bit [31:3] - Reserved */ +#define EEFC_FSR_FLOCKE (0x01 << 2) +#define EEFC_FSR_FCMDE (0x01 << 1) +#define EEFC_FSR_FRDY (0x01 << 0) + +static inline void eefc_set_latency(uint8_t wait) +{ +#if defined(SAM3A) || defined(SAM3U) || defined(SAM3X) + EEFC_FMR(EEFC0) = (EEFC_FMR(EEFC0) & ~EEFC_FMR_FWS_MASK) | (wait << 8); + EEFC_FMR(EEFC1) = (EEFC_FMR(EEFC1) & ~EEFC_FMR_FWS_MASK) | (wait << 8); +#elif defined(SAM3N) || defined(SAM3S) + EEFC_FMR(EEFC) = (EEFC_FMR(EEFC) & ~EEFC_FMR_FWS_MASK) | (wait << 8); +#endif +} + +#endif + diff --git a/libopencm3/include/libopencm3/sam/gpio.h b/libopencm3/include/libopencm3/sam/gpio.h new file mode 100644 index 0000000..20fd9ad --- /dev/null +++ b/libopencm3/include/libopencm3/sam/gpio.h @@ -0,0 +1,51 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM3X_GPIO_H +#define SAM3X_GPIO_H + +#include + +/* flags may be or'd together, but only contain one of + * GPOUTPUT, PERIPHA and PERIPHB */ +enum gpio_flags { + GPIO_FLAG_GPINPUT = 0, + GPIO_FLAG_GPOUTPUT = 1, + GPIO_FLAG_PERIPHA = 2, + GPIO_FLAG_PERIPHB = 3, + GPIO_FLAG_OPEN_DRAIN = 4, + GPIO_FLAG_PULL_UP = 8, +}; + +void gpio_init(uint32_t gpioport, uint32_t pins, enum gpio_flags flags); + +static inline void gpio_set(uint32_t gpioport, uint32_t gpios) +{ + PIO_SODR(gpioport) = gpios; +} + +static inline void gpio_clear(uint32_t gpioport, uint32_t gpios) +{ + PIO_CODR(gpioport) = gpios; +} + +void gpio_toggle(uint32_t gpioport, uint32_t gpios); + +#endif + diff --git a/libopencm3/include/libopencm3/sam/memorymap.h b/libopencm3/include/libopencm3/sam/memorymap.h new file mode 100644 index 0000000..eb1b85b --- /dev/null +++ b/libopencm3/include/libopencm3/sam/memorymap.h @@ -0,0 +1,39 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin + * Copyright (C) 2014 Felix Held + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM_MEMORYMAP_H +#define SAM_MEMORYMAP_H + +#if defined(SAM3A) +# include +#elif defined(SAM3N) +# include +#elif defined(SAM3S) +# include +#elif defined(SAM3U) +# include +#elif defined(SAM3X) +# include +#else +# error "Processor family not defined." +#endif + +#endif + diff --git a/libopencm3/include/libopencm3/sam/pio.h b/libopencm3/include/libopencm3/sam/pio.h new file mode 100644 index 0000000..3288718 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/pio.h @@ -0,0 +1,96 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM_PIO_H +#define SAM_PIO_H + +#include +#include + +/* --- Convenience macros ------------------------------------------------ */ + +/* GPIO port base addresses (for convenience) */ +#define PIOA PIOA_BASE +#define PIOB PIOB_BASE +#define PIOC PIOC_BASE +#define PIOD PIOD_BASE +#define PIOE PIOE_BASE +#define PIOF PIOF_BASE +#define PIOG PIOG_BASE +#define PIOH PIOH_BASE + +/* --- PIO registers ----------------------------------------------------- */ + +#define PIO_PER(port) MMIO32((port) + 0x0000) +#define PIO_PDR(port) MMIO32((port) + 0x0004) +#define PIO_PSR(port) MMIO32((port) + 0x0008) +/* 0x000C - Reserved */ +#define PIO_OER(port) MMIO32((port) + 0x0010) +#define PIO_ODR(port) MMIO32((port) + 0x0014) +#define PIO_OSR(port) MMIO32((port) + 0x0018) +/* 0x001C - Reserved */ +#define PIO_IFER(port) MMIO32((port) + 0x0020) +#define PIO_IFDR(port) MMIO32((port) + 0x0024) +#define PIO_IFSR(port) MMIO32((port) + 0x0028) +/* 0x002C - Reserved */ +#define PIO_SODR(port) MMIO32((port) + 0x0030) +#define PIO_CODR(port) MMIO32((port) + 0x0034) +#define PIO_ODSR(port) MMIO32((port) + 0x0038) +#define PIO_PDSR(port) MMIO32((port) + 0x003C) +#define PIO_IER(port) MMIO32((port) + 0x0040) +#define PIO_IDR(port) MMIO32((port) + 0x0044) +#define PIO_IMR(port) MMIO32((port) + 0x0048) +#define PIO_ISR(port) MMIO32((port) + 0x004C) +#define PIO_MDER(port) MMIO32((port) + 0x0050) +#define PIO_MDDR(port) MMIO32((port) + 0x0054) +#define PIO_MDSR(port) MMIO32((port) + 0x0058) +/* 0x005C - Reserved */ +#define PIO_PUDR(port) MMIO32((port) + 0x0060) +#define PIO_PUER(port) MMIO32((port) + 0x0064) +#define PIO_PUSR(port) MMIO32((port) + 0x0068) +/* 0x006C - Reserved */ +#define PIO_ABSR(port) MMIO32((port) + 0x0070) +/* 0x0074-0x007C - Reserved */ +#define PIO_SCIFSR(port) MMIO32((port) + 0x0080) +#define PIO_DIFSR(port) MMIO32((port) + 0x0084) +#define PIO_IFDGSR(port) MMIO32((port) + 0x0088) +#define PIO_SCDR(port) MMIO32((port) + 0x008C) +/* 0x0090-0x009C - Reserved */ +#define PIO_OWER(port) MMIO32((port) + 0x00A0) +#define PIO_OWDR(port) MMIO32((port) + 0x00A4) +#define PIO_OWSR(port) MMIO32((port) + 0x00A8) +/* 0x00AC - Reserved */ +#define PIO_AIMER(port) MMIO32((port) + 0x00B0) +#define PIO_AIMDR(port) MMIO32((port) + 0x00B4) +#define PIO_AIMMR(port) MMIO32((port) + 0x00B8) +/* 0x00BC - Reserved */ +#define PIO_ESR(port) MMIO32((port) + 0x00C0) +#define PIO_LSR(port) MMIO32((port) + 0x00C4) +#define PIO_ELSR(port) MMIO32((port) + 0x00C8) +/* 0x00CC - Reserved */ +#define PIO_FELLSR(port) MMIO32((port) + 0x00D0) +#define PIO_REHLSR(port) MMIO32((port) + 0x00D4) +#define PIO_FRLHSR(port) MMIO32((port) + 0x00D8) +/* 0x00DC - Reserved */ +#define PIO_LOCKSR(port) MMIO32((port) + 0x00E0) +#define PIO_WPMR(port) MMIO32((port) + 0x00E4) +#define PIO_WPSR(port) MMIO32((port) + 0x00E8) +/* 0x00EC-0x0144 - Reserved */ + +#endif diff --git a/libopencm3/include/libopencm3/sam/pmc.h b/libopencm3/include/libopencm3/sam/pmc.h new file mode 100644 index 0000000..ab90148 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/pmc.h @@ -0,0 +1,146 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM3X_PMC_H +#define SAM3X_PMC_H + +#include +#include + +/* --- Power Management Controller (PMC) registers ----------------------- */ + +#define PMC_SCER MMIO32(PMC_BASE + 0x0000) +#define PMC_SCDR MMIO32(PMC_BASE + 0x0004) +#define PMC_SCSR MMIO32(PMC_BASE + 0x0008) +/* 0x000C - Reserved */ +#define PMC_PCER0 MMIO32(PMC_BASE + 0x0010) +#define PMC_PCDR0 MMIO32(PMC_BASE + 0x0014) +#define PMC_PCSR0 MMIO32(PMC_BASE + 0x0018) +#define CKGR_UCKR MMIO32(PMC_BASE + 0x001C) +#define CKGR_MOR MMIO32(PMC_BASE + 0x0020) +#define CKGR_MCFR MMIO32(PMC_BASE + 0x0024) +#define CKGR_PLLAR MMIO32(PMC_BASE + 0x0028) +/* 0x002C - Reserved */ +#define PMC_MCKR MMIO32(PMC_BASE + 0x0030) +/* 0x0034 - Reserved */ +#define PMC_USB MMIO32(PMC_BASE + 0x0038) +/* 0x003C - Reserved */ +#define PMC_PCK0 MMIO32(PMC_BASE + 0x0040) +#define PMC_PCK1 MMIO32(PMC_BASE + 0x0044) +#define PMC_PCK2 MMIO32(PMC_BASE + 0x0048) +/* 0x004C-0x005C - Reserved */ +#define PMC_IER MMIO32(PMC_BASE + 0x0060) +#define PMC_IDR MMIO32(PMC_BASE + 0x0064) +#define PMC_SR MMIO32(PMC_BASE + 0x0068) +#define PMC_IMR MMIO32(PMC_BASE + 0x006C) +#define PMC_FSMR MMIO32(PMC_BASE + 0x0070) +#define PMC_FSPR MMIO32(PMC_BASE + 0x0074) +#define PMC_FOCR MMIO32(PMC_BASE + 0x0078) +/* 0x007C-0x00E0 - Reserved */ +#define PMC_WPMR MMIO32(PMC_BASE + 0x00E4) +#define PMC_WPSR MMIO32(PMC_BASE + 0x00E8) +/* 0x00EC-0x00FC - Reserved */ +#define PMC_PCER1 MMIO32(PMC_BASE + 0x0100) +#define PMC_PCDR1 MMIO32(PMC_BASE + 0x0104) +#define PMC_PCSR1 MMIO32(PMC_BASE + 0x0108) +#define PMC_PCR MMIO32(PMC_BASE + 0x010C) + +/* PMC UTMI Clock Configuration Register (CKGR_UCKR) */ +/* Bit [31:22] - Reserved */ +#define CKGR_CKGR_UPLLCOUNT_MASK (0x0F << 20) +/* Bit [19:17] - Reserved */ +#define CKGR_CKGR_UPLLEN (0x01 << 16) +/* Bit [15:0] - Reserved */ + +/* PMC Clock Generator Main Oscillator Register (CKGR_MOR) */ +/* Bit [31:26] - Reserved */ +#define CKGR_MOR_CFDEN (0x01 << 25) +#define CKGR_MOR_MOSCSEL (0x01 << 24) +#define CKGR_MOR_KEY (0x37 << 16) +#define CKGR_MOR_MOSCXTST_MASK (0xFF << 8) +/* Bit 7 - Reserved */ +#define CKGR_MOR_MOSCRCF_MASK (0x07 << 4) +#define CKGR_MOR_MOSCRCEN (0x01 << 3) +/* Bit 2 - Reserved */ +#define CKGR_MOR_MOSCXTBY (0x01 << 1) +#define CKGR_MOR_MOSCXTEN (0x01 << 0) + +/* PMC Clock Generator PLLA Register (CKGR_PLLAR) */ +#define CKGR_PLLAR_ONE (0x01 << 29) +#define CKGR_PLLAR_MULA_MASK (0x7FF << 16) +#define CKGR_PLLAR_PLLACOUNT_MASK (0x3F << 8) +#define CKGR_PLLAR_DIVA_MASK (0xFF << 0) + +/* PMC Master Clock Register (PMC_MCKR) */ +/* Bit [31:14] - Reserved */ +#define PMC_MCKR_UPLLDIV2 (0x01 << 13) +#define PMC_MCKR_PLLADIV2 (0x01 << 12) +/* Bit [11:7] - Reserved */ +#define PMC_MCKR_PRES_MASK (0x07 << 4) +/* Bit [3:2] - Reserved */ +#define PMC_MCKR_CSS_MASK (0x03 << 0) +#define PMC_MCKR_CSS_SLOW_CLK (0x00 << 0) +#define PMC_MCKR_CSS_MAIN_CLK (0x01 << 0) +#define PMC_MCKR_CSS_PLLA_CLK (0x02 << 0) +#define PMC_MCKR_CSS_UPLL_CLK (0x03 << 0) + +/* PMC USB Clock Register (PMC_USB) */ +/* Bit [31:12] - Reserved */ +#define PMC_USB_USBDIV_MASK (0x0F << 8) +/* Bit [7:1] - Reserved */ +#define PMC_USB_USBS (0x01 << 0) + +/* PMC Status Register (PMC_SR) */ +/* Bits [31:21] - Reserved */ +#define PMC_SR_FOS (0x01 << 20) +#define PMC_SR_CFDS (0x01 << 19) +#define PMC_SR_CFDEV (0x01 << 18) +#define PMC_SR_MOSCRCS (0x01 << 17) +#define PMC_SR_MOSCSELS (0x01 << 16) +/* Bits [15:11] - Reserved */ +#define PMC_SR_PCKRDY2 (0x01 << 10) +#define PMC_SR_PCKRDY1 (0x01 << 9) +#define PMC_SR_PCKRDY0 (0x01 << 8) +#define PMC_SR_OSCSELS (0x01 << 7) +#define PMC_SR_LOCKU (0x01 << 6) +/* Bits [5:4] - Reserved */ +#define PMC_SR_MCKRDY (0x01 << 3) +/* Bit [2] - Reserved */ +#define PMC_SR_LOCKA (0x01 << 1) +#define PMC_SR_MOSCXTS (0x01 << 0) + +extern uint32_t pmc_mck_frequency; + +enum mck_src { + MCK_SRC_SLOW = 0, + MCK_SRC_MAIN = 1, + MCK_SRC_PLLA = 2, + MCK_SRC_UPLL = 3, +}; + +void pmc_mck_set_source(enum mck_src src); +void pmc_xtal_enable(bool en, uint8_t startup_time); +void pmc_plla_config(uint8_t mul, uint8_t div); +void pmc_peripheral_clock_enable(uint8_t pid); +void pmc_peripheral_clock_disable(uint8_t pid); +void pmc_clock_setup_in_xtal_12mhz_out_84mhz(void); +void pmc_clock_setup_in_rc_4mhz_out_84mhz(void); + +#endif + diff --git a/libopencm3/include/libopencm3/sam/pwm.h b/libopencm3/include/libopencm3/sam/pwm.h new file mode 100644 index 0000000..fabb8b1 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/pwm.h @@ -0,0 +1,109 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM3X_PWM_H +#define SAM3X_PWM_H + +#include +#include + +/* --- Pulse Width Modulation (PWM) registers ----------------------- */ + +#define PWM_CLK MMIO32(PWM_BASE + 0x0000) +#define PWM_ENA MMIO32(PWM_BASE + 0x0004) +#define PWM_DIS MMIO32(PWM_BASE + 0x0008) +#define PWM_SR MMIO32(PWM_BASE + 0x000C) +#define PWM_IER1 MMIO32(PWM_BASE + 0x0010) +#define PWM_IDR1 MMIO32(PWM_BASE + 0x0014) +#define PWM_IMR1 MMIO32(PWM_BASE + 0x0018) +#define PWM_ISR1 MMIO32(PWM_BASE + 0x001C) +#define PWM_SCM MMIO32(PWM_BASE + 0x0020) +/* 0x0024 - Reserved */ +#define PWM_SCUC MMIO32(PWM_BASE + 0x0028) +#define PWM_SCUP MMIO32(PWM_BASE + 0x002C) +#define PWM_SCUPUPD MMIO32(PWM_BASE + 0x0030) +#define PWM_IER2 MMIO32(PWM_BASE + 0x0034) +#define PWM_IDR2 MMIO32(PWM_BASE + 0x0038) +#define PWM_IMR2 MMIO32(PWM_BASE + 0x003C) +#define PWM_ISR2 MMIO32(PWM_BASE + 0x0040) +#define PWM_OOV MMIO32(PWM_BASE + 0x0044) +#define PWM_OS MMIO32(PWM_BASE + 0x0048) +#define PWM_OSS MMIO32(PWM_BASE + 0x004C) +#define PWM_OSC MMIO32(PWM_BASE + 0x0050) +#define PWM_OSSUPD MMIO32(PWM_BASE + 0x0054) +#define PWM_OSCUPD MMIO32(PWM_BASE + 0x0058) +#define PWM_FMR MMIO32(PWM_BASE + 0x005C) +#define PWM_FSR MMIO32(PWM_BASE + 0x0060) +#define PWM_FCR MMIO32(PWM_BASE + 0x0064) +#define PWM_FPV MMIO32(PWM_BASE + 0x0068) +#define PWM_FPE1 MMIO32(PWM_BASE + 0x006C) +#define PWM_FPE2 MMIO32(PWM_BASE + 0x0070) +/* 0x0074:0x0078 - Reserved */ +#define PWM_ELMR0 MMIO32(PWM_BASE + 0x007C) +#define PWM_ELMR1 MMIO32(PWM_BASE + 0x0080) +/* 0x0084:0x00AC - Reserved */ +#define PWM_SMMR MMIO32(PWM_BASE + 0x00B0) +/* 0x00B4:0x00E0 - Reserved */ +#define PWM_WPCR MMIO32(PWM_BASE + 0x00E4) +#define PWM_WPSR MMIO32(PWM_BASE + 0x00E8) +/* 0x00EC:0x00FC - Reserved */ +/* 0x0100:0x012C - Reserved */ +#define PWM_CMPV(x) MMIO32(PWM_BASE + 0x0130 + 0x10*(x)) +#define PWM_CMPVUPD(x) MMIO32(PWM_BASE + 0x0134 + 0x10*(x)) +#define PWM_CMMV(x) MMIO32(PWM_BASE + 0x0138 + 0x10*(x)) +#define PWM_CMMVUPD(x) MMIO32(PWM_BASE + 0x013C + 0x10*(x)) +/* 0x01B0:0x01FC - Reserved */ +#define PWM_CMR(x) MMIO32(PWM_BASE + 0x0200 + 0x20*(x)) +#define PWM_CDTY(x) MMIO32(PWM_BASE + 0x0204 + 0x20*(x)) +#if defined(SAM3X) +# define PWM_CDTYUPD(x) MMIO32(PWM_BASE + 0x0208 + 0x20*(x)) +# define PWM_CPRD(x) MMIO32(PWM_BASE + 0x020C + 0x20*(x)) +# define PWM_CPRDUPD(x) MMIO32(PWM_BASE + 0x0210 + 0x20*(x)) +# define PWM_CCNT(x) MMIO32(PWM_BASE + 0x0214 + 0x20*(x)) +# define PWM_DT(x) MMIO32(PWM_BASE + 0x0218 + 0x20*(x)) +# define PWM_DTUPD(x) MMIO32(PWM_BASE + 0x021C + 0x20*(x)) +#elif defined(SAM3N) +# define PWM_CPRD(x) MMIO32(PWM_BASE + 0x0208 + 0x20*(x)) +# define PWM_CCNT(x) MMIO32(PWM_BASE + 0x020C + 0x20*(x)) +# define PWM_CUPD(x) MMIO32(PWM_BASE + 0x0210 + 0x20*(x)) +#else +# error "Processor family not defined." +#endif + +static inline void pwm_set_period(int ch, uint32_t period) +{ + PWM_CPRD(ch) = period; +} + +static inline void pwm_set_duty(int ch, uint32_t duty) +{ + PWM_CDTY(ch) = duty; +} + +static inline void pwm_enable(int ch) +{ + PWM_ENA = 1 << ch; +} + +static inline void pwm_disable(int ch) +{ + PWM_DIS = 1 << ch; +} + +#endif diff --git a/libopencm3/include/libopencm3/sam/tc.h b/libopencm3/include/libopencm3/sam/tc.h new file mode 100644 index 0000000..864cc4a --- /dev/null +++ b/libopencm3/include/libopencm3/sam/tc.h @@ -0,0 +1,52 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM3X_TC_H +#define SAM3X_TC_H + +#include +#include + +/* --- Timer Counter (TC) registers -------------------------------------- */ + +#define TC_CCR(x) MMIO32(TC_BASE + 0x00 + 0x40*(x)) +#define TC_CMR(x) MMIO32(TC_BASE + 0x04 + 0x40*(x)) +#define TC_SMMR(x) MMIO32(TC_BASE + 0x08 + 0x40*(x)) +/* 0x0C + 0x40*channel - Reserved */ +#define TC_CV(x) MMIO32(TC_BASE + 0x10 + 0x40*(x)) +#define TC_RA(x) MMIO32(TC_BASE + 0x14 + 0x40*(x)) +#define TC_RB(x) MMIO32(TC_BASE + 0x18 + 0x40*(x)) +#define TC_RC(x) MMIO32(TC_BASE + 0x1C + 0x40*(x)) +#define TC_SR(x) MMIO32(TC_BASE + 0x20 + 0x40*(x)) +#define TC_IER(x) MMIO32(TC_BASE + 0x24 + 0x40*(x)) +#define TC_IDR(x) MMIO32(TC_BASE + 0x28 + 0x40*(x)) +#define TC_IMR(x) MMIO32(TC_BASE + 0x2C + 0x40*(x)) +#define TC_BCR MMIO32(TC_BASE + 0xC0) +#define TC_BMR MMIO32(TC_BASE + 0xC4) +#define TC_QIER MMIO32(TC_BASE + 0xC8) +#define TC_QIDR MMIO32(TC_BASE + 0xCC) +#define TC_QIMR MMIO32(TC_BASE + 0xD0) +#define TC_QISR MMIO32(TC_BASE + 0xD4) +#define TC_FMR MMIO32(TC_BASE + 0xD8) +/* 0x00DC:0x00E0 - Undocumented */ +#define TC_WPMR MMIO32(TC_BASE + 0xE4) +/* 0x00E8:0x00F8 - Undocumented */ +/* 0x00FC - Reserved */ + +#endif diff --git a/libopencm3/include/libopencm3/sam/uart.h b/libopencm3/include/libopencm3/sam/uart.h new file mode 100644 index 0000000..becfcb5 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/uart.h @@ -0,0 +1,85 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM3X_UART_H +#define SAM3X_UART_H + +#include +#include + +/* --- Universal Asynchronous Receiver Transmitter (UART) registers ------- */ +#define UART_CR MMIO32(UART_BASE + 0x0000) +#define UART_MR MMIO32(UART_BASE + 0x0004) +#define UART_IER MMIO32(UART_BASE + 0x0008) +#define UART_IDR MMIO32(UART_BASE + 0x000C) +#define UART_IMR MMIO32(UART_BASE + 0x0010) +#define UART_SR MMIO32(UART_BASE + 0x0014) +#define UART_RHR MMIO32(UART_BASE + 0x0018) +#define UART_THR MMIO32(UART_BASE + 0x001C) +#define UART_BRGR MMIO32(UART_BASE + 0x0020) +/* 0x0024:0x003C - Reserved */ +/* 0x004C:0x00FC - Reserved */ +/* 0x0100:0x0124 - PDC Area */ + + +/* UART Control Register (UART_CR) */ +/* Bits [31:9] - Reserved */ +#define UART_CR_RSTSTA (0x01 << 8) +#define UART_CR_TXDIS (0x01 << 7) +#define UART_CR_TXEN (0x01 << 6) +#define UART_CR_RXDIS (0x01 << 5) +#define UART_CR_RXEN (0x01 << 4) +#define UART_CR_RSTTX (0x01 << 3) +#define UART_CR_RSTRX (0x01 << 2) +/* Bit [1:0] - Reserved */ + +/* UART Mode Register (UART_MR) */ +/* Bits [31:16] - Reserved */ +#define UART_MR_CHMODE_MASK (0x03 << 14) +#define UART_MR_CHMODE_NORMAL (0x00 << 14) +#define UART_MR_CHMODE_AUTOMATIC (0x01 << 14) +#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x02 << 14) +#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x03 << 14) +/* Bits [13:12] - Reserved */ +#define UART_MR_PAR_MASK (0x07 << 9) +#define UART_MR_PAR_EVEN (0x00 << 9) +#define UART_MR_PAR_ODD (0x01 << 9) +#define UART_MR_PAR_SPACE (0x02 << 9) +#define UART_MR_PAR_MARK (0x03 << 9) +#define UART_MR_PAR_NO (0x04 << 9) +/* Bits [8:0] - Reserved */ + +/* UART Status Register (UART_SR) */ +/* Bits [31:13] - Reserved */ +#define UART_SR_RXBUFF (0x01 << 12) +#define UART_SR_TXBUFF (0x01 << 11) +/* Bit [10] - Reserved */ +#define UART_SR_TXEMPTY (0x01 << 9) +/* Bit [8] - Reserved */ +#define UART_SR_PARE (0x01 << 7) +#define UART_SR_FRAME (0x01 << 6) +#define UART_SR_OVRE (0x01 << 5) +#define UART_SR_ENDTX (0x01 << 4) +#define UART_SR_ENDRX (0x01 << 3) +/* Bit [2] - Reserved */ +#define UART_SR_TXRDY (0x01 << 1) +#define UART_SR_RXRDY (0x01 << 0) + +#endif + diff --git a/libopencm3/include/libopencm3/sam/usart.h b/libopencm3/include/libopencm3/sam/usart.h new file mode 100644 index 0000000..757e93d --- /dev/null +++ b/libopencm3/include/libopencm3/sam/usart.h @@ -0,0 +1,217 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM3X_USART_H +#define SAM3X_USART_H + +#include +#include + +#define USART0 USART0_BASE +#define USART1 USART1_BASE +#define USART2 USART2_BASE +#define USART3 USART3_BASE + +/* --- Universal Synchronous Asynchronous Receiver Transmitter (USART) */ +#define USART_CR(x) MMIO32((x) + 0x0000) +#define USART_MR(x) MMIO32((x) + 0x0004) +#define USART_IER(x) MMIO32((x) + 0x0008) +#define USART_IDR(x) MMIO32((x) + 0x000C) +#define USART_IMR(x) MMIO32((x) + 0x0010) +#define USART_CSR(x) MMIO32((x) + 0x0014) +#define USART_RHR(x) MMIO32((x) + 0x0018) +#define USART_THR(x) MMIO32((x) + 0x001C) +#define USART_BRGR(x) MMIO32((x) + 0x0020) +#define USART_RTOR(x) MMIO32((x) + 0x0024) +#define USART_TTGR(x) MMIO32((x) + 0x0028) +/* 0x002C:0x003C - Reserved */ +#define USART_FIDI(x) MMIO32((x) + 0x0040) +#define USART_NER(x) MMIO32((x) + 0x0044) +#define USART_NER(x) MMIO32((x) + 0x0044) +/* 0x0048 - Reserved */ +#define USART_IF(x) MMIO32((x) + 0x004C) +#define USART_MAN(x) MMIO32((x) + 0x0050) +#define USART_LINMR(x) MMIO32((x) + 0x0054) +#define USART_LINIR(x) MMIO32((x) + 0x0058) +/* 0x005C:0x00E0 - Reserved */ +#define USART_WPMR(x) MMIO32((x) + 0x00E4) +#define USART_WPSR(x) MMIO32((x) + 0x00E8) +/* 0x00EC:0x00F8 - Reserved */ +#define USART_VERSION(x) MMIO32((x) + 0x00FC) +/* 0x0100:0x0124 - PDC Area */ + + +/* USART Control Register (USART_CR) */ +/* Bits [31:22] - Reserved */ +#define USART_CR_LINWKUP (0x01 << 21) +#define USART_CR_LINABT (0x01 << 20) +#define USART_CR_RTSDIS (0x01 << 19) +#define USART_CR_RCS (0x01 << 19) +#define USART_CR_RTSEN (0x01 << 18) +#define USART_CR_FCS (0x01 << 18) +/* Bits [17:16] - Reserved */ +#define USART_CR_RETTO (0x01 << 15) +#define USART_CR_RSTNACK (0x01 << 14) +#define USART_CR_RSTIT (0x01 << 13) +#define USART_CR_SENDA (0x01 << 12) +#define USART_CR_STTTO (0x01 << 11) +#define USART_CR_STPBRK (0x01 << 10) +#define USART_CR_STTBRK (0x01 << 9) +#define USART_CR_RSTSTA (0x01 << 8) +#define USART_CR_TXDIS (0x01 << 7) +#define USART_CR_TXEN (0x01 << 6) +#define USART_CR_RXDIS (0x01 << 5) +#define USART_CR_RXEN (0x01 << 4) +#define USART_CR_RSTTX (0x01 << 3) +#define USART_CR_RSTRX (0x01 << 2) +/* Bits [1:0] - Reserved */ + +/* USART Mode Register (USART_MR) */ +#define USART_MR_ONEBIT (0x01 << 31) +#define USART_MR_MODSYNC (0x01 << 30) +#define USART_MR_MAN (0x01 << 29) +#define USART_MR_FILTER (0x01 << 28) +/* Bit [27] - Reserved */ +#define USART_MR_MAX_ITERATION_MASK (0x07 << 24) +#define USART_MR_INVDATA (0x01 << 23) +#define USART_MR_VAR_SYNC (0x01 << 22) +#define USART_MR_DSNACK (0x01 << 21) +#define USART_MR_INACK (0x01 << 20) +#define USART_MR_OVER (0x01 << 19) +#define USART_MR_CLKO (0x01 << 18) +#define USART_MR_MODE9 (0x01 << 17) +#define USART_MR_MSBF (0x01 << 16) +#define USART_MR_CPOL (0x01 << 16) +#define USART_MR_CHMODE_MASK (0x03 << 14) +#define USART_MR_CHMODE_NORMAL (0x00 << 14) +#define USART_MR_CHMODE_AUTOMATIC (0x01 << 14) +#define USART_MR_CHMODE_LOCAL_LOOPBACK (0x02 << 14) +#define USART_MR_CHMODE_REMOTE_LOOPBACK (0x03 << 14) +#define USART_MR_NBSTOP_MASK (0x03 << 12) +#define USART_MR_NBSTOP_1_BIT (0x00 << 12) +#define USART_MR_NBSTOP_1_5_BIT (0x01 << 12) +#define USART_MR_NBSTOP_2_BIT (0x02 << 12) +/* Bits [13:12] - Reserved */ +#define USART_MR_PAR_MASK (0x07 << 9) +#define USART_MR_PAR_EVEN (0x00 << 9) +#define USART_MR_PAR_ODD (0x01 << 9) +#define USART_MR_PAR_SPACE (0x02 << 9) +#define USART_MR_PAR_MARK (0x03 << 9) +#define USART_MR_PAR_NO (0x04 << 9) +/* Bits [8:0] - Reserved */ +#define USART_MR_SYNC (0x01 << 8) +#define USART_MR_CPHA (0x01 << 8) +#define USART_MR_CHRL_MASK (0x03 << 6) +#define USART_MR_CHRL_5BIT (0x00 << 6) +#define USART_MR_CHRL_6BIT (0x01 << 6) +#define USART_MR_CHRL_7BIT (0x02 << 6) +#define USART_MR_CHRL_8BIT (0x03 << 6) +#define USART_MR_USCLKS_MASK (0x03 << 4) +#define USART_MR_USCLKS_MCK (0x00 << 4) +#define USART_MR_USCLKS_DIV (0x01 << 4) +#define USART_MR_USCLKS_SCK (0x03 << 4) +#define USART_MR_MODE_MASK (0x0F << 0) +#define USART_MR_MODE_NORMAL (0x00 << 0) +#define USART_MR_MODE_RS485 (0x01 << 0) +#define USART_MR_MODE_HW_HANDSHAKING (0x02 << 0) +#define USART_MR_MODE_ISO7816_T_0 (0x03 << 0) +#define USART_MR_MODE_ISO7816_T_1 (0x04 << 0) +#define USART_MR_MODE_IRDA (0x06 << 0) +#define USART_MR_MODE_LIN_MASTER (0x0A << 0) +#define USART_MR_MODE_LIN_SLAVE (0x0B << 0) +#define USART_MR_MODE_SPI_MASTER (0x0E << 0) +#define USART_MR_MODE_SPI_SLAVE (0x0F << 0) + +/* USART Status Register (USART_CSR) */ +/* Bits [31:30] - Reserved */ +#define USART_CSR_LINSNRE (0x01 << 29) +#define USART_CSR_LINCE (0x01 << 28) +#define USART_CSR_LINIPE (0x01 << 27) +#define USART_CSR_LINSFE (0x01 << 26) +#define USART_CSR_LINBE (0x01 << 25) +#define USART_CSR_MANERR (0x01 << 24) +#define USART_CSR_CTS (0x01 << 23) +#define USART_CSR_LINBLS (0x01 << 23) +/* Bits [22:20] - Reserved */ +#define USART_CSR_CTSIC (0x01 << 19) +/* Bits [18:16] - Reserved */ +#define USART_CSR_LINTC (0x01 << 15) +#define USART_CSR_LINID (0x01 << 14) +#define USART_CSR_NACK (0x01 << 13) +#define USART_CSR_LINBK (0x01 << 13) +#define USART_CSR_RXBUFF (0x01 << 12) +#define USART_CSR_TXBUFE (0x01 << 11) +/* Bit [10] - Reserved */ +#define USART_CSR_TXEMPTY (0x01 << 9) +/* Bit [8] - Reserved */ +#define USART_CSR_PARE (0x01 << 7) +#define USART_CSR_FRAME (0x01 << 6) +#define USART_CSR_OVRE (0x01 << 5) +#define USART_CSR_ENDTX (0x01 << 4) +#define USART_CSR_ENDRX (0x01 << 3) +/* Bit [2] - Reserved */ +#define USART_CSR_TXRDY (0x01 << 1) +#define USART_CSR_RXRDY (0x01 << 0) + +enum usart_stopbits { + USART_STOPBITS_1, + USART_STOPBITS_1_5, + USART_STOPBITS_2, +}; + +enum usart_parity { + USART_PARITY_EVEN, + USART_PARITY_ODD, + USART_PARITY_SPACE, + USART_PARITY_MARK, + USART_PARITY_NONE, + USART_PARITY_MULTIDROP, +}; + +enum usart_mode { + USART_MODE_DISABLED, + USART_MODE_RX, + USART_MODE_TX, + USART_MODE_TX_RX, +}; + +enum usart_flowcontrol { + USART_FLOWCONTROL_NONE, + USART_FLOWCONTROL_RTS_CTS, +}; + +void usart_set_baudrate(uint32_t usart, uint32_t baud); +void usart_set_databits(uint32_t usart, int bits); +void usart_set_stopbits(uint32_t usart, enum usart_stopbits); +void usart_set_parity(uint32_t usart, enum usart_parity); +void usart_set_mode(uint32_t usart, enum usart_mode); +void usart_set_flow_control(uint32_t usart, enum usart_flowcontrol); +void usart_enable(uint32_t usart); +void usart_disable(uint32_t usart); +void usart_send(uint32_t usart, uint16_t data); +uint16_t usart_recv(uint32_t usart); +void usart_wait_send_ready(uint32_t usart); +void usart_wait_recv_ready(uint32_t usart); +void usart_send_blocking(uint32_t usart, uint16_t data); +uint16_t usart_recv_blocking(uint32_t usart); +void usart_enable_rx_interrupt(uint32_t usart); +void usart_disable_rx_interrupt(uint32_t usart); + +#endif + diff --git a/libopencm3/include/libopencm3/sam/wdt.h b/libopencm3/include/libopencm3/sam/wdt.h new file mode 100644 index 0000000..566ac95 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/wdt.h @@ -0,0 +1,57 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef SAM3X_WDT_H +#define SAM3X_WDT_H + +#include +#include + + +/* --- WDT registers ----------------------------------------------------- */ + +#define WDT_CR MMIO32(WDT_BASE + 0x00) +#define WDT_MR MMIO32(WDT_BASE + 0x04) +#define WDT_SR MMIO32(WDT_BASE + 0x08) + +/* --- WDT_CR values ------------------------------------------------------ */ + +#define WDT_CR_KEY (0xA5 << 24) +/* Bits [23:1]: Reserved. */ +#define WDT_CR_WDRSTT (1 << 0) + +/* --- WDT_MR values ------------------------------------------------------ */ + +/* Bits [31:32]: Reserved. */ +#define WDT_MR_WDIDLEHLT (1 << 29) +#define WDT_MR_WDDBGHLT (1 << 28) +#define WDT_MR_WDD_MASK (0xFFF << 16) +#define WDT_MR_WDDIS (1 << 15) +#define WDT_MR_WDRPROC (1 << 14) +#define WDT_MR_WDRSTEN (1 << 13) +#define WDT_MR_WDFIEN (1 << 12) +#define WDT_MR_WDV_MASK (0xFFF << 0) + +/* --- WDT_SR values ------------------------------------------------------ */ + +/* Bits [31:2]: Reserved. */ +#define WDT_SR_WDERR (1 << 1) +#define WDT_SR_WDUNF (1 << 0) + +#endif diff --git a/libopencm3/include/libopencm3/stm32/adc.h b/libopencm3/include/libopencm3/stm32/adc.h new file mode 100644 index 0000000..54388be --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/adc.h @@ -0,0 +1,36 @@ +/* This provides unification of code over STM32F subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#if defined(STM32F0) +# include +#elif defined(STM32F1) +# include +#elif defined(STM32F3) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." +#endif + diff --git a/libopencm3/include/libopencm3/stm32/can.h b/libopencm3/include/libopencm3/stm32/can.h new file mode 100644 index 0000000..53b0ef5 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/can.h @@ -0,0 +1,679 @@ +/** @defgroup can_defines CAN defines + +@ingroup STM32F_defines + +@brief libopencm3 Defined Constants and Types for STM32 CAN + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski + +@date 12 November 2012 + +LGPL License Terms @ref lgpl_license +*/ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Piotr Esden-Tempski + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CAN_H +#define LIBOPENCM3_CAN_H + +#include +#include + +/**@{*/ + +/* --- Convenience macros -------------------------------------------------- */ + +/* CAN register base addresses (for convenience) */ +/*****************************************************************************/ +/** @defgroup can_reg_base CAN register base address +@ingroup can_defines + +@{*/ +#define CAN1 BX_CAN1_BASE +#define CAN2 BX_CAN2_BASE +/**@}*/ + +/* --- CAN registers ------------------------------------------------------- */ + +/* CAN master control register (CAN_MCR) */ +#define CAN_MCR(can_base) MMIO32(can_base + 0x000) +/* CAN master status register (CAN_MSR) */ +#define CAN_MSR(can_base) MMIO32(can_base + 0x004) +/* CAN transmit status register (CAN_TSR) */ +#define CAN_TSR(can_base) MMIO32(can_base + 0x008) + +/* CAN receive FIFO 0 register (CAN_RF0R) */ +#define CAN_RF0R(can_base) MMIO32(can_base + 0x00C) +/* CAN receive FIFO 1 register (CAN_RF1R) */ +#define CAN_RF1R(can_base) MMIO32(can_base + 0x010) + +/* CAN interrupt enable register (CAN_IER) */ +#define CAN_IER(can_base) MMIO32(can_base + 0x014) +/* CAN error status register (CAN_ESR) */ +#define CAN_ESR(can_base) MMIO32(can_base + 0x018) +/* CAN bit timing register (CAN_BTR) */ +#define CAN_BTR(can_base) MMIO32(can_base + 0x01C) + +/* Registers in the offset range 0x020 to 0x17F are reserved. */ + +/* --- CAN mailbox registers ----------------------------------------------- */ + +/* CAN mailbox / FIFO register offsets */ +#define CAN_MBOX0 0x180 +#define CAN_MBOX1 0x190 +#define CAN_MBOX2 0x1A0 +#define CAN_FIFO0 0x1B0 +#define CAN_FIFO1 0x1C0 + +/* CAN TX mailbox identifier register (CAN_TIxR) */ +#define CAN_TIxR(can_base, mbox) MMIO32(can_base + mbox + 0x0) +#define CAN_TI0R(can_base) CAN_TIxR(can_base, CAN_MBOX0) +#define CAN_TI1R(can_base) CAN_TIxR(can_base, CAN_MBOX1) +#define CAN_TI2R(can_base) CAN_TIxR(can_base, CAN_MBOX2) + +/* CAN mailbox data length control and time stamp register (CAN_TDTxR) */ +#define CAN_TDTxR(can_base, mbox) MMIO32(can_base + mbox + 0x4) +#define CAN_TDT0R(can_base) CAN_TDTxR(can_base, CAN_MBOX0) +#define CAN_TDT1R(can_base) CAN_TDTxR(can_base, CAN_MBOX1) +#define CAN_TDT2R(can_base) CAN_TDTxR(can_base, CAN_MBOX2) + +/* CAN mailbox data low register (CAN_TDLxR) */ +#define CAN_TDLxR(can_base, mbox) MMIO32(can_base + mbox + 0x8) +#define CAN_TDL0R(can_base) CAN_TDLxR(can_base, CAN_MBOX0) +#define CAN_TDL1R(can_base) CAN_TDLxR(can_base, CAN_MBOX1) +#define CAN_TDL2R(can_base) CAN_TDLxR(can_base, CAN_MBOX2) + +/* CAN mailbox data high register (CAN_TDHxR) */ +#define CAN_TDHxR(can_base, mbox) MMIO32(can_base + mbox + 0xC) +#define CAN_TDH0R(can_base) CAN_TDHxR(can_base, CAN_MBOX0) +#define CAN_TDH1R(can_base) CAN_TDHxR(can_base, CAN_MBOX1) +#define CAN_TDH2R(can_base) CAN_TDHxR(can_base, CAN_MBOX2) + +/* CAN RX FIFO identifier register (CAN_RIxR) */ +#define CAN_RIxR(can_base, fifo) MMIO32(can_base + fifo + 0x0) +#define CAN_RI0R(can_base) CAN_RIxR(can_base, CAN_FIFO0) +#define CAN_RI1R(can_base) CAN_RIxR(can_base, CAN_FIFO1) + +/* CAN RX FIFO mailbox data length control & time stamp register (CAN_RDTxR) */ +#define CAN_RDTxR(can_base, fifo) MMIO32(can_base + fifo + 0x4) +#define CAN_RDT0R(can_base) CAN_RDTxR(can_base, CAN_FIFO0) +#define CAN_RDT1R(can_base) CAN_RDTxR(can_base, CAN_FIFO1) + +/* CAN RX FIFO mailbox data low register (CAN_RDLxR) */ +#define CAN_RDLxR(can_base, fifo) MMIO32(can_base + fifo + 0x8) +#define CAN_RDL0R(can_base) CAN_RDLxR(can_base, CAN_FIFO0) +#define CAN_RDL1R(can_base) CAN_RDLxR(can_base, CAN_FIFO1) + +/* CAN RX FIFO mailbox data high register (CAN_RDHxR) */ +#define CAN_RDHxR(can_base, fifo) MMIO32(can_base + fifo + 0xC) +#define CAN_RDH0R(can_base) CAN_RDHxR(can_base, CAN_FIFO0) +#define CAN_RDH1R(can_base) CAN_RDHxR(can_base, CAN_FIFO1) + +/* --- CAN filter registers ------------------------------------------------ */ + +/* CAN filter master register (CAN_FMR) */ +#define CAN_FMR(can_base) MMIO32(can_base + 0x200) + +/* CAN filter mode register (CAN_FM1R) */ +#define CAN_FM1R(can_base) MMIO32(can_base + 0x204) + +/* Register offset 0x208 is reserved. */ + +/* CAN filter scale register (CAN_FS1R) */ +#define CAN_FS1R(can_base) MMIO32(can_base + 0x20C) + +/* Register offset 0x210 is reserved. */ + +/* CAN filter FIFO assignement register (CAN_FFA1R) */ +#define CAN_FFA1R(can_base) MMIO32(can_base + 0x214) + +/* Register offset 0x218 is reserved. */ + +/* CAN filter activation register (CAN_FA1R) */ +#define CAN_FA1R(can_base) MMIO32(can_base + 0x21C) + +/* Register offset 0x220 is reserved. */ + +/* Registers with offset 0x224 to 0x23F are reserved. */ + +/* CAN filter bank registers (CAN_FiRx) */ +/* + * Connectivity line devices have 28 banks so the bank ID spans 0..27 + * all other devices have 14 banks so the bank ID spans 0..13. + */ +#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + \ + (bank * 0x8) + 0x0) +#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + \ + (bank * 0x8) + 0x4) + +/* --- CAN_MCR values ------------------------------------------------------ */ + +/* 31:17 Reserved, forced by hardware to 0 */ + +/* DBF: Debug freeze */ +#define CAN_MCR_DBF (1 << 16) + +/* RESET: bxCAN software master reset */ +#define CAN_MCR_RESET (1 << 15) + +/* 14:8 Reserved, forced by hardware to 0 */ + +/* TTCM: Time triggered communication mode */ +#define CAN_MCR_TTCM (1 << 7) + +/* ABOM: Automatic bus-off management */ +#define CAN_MCR_ABOM (1 << 6) + +/* AWUM: Automatic wakeup mode */ +#define CAN_MCR_AWUM (1 << 5) + +/* NART: No automatic retransmission */ +#define CAN_MCR_NART (1 << 4) + +/* RFLM: Receive FIFO locked mode */ +#define CAN_MCR_RFLM (1 << 3) + +/* TXFP: Transmit FIFO priority */ +#define CAN_MCR_TXFP (1 << 2) + +/* SLEEP: Sleep mode request */ +#define CAN_MCR_SLEEP (1 << 1) + +/* INRQ: Initialization request */ +#define CAN_MCR_INRQ (1 << 0) + +/* --- CAN_MSR values ------------------------------------------------------ */ + +/* 31:12 Reserved, forced by hardware to 0 */ + +/* RX: CAN Rx signal */ +#define CAN_MSR_RX (1 << 11) + +/* SAMP: Last sample point */ +#define CAN_MSR_SAMP (1 << 10) + +/* RXM: Receive mode */ +#define CAN_MSR_RXM (1 << 9) + +/* TXM: Transmit mode */ +#define CAN_MSR_TXM (1 << 8) + +/* 7:5 Reserved, forced by hardware to 0 */ + +/* SLAKI: Sleep acknowledge interrupt */ +#define CAN_MSR_SLAKI (1 << 4) + +/* WKUI: Wakeup interrupt */ +#define CAN_MSR_WKUI (1 << 3) + +/* ERRI: Error interrupt */ +#define CAN_MSR_ERRI (1 << 2) + +/* SLAK: Sleep acknowledge */ +#define CAN_MSR_SLAK (1 << 1) + +/* INAK: Initialization acknowledge */ +#define CAN_MSR_INAK (1 << 0) + +/* --- CAN_TSR values ------------------------------------------------------ */ + +/* LOW2: Lowest priority flag for mailbox 2 */ +#define CAN_TSR_LOW2 (1 << 31) + +/* LOW1: Lowest priority flag for mailbox 1 */ +#define CAN_TSR_LOW1 (1 << 30) + +/* LOW0: Lowest priority flag for mailbox 0 */ +#define CAN_TSR_LOW0 (1 << 29) + +/* TME2: Transmit mailbox 2 empty */ +#define CAN_TSR_TME2 (1 << 28) + +/* TME1: Transmit mailbox 1 empty */ +#define CAN_TSR_TME1 (1 << 27) + +/* TME0: Transmit mailbox 0 empty */ +#define CAN_TSR_TME0 (1 << 26) + +/* CODE[1:0]: Mailbox code */ +#define CAN_TSR_CODE_MASK (0x3 << 24) + +/* ABRQ2: Abort request for mailbox 2 */ +#define CAN_TSR_TABRQ2 (1 << 23) + +/* 22:20 Reserved, forced by hardware to 0 */ + +/* TERR2: Transmission error for mailbox 2 */ +#define CAN_TSR_TERR2 (1 << 19) + +/* ALST2: Arbitration lost for mailbox 2 */ +#define CAN_TSR_ALST2 (1 << 18) + +/* TXOK2: Transmission OK for mailbox 2 */ +#define CAN_TSR_TXOK2 (1 << 17) + +/* RQCP2: Request completed mailbox 2 */ +#define CAN_TSR_RQCP2 (1 << 16) + +/* ABRQ1: Abort request for mailbox 1 */ +#define CAN_TSR_ABRQ1 (1 << 15) + +/* 14:12 Reserved, forced by hardware to 0 */ + +/* TERR1: Transmission error for mailbox 1 */ +#define CAN_TSR_TERR1 (1 << 11) + +/* ALST1: Arbitration lost for mailbox 1 */ +#define CAN_TSR_ALST1 (1 << 10) + +/* TXOK1: Transmission OK for mailbox 1 */ +#define CAN_TSR_TXOK1 (1 << 9) + +/* RQCP1: Request completed mailbox 1 */ +#define CAN_TSR_RQCP1 (1 << 8) + +/* ABRQ0: Abort request for mailbox 0 */ +#define CAN_TSR_ABRQ0 (1 << 7) + +/* 6:4 Reserved, forced by hardware to 0 */ + +/* TERR0: Transmission error for mailbox 0 */ +#define CAN_TSR_TERR0 (1 << 3) + +/* ALST0: Arbitration lost for mailbox 0 */ +#define CAN_TSR_ALST0 (1 << 2) + +/* TXOK0: Transmission OK for mailbox 0 */ +#define CAN_TSR_TXOK0 (1 << 1) + +/* RQCP0: Request completed mailbox 0 */ +#define CAN_TSR_RQCP0 (1 << 0) + +/* --- CAN_RF0R values ----------------------------------------------------- */ + +/* 31:6 Reserved, forced by hardware to 0 */ + +/* RFOM0: Release FIFO 0 output mailbox */ +#define CAN_RF0R_RFOM0 (1 << 5) + +/* FOVR0: FIFO 0 overrun */ +#define CAN_RF0R_FAVR0 (1 << 4) + +/* FULL0: FIFO 0 full */ +#define CAN_RF0R_FULL0 (1 << 3) + +/* 2 Reserved, forced by hardware to 0 */ + +/* FMP0[1:0]: FIFO 0 message pending */ +#define CAN_RF0R_FMP0_MASK (0x3 << 0) + +/* --- CAN_RF1R values ----------------------------------------------------- */ + +/* 31:6 Reserved, forced by hardware to 0 */ + +/* RFOM1: Release FIFO 1 output mailbox */ +#define CAN_RF1R_RFOM1 (1 << 5) + +/* FOVR1: FIFO 1 overrun */ +#define CAN_RF1R_FAVR1 (1 << 4) + +/* FULL1: FIFO 1 full */ +#define CAN_RF1R_FULL1 (1 << 3) + +/* 2 Reserved, forced by hardware to 0 */ + +/* FMP1[1:0]: FIFO 1 message pending */ +#define CAN_RF1R_FMP1_MASK (0x3 << 0) + +/* --- CAN_IER values ------------------------------------------------------ */ + +/* 32:18 Reserved, forced by hardware to 0 */ + +/* SLKIE: Sleep interrupt enable */ +#define CAN_IER_SLKIE (1 << 17) + +/* WKUIE: Wakeup interrupt enable */ +#define CAN_IER_WKUIE (1 << 16) + +/* ERRIE: Error interrupt enable */ +#define CAN_IER_ERRIE (1 << 15) + +/* 14:12 Reserved, forced by hardware to 0 */ + +/* LECIE: Last error code interrupt enable */ +#define CAN_IER_LECIE (1 << 11) + +/* BOFIE: Bus-off interrupt enable */ +#define CAN_IER_BOFIE (1 << 10) + +/* EPVIE: Error passive interrupt enable */ +#define CAN_IER_EPVIE (1 << 9) + +/* EWGIE: Error warning interrupt enable */ +#define CAN_IER_EWGIE (1 << 8) + +/* 7 Reserved, forced by hardware to 0 */ + +/* FOVIE1: FIFO overrun interrupt enable */ +#define CAN_IER_FOVIE1 (1 << 6) + +/* FFIE1: FIFO full interrupt enable */ +#define CAN_IER_FFIE1 (1 << 5) + +/* FMPIE1: FIFO message pending interrupt enable */ +#define CAN_IER_FMPIE1 (1 << 4) + +/* FOVIE0: FIFO overrun interrupt enable */ +#define CAN_IER_FOVIE0 (1 << 3) + +/* FFIE0: FIFO full interrupt enable */ +#define CAN_IER_FFIE0 (1 << 2) + +/* FMPIE0: FIFO message pending interrupt enable */ +#define CAN_IER_FMPIE0 (1 << 1) + +/* TMEIE: Transmit mailbox empty interrupt enable */ +#define CAN_IER_TMEIE (1 << 0) + +/* --- CAN_ESR values ------------------------------------------------------ */ + +/* REC[7:0]: Receive error counter */ +#define CAN_ESR_REC_MASK (0xF << 24) + +/* TEC[7:0]: Least significant byte of the 9-bit transmit error counter */ +#define CAN_ESR_TEC_MASK (0xF << 16) + +/* 15:7 Reserved, forced by hardware to 0 */ + +/* LEC[2:0]: Last error code */ +#define CAN_ESR_LEC_NO_ERROR (0x0 << 4) +#define CAN_ESR_LEC_STUFF_ERROR (0x1 << 4) +#define CAN_ESR_LEC_FORM_ERROR (0x2 << 4) +#define CAN_ESR_LEC_ACK_ERROR (0x3 << 4) +#define CAN_ESR_LEC_REC_ERROR (0x4 << 4) +#define CAN_ESR_LEC_DOM_ERROR (0x5 << 4) +#define CAN_ESR_LEC_CRC_ERROR (0x6 << 4) +#define CAN_ESR_LEC_SOFT_ERROR (0x7 << 4) +#define CAN_ESR_LEC_MASK (0x7 << 4) + +/* 3 Reserved, forced by hardware to 0 */ + +/* BOFF: Bus-off flag */ +#define CAN_ESR_BOFF (1 << 2) + +/* EPVF: Error passive flag */ +#define CAN_ESR_EPVF (1 << 1) + +/* EWGF: Error warning flag */ +#define CAN_ESR_EWGF (1 << 0) + +/* --- CAN_BTR values ------------------------------------------------------ */ + +/* SILM: Silent mode (debug) */ +#define CAN_BTR_SILM (1 << 31) + +/* LBKM: Loop back mode (debug) */ +#define CAN_BTR_LBKM (1 << 30) + +/* 29:26 Reserved, forced by hardware to 0 */ + +/* SJW[1:0]: Resynchronization jump width */ +#define CAN_BTR_SJW_1TQ (0x0 << 24) +#define CAN_BTR_SJW_2TQ (0x1 << 24) +#define CAN_BTR_SJW_3TQ (0x2 << 24) +#define CAN_BTR_SJW_4TQ (0x3 << 24) +#define CAN_BTR_SJW_MASK (0x3 << 24) +#define CAN_BTR_SJW_SHIFT 24 + +/* 23 Reserved, forced by hardware to 0 */ + +/* TS2[2:0]: Time segment 2 */ +#define CAN_BTR_TS2_1TQ (0x0 << 20) +#define CAN_BTR_TS2_2TQ (0x1 << 20) +#define CAN_BTR_TS2_3TQ (0x2 << 20) +#define CAN_BTR_TS2_4TQ (0x3 << 20) +#define CAN_BTR_TS2_5TQ (0x4 << 20) +#define CAN_BTR_TS2_6TQ (0x5 << 20) +#define CAN_BTR_TS2_7TQ (0x6 << 20) +#define CAN_BTR_TS2_8TQ (0x7 << 20) +#define CAN_BTR_TS2_MASK (0x7 << 20) +#define CAN_BTR_TS2_SHIFT 20 + +/* TS1[3:0]: Time segment 1 */ +#define CAN_BTR_TS1_1TQ (0x0 << 16) +#define CAN_BTR_TS1_2TQ (0x1 << 16) +#define CAN_BTR_TS1_3TQ (0x2 << 16) +#define CAN_BTR_TS1_4TQ (0x3 << 16) +#define CAN_BTR_TS1_5TQ (0x4 << 16) +#define CAN_BTR_TS1_6TQ (0x5 << 16) +#define CAN_BTR_TS1_7TQ (0x6 << 16) +#define CAN_BTR_TS1_8TQ (0x7 << 16) +#define CAN_BTR_TS1_9TQ (0x8 << 16) +#define CAN_BTR_TS1_10TQ (0x9 << 16) +#define CAN_BTR_TS1_11TQ (0xA << 16) +#define CAN_BTR_TS1_12TQ (0xB << 16) +#define CAN_BTR_TS1_13TQ (0xC << 16) +#define CAN_BTR_TS1_14TQ (0xD << 16) +#define CAN_BTR_TS1_15TQ (0xE << 16) +#define CAN_BTR_TS1_16TQ (0xF << 16) +#define CAN_BTR_TS1_MASK (0xF << 16) +#define CAN_BTR_TS1_SHIFT 16 + +/* 15:10 Reserved, forced by hardware to 0 */ + +/* BRP[9:0]: Baud rate prescaler */ +#define CAN_BTR_BRP_MASK (0x1FFUL << 0) + +/* --- CAN_TIxR values ------------------------------------------------------ */ + +/* STID[10:0]: Standard identifier */ +#define CAN_TIxR_STID_MASK (0x7FF << 21) +#define CAN_TIxR_STID_SHIFT 21 + +/* EXID[15:0]: Extended identifier */ +#define CAN_TIxR_EXID_MASK (0x1FFFFFF << 3) +#define CAN_TIxR_EXID_SHIFT 3 + +/* IDE: Identifier extension */ +#define CAN_TIxR_IDE (1 << 2) + +/* RTR: Remote transmission request */ +#define CAN_TIxR_RTR (1 << 1) + +/* TXRQ: Transmit mailbox request */ +#define CAN_TIxR_TXRQ (1 << 0) + +/* --- CAN_TDTxR values ----------------------------------------------------- */ + +/* TIME[15:0]: Message time stamp */ +#define CAN_TDTxR_TIME_MASK (0xFFFF << 15) +#define CAN_TDTxR_TIME_SHIFT 15 + +/* 15:6 Reserved, forced by hardware to 0 */ + +/* TGT: Transmit global time */ +#define CAN_TDTxR_TGT (1 << 5) + +/* 7:4 Reserved, forced by hardware to 0 */ + +/* DLC[3:0]: Data length code */ +#define CAN_TDTxR_DLC_MASK (0xF << 0) +#define CAN_TDTxR_DLC_SHIFT 0 + +/* --- CAN_TDLxR values ----------------------------------------------------- */ + +/* DATA3[7:0]: Data byte 3 */ +/* DATA2[7:0]: Data byte 2 */ +/* DATA1[7:0]: Data byte 1 */ +/* DATA0[7:0]: Data byte 0 */ + +/* --- CAN_TDHxR values ----------------------------------------------------- */ + +/* DATA7[7:0]: Data byte 7 */ +/* DATA6[7:0]: Data byte 6 */ +/* DATA5[7:0]: Data byte 5 */ +/* DATA4[7:0]: Data byte 4 */ + +/* --- CAN_RIxR values ------------------------------------------------------ */ + +/* STID[10:0]: Standard identifier */ +#define CAN_RIxR_STID_MASK (0x7FF) +#define CAN_RIxR_STID_SHIFT 21 + +/* EXID[15:0]: Extended identifier */ +#define CAN_RIxR_EXID_MASK (0x1FFFFFFF) +#define CAN_RIxR_EXID_SHIFT 3 + +/* IDE: Identifier extension */ +#define CAN_RIxR_IDE (1 << 2) + +/* RTR: Remote transmission request */ +#define CAN_RIxR_RTR (1 << 1) + +/* 0 Reserved */ + +/* --- CAN_RDTxR values ----------------------------------------------------- */ + +/* TIME[15:0]: Message time stamp */ +#define CAN_RDTxR_TIME_MASK (0xFFFF << 15) +#define CAN_RDTxR_TIME_SHIFT 15 + +/* FMI[7:0]: Filter match index */ +#define CAN_RDTxR_FMI_MASK (0xFF << 8) +#define CAN_RDTxR_FMI_SHIFT 8 + +/* 7:4 Reserved, forced by hardware to 0 */ + +/* DLC[3:0]: Data length code */ +#define CAN_RDTxR_DLC_MASK (0xF << 0) +#define CAN_RDTxR_DLC_SHIFT 0 + +/* --- CAN_RDLxR values ----------------------------------------------------- */ + +/* DATA3[7:0]: Data byte 3 */ +/* DATA2[7:0]: Data byte 2 */ +/* DATA1[7:0]: Data byte 1 */ +/* DATA0[7:0]: Data byte 0 */ + +/* --- CAN_RDHxR values ----------------------------------------------------- */ + +/* DATA7[7:0]: Data byte 7 */ +/* DATA6[7:0]: Data byte 6 */ +/* DATA5[7:0]: Data byte 5 */ +/* DATA4[7:0]: Data byte 4 */ + +/* --- CAN_FMR values ------------------------------------------------------- */ + +/* 31:14 Reserved, forced to reset value */ + +/* + * CAN2SB[5:0]: CAN2 start bank + * (only on connectivity line devices otherwise reserved) + */ +#define CAN_FMR_CAN2SB_MASK (0x3F << 8) +#define CAN_FMR_CAN2SB_SHIFT 15 + +/* 7:1 Reserved, forced to reset value */ + +/* FINIT: Filter init mode */ +#define CAN_FMR_FINIT (1 << 0) + +/* --- CAN_FM1R values ------------------------------------------------------ */ + +/* 31:28 Reserved, forced by hardware to 0 */ + +/* + * FBMx: Filter mode + * x is 0..27 should be calculated by a helper function making so many macros + * seems like an overkill? + */ + +/* --- CAN_FS1R values ------------------------------------------------------ */ + +/* 31:28 Reserved, forced by hardware to 0 */ + +/* + * FSCx: Filter scale configuration + * x is 0..27 should be calculated by a helper function making so many macros + * seems like an overkill? + */ + +/* --- CAN_FFA1R values ----------------------------------------------------- */ + +/* 31:28 Reserved, forced by hardware to 0 */ + +/* + * FFAx: Filter scale configuration + * x is 0..27 should be calculated by a helper function making so many macros + * seems like an overkill? + */ + +/* --- CAN_FA1R values ------------------------------------------------------ */ + +/* 31:28 Reserved, forced by hardware to 0 */ + +/* + * FACTx: Filter active + * x is 0..27 should be calculated by a helper function making so many macros + * seems like an overkill? + */ + +/* --- CAN_FiRx values ------------------------------------------------------ */ + +/* FB[31:0]: Filter bits */ + +/* --- CAN functions -------------------------------------------------------- */ + +BEGIN_DECLS + +void can_reset(uint32_t canport); +int can_init(uint32_t canport, bool ttcm, bool abom, bool awum, bool nart, + bool rflm, bool txfp, uint32_t sjw, uint32_t ts1, uint32_t ts2, + uint32_t brp, bool loopback, bool silent); + +void can_filter_init(uint32_t canport, uint32_t nr, bool scale_32bit, + bool id_list_mode, uint32_t fr1, uint32_t fr2, + uint32_t fifo, bool enable); +void can_filter_id_mask_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1, + uint16_t mask1, uint16_t id2, + uint16_t mask2, uint32_t fifo, bool enable); +void can_filter_id_mask_32bit_init(uint32_t canport, uint32_t nr, uint32_t id, + uint32_t mask, uint32_t fifo, bool enable); +void can_filter_id_list_16bit_init(uint32_t canport, uint32_t nr, uint16_t id1, + uint16_t id2, uint16_t id3, uint16_t id4, + uint32_t fifo, bool enable); +void can_filter_id_list_32bit_init(uint32_t canport, uint32_t nr, uint32_t id1, + uint32_t id2, uint32_t fifo, bool enable); + +void can_enable_irq(uint32_t canport, uint32_t irq); +void can_disable_irq(uint32_t canport, uint32_t irq); + +int can_transmit(uint32_t canport, uint32_t id, bool ext, bool rtr, + uint8_t length, uint8_t *data); +void can_receive(uint32_t canport, uint8_t fifo, bool release, uint32_t *id, + bool *ext, bool *rtr, uint32_t *fmi, uint8_t *length, + uint8_t *data); + +void can_fifo_release(uint32_t canport, uint8_t fifo); +bool can_available_mailbox(uint32_t canport); +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/stm32/cec.h b/libopencm3/include/libopencm3/stm32/cec.h new file mode 100644 index 0000000..e2a040b --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/cec.h @@ -0,0 +1,28 @@ +/* This provides unification of code over STM32F subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#if defined(STM32F0) +# include +#else +# error "stm32 family not defined." +#endif + diff --git a/libopencm3/include/libopencm3/stm32/common/adc_common_v1.h b/libopencm3/include/libopencm3/stm32/common/adc_common_v1.h new file mode 100644 index 0000000..3ab2dfd --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/adc_common_v1.h @@ -0,0 +1,410 @@ +/** @addtogroup adc_defines + +@author @htmlonly © @endhtmlonly 2014 Karl Palsson + + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2014 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA ADC.H +The order of header inclusion is important. adc.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_ADC_H +/** @endcond */ +#ifndef LIBOPENCM3_ADC_COMMON_V1_H +#define LIBOPENCM3_ADC_COMMON_V1_H + +/* --- Convenience macros -------------------------------------------------- */ + +/* ADC port base addresses (for convenience) */ +/****************************************************************************/ +/** @defgroup adc_reg_base ADC register base addresses +@ingroup STM32xx_adc_defines + +@{*/ +#define ADC1 ADC1_BASE +/**@}*/ + +/* --- ADC registers ------------------------------------------------------- */ + +/* ADC status register (ADC_SR) */ +#define ADC_SR(block) MMIO32(block + 0x00) + +/* ADC control register 1 (ADC_CR1) */ +#define ADC_CR1(block) MMIO32(block + 0x04) + +/* ADC control register 2 (ADC_CR2) */ +#define ADC_CR2(block) MMIO32(block + 0x08) + +/* ADC sample time register 1 (ADC_SMPR1) */ +#define ADC_SMPR1(block) MMIO32(block + 0x0c) + +/* ADC sample time register 2 (ADC_SMPR2) */ +#define ADC_SMPR2(block) MMIO32(block + 0x10) + +#define ADC1_SR ADC_SR(ADC1) +#define ADC1_CR1 ADC_CR1(ADC1) +#define ADC1_CR2 ADC_CR2(ADC1) +#define ADC1_SMPR1 ADC_SMPR1(ADC1) +#define ADC1_SMPR2 ADC_SMPR2(ADC1) + +#define ADC1_JOFR1 ADC_JOFR1(ADC1) +#define ADC1_JOFR2 ADC_JOFR2(ADC1) +#define ADC1_JOFR3 ADC_JOFR3(ADC1) +#define ADC1_JOFR4 ADC_JOFR4(ADC1) + +#define ADC1_HTR ADC_HTR(ADC1) +#define ADC1_LTR ADC_LTR(ADC1) + +#define ADC1_SQR1 ADC_SQR1(ADC1) +#define ADC1_SQR2 ADC_SQR2(ADC1) +#define ADC1_SQR3 ADC_SQR3(ADC1) +#define ADC1_JSQR ADC_JSQR(ADC1) + +#define ADC1_JDR1 ADC_JDR1(ADC1) +#define ADC1_JDR2 ADC_JDR2(ADC1) +#define ADC1_JDR3 ADC_JDR3(ADC1) +#define ADC1_JDR4 ADC_JDR4(ADC1) +#define ADC1_DR ADC_DR(ADC1) + +#if defined(ADC2_BASE) +#define ADC2 ADC2_BASE +#define ADC2_SR ADC_SR(ADC2) +#define ADC2_CR1 ADC_CR1(ADC2) +#define ADC2_CR2 ADC_CR2(ADC2) +#define ADC2_SMPR1 ADC_SMPR1(ADC2) +#define ADC2_SMPR2 ADC_SMPR2(ADC2) + +#define ADC2_JOFR1 ADC_JOFR1(ADC2) +#define ADC2_JOFR2 ADC_JOFR2(ADC2) +#define ADC2_JOFR3 ADC_JOFR3(ADC2) +#define ADC2_JOFR4 ADC_JOFR4(ADC2) + +/* ADC watchdog high threshold register (ADC_HTR) */ +#define ADC2_HTR ADC_HTR(ADC2) +/* ADC watchdog low threshold register (ADC_LTR) */ +#define ADC2_LTR ADC_LTR(ADC2) + +/* ADC regular sequence register 1 (ADC_SQR1) */ +#define ADC2_SQR1 ADC_SQR1(ADC2) +/* ADC regular sequence register 2 (ADC_SQR2) */ +#define ADC2_SQR2 ADC_SQR2(ADC2) +/* ADC regular sequence register 3 (ADC_SQR3) */ +#define ADC2_SQR3 ADC_SQR3(ADC2) +/* ADC injected sequence register (ADC_JSQR) */ +#define ADC2_JSQR ADC_JSQR(ADC2) + +/* ADC injected data register x (ADC_JDRx) (x=1..4) */ +#define ADC2_JDR1 ADC_JDR1(ADC2) +#define ADC2_JDR2 ADC_JDR2(ADC2) +#define ADC2_JDR3 ADC_JDR3(ADC2) +#define ADC2_JDR4 ADC_JDR4(ADC2) +/* ADC regular data register (ADC_DR) */ +#define ADC2_DR ADC_DR(ADC2) +#endif + +#if defined(ADC3_BASE) +#define ADC3 ADC3_BASE +#define ADC3_SR ADC_SR(ADC3) +#define ADC3_CR1 ADC_CR1(ADC3) +#define ADC3_CR2 ADC_CR2(ADC3) +#define ADC3_SMPR1 ADC_SMPR1(ADC3) +#define ADC3_SMPR2 ADC_SMPR2(ADC3) + +#define ADC3_JOFR1 ADC_JOFR1(ADC3) +#define ADC3_JOFR2 ADC_JOFR2(ADC3) +#define ADC3_JOFR3 ADC_JOFR3(ADC3) +#define ADC3_JOFR4 ADC_JOFR4(ADC3) + +#define ADC3_HTR ADC_HTR(ADC3) +#define ADC3_LTR ADC_LTR(ADC3) + +#define ADC3_SQR1 ADC_SQR1(ADC3) +#define ADC3_SQR2 ADC_SQR2(ADC3) +#define ADC3_SQR3 ADC_SQR3(ADC3) +#define ADC3_JSQR ADC_JSQR(ADC3) + +#define ADC3_JDR1 ADC_JDR1(ADC3) +#define ADC3_JDR2 ADC_JDR2(ADC3) +#define ADC3_JDR3 ADC_JDR3(ADC3) +#define ADC3_JDR4 ADC_JDR4(ADC3) +#define ADC3_DR ADC_DR(ADC3) +#endif + + + +/* --- ADC Channels ------------------------------------------------------- */ + +/****************************************************************************/ +/** @defgroup adc_channel ADC Channel Numbers +@ingroup STM32xx_adc_defines + +@{*/ +#define ADC_CHANNEL0 0x00 +#define ADC_CHANNEL1 0x01 +#define ADC_CHANNEL2 0x02 +#define ADC_CHANNEL3 0x03 +#define ADC_CHANNEL4 0x04 +#define ADC_CHANNEL5 0x05 +#define ADC_CHANNEL6 0x06 +#define ADC_CHANNEL7 0x07 +#define ADC_CHANNEL8 0x08 +#define ADC_CHANNEL9 0x09 +#define ADC_CHANNEL10 0x0A +#define ADC_CHANNEL11 0x0B +#define ADC_CHANNEL12 0x0C +#define ADC_CHANNEL13 0x0D +#define ADC_CHANNEL14 0x0E +#define ADC_CHANNEL15 0x0F +#define ADC_CHANNEL16 0x10 +#define ADC_CHANNEL17 0x11 +#define ADC_CHANNEL18 0x12 + +#define ADC_CHANNEL_MASK 0x1F + + +/* --- ADC_SR values ------------------------------------------------------- */ + +#define ADC_SR_STRT (1 << 4) +#define ADC_SR_JSTRT (1 << 3) +#define ADC_SR_JEOC (1 << 2) +#define ADC_SR_EOC (1 << 1) +#define ADC_SR_AWD (1 << 0) + +/* --- ADC_CR1 values ------------------------------------------------------ */ + +/* AWDEN: Analog watchdog enable on regular channels */ +#define ADC_CR1_AWDEN (1 << 23) + +/* JAWDEN: Analog watchdog enable on injected channels */ +#define ADC_CR1_JAWDEN (1 << 22) + +/* Note: Bits [21:20] are reserved, and must be kept at reset value. */ + + +/* DISCNUM[2:0]: Discontinuous mode channel count. */ +/****************************************************************************/ +/** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode. +@ingroup STM32_adc_defines + +@{*/ +#define ADC_CR1_DISCNUM_1CHANNELS (0x0 << 13) +#define ADC_CR1_DISCNUM_2CHANNELS (0x1 << 13) +#define ADC_CR1_DISCNUM_3CHANNELS (0x2 << 13) +#define ADC_CR1_DISCNUM_4CHANNELS (0x3 << 13) +#define ADC_CR1_DISCNUM_5CHANNELS (0x4 << 13) +#define ADC_CR1_DISCNUM_6CHANNELS (0x5 << 13) +#define ADC_CR1_DISCNUM_7CHANNELS (0x6 << 13) +#define ADC_CR1_DISCNUM_8CHANNELS (0x7 << 13) +/**@}*/ +#define ADC_CR1_DISCNUM_MASK (0x7 << 13) +#define ADC_CR1_DISCNUM_SHIFT 13 + +/* JDISCEN: */ /** Discontinuous mode on injected channels. */ +#define ADC_CR1_JDISCEN (1 << 12) + +/* DISCEN: */ /** Discontinuous mode on regular channels. */ +#define ADC_CR1_DISCEN (1 << 11) + +/* JAUTO: */ /** Automatic Injection Group conversion. */ +#define ADC_CR1_JAUTO (1 << 10) + +/* AWDSGL: */ /** Enable the watchdog on a single channel in scan mode. */ +#define ADC_CR1_AWDSGL (1 << 9) + +/* SCAN: */ /** Scan mode. */ +#define ADC_CR1_SCAN (1 << 8) + +/* JEOCIE: */ /** Interrupt enable for injected channels. */ +#define ADC_CR1_JEOCIE (1 << 7) + +/* AWDIE: */ /** Analog watchdog interrupt enable. */ +#define ADC_CR1_AWDIE (1 << 6) + +/* EOCIE: */ /** Interrupt enable EOC. */ +#define ADC_CR1_EOCIE (1 << 5) + +/* AWDCH[4:0]: Analog watchdog channel bits. (Up to 17 other values reserved) */ +/* Notes: Depending on part, and ADC peripheral, some channels are connected + * to V_SS, or to temperature/reference/battery inputs + */ +/****************************************************************************/ +/* ADC_CR1 AWDCH[4:0] ADC watchdog channel */ +/** @defgroup adc_watchdog_channel ADC watchdog channel +@ingroup STM32xx_adc_defines + +@{*/ +#define ADC_CR1_AWDCH_CHANNEL0 (0x00 << 0) +#define ADC_CR1_AWDCH_CHANNEL1 (0x01 << 0) +#define ADC_CR1_AWDCH_CHANNEL2 (0x02 << 0) +#define ADC_CR1_AWDCH_CHANNEL3 (0x03 << 0) +#define ADC_CR1_AWDCH_CHANNEL4 (0x04 << 0) +#define ADC_CR1_AWDCH_CHANNEL5 (0x05 << 0) +#define ADC_CR1_AWDCH_CHANNEL6 (0x06 << 0) +#define ADC_CR1_AWDCH_CHANNEL7 (0x07 << 0) +#define ADC_CR1_AWDCH_CHANNEL8 (0x08 << 0) +#define ADC_CR1_AWDCH_CHANNEL9 (0x09 << 0) +#define ADC_CR1_AWDCH_CHANNEL10 (0x0A << 0) +#define ADC_CR1_AWDCH_CHANNEL11 (0x0B << 0) +#define ADC_CR1_AWDCH_CHANNEL12 (0x0C << 0) +#define ADC_CR1_AWDCH_CHANNEL13 (0x0D << 0) +#define ADC_CR1_AWDCH_CHANNEL14 (0x0E << 0) +#define ADC_CR1_AWDCH_CHANNEL15 (0x0F << 0) +#define ADC_CR1_AWDCH_CHANNEL16 (0x10 << 0) +#define ADC_CR1_AWDCH_CHANNEL17 (0x11 << 0) +/**@}*/ +#define ADC_CR1_AWDCH_MASK (0x1F << 0) +#define ADC_CR1_AWDCH_SHIFT 0 + +/* --- ADC_CR2 values ------------------------------------------------------ */ + +/* ALIGN: Data alignement. */ +#define ADC_CR2_ALIGN_RIGHT (0 << 11) +#define ADC_CR2_ALIGN_LEFT (1 << 11) +#define ADC_CR2_ALIGN (1 << 11) + +/* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */ +#define ADC_CR2_DMA (1 << 8) + +/* CONT: Continous conversion. */ +#define ADC_CR2_CONT (1 << 1) + +/* ADON: A/D converter On/Off. */ +/* Note: If any other bit in this register apart from ADON is changed at the + * same time, then conversion is not triggered. This is to prevent triggering + * an erroneous conversion. + * Conclusion: Must be separately written. + */ +#define ADC_CR2_ADON (1 << 0) + +/* --- ADC_JOFRx, ADC_HTR, ADC_LTR values ---------------------------------- */ + +#define ADC_JOFFSET_LSB 0 +#define ADC_JOFFSET_MSK 0xfff +#define ADC_HT_LSB 0 +#define ADC_HT_MSK 0xfff +#define ADC_LT_LSB 0 +#define ADC_LT_MSK 0xfff + +/* --- ADC_SQR1 values ----------------------------------------------------- */ +/* The sequence length field is always in the same place, but sized + * differently on various parts */ +#define ADC_SQR1_L_LSB 20 + +/* --- ADC_JSQR values ----------------------------------------------------- */ +#define ADC_JSQR_JL_LSB 20 +#define ADC_JSQR_JSQ4_LSB 15 +#define ADC_JSQR_JSQ3_LSB 10 +#define ADC_JSQR_JSQ2_LSB 5 +#define ADC_JSQR_JSQ1_LSB 0 + +/* JL[2:0]: Discontinous mode channel count injected channels. */ +/****************************************************************************/ +/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous injected mode +@ingroup STM32xx_adc_defines + +@{*/ +#define ADC_JSQR_JL_1CHANNELS (0x0 << ADC_JSQR_JL_LSB) +#define ADC_JSQR_JL_2CHANNELS (0x1 << ADC_JSQR_JL_LSB) +#define ADC_JSQR_JL_3CHANNELS (0x2 << ADC_JSQR_JL_LSB) +#define ADC_JSQR_JL_4CHANNELS (0x3 << ADC_JSQR_JL_LSB) +/**@}*/ +#define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB) +#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB) +#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB) +#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB) +#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB) + +#define ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 5)) +#define ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_LSB) + +#if (defined(THESE_HAVE_BAD_NAMES_PROBABLY) && (THESE_HAVE_BAD_NAMES_PROBABLY)) +/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ + +#define ADC_JDATA_LSB 0 +#define ADC_DATA_LSB 0 +#define ADC_ADC2DATA_LSB 16 /* ADC1 only (dual mode) */ +#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB) +#define ADC_DATA_MSK (0xffff << ADC_DA) +#define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB) +/* ADC1 only (dual mode) */ +#endif + + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void adc_power_on(uint32_t adc); +void adc_off(uint32_t adc); +void adc_enable_analog_watchdog_regular(uint32_t adc); +void adc_disable_analog_watchdog_regular(uint32_t adc); +void adc_enable_analog_watchdog_injected(uint32_t adc); +void adc_disable_analog_watchdog_injected(uint32_t adc); +void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length); +void adc_disable_discontinuous_mode_regular(uint32_t adc); +void adc_enable_discontinuous_mode_injected(uint32_t adc); +void adc_disable_discontinuous_mode_injected(uint32_t adc); +void adc_enable_automatic_injected_group_conversion(uint32_t adc); +void adc_disable_automatic_injected_group_conversion(uint32_t adc); +void adc_enable_analog_watchdog_on_all_channels(uint32_t adc); +void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, + uint8_t channel); +void adc_enable_scan_mode(uint32_t adc); +void adc_disable_scan_mode(uint32_t adc); +void adc_enable_eoc_interrupt_injected(uint32_t adc); +void adc_disable_eoc_interrupt_injected(uint32_t adc); +void adc_enable_awd_interrupt(uint32_t adc); +void adc_disable_awd_interrupt(uint32_t adc); +void adc_enable_eoc_interrupt(uint32_t adc); +void adc_disable_eoc_interrupt(uint32_t adc); +void adc_set_left_aligned(uint32_t adc); +void adc_set_right_aligned(uint32_t adc); +bool adc_eoc(uint32_t adc); +bool adc_eoc_injected(uint32_t adc); +uint32_t adc_read_regular(uint32_t adc); +uint32_t adc_read_injected(uint32_t adc, uint8_t reg); +void adc_set_continuous_conversion_mode(uint32_t adc); +void adc_set_single_conversion_mode(uint32_t adc); +void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]); +void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]); +void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset); +void adc_set_watchdog_high_threshold(uint32_t adc, uint16_t threshold); +void adc_set_watchdog_low_threshold(uint32_t adc, uint16_t threshold); +void adc_start_conversion_regular(uint32_t adc); +void adc_start_conversion_injected(uint32_t adc); +void adc_enable_dma(uint32_t adc); +void adc_disable_dma(uint32_t adc); + +/* common methods that have slight differences */ +void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time); +void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time); +void adc_disable_external_trigger_regular(uint32_t adc); +void adc_disable_external_trigger_injected(uint32_t adc); + +END_DECLS + +#endif +#endif /* ADC_COMMON_V1_H */ +/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/common/crc_common_all.h b/libopencm3/include/libopencm3/stm32/common/crc_common_all.h new file mode 100644 index 0000000..4d16c20 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/crc_common_all.h @@ -0,0 +1,118 @@ +/** @addtogroup crc_defines + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto + +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA CRC.H +The order of header inclusion is important. crc.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_CRC_H +/** @endcond */ +#ifndef LIBOPENCM3_CRC_COMMON_ALL_H +#define LIBOPENCM3_CRC_COMMON_ALL_H + +/**@{*/ + +/*****************************************************************************/ +/* Module definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Register definitions */ +/*****************************************************************************/ + +/* Data register (CRC_DR) */ +#define CRC_DR MMIO32(CRC_BASE + 0x00) + +/* Independent data register (CRC_IDR) */ +#define CRC_IDR MMIO32(CRC_BASE + 0x04) + +/* Control register (CRC_CR) */ +#define CRC_CR MMIO32(CRC_BASE + 0x08) + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +/* --- CRC_DR values ------------------------------------------------------- */ + +/* Bits [31:0]: Data register */ + +/* --- CRC_IDR values ------------------------------------------------------ */ + +/* Bits [31:8]: Reserved */ + +/* Bits [7:0]: General-purpose 8-bit data register bits */ + +/* --- CRC_CR values ------------------------------------------------------- */ + +/* Bits [31:1]: Reserved */ + +/* RESET bit */ +#define CRC_CR_RESET (1 << 0) + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + +BEGIN_DECLS + +/* TODO */ + +/** + * Reset the CRC calculator to initial values. + */ +void crc_reset(void); + +/** + * Add a word to the CRC calculator and return the result. + * @param data new word to add to the CRC calculator + * @return final CRC calculator value + */ +uint32_t crc_calculate(uint32_t data); + +/** + * Add a block of data to the CRC calculator and return the final result + * @param datap pointer to the start of a block of 32bit data words + * @param size length of data, in 32bit increments + * @return final CRC calculator value + */ +uint32_t crc_calculate_block(uint32_t *datap, int size); + +END_DECLS + +/**@}*/ + +#endif +/** @cond */ +#else +#warning "crc_common_all.h should not be included explicitly, only via crc.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/crypto_common_f24.h b/libopencm3/include/libopencm3/stm32/common/crypto_common_f24.h new file mode 100644 index 0000000..eb885c8 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/crypto_common_f24.h @@ -0,0 +1,290 @@ +/** @addtogroup crypto_defines + * + * @warning The CRYP subsystem is present only in a limited set of devices, + * see next section for list of supported devices. + * + * @section crypto_api_supported Supported devices + * + * - STM32F205 + * - STM32F207 + * - STM32F215 + * - STM32F217 + * - STM32F405 + * - STM32F407 + * - STM32F415 + * - STM32F417 (tested) + * - STM32F427 + * - STM32F437 + * + * @section crypto_api_theory Theory of operation + * + * + * + * @section crypto_api_basic Basic handling API + * + * + * @b Example @b 1: Blocking mode + * + * @code + * //[enable-clocks] + * crypto_set_key(CRYPTO_KEY_128BIT,key); + * crypto_set_iv(iv); // only in CBC or CTR mode + * crypto_set_datatype(CRYPTO_DATA_16BIT); + * crypto_set_algorithm(ENCRYPT_AES_ECB); + * crypto_start(); + * foreach(block in blocks) + * crypto_process_block(plaintext,ciphertext,blocksize); + * crypto_stop(); + * @endcode + * + * @section crypto_api_interrupt Interrupt supported handling API + * + * @warning This operation mode is currently not supported. + * + * @b Example @b 2: Interrupt mode + * + * @code + * //[enable-clocks] + * crypto_set_key(CRYPTO_KEY_128BIT,key); + * crypto_set_iv(iv); // only in CBC or CTR mode + * crypto_set_datatype(CRYPTO_DATA_16BIT); + * crypto_set_algorithm(ENCRYPT_AES_ECB); + * crypto_start(); + * [... API to be described later ...] + * crypto_stop(); + * @endcode + * + * @section crypto_api_dma DMA handling API + * + * @warning This operation mode is currently not supported. + * + * @b Example @b 3: DMA mode + * + * @code + * //[enable-clocks] + * crypto_set_key(CRYPTO_KEY_128BIT,key); + * crypto_set_iv(iv); // only in CBC or CTR mode + * crypto_set_datatype(CRYPTO_DATA_16BIT); + * crypto_set_algorithm(ENCRYPT_AES_ECB); + * crypto_start(); + * [... API to be described later ...] + * crypto_stop(); + * @endcode + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA CRYP.H +The order of header inclusion is important. cryp.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_CRYPTO_H +/** @endcond */ + +#ifndef LIBOPENCM3_CRYPTO_COMMON_F24_H +#define LIBOPENCM3_CRYPTO_COMMON_F24_H + +/**@{*/ + +/* --- CRYP registers ------------------------------------------------------ */ +/** @defgroup crypto_registers_gen Registers (Generic) + * + * @brief Register access to the CRYP controller. (All chips) + * + * @ingroup crypto_defines + */ +/**@{*/ + +#define CRYP CRYP_BASE + +/* CRYP Control Register (CRYP_CR) */ +#define CRYP_CR MMIO32(CRYP_BASE + 0x00) + +/* CRYP Status Register (CRYP_SR) */ +#define CRYP_SR MMIO32(CRYP_BASE + 0x04) + +/* CRYP Data Input Register (CRYP_DIN) */ +#define CRYP_DIN MMIO32(CRYP_BASE + 0x08) + +/** CRYP Data Output Register (CRYP_DOUT) @see blablabla */ +#define CRYP_DOUT MMIO32(CRYP_BASE + 0x0C) + +/* CRYP DMA Control Register (CRYP_DMACR) */ +#define CRYP_DMACR MMIO32(CRYP_BASE + 0x10) + +/* CRYP Interrupt mask set/clear register (CRYP_IMSCR) */ +#define CRYP_IMSCR MMIO32(CRYP_BASE + 0x14) + +/* CRYP Raw Interrupt status register (CRYP_RISR) */ +#define CRYP_RISR MMIO32(CRYP_BASE + 0x18) + +/* CRYP Masked Interrupt status register (CRYP_MISR) */ +#define CRYP_MISR MMIO32(CRYP_BASE + 0x1C) + +/* CRYP Key registers (CRYP_KxLR) x=0..3 */ +#define CRYP_KR(i) MMIO64(CRYP_BASE + 0x20 + (i) * 8) + +/* CRYP Initialization Vector Registers (CRYP_IVxLR) x=0..1 */ +#define CRYP_IVR(i) MMIO32(CRYP_BASE + 0x40 + (i) * 8) + +/* --- CRYP_CR values ------------------------------------------------------ */ + +/* ALGODIR: Algorithm direction */ +#define CRYP_CR_ALGODIR (1 << 2) + +/* ALGOMODE: Algorithm mode */ +#define CRYP_CR_ALGOMODE_SHIFT 3 +#define CRYP_CR_ALGOMODE (7 << CRYP_CR_ALGOMODE_SHIFT) +#define CRYP_CR_ALGOMODE_TDES_ECB (0 << CRYP_CR_ALGOMODE_SHIFT) +#define CRYP_CR_ALGOMODE_TDES_CBC (1 << CRYP_CR_ALGOMODE_SHIFT) +#define CRYP_CR_ALGOMODE_DES_ECB (2 << CRYP_CR_ALGOMODE_SHIFT) +#define CRYP_CR_ALGOMODE_DES_CBC (3 << CRYP_CR_ALGOMODE_SHIFT) +#define CRYP_CR_ALGOMODE_AES_ECB (4 << CRYP_CR_ALGOMODE_SHIFT) +#define CRYP_CR_ALGOMODE_AES_CBC (5 << CRYP_CR_ALGOMODE_SHIFT) +#define CRYP_CR_ALGOMODE_AES_CTR (6 << CRYP_CR_ALGOMODE_SHIFT) +#define CRYP_CR_ALGOMODE_AES_PREP (7 << CRYP_CR_ALGOMODE_SHIFT) + +/* DATATYPE: Data type selection */ +#define CRYP_CR_DATATYPE_SHIFT 6 +#define CRYP_CR_DATATYPE (3 << CRYP_CR_DATATYPE_SHIFT) +#define CRYP_CR_DATATYPE_32 (0 << CRYP_CR_DATATYPE_SHIFT) +#define CRYP_CR_DATATYPE_16 (1 << CRYP_CR_DATATYPE_SHIFT) +#define CRYP_CR_DATATYPE_8 (2 << CRYP_CR_DATATYPE_SHIFT) +#define CRYP_CR_DATATYPE_BIT (3 << CRYP_CR_DATATYPE_SHIFT) + +/* KEYSIZE: Key size selection (AES mode only)*/ +#define CRYP_CR_KEYSIZE_SHIFT 8 +#define CRYP_CR_KEYSIZE (3 << CRYP_CR_KEYSIZE_SHIFT) +#define CRYP_CR_KEYSIZE_128 (0 << CRYP_CR_KEYSIZE_SHIFT) +#define CRYP_CR_KEYSIZE_192 (1 << CRYP_CR_KEYSIZE_SHIFT) +#define CRYP_CR_KEYSIZE_256 (2 << CRYP_CR_KEYSIZE_SHIFT) + +/* FFLUSH: FIFO Flush */ +#define CRYP_CR_FFLUSH (1 << 14) + +/* CRYPEN: Cryptographic processor enable*/ +#define CRYP_CR_CRYPEN (1 << 15) + +/* --- CRYP_SR values ------------------------------------------------------ */ + +/* IFEM: Input FIFO empty */ +#define CRYP_SR_IFEM (1 << 0) + +/* IFNF: Input FIFO not full */ +#define CRYP_SR_IFNF (1 << 1) + +/* OFNE: Output FIFO not empty */ +#define CRYP_SR_OFNE (1 << 2) + +/* OFFU: Output FIFO full */ +#define CRYP_SR_OFFU (1 << 3) + +/* BUSY: Busy bit */ +#define CRYP_SR_BUSY (1 << 4) + +/* --- CRYP_DMACR values --------------------------------------------------- */ + +/* DIEN: DMA input enable */ +#define CRYP_DMACR_DIEN (1 << 0) + +/* DOEN: DMA output enable */ +#define CRYP_DMACR_DOEN (1 << 1) + +/* --- CRYP_IMSCR values --------------------------------------------------- */ + +/* INIM: Input FIFO service interrupt mask */ +#define CRYP_IMSCR_INIM (1 << 0) + +/* OUTIM: Output FIFO service interrupt mask */ +#define CRYP_IMSCR_OUTIM (1 << 1) + +/* --- CRYP_RISR values ---------------------------------------------------- */ + +/* INRIS: Input FIFO service raw interrupt status */ +#define CRYP_RISR_INRIS (1 << 0) + +/* OUTRIS: Output FIFO service raw data */ +#define CRYP_RISR_OUTRIS (1 << 0) + +/* --- CRYP_MISR values ---------------------------------------------------- */ + +/* INMIS: Input FIFO service masked interrupt status */ +#define CRYP_MISR_INMIS (1 << 0) + +/* OUTMIS: Output FIFO service masked interrupt status */ +#define CRYP_MISR_OUTMIS (1 << 0) + +/**@}*/ + +/** @defgroup crypto_api_gen API (Generic) + * + * @brief API for the CRYP controller + * + * @ingroup crypto_defines + */ +/**@{*/ + +enum crypto_mode { + ENCRYPT_TDES_ECB = CRYP_CR_ALGOMODE_TDES_ECB, + ENCRYPT_TDES_CBC = CRYP_CR_ALGOMODE_TDES_CBC, + ENCRYPT_DES_ECB = CRYP_CR_ALGOMODE_DES_ECB, + ENCRYPT_DES_CBC = CRYP_CR_ALGOMODE_DES_CBC, + ENCRYPT_AES_ECB = CRYP_CR_ALGOMODE_AES_ECB, + ENCRYPT_AES_CBC = CRYP_CR_ALGOMODE_AES_CBC, + ENCRYPT_AES_CTR = CRYP_CR_ALGOMODE_AES_CTR, + DECRYPT_TDES_ECB = CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGODIR, + DECRYPT_TDES_CBC = CRYP_CR_ALGOMODE_TDES_CBC | CRYP_CR_ALGODIR, + DECRYPT_DES_ECB = CRYP_CR_ALGOMODE_DES_ECB | CRYP_CR_ALGODIR, + DECRYPT_DES_CBC = CRYP_CR_ALGOMODE_DES_CBC | CRYP_CR_ALGODIR, + DECRYPT_AES_ECB = CRYP_CR_ALGOMODE_AES_ECB | CRYP_CR_ALGODIR, + DECRYPT_AES_CBC = CRYP_CR_ALGOMODE_AES_CBC | CRYP_CR_ALGODIR, + DECRYPT_AES_CTR = CRYP_CR_ALGOMODE_AES_CTR,/* XOR is same ENC as DEC */ +}; +enum crypto_keysize { + CRYPTO_KEY_128BIT = 0, + CRYPTO_KEY_192BIT, + CRYPTO_KEY_256BIT, +}; +enum crypto_datatype { + + CRYPTO_DATA_32BIT = 0, + CRYPTO_DATA_16BIT, + CRYPTO_DATA_8BIT, + CRYPTO_DATA_BIT, +}; + +BEGIN_DECLS +void crypto_wait_busy(void); +void crypto_set_key(enum crypto_keysize keysize, uint64_t key[]); +void crypto_set_iv(uint64_t iv[]); +void crypto_set_datatype(enum crypto_datatype datatype); +void crypto_set_algorithm(enum crypto_mode mode); +void crypto_start(void); +void crypto_stop(void); +uint32_t crypto_process_block(uint32_t *inp, uint32_t *outp, uint32_t length); +END_DECLS +/**@}*/ +/**@}*/ +#endif +/** @cond */ +#else +#warning "crypto_common_f24.h should not be included explicitly, " + "only via crypto.h" +#endif +/** @endcond */ diff --git a/libopencm3/include/libopencm3/stm32/common/dac_common_all.h b/libopencm3/include/libopencm3/stm32/common/dac_common_all.h new file mode 100644 index 0000000..7a241ab --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/dac_common_all.h @@ -0,0 +1,422 @@ +/** @addtogroup dac_defines + +@author @htmlonly © @endhtmlonly 2012 +Felix Held + +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Felix Held + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DAC.H +The order of header inclusion is important. dac.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_DAC_H +/** @endcond */ +#ifndef LIBOPENCM3_DAC_COMMON_ALL_H +#define LIBOPENCM3_DAC_COMMON_ALL_H + +/* --- DAC registers ------------------------------------------------------- */ + +/* DAC control register (DAC_CR) */ +#define DAC_CR MMIO32(DAC_BASE + 0x00) + +/* DAC software trigger register (DAC_SWTRIGR) */ +#define DAC_SWTRIGR MMIO32(DAC_BASE + 0x04) + +/* DAC channel1 12-bit right-aligned data holding register (DAC_DHR12R1) */ +#define DAC_DHR12R1 MMIO32(DAC_BASE + 0x08) + +/* DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1) */ +#define DAC_DHR12L1 MMIO32(DAC_BASE + 0x0C) + +/* DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1) */ +#define DAC_DHR8R1 MMIO32(DAC_BASE + 0x10) + +/* DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2) */ +#define DAC_DHR12R2 MMIO32(DAC_BASE + 0x14) + +/* DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2) */ +#define DAC_DHR12L2 MMIO32(DAC_BASE + 0x18) + +/* DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2) */ +#define DAC_DHR8R2 MMIO32(DAC_BASE + 0x1C) + +/* Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD) */ +#define DAC_DHR12RD MMIO32(DAC_BASE + 0x20) + +/* DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) */ +#define DAC_DHR12LD MMIO32(DAC_BASE + 0x24) + +/* DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) */ +#define DAC_DHR8RD MMIO32(DAC_BASE + 0x28) + +/* DAC channel1 data output register (DAC_DOR1) */ +#define DAC_DOR1 MMIO32(DAC_BASE + 0x2C) + +/* DAC channel2 data output register (DAC_DOR2) */ +#define DAC_DOR2 MMIO32(DAC_BASE + 0x30) + + +/* --- DAC_CR values ------------------------------------------------------- */ + +/* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */ +/* doesn't exist in most members of the STM32F1 family */ +#define DAC_CR_DMAUDRIE2 (1 << 29) + +/* DMAEN2: DAC channel2 DMA enable */ +#define DAC_CR_DMAEN2 (1 << 28) + +/* MAMP2[3:0]: DAC channel2 mask/amplitude selector */ +/* DAC_CR_MAMP2_n: + * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1 + */ +#define DAC_CR_MAMP2_SHIFT 24 +/** @defgroup dac_mamp2 DAC Channel 2 LFSR Mask and Triangle Wave Amplitude +values +@ingroup dac_defines + +Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1 +@{*/ +#define DAC_CR_MAMP2_1 (0x0 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_2 (0x1 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_3 (0x2 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_4 (0x3 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_5 (0x4 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_6 (0x5 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_7 (0x6 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_8 (0x7 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_9 (0x8 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_10 (0x9 << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_11 (0xA << DAC_CR_MAMP2_SHIFT) +#define DAC_CR_MAMP2_12 (0xB << DAC_CR_MAMP2_SHIFT) +/**@}*/ + +/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */ +/* Legend: + * DIS: wave generation disabled + * NOISE: Noise wave generation enabled + * TRI: Triangle wave generation enabled + * + * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) + */ +#define DAC_CR_WAVE2_SHIFT 22 +#define DAC_CR_WAVE2_DIS (0x3 << DAC_CR_WAVE2_SHIFT) +/** @defgroup dac_wave2_en DAC Channel 2 Waveform Generation Enable +@ingroup dac_defines + +@li NOISE: Noise wave generation enabled +@li TRI: Triangle wave generation enabled + +@note: only used if bit TEN2 is set (DAC channel2 trigger enabled) +@{*/ +#define DAC_CR_WAVE2_NOISE (0x1 << DAC_CR_WAVE2_SHIFT) +#define DAC_CR_WAVE2_TRI (0x2 << DAC_CR_WAVE2_SHIFT) +/**@}*/ + +/* TSEL2[2:0]: DAC channel2 trigger selection */ +/* Legend: + * + * T6: Timer 6 TRGO event + * T3: Timer 3 TRGO event + * T8: Timer 8 TRGO event + * T7: Timer 7 TRGO event + * T5: Timer 5 TRGO event + * T15: Timer 15 TRGO event + * T2: Timer 2 TRGO event + * T4: Timer 4 TRGO event + * E9: External line9 + * SW: Software trigger + * + * Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) + * Note: T3 == T8; T5 == T15; not both present on one device + * Note: this is *not* valid for the STM32L1 family + */ +#define DAC_CR_TSEL2_SHIFT 19 +/** @defgroup dac_trig2_sel DAC Channel 2 Trigger Source Selection +@ingroup dac_defines + +@li T6: Timer 6 TRGO event +@li T3: Timer 3 TRGO event +@li T8: Timer 8 TRGO event +@li T7: Timer 7 TRGO event +@li T5: Timer 5 TRGO event +@li T15: Timer 15 TRGO event +@li T2: Timer 2 TRGO event +@li T4: Timer 4 TRGO event +@li E9: External line9 +@li SW: Software trigger + +@note: Refer to the timer documentation for details of the TRGO event. +@note: T3 replaced by T8 and T5 replaced by T15 in some devices. +@note: this is not valid for the STM32L1 family. +@note: only used if bit TEN2 is set (DAC channel 2 trigger enabled) +@{*/ +#define DAC_CR_TSEL2_T6 (0x0 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T3 (0x1 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T8 (0x1 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T7 (0x2 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T5 (0x3 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T15 (0x3 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T2 (0x4 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_T4 (0x5 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_E9 (0x6 << DAC_CR_TSEL2_SHIFT) +#define DAC_CR_TSEL2_SW (0x7 << DAC_CR_TSEL2_SHIFT) +/**@}*/ + +/* TEN2: DAC channel2 trigger enable */ +#define DAC_CR_TEN2 (1 << 18) + +/* BOFF2: DAC channel2 output buffer disable */ +#define DAC_CR_BOFF2 (1 << 17) + +/* EN2: DAC channel2 enable */ +#define DAC_CR_EN2 (1 << 16) + +/* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */ +/* doesn't exist in most members of the STM32F1 family */ +#define DAC_CR_DMAUDRIE1 (1 << 13) + +/* DMAEN1: DAC channel1 DMA enable */ +#define DAC_CR_DMAEN1 (1 << 12) + +/* MAMP1[3:0]: DAC channel1 mask/amplitude selector */ +/* DAC_CR_MAMP1_n: + * Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1 + */ +#define DAC_CR_MAMP1_SHIFT 8 +/** @defgroup dac_mamp1 DAC Channel 1 LFSR Mask and Triangle Wave Amplitude +values +@ingroup dac_defines + +Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1 +@{*/ +#define DAC_CR_MAMP1_1 (0x0 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_2 (0x1 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_3 (0x2 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_4 (0x3 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_5 (0x4 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_6 (0x5 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_7 (0x6 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_8 (0x7 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_9 (0x8 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_10 (0x9 << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_11 (0xA << DAC_CR_MAMP1_SHIFT) +#define DAC_CR_MAMP1_12 (0xB << DAC_CR_MAMP1_SHIFT) +/**@}*/ + +/* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */ +/* Legend: + * DIS: wave generation disabled + * NOISE: Noise wave generation enabled + * TRI: Triangle wave generation enabled + * + * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled) + */ +#define DAC_CR_WAVE1_SHIFT 6 +#define DAC_CR_WAVE1_DIS (0x3 << DAC_CR_WAVE1_SHIFT) +/** @defgroup dac_wave1_en DAC Channel 1 Waveform Generation Enable +@ingroup dac_defines + +@li DIS: wave generation disabled +@li NOISE: Noise wave generation enabled +@li TRI: Triangle wave generation enabled + +@note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled) +@{*/ +#define DAC_CR_WAVE1_NOISE (0x1 << DAC_CR_WAVE1_SHIFT) +#define DAC_CR_WAVE1_TRI (0x2 << DAC_CR_WAVE1_SHIFT) +/**@}*/ + +/* TSEL1[2:0]: DAC channel1 trigger selection */ +/* Legend: + * + * T6: Timer 6 TRGO event + * T3: Timer 3 TRGO event in connectivity line devices + * T8: Timer 8 TRGO event in high-density and XL-density devices + * T7: Timer 7 TRGO event + * T5: Timer 5 TRGO event + * T15: Timer 15 TRGO event + * T2: Timer 2 TRGO event + * T4: Timer 4 TRGO event + * E9: External line9 + * SW: Software trigger + * + * Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled) + * Note: T3 == T8; T5 == T15; not both present on one device + * Note: this is *not* valid for the STM32L1 family + */ +#define DAC_CR_TSEL1_SHIFT 3 +/** @defgroup dac_trig1_sel DAC Channel 1 Trigger Source Selection +@ingroup dac_defines + +@li T6: Timer 6 TRGO event +@li T3: Timer 3 TRGO event +@li T8: Timer 8 TRGO event +@li T7: Timer 7 TRGO event +@li T5: Timer 5 TRGO event +@li T15: Timer 15 TRGO event +@li T2: Timer 2 TRGO event +@li T4: Timer 4 TRGO event +@li E9: External line 9 +@li SW: Software trigger + +@note: Refer to the timer documentation for details of the TRGO event. +@note: T3 replaced by T8 and T5 replaced by T15 in some devices. +@note: this is not valid for the STM32L1 family. +@note: only used if bit TEN2 is set (DAC channel 1 trigger enabled). +@{*/ +#define DAC_CR_TSEL1_T6 (0x0 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T3 (0x1 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T8 (0x1 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T7 (0x2 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T5 (0x3 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T15 (0x3 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T2 (0x4 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_T4 (0x5 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_E9 (0x6 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_SW (0x7 << DAC_CR_TSEL1_SHIFT) +/**@}*/ + +/* TEN1: DAC channel1 trigger enable */ +#define DAC_CR_TEN1 (1 << 2) + +/* BOFF1: DAC channel1 output buffer disable */ +#define DAC_CR_BOFF1 (1 << 1) + +/* EN1: DAC channel1 enable */ +#define DAC_CR_EN1 (1 << 0) + + +/* --- DAC_SWTRIGR values -------------------------------------------------- */ + +/* SWTRIG2: DAC channel2 software trigger */ +#define DAC_SWTRIGR_SWTRIG2 (1 << 1) + +/* SWTRIG1: DAC channel1 software trigger */ +#define DAC_SWTRIGR_SWTRIG1 (1 << 0) + + +/* --- DAC_DHR12R1 values -------------------------------------------------- */ +#define DAC_DHR12R1_DACC1DHR_LSB (1 << 0) +#define DAC_DHR12R1_DACC1DHR_MSK (0x0FFF << 0) + + +/* --- DAC_DHR12L1 values -------------------------------------------------- */ +#define DAC_DHR12L1_DACC1DHR_LSB (1 << 4) +#define DAC_DHR12L1_DACC1DHR_MSK (0x0FFF << 4) + + +/* --- DAC_DHR8R1 values --------------------------------------------------- */ +#define DAC_DHR8R1_DACC1DHR_LSB (1 << 0) +#define DAC_DHR8R1_DACC1DHR_MSK (0x00FF << 0) + + +/* --- DAC_DHR12R2 values -------------------------------------------------- */ +#define DAC_DHR12R2_DACC2DHR_LSB (1 << 0) +#define DAC_DHR12R2_DACC2DHR_MSK (0x00FFF << 0) + + +/* --- DAC_DHR12L2 values -------------------------------------------------- */ +#define DAC_DHR12L2_DACC2DHR_LSB (1 << 4) +#define DAC_DHR12L2_DACC2DHR_MSK (0x0FFF << 4) + + +/* --- DAC_DHR8R2 values --------------------------------------------------- */ +#define DAC_DHR8R2_DACC2DHR_LSB (1 << 0) +#define DAC_DHR8R2_DACC2DHR_MSK (0x00FF << 0) + + +/* --- DAC_DHR12RD values -------------------------------------------------- */ +#define DAC_DHR12RD_DACC2DHR_LSB (1 << 16) +#define DAC_DHR12RD_DACC2DHR_MSK (0x0FFF << 16) +#define DAC_DHR12RD_DACC1DHR_LSB (1 << 0) +#define DAC_DHR12RD_DACC1DHR_MSK (0x0FFF << 0) + + +/* --- DAC_DHR12LD values -------------------------------------------------- */ +#define DAC_DHR12LD_DACC2DHR_LSB (1 << 16) +#define DAC_DHR12LD_DACC2DHR_MSK (0x0FFF << 20) +#define DAC_DHR12LD_DACC1DHR_LSB (1 << 0) +#define DAC_DHR12LD_DACC1DHR_MSK (0x0FFF << 4) + + +/* --- DAC_DHR8RD values --------------------------------------------------- */ +#define DAC_DHR8RD_DACC2DHR_LSB (1 << 8) +#define DAC_DHR8RD_DACC2DHR_MSK (0x00FF << 8) +#define DAC_DHR8RD_DACC1DHR_LSB (1 << 0) +#define DAC_DHR8RD_DACC1DHR_MSK (0x00FF << 0) + + +/* --- DAC_DOR1 values ----------------------------------------------------- */ +#define DAC_DOR1_DACC1DOR_LSB (1 << 0) +#define DAC_DOR1_DACC1DOR_MSK (0x0FFF << 0) + + +/* --- DAC_DOR2 values ----------------------------------------------------- */ +#define DAC_DOR2_DACC2DOR_LSB (1 << 0) +#define DAC_DOR2_DACC2DOR_MSK (0x0FFF << 0) + +/** DAC channel identifier */ +typedef enum { + CHANNEL_1, CHANNEL_2, CHANNEL_D +} data_channel; + +/** DAC data size (8/12 bits), alignment (right/left) */ +typedef enum { + RIGHT8, RIGHT12, LEFT12 +} data_align; + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void dac_enable(data_channel dac_channel); +void dac_disable(data_channel dac_channel); +void dac_buffer_enable(data_channel dac_channel); +void dac_buffer_disable(data_channel dac_channel); +void dac_dma_enable(data_channel dac_channel); +void dac_dma_disable(data_channel dac_channel); +void dac_trigger_enable(data_channel dac_channel); +void dac_trigger_disable(data_channel dac_channel); +void dac_set_trigger_source(uint32_t dac_trig_src); +void dac_set_waveform_generation(uint32_t dac_wave_ens); +void dac_disable_waveform_generation(data_channel dac_channel); +void dac_set_waveform_characteristics(uint32_t dac_mamp); +void dac_load_data_buffer_single(uint16_t dac_data, data_align dac_data_format, + data_channel dac_channel); +void dac_load_data_buffer_dual(uint16_t dac_data1, uint16_t dac_data2, + data_align dac_data_format); +void dac_software_trigger(data_channel dac_channel); + +END_DECLS + +#endif +/** @cond */ +#else +#warning "dac_common_all.h should not be included explicitly, only via dac.h" +#endif +/** @endcond */ + +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/common/dma_common_f24.h b/libopencm3/include/libopencm3/stm32/common/dma_common_f24.h new file mode 100644 index 0000000..922a8b3 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/dma_common_f24.h @@ -0,0 +1,626 @@ +/** @addtogroup dma_defines + +@author @htmlonly © @endhtmlonly 2011 +Fergus Noble +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies + +*/ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * Copyright (C) 2012 Ken Sarkies + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H +The order of header inclusion is important. dma.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_DMA_H +/** @endcond */ +#ifndef LIBOPENCM3_DMA_COMMON_F24_H +#define LIBOPENCM3_DMA_COMMON_F24_H + +/**@{*/ + +/* --- Convenience macros -------------------------------------------------- */ + +/* DMA controller base addresses (for convenience) */ +#define DMA1 DMA1_BASE +#define DMA2 DMA2_BASE + +/* DMA stream base addresses (for API parameters) */ +/** @defgroup dma_st_number DMA Stream Number +@ingroup STM32F4xx_dma_defines + +@{*/ +#define DMA_STREAM0 0 +#define DMA_STREAM1 1 +#define DMA_STREAM2 2 +#define DMA_STREAM3 3 +#define DMA_STREAM4 4 +#define DMA_STREAM5 5 +#define DMA_STREAM6 6 +#define DMA_STREAM7 7 +/**@}*/ + +#define DMA_STREAM(port, n) ((port) + 0x10 + (24 * (n))) +#define DMA1_STREAM(n) DMA_STREAM(DMA1, n) +#define DMA2_STREAM(n) DMA_STREAM(DMA2, n) + +#define DMA1_STREAM0 DMA1_STREAM(0) +#define DMA1_STREAM1 DMA1_STREAM(1) +#define DMA1_STREAM2 DMA1_STREAM(2) +#define DMA1_STREAM3 DMA1_STREAM(3) +#define DMA1_STREAM4 DMA1_STREAM(4) +#define DMA1_STREAM5 DMA1_STREAM(5) +#define DMA1_STREAM6 DMA1_STREAM(6) +#define DMA1_STREAM7 DMA1_STREAM(7) + +#define DMA2_STREAM0 DMA2_STREAM(0) +#define DMA2_STREAM1 DMA2_STREAM(1) +#define DMA2_STREAM2 DMA2_STREAM(2) +#define DMA2_STREAM3 DMA2_STREAM(3) +#define DMA2_STREAM4 DMA2_STREAM(4) +#define DMA2_STREAM5 DMA2_STREAM(5) +#define DMA2_STREAM6 DMA2_STREAM(6) +#define DMA2_STREAM7 DMA2_STREAM(7) + +/* --- DMA controller registers -------------------------------------------- */ + +/* DMA low interrupt status register (DMAx_LISR) */ +#define DMA_LISR(port) MMIO32(port + 0x00) +#define DMA1_LISR DMA_LISR(DMA1) +#define DMA2_LISR DMA_LISR(DMA2) + +/* DMA high interrupt status register (DMAx_HISR) */ +#define DMA_HISR(port) MMIO32(port + 0x04) +#define DMA1_HISR DMA_HISR(DMA1) +#define DMA2_HISR DMA_HISR(DMA2) + +/* DMA low interrupt flag clear register (DMAx_LIFCR) */ +#define DMA_LIFCR(port) MMIO32(port + 0x08) +#define DMA1_LIFCR DMA_LIFCR(DMA1) +#define DMA2_LIFCR DMA_LIFCR(DMA2) + +/* DMA high interrupt flag clear register (DMAx_HIFCR) */ +#define DMA_HIFCR(port) MMIO32(port + 0x0C) +#define DMA1_HIFCR DMA_HIFCR(DMA1) +#define DMA2_HIFCR DMA_HIFCR(DMA2) + +/* --- DMA stream registers ------------------------------------------------ */ + +/* DMA Stream x configuration register (DMA_SxCR) */ +#define DMA_SCR(port, n) MMIO32(DMA_STREAM(port, n) + 0x00) +#define DMA1_SCR(n) DMA_SCR(DMA1, n) +#define DMA2_SCR(n) DMA_SCR(DMA2, n) + +#define DMA1_S0CR DMA1_SCR(0) +#define DMA1_S1CR DMA1_SCR(1) +#define DMA1_S2CR DMA1_SCR(2) +#define DMA1_S3CR DMA1_SCR(3) +#define DMA1_S4CR DMA1_SCR(4) +#define DMA1_S5CR DMA1_SCR(5) +#define DMA1_S6CR DMA1_SCR(6) +#define DMA1_S7CR DMA1_SCR(7) + +#define DMA2_S0CR DMA2_SCR(0) +#define DMA2_S1CR DMA2_SCR(1) +#define DMA2_S2CR DMA2_SCR(2) +#define DMA2_S3CR DMA2_SCR(3) +#define DMA2_S4CR DMA2_SCR(4) +#define DMA2_S5CR DMA2_SCR(5) +#define DMA2_S6CR DMA2_SCR(6) +#define DMA2_S7CR DMA2_SCR(7) + +/* DMA Stream x number of data register (DMA_SxNDTR) */ +#define DMA_SNDTR(port, n) MMIO32(DMA_STREAM(port, n) + 0x04) +#define DMA1_SNDTR(n) DMA_SNDTR(DMA1, n) +#define DMA2_SNDTR(n) DMA_SNDTR(DMA2, n) + +#define DMA1_S0NDTR DMA1_SNDTR(0) +#define DMA1_S1NDTR DMA1_SNDTR(1) +#define DMA1_S2NDTR DMA1_SNDTR(2) +#define DMA1_S3NDTR DMA1_SNDTR(3) +#define DMA1_S4NDTR DMA1_SNDTR(4) +#define DMA1_S5NDTR DMA1_SNDTR(5) +#define DMA1_S6NDTR DMA1_SNDTR(6) +#define DMA1_S7NDTR DMA1_SNDTR(7) + +#define DMA2_S0NDTR DMA2_SNDTR(0) +#define DMA2_S1NDTR DMA2_SNDTR(1) +#define DMA2_S2NDTR DMA2_SNDTR(2) +#define DMA2_S3NDTR DMA2_SNDTR(3) +#define DMA2_S4NDTR DMA2_SNDTR(4) +#define DMA2_S5NDTR DMA2_SNDTR(5) +#define DMA2_S6NDTR DMA2_SNDTR(6) +#define DMA2_S7NDTR DMA2_SNDTR(7) + +/* DMA Stream x peripheral address register (DMA_SxPAR) */ +#define DMA_SPAR(port, n) (*(volatile void **)\ + (DMA_STREAM(port, n) + 0x08)) +#define DMA1_SPAR(n) DMA_SPAR(DMA1, n) +#define DMA2_SPAR(n) DMA_SPAR(DMA2, n) + +#define DMA1_S0PAR DMA1_SPAR(0) +#define DMA1_S1PAR DMA1_SPAR(1) +#define DMA1_S2PAR DMA1_SPAR(2) +#define DMA1_S3PAR DMA1_SPAR(3) +#define DMA1_S4PAR DMA1_SPAR(4) +#define DMA1_S5PAR DMA1_SPAR(5) +#define DMA1_S6PAR DMA1_SPAR(6) +#define DMA1_S7PAR DMA1_SPAR(7) + +#define DMA2_S0PAR DMA2_SPAR(0) +#define DMA2_S1PAR DMA2_SPAR(1) +#define DMA2_S2PAR DMA2_SPAR(2) +#define DMA2_S3PAR DMA2_SPAR(3) +#define DMA2_S4PAR DMA2_SPAR(4) +#define DMA2_S5PAR DMA2_SPAR(5) +#define DMA2_S6PAR DMA2_SPAR(6) +#define DMA2_S7PAR DMA2_SPAR(7) + +/* DMA Stream x memory address 0 register (DMA_SxM0AR) */ +#define DMA_SM0AR(port, n) (*(volatile void **) \ + (DMA_STREAM(port, n) + 0x0c)) +#define DMA1_SM0AR(n) DMA_SM0AR(DMA1, n) +#define DMA2_SM0AR(n) DMA_SM0AR(DMA2, n) + +#define DMA1_S0M0AR DMA1_SM0AR(0) +#define DMA1_S1M0AR DMA1_SM0AR(1) +#define DMA1_S2M0AR DMA1_SM0AR(2) +#define DMA1_S3M0AR DMA1_SM0AR(3) +#define DMA1_S4M0AR DMA1_SM0AR(4) +#define DMA1_S5M0AR DMA1_SM0AR(5) +#define DMA1_S6M0AR DMA1_SM0AR(6) +#define DMA1_S7M0AR DMA1_SM0AR(7) + +#define DMA2_S0M0AR DMA2_SM0AR(0) +#define DMA2_S1M0AR DMA2_SM0AR(1) +#define DMA2_S2M0AR DMA2_SM0AR(2) +#define DMA2_S3M0AR DMA2_SM0AR(3) +#define DMA2_S4M0AR DMA2_SM0AR(4) +#define DMA2_S5M0AR DMA2_SM0AR(5) +#define DMA2_S6M0AR DMA2_SM0AR(6) +#define DMA2_S7M0AR DMA2_SM0AR(7) + +/* DMA Stream x memory address 1 register (DMA_SxM1AR) */ +#define DMA_SM1AR(port, n) (*(volatile void **)\ + (DMA_STREAM(port, n) + 0x10)) +#define DMA1_SM1AR(n) DMA_SM1AR(DMA1, n) +#define DMA2_SM1AR(n) DMA_SM1AR(DMA2, n) + +#define DMA1_S0M1AR DMA1_SM1AR(0) +#define DMA1_S1M1AR DMA1_SM1AR(1) +#define DMA1_S2M1AR DMA1_SM1AR(2) +#define DMA1_S3M1AR DMA1_SM1AR(3) +#define DMA1_S4M1AR DMA1_SM1AR(4) +#define DMA1_S5M1AR DMA1_SM1AR(5) +#define DMA1_S6M1AR DMA1_SM1AR(6) +#define DMA1_S7M1AR DMA1_SM1AR(7) + +#define DMA2_S0M1AR DMA2_SM1AR(0) +#define DMA2_S1M1AR DMA2_SM1AR(1) +#define DMA2_S2M1AR DMA2_SM1AR(2) +#define DMA2_S3M1AR DMA2_SM1AR(3) +#define DMA2_S4M1AR DMA2_SM1AR(4) +#define DMA2_S5M1AR DMA2_SM1AR(5) +#define DMA2_S6M1AR DMA2_SM1AR(6) +#define DMA2_S7M1AR DMA2_SM1AR(7) + +/* DMA Stream x FIFO control register (DMA_SxFCR) */ +#define DMA_SFCR(port, n) MMIO32(DMA_STREAM(port, n) + 0x14) +#define DMA1_SFCR(n) DMA_SFCR(DMA1, n) +#define DMA2_SFCR(n) DMA_SFCR(DMA2, n) + +#define DMA1_S0FCR DMA1_SFCR(0) +#define DMA1_S1FCR DMA1_SFCR(1) +#define DMA1_S2FCR DMA1_SFCR(2) +#define DMA1_S3FCR DMA1_SFCR(3) +#define DMA1_S4FCR DMA1_SFCR(4) +#define DMA1_S5FCR DMA1_SFCR(5) +#define DMA1_S6FCR DMA1_SFCR(6) +#define DMA1_S7FCR DMA1_SFCR(7) + +#define DMA2_S0FCR DMA2_SFCR(0) +#define DMA2_S1FCR DMA2_SFCR(1) +#define DMA2_S2FCR DMA2_SFCR(2) +#define DMA2_S3FCR DMA2_SFCR(3) +#define DMA2_S4FCR DMA2_SFCR(4) +#define DMA2_S5FCR DMA2_SFCR(5) +#define DMA2_S6FCR DMA2_SFCR(6) +#define DMA2_S7FCR DMA2_SFCR(7) + +/* --- DMA Interrupt Flag offset values ------------------------------------- */ + +/* For API parameters. These are based on every interrupt flag and flag clear +being at the same relative location */ +/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within stream flag group. +@ingroup dma_defines + +@{*/ +/** Transfer Complete Interrupt Flag */ +#define DMA_TCIF (1 << 5) +/** Half Transfer Interrupt Flag */ +#define DMA_HTIF (1 << 4) +/** Transfer Error Interrupt Flag */ +#define DMA_TEIF (1 << 3) +/** Direct Mode Error Interrupt Flag */ +#define DMA_DMEIF (1 << 2) +/** FIFO Error Interrupt Flag */ +#define DMA_FEIF (1 << 0) +/**@}*/ + +/* Offset within interrupt status register to start of stream interrupt flag + * field + */ +#define DMA_ISR_OFFSET(stream) (6*(stream & 0x01)+16*((stream & 0x02) >> 1)) +#define DMA_ISR_FLAGS (DMA_TCIF | DMA_HTIF | DMA_TEIF | DMA_DMEIF | \ + DMA_FEIF) +#define DMA_ISR_MASK(stream) (DMA_ISR_FLAGS << DMA_ISR_OFFSET(stream)) + +/* --- DMA_LISR values ----------------------------------------------------- */ + +#define DMA_LISR_FEIF0 (1 << 0) +#define DMA_LISR_DMEIF0 (1 << 2) +#define DMA_LISR_TEIF0 (1 << 3) +#define DMA_LISR_HTIF0 (1 << 4) +#define DMA_LISR_TCIF0 (1 << 5) + +#define DMA_LISR_FEIF1 (1 << 6) +#define DMA_LISR_DMEIF1 (1 << 8) +#define DMA_LISR_TEIF1 (1 << 9) +#define DMA_LISR_HTIF1 (1 << 10) +#define DMA_LISR_TCIF1 (1 << 11) + +#define DMA_LISR_FEIF2 (1 << 16) +#define DMA_LISR_DMEIF2 (1 << 18) +#define DMA_LISR_TEIF2 (1 << 19) +#define DMA_LISR_HTIF2 (1 << 20) +#define DMA_LISR_TCIF2 (1 << 21) + +#define DMA_LISR_FEIF3 (1 << 22) +#define DMA_LISR_DMEIF3 (1 << 24) +#define DMA_LISR_TEIF3 (1 << 25) +#define DMA_LISR_HTIF3 (1 << 26) +#define DMA_LISR_TCIF3 (1 << 27) + +/* --- DMA_HISR values ----------------------------------------------------- */ + +#define DMA_HISR_FEIF4 (1 << 0) +#define DMA_HISR_DMEIF4 (1 << 2) +#define DMA_HISR_TEIF4 (1 << 3) +#define DMA_HISR_HTIF4 (1 << 4) +#define DMA_HISR_TCIF4 (1 << 5) + +#define DMA_HISR_FEIF5 (1 << 6) +#define DMA_HISR_DMEIF5 (1 << 8) +#define DMA_HISR_TEIF5 (1 << 9) +#define DMA_HISR_HTIF5 (1 << 10) +#define DMA_HISR_TCIF5 (1 << 11) + +#define DMA_HISR_FEIF6 (1 << 16) +#define DMA_HISR_DMEIF6 (1 << 18) +#define DMA_HISR_TEIF6 (1 << 19) +#define DMA_HISR_HTIF6 (1 << 20) +#define DMA_HISR_TCIF6 (1 << 21) + +#define DMA_HISR_FEIF7 (1 << 22) +#define DMA_HISR_DMEIF7 (1 << 24) +#define DMA_HISR_TEIF7 (1 << 25) +#define DMA_HISR_HTIF7 (1 << 26) +#define DMA_HISR_TCIF7 (1 << 27) + +/* --- DMA_LIFCR values ----------------------------------------------------- */ + +#define DMA_LIFCR_CFEIF0 (1 << 0) +#define DMA_LIFCR_CDMEIF0 (1 << 2) +#define DMA_LIFCR_CTEIF0 (1 << 3) +#define DMA_LIFCR_CHTIF0 (1 << 4) +#define DMA_LIFCR_CTCIF0 (1 << 5) + +#define DMA_LIFCR_CFEIF1 (1 << 6) +#define DMA_LIFCR_CDMEIF1 (1 << 8) +#define DMA_LIFCR_CTEIF1 (1 << 9) +#define DMA_LIFCR_CHTIF1 (1 << 10) +#define DMA_LIFCR_CTCIF1 (1 << 11) + +#define DMA_LIFCR_CFEIF2 (1 << 16) +#define DMA_LIFCR_CDMEIF2 (1 << 18) +#define DMA_LIFCR_CTEIF2 (1 << 19) +#define DMA_LIFCR_CHTIF2 (1 << 20) +#define DMA_LIFCR_CTCIF2 (1 << 21) + +#define DMA_LIFCR_CFEIF3 (1 << 22) +#define DMA_LIFCR_CDMEIF3 (1 << 24) +#define DMA_LIFCR_CTEIF3 (1 << 25) +#define DMA_LIFCR_CHTIF3 (1 << 26) +#define DMA_LIFCR_CTCIF3 (1 << 27) + +/* --- DMA_HIFCR values ----------------------------------------------------- */ + +#define DMA_HIFCR_CFEIF4 (1 << 0) +#define DMA_HIFCR_CDMEIF4 (1 << 2) +#define DMA_HIFCR_CTEIF4 (1 << 3) +#define DMA_HIFCR_CHTIF4 (1 << 4) +#define DMA_HIFCR_CTCIF4 (1 << 5) + +#define DMA_HIFCR_CFEIF5 (1 << 6) +#define DMA_HIFCR_CDMEIF5 (1 << 8) +#define DMA_HIFCR_CTEIF5 (1 << 9) +#define DMA_HIFCR_CHTIF5 (1 << 10) +#define DMA_HIFCR_CTCIF5 (1 << 11) + +#define DMA_HIFCR_CFEIF6 (1 << 16) +#define DMA_HIFCR_CDMEIF6 (1 << 18) +#define DMA_HIFCR_CTEIF6 (1 << 19) +#define DMA_HIFCR_CHTIF6 (1 << 20) +#define DMA_HIFCR_CTCIF6 (1 << 21) + +#define DMA_HIFCR_CFEIF7 (1 << 22) +#define DMA_HIFCR_CDMEIF7 (1 << 24) +#define DMA_HIFCR_CTEIF7 (1 << 25) +#define DMA_HIFCR_CHTIF7 (1 << 26) +#define DMA_HIFCR_CTCIF7 (1 << 27) + +/* --- DMA_SxCR values ----------------------------------------------------- */ + +/* EN: Stream enable */ +#define DMA_SxCR_EN (1 << 0) +/* DMEIE: Direct Mode error interrupt enable */ +#define DMA_SxCR_DMEIE (1 << 1) +/* TEIE: Transfer error interrupt enable */ +#define DMA_SxCR_TEIE (1 << 2) +/* HTIE: Half transfer interrupt enable */ +#define DMA_SxCR_HTIE (1 << 3) +/* TCIE: Transfer complete interrupt enable */ +#define DMA_SxCR_TCIE (1 << 4) +/* PFCTRL: Peripheral Flow Controller */ +#define DMA_SxCR_PFCTRL (1 << 5) + +/* DIR[7:6]: Data transfer direction */ +/** @defgroup dma_st_dir DMA Stream Data transfer direction +@ingroup dma_defines + +@{*/ +#define DMA_SxCR_DIR_PERIPHERAL_TO_MEM (0 << 6) +#define DMA_SxCR_DIR_MEM_TO_PERIPHERAL (1 << 6) +#define DMA_SxCR_DIR_MEM_TO_MEM (2 << 6) +/**@}*/ +#define DMA_SxCR_DIR_SHIFT 6 +#define DMA_SxCR_DIR_MASK (3 << 6) + +/* CIRC: Circular mode */ +#define DMA_SxCR_CIRC (1 << 8) +/* PINC: Peripheral increment mode */ +#define DMA_SxCR_PINC (1 << 9) +/* MINC: Memory increment mode */ +#define DMA_SxCR_MINC (1 << 10) + +/* PSIZE[12:11]: Peripheral size */ +/** @defgroup dma_st_perwidth DMA Stream Peripheral Word Width +@ingroup STM32F4xx_dma_defines + +@{*/ +#define DMA_SxCR_PSIZE_8BIT (0 << 11) +#define DMA_SxCR_PSIZE_16BIT (1 << 11) +#define DMA_SxCR_PSIZE_32BIT (2 << 11) +/**@}*/ +#define DMA_SxCR_PSIZE_SHIFT 11 +#define DMA_SxCR_PSIZE_MASK (3 << 11) + +/* MSIZE[14:13]: Memory size */ +/** @defgroup dma_st_memwidth DMA Stream Memory Word Width +@ingroup STM32F4xx_dma_defines + +@{*/ +#define DMA_SxCR_MSIZE_8BIT (0 << 13) +#define DMA_SxCR_MSIZE_16BIT (1 << 13) +#define DMA_SxCR_MSIZE_32BIT (2 << 13) +/**@}*/ +#define DMA_SxCR_MSIZE_SHIFT 13 +#define DMA_SxCR_MSIZE_MASK (3 << 13) + +/* PINCOS: Peripheral increment offset size */ +#define DMA_SxCR_PINCOS (1 << 15) + +/* PL[17:16]: Stream priority level */ +/** @defgroup dma_st_pri DMA Stream Priority Levels +@ingroup dma_defines + +@{*/ +#define DMA_SxCR_PL_LOW (0 << 16) +#define DMA_SxCR_PL_MEDIUM (1 << 16) +#define DMA_SxCR_PL_HIGH (2 << 16) +#define DMA_SxCR_PL_VERY_HIGH (3 << 16) +/**@}*/ +#define DMA_SxCR_PL_SHIFT 16 +#define DMA_SxCR_PL_MASK (3 << 16) + +/* DBM: Double buffered mode */ +#define DMA_SxCR_DBM (1 << 18) +/* CT: Current target (in double buffered mode) */ +#define DMA_SxCR_CT (1 << 19) + +/* Bit 20 reserved */ + +/* PBURST[13:12]: Peripheral Burst Configuration */ +/** @defgroup dma_pburst DMA Peripheral Burst Length +@ingroup dma_defines + +@{*/ +#define DMA_SxCR_PBURST_SINGLE (0 << 21) +#define DMA_SxCR_PBURST_INCR4 (1 << 21) +#define DMA_SxCR_PBURST_INCR8 (2 << 21) +#define DMA_SxCR_PBURST_INCR16 (3 << 21) +/**@}*/ +#define DMA_SxCR_PBURST_SHIFT 21 +#define DMA_SxCR_PBURST_MASK (3 << 21) + +/* MBURST[13:12]: Memory Burst Configuration */ +/** @defgroup dma_mburst DMA Memory Burst Length +@ingroup STM32F4xx_dma_defines + +@{*/ +#define DMA_SxCR_MBURST_SINGLE (0 << 23) +#define DMA_SxCR_MBURST_INCR4 (1 << 23) +#define DMA_SxCR_MBURST_INCR8 (2 << 23) +#define DMA_SxCR_MBURST_INCR16 (3 << 23) +/**@}*/ +#define DMA_SxCR_MBURST_SHIFT 23 +#define DMA_SxCR_MBURST_MASK (3 << 23) + +/* CHSEL[25:27]: Channel Select */ +/** @defgroup dma_ch_sel DMA Channel Select +@ingroup dma_defines + +@{*/ +#define DMA_SxCR_CHSEL_0 (0 << DMA_SxCR_CHSEL_SHIFT) +#define DMA_SxCR_CHSEL_1 (1 << DMA_SxCR_CHSEL_SHIFT) +#define DMA_SxCR_CHSEL_2 (2 << DMA_SxCR_CHSEL_SHIFT) +#define DMA_SxCR_CHSEL_3 (3 << DMA_SxCR_CHSEL_SHIFT) +#define DMA_SxCR_CHSEL_4 (4 << DMA_SxCR_CHSEL_SHIFT) +#define DMA_SxCR_CHSEL_5 (5 << DMA_SxCR_CHSEL_SHIFT) +#define DMA_SxCR_CHSEL_6 (6 << DMA_SxCR_CHSEL_SHIFT) +#define DMA_SxCR_CHSEL_7 (7 << DMA_SxCR_CHSEL_SHIFT) +/**@}*/ +#define DMA_SxCR_CHSEL_SHIFT 25 +#define DMA_SxCR_CHSEL_MASK (7 << 25) +#define DMA_SxCR_CHSEL(n) (n << DMA_SxCR_CHSEL_SHIFT) + +/* Reserved [31:28] */ + +/* --- DMA_SxNDTR values --------------------------------------------------- */ + +/* DMA_SxNDTR[15:0]: Number of data register. */ + +/* --- DMA_SxPAR values ---------------------------------------------------- */ + +/* DMA_SxPAR[31:0]: Peripheral address register. */ + +/* --- DMA_SxM0AR values --------------------------------------------------- */ + +/* DMA_SxM0AR[31:0]: Memory 0 address register. */ + +/* --- DMA_SxM1AR values --------------------------------------------------- */ + +/* DMA_SxM1AR[31:0]: Memory 1 address register. */ + +/* --- DMA_SxFCR values ---------------------------------------------------- */ + +/* FTH[1:0]: FIFO Threshold selection */ +/** @defgroup dma_fifo_thresh FIFO Threshold selection +@ingroup STM32F4xx_dma_defines + +@{*/ +#define DMA_SxFCR_FTH_1_4_FULL (0 << 0) +#define DMA_SxFCR_FTH_2_4_FULL (1 << 0) +#define DMA_SxFCR_FTH_3_4_FULL (2 << 0) +#define DMA_SxFCR_FTH_4_4_FULL (3 << 0) +/**@}*/ +#define DMA_SxFCR_FTH_SHIFT 0 +#define DMA_SxFCR_FTH_MASK (3 << 0) + +/* DMDIS: Direct Mode disable */ +#define DMA_SxFCR_DMDIS (1 << 2) + +/* FS[5:3]: FIFO Status */ +/** @defgroup dma_fifo_status FIFO Status +@ingroup STM32F4xx_dma_defines + +@{*/ +#define DMA_SxFCR_FS_LT_1_4_FULL (0 << 0) +#define DMA_SxFCR_FS_LT_2_4_FULL (1 << 0) +#define DMA_SxFCR_FS_LT_3_4_FULL (2 << 0) +#define DMA_SxFCR_FS_LT_4_4_FULL (3 << 0) +#define DMA_SxFCR_FS_FULL (4 << 3) +#define DMA_SxFCR_FS_EMPTY (5 << 3) +/**@}*/ +#define DMA_SxFCR_FS_SHIFT 3 +#define DMA_SxFCR_FS_MASK (7 << 3) + +/* [6]: reserved */ + +/* FEIE[7]: FIFO error interrupt enable */ +#define DMA_SxFCR_FEIE (1 << 7) + +/* [31:8]: Reserved */ + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +/* + * Note: The F2 and F4 series have a completely new DMA peripheral with + * different configuration options. + */ + +void dma_stream_reset(uint32_t dma, uint8_t stream); +void dma_clear_interrupt_flags(uint32_t dma, uint8_t stream, + uint32_t interrupts); +bool dma_get_interrupt_flag(uint32_t dma, uint8_t stream, uint32_t interrupt); +void dma_set_transfer_mode(uint32_t dma, uint8_t stream, uint32_t direction); +void dma_set_priority(uint32_t dma, uint8_t stream, uint32_t prio); +void dma_set_memory_size(uint32_t dma, uint8_t stream, uint32_t mem_size); +void dma_set_peripheral_size(uint32_t dma, uint8_t stream, + uint32_t peripheral_size); +void dma_enable_memory_increment_mode(uint32_t dma, uint8_t stream); +void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel); +void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t stream); +void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t channel); +void dma_enable_fixed_peripheral_increment_mode(uint32_t dma, uint8_t stream); +void dma_enable_circular_mode(uint32_t dma, uint8_t stream); +void dma_channel_select(uint32_t dma, uint8_t stream, uint32_t channel); +void dma_set_memory_burst(uint32_t dma, uint8_t stream, uint32_t burst); +void dma_set_peripheral_burst(uint32_t dma, uint8_t stream, uint32_t burst); +void dma_set_initial_target(uint32_t dma, uint8_t stream, uint8_t memory); +uint8_t dma_get_target(uint32_t dma, uint8_t stream); +void dma_enable_double_buffer_mode(uint32_t dma, uint8_t stream); +void dma_disable_double_buffer_mode(uint32_t dma, uint8_t stream); +void dma_set_peripheral_flow_control(uint32_t dma, uint8_t stream); +void dma_set_dma_flow_control(uint32_t dma, uint8_t stream); +void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t stream); +void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t stream); +void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t stream); +void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t stream); +void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t stream); +void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t stream); +uint32_t dma_fifo_status(uint32_t dma, uint8_t stream); +void dma_enable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream); +void dma_disable_direct_mode_error_interrupt(uint32_t dma, uint8_t stream); +void dma_enable_fifo_error_interrupt(uint32_t dma, uint8_t stream); +void dma_disable_fifo_error_interrupt(uint32_t dma, uint8_t stream); +void dma_enable_direct_mode(uint32_t dma, uint8_t stream); +void dma_enable_fifo_mode(uint32_t dma, uint8_t stream); +void dma_set_fifo_threshold(uint32_t dma, uint8_t stream, uint32_t threshold); +void dma_enable_stream(uint32_t dma, uint8_t stream); +void dma_disable_stream(uint32_t dma, uint8_t stream); +void dma_set_peripheral_address(uint32_t dma, uint8_t stream, uint32_t address); +void dma_set_memory_address(uint32_t dma, uint8_t stream, uint32_t address); +void dma_set_memory_address_1(uint32_t dma, uint8_t stream, uint32_t address); +void dma_set_number_of_data(uint32_t dma, uint8_t stream, uint16_t number); + +END_DECLS +/**@}*/ +#endif +/** @cond */ +#else +#warning "dma_common_f24.h should not be included explicitly, only via dma.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/dma_common_l1f013.h b/libopencm3/include/libopencm3/stm32/common/dma_common_l1f013.h new file mode 100644 index 0000000..cb781a4 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/dma_common_l1f013.h @@ -0,0 +1,425 @@ +/** @addtogroup dma_defines + +@author @htmlonly © @endhtmlonly 2010 +Thomas Otto +@author @htmlonly © @endhtmlonly 2012 +Piotr Esden-Tempski + +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2012 Piotr Esden-Tempski + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H +The order of header inclusion is important. dma.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_DMA_H +/** @endcond */ +#ifndef LIBOPENCM3_DMA_COMMON_F13_H +#define LIBOPENCM3_DMA_COMMON_F13_H + +/* --- Convenience macros -------------------------------------------------- */ + +/* DMA register base adresses (for convenience) */ +#define DMA1 DMA1_BASE +#define DMA2 DMA2_BASE + +/* --- DMA registers ------------------------------------------------------- */ + +/* DMA interrupt status register (DMAx_ISR) */ +#define DMA_ISR(dma_base) MMIO32(dma_base + 0x00) +#define DMA1_ISR DMA_ISR(DMA1) +#define DMA2_ISR DMA_ISR(DMA2) + +/* DMA interrupt flag clear register (DMAx_IFCR) */ +#define DMA_IFCR(dma_base) MMIO32(dma_base + 0x04) +#define DMA1_IFCR DMA_IFCR(DMA1) +#define DMA2_IFCR DMA_IFCR(DMA2) + +/* DMA channel configuration register (DMAx_CCRy) */ +#define DMA_CCR(dma_base, channel) MMIO32(dma_base + 0x08 + \ + (0x14 * ((channel) - 1))) + +#define DMA1_CCR(channel) DMA_CCR(DMA1, channel) +#define DMA1_CCR1 DMA1_CCR(DMA_CHANNEL1) +#define DMA1_CCR2 DMA1_CCR(DMA_CHANNEL2) +#define DMA1_CCR3 DMA1_CCR(DMA_CHANNEL3) +#define DMA1_CCR4 DMA1_CCR(DMA_CHANNEL4) +#define DMA1_CCR5 DMA1_CCR(DMA_CHANNEL5) +#define DMA1_CCR6 DMA1_CCR(DMA_CHANNEL6) +#define DMA1_CCR7 DMA1_CCR(DMA_CHANNEL7) + +#define DMA2_CCR(channel) DMA_CCR(DMA2, channel) +#define DMA2_CCR1 DMA2_CCR(DMA_CHANNEL1) +#define DMA2_CCR2 DMA2_CCR(DMA_CHANNEL2) +#define DMA2_CCR3 DMA2_CCR(DMA_CHANNEL3) +#define DMA2_CCR4 DMA2_CCR(DMA_CHANNEL4) +#define DMA2_CCR5 DMA2_CCR(DMA_CHANNEL5) + +/* DMA number of data register (DMAx_CNDTRy) */ +#define DMA_CNDTR(dma_base, channel) MMIO32(dma_base + 0x0C + \ + (0x14 * ((channel) - 1))) + +#define DMA1_CNDTR(channel) DMA_CNDTR(DMA1, channel) +#define DMA1_CNDTR1 DMA1_CNDTR(DMA_CHANNEL1) +#define DMA1_CNDTR2 DMA1_CNDTR(DMA_CHANNEL2) +#define DMA1_CNDTR3 DMA1_CNDTR(DMA_CHANNEL3) +#define DMA1_CNDTR4 DMA1_CNDTR(DMA_CHANNEL4) +#define DMA1_CNDTR5 DMA1_CNDTR(DMA_CHANNEL5) +#define DMA1_CNDTR6 DMA1_CNDTR(DMA_CHANNEL6) +#define DMA1_CNDTR7 DMA1_CNDTR(DMA_CHANNEL7) + +#define DMA2_CNDTR(channel) DMA_CNDTR(DMA2, channel) +#define DMA2_CNDTR1 DMA2_CNDTR(DMA_CHANNEL1) +#define DMA2_CNDTR2 DMA2_CNDTR(DMA_CHANNEL2) +#define DMA2_CNDTR3 DMA2_CNDTR(DMA_CHANNEL3) +#define DMA2_CNDTR4 DMA2_CNDTR(DMA_CHANNEL4) +#define DMA2_CNDTR5 DMA2_CNDTR(DMA_CHANNEL5) + +/* DMA peripheral address register (DMAx_CPARy) */ +#define DMA_CPAR(dma_base, channel) MMIO32(dma_base + 0x10 + \ + (0x14 * ((channel) - 1))) + +#define DMA1_CPAR(channel) DMA_CPAR(DMA1, channel) +#define DMA1_CPAR1 DMA1_CPAR(DMA_CHANNEL1) +#define DMA1_CPAR2 DMA1_CPAR(DMA_CHANNEL2) +#define DMA1_CPAR3 DMA1_CPAR(DMA_CHANNEL3) +#define DMA1_CPAR4 DMA1_CPAR(DMA_CHANNEL4) +#define DMA1_CPAR5 DMA1_CPAR(DMA_CHANNEL5) +#define DMA1_CPAR6 DMA1_CPAR(DMA_CHANNEL6) +#define DMA1_CPAR7 DMA1_CPAR(DMA_CHANNEL7) + +#define DMA2_CPAR(channel) DMA_CPAR(DMA2, channel) +#define DMA2_CPAR1 DMA2_CPAR(DMA_CHANNEL1) +#define DMA2_CPAR2 DMA2_CPAR(DMA_CHANNEL2) +#define DMA2_CPAR3 DMA2_CPAR(DMA_CHANNEL3) +#define DMA2_CPAR4 DMA2_CPAR(DMA_CHANNEL4) +#define DMA2_CPAR5 DMA2_CPAR(DMA_CHANNEL5) + +/* DMA memory address register (DMAx_CMARy) */ + +#define DMA_CMAR(dma_base, channel) MMIO32(dma_base + 0x14 + \ + (0x14 * ((channel) - 1))) + +#define DMA1_CMAR(channel) DMA_CMAR(DMA1, channel) +#define DMA1_CMAR1 DMA1_CMAR(DMA_CHANNEL1) +#define DMA1_CMAR2 DMA1_CMAR(DMA_CHANNEL2) +#define DMA1_CMAR3 DMA1_CMAR(DMA_CHANNEL3) +#define DMA1_CMAR4 DMA1_CMAR(DMA_CHANNEL4) +#define DMA1_CMAR5 DMA1_CMAR(DMA_CHANNEL5) +#define DMA1_CMAR6 DMA1_CMAR(DMA_CHANNEL6) +#define DMA1_CMAR7 DMA1_CMAR(DMA_CHANNEL7) + +#define DMA2_CMAR(channel) DMA_CMAR(DMA2, channel) +#define DMA2_CMAR1 DMA2_CMAR(DMA_CHANNEL1) +#define DMA2_CMAR2 DMA2_CMAR(DMA_CHANNEL2) +#define DMA2_CMAR3 DMA2_CMAR(DMA_CHANNEL3) +#define DMA2_CMAR4 DMA2_CMAR(DMA_CHANNEL4) +#define DMA2_CMAR5 DMA2_CMAR(DMA_CHANNEL5) + +/* --- DMA_ISR values ------------------------------------------------------ */ + +/* --- DMA Interrupt Flag offset values ------------------------------------- */ +/* These are based on every interrupt flag and flag clear being at the same + * relative location + */ +/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within channel flag +group. +@ingroup dma_defines + +@{*/ +/** Transfer Error Interrupt Flag */ +#define DMA_TEIF (1 << 3) +/** Half Transfer Interrupt Flag */ +#define DMA_HTIF (1 << 2) +/** Transfer Complete Interrupt Flag */ +#define DMA_TCIF (1 << 1) +/** Global Interrupt Flag */ +#define DMA_GIF (1 << 0) +/**@}*/ + +/* Offset within interrupt status register to start of channel interrupt flag + * field + */ +#define DMA_FLAG_OFFSET(channel) (4*(channel - 1)) +#define DMA_FLAGS (DMA_TEIF | DMA_TCIF | DMA_HTIF | \ + DMA_GIF) +#define DMA_ISR_MASK(channel) (DMA_FLAGS << DMA_FLAG_OFFSET(channel)) + +/* TEIF: Transfer error interrupt flag */ +#define DMA_ISR_TEIF_BIT DMA_TEIF +#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) + +#define DMA_ISR_TEIF1 DMA_ISR_TEIF(DMA_CHANNEL1) +#define DMA_ISR_TEIF2 DMA_ISR_TEIF(DMA_CHANNEL2) +#define DMA_ISR_TEIF3 DMA_ISR_TEIF(DMA_CHANNEL3) +#define DMA_ISR_TEIF4 DMA_ISR_TEIF(DMA_CHANNEL4) +#define DMA_ISR_TEIF5 DMA_ISR_TEIF(DMA_CHANNEL5) +#define DMA_ISR_TEIF6 DMA_ISR_TEIF(DMA_CHANNEL6) +#define DMA_ISR_TEIF7 DMA_ISR_TEIF(DMA_CHANNEL7) + +/* HTIF: Half transfer interrupt flag */ +#define DMA_ISR_HTIF_BIT DMA_HTIF +#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) + +#define DMA_ISR_HTIF1 DMA_ISR_HTIF(DMA_CHANNEL1) +#define DMA_ISR_HTIF2 DMA_ISR_HTIF(DMA_CHANNEL2) +#define DMA_ISR_HTIF3 DMA_ISR_HTIF(DMA_CHANNEL3) +#define DMA_ISR_HTIF4 DMA_ISR_HTIF(DMA_CHANNEL4) +#define DMA_ISR_HTIF5 DMA_ISR_HTIF(DMA_CHANNEL5) +#define DMA_ISR_HTIF6 DMA_ISR_HTIF(DMA_CHANNEL6) +#define DMA_ISR_HTIF7 DMA_ISR_HTIF(DMA_CHANNEL7) + +/* TCIF: Transfer complete interrupt flag */ +#define DMA_ISR_TCIF_BIT DMA_TCIF +#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) + +#define DMA_ISR_TCIF1 DMA_ISR_TCIF(DMA_CHANNEL1) +#define DMA_ISR_TCIF2 DMA_ISR_TCIF(DMA_CHANNEL2) +#define DMA_ISR_TCIF3 DMA_ISR_TCIF(DMA_CHANNEL3) +#define DMA_ISR_TCIF4 DMA_ISR_TCIF(DMA_CHANNEL4) +#define DMA_ISR_TCIF5 DMA_ISR_TCIF(DMA_CHANNEL5) +#define DMA_ISR_TCIF6 DMA_ISR_TCIF(DMA_CHANNEL6) +#define DMA_ISR_TCIF7 DMA_ISR_TCIF(DMA_CHANNEL7) + +/* GIF: Global interrupt flag */ +#define DMA_ISR_GIF_BIT DMA_GIF +#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) + +#define DMA_ISR_GIF1 DMA_ISR_GIF(DMA_CHANNEL1) +#define DMA_ISR_GIF2 DMA_ISR_GIF(DMA_CHANNEL2) +#define DMA_ISR_GIF3 DMA_ISR_GIF(DMA_CHANNEL3) +#define DMA_ISR_GIF4 DMA_ISR_GIF(DMA_CHANNEL4) +#define DMA_ISR_GIF5 DMA_ISR_GIF(DMA_CHANNEL5) +#define DMA_ISR_GIF6 DMA_ISR_GIF(DMA_CHANNEL6) +#define DMA_ISR_GIF7 DMA_ISR_GIF(DMA_CHANNEL7) + +/* --- DMA_IFCR values ----------------------------------------------------- */ + +/* CTEIF: Transfer error clear */ +#define DMA_IFCR_CTEIF_BIT DMA_TEIF +#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) + +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF(DMA_CHANNEL1) +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF(DMA_CHANNEL2) +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF(DMA_CHANNEL3) +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF(DMA_CHANNEL4) +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF(DMA_CHANNEL5) +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF(DMA_CHANNEL6) +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF(DMA_CHANNEL7) + +/* CHTIF: Half transfer clear */ +#define DMA_IFCR_CHTIF_BIT DMA_HTIF +#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) + +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF(DMA_CHANNEL1) +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF(DMA_CHANNEL2) +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF(DMA_CHANNEL3) +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF(DMA_CHANNEL4) +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF(DMA_CHANNEL5) +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF(DMA_CHANNEL6) +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF(DMA_CHANNEL7) + +/* CTCIF: Transfer complete clear */ +#define DMA_IFCR_CTCIF_BIT DMA_TCIF +#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) + +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF(DMA_CHANNEL1) +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF(DMA_CHANNEL2) +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF(DMA_CHANNEL3) +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF(DMA_CHANNEL4) +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF(DMA_CHANNEL5) +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF(DMA_CHANNEL6) +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF(DMA_CHANNEL7) + +/* CGIF: Global interrupt clear */ +#define DMA_IFCR_CGIF_BIT DMA_GIF +#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) + +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF(DMA_CHANNEL1) +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF(DMA_CHANNEL2) +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF(DMA_CHANNEL3) +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF(DMA_CHANNEL4) +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF(DMA_CHANNEL5) +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF(DMA_CHANNEL6) +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF(DMA_CHANNEL7) + +/* Clear interrupts mask */ +#define DMA_IFCR_CIF_BIT 0xF +#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) + +#define DMA_IFCR_CIF1 DMA_IFCR_CIF(DMA_CHANNEL1) +#define DMA_IFCR_CIF2 DMA_IFCR_CIF(DMA_CHANNEL2) +#define DMA_IFCR_CIF3 DMA_IFCR_CIF(DMA_CHANNEL3) +#define DMA_IFCR_CIF4 DMA_IFCR_CIF(DMA_CHANNEL4) +#define DMA_IFCR_CIF5 DMA_IFCR_CIF(DMA_CHANNEL5) +#define DMA_IFCR_CIF6 DMA_IFCR_CIF(DMA_CHANNEL6) +#define DMA_IFCR_CIF7 DMA_IFCR_CIF(DMA_CHANNEL7) + +/* --- DMA_CCRx generic values --------------------------------------------- */ + +/* MEM2MEM: Memory to memory mode */ +#define DMA_CCR_MEM2MEM (1 << 14) + +/* PL[13:12]: Channel priority level */ +/** @defgroup dma_ch_pri DMA Channel Priority Levels +@ingroup dma_defines + +@{*/ +#define DMA_CCR_PL_LOW (0x0 << 12) +#define DMA_CCR_PL_MEDIUM (0x1 << 12) +#define DMA_CCR_PL_HIGH (0x2 << 12) +#define DMA_CCR_PL_VERY_HIGH (0x3 << 12) +/**@}*/ +#define DMA_CCR_PL_MASK (0x3 << 12) +#define DMA_CCR_PL_SHIFT 12 + +/* MSIZE[11:10]: Memory size */ +/** @defgroup dma_ch_memwidth DMA Channel Memory Word Width +@ingroup dma_defines + +@{*/ +#define DMA_CCR_MSIZE_8BIT (0x0 << 10) +#define DMA_CCR_MSIZE_16BIT (0x1 << 10) +#define DMA_CCR_MSIZE_32BIT (0x2 << 10) +/**@}*/ +#define DMA_CCR_MSIZE_MASK (0x3 << 10) +#define DMA_CCR_MSIZE_SHIFT 10 + +/* PSIZE[9:8]: Peripheral size */ +/** @defgroup dma_ch_perwidth DMA Channel Peripheral Word Width +@ingroup dma_defines + +@{*/ +#define DMA_CCR_PSIZE_8BIT (0x0 << 8) +#define DMA_CCR_PSIZE_16BIT (0x1 << 8) +#define DMA_CCR_PSIZE_32BIT (0x2 << 8) +/**@}*/ +#define DMA_CCR_PSIZE_MASK (0x3 << 8) +#define DMA_CCR_PSIZE_SHIFT 8 + +/* MINC: Memory increment mode */ +#define DMA_CCR_MINC (1 << 7) + +/* PINC: Peripheral increment mode */ +#define DMA_CCR_PINC (1 << 6) + +/* CIRC: Circular mode */ +#define DMA_CCR_CIRC (1 << 5) + +/* DIR: Data transfer direction */ +#define DMA_CCR_DIR (1 << 4) + +/* TEIE: Transfer error interrupt enable */ +#define DMA_CCR_TEIE (1 << 3) + +/* HTIE: Half transfer interrupt enable */ +#define DMA_CCR_HTIE (1 << 2) + +/* TCIE: Transfer complete interrupt enable */ +#define DMA_CCR_TCIE (1 << 1) + +/* EN: Channel enable */ +#define DMA_CCR_EN (1 << 0) + +/* --- DMA_CNDTRx values --------------------------------------------------- */ + +/* NDT[15:0]: Number of data to transfer */ + +/* --- DMA_CPARx values ---------------------------------------------------- */ + +/* PA[31:0]: Peripheral address */ + +/* --- DMA_CMARx values ---------------------------------------------------- */ + +/* MA[31:0]: Memory address */ + +/* --- Generic values ------------------------------------------------------ */ + +/** @defgroup dma_ch DMA Channel Number +@ingroup dma_defines + +@{*/ +#define DMA_CHANNEL1 1 +#define DMA_CHANNEL2 2 +#define DMA_CHANNEL3 3 +#define DMA_CHANNEL4 4 +#define DMA_CHANNEL5 5 +#define DMA_CHANNEL6 6 +#define DMA_CHANNEL7 7 +/**@}*/ + +/* --- function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void dma_channel_reset(uint32_t dma, uint8_t channel); +void dma_clear_interrupt_flags(uint32_t dma, uint8_t channel, + uint32_t interrupts); +bool dma_get_interrupt_flag(uint32_t dma, uint8_t channel, uint32_t interrupts); +void dma_enable_mem2mem_mode(uint32_t dma, uint8_t channel); +void dma_set_priority(uint32_t dma, uint8_t channel, uint32_t prio); +void dma_set_memory_size(uint32_t dma, uint8_t channel, uint32_t mem_size); +void dma_set_peripheral_size(uint32_t dma, uint8_t channel, + uint32_t peripheral_size); +void dma_enable_memory_increment_mode(uint32_t dma, uint8_t channel); +void dma_disable_memory_increment_mode(uint32_t dma, uint8_t channel); +void dma_enable_peripheral_increment_mode(uint32_t dma, uint8_t channel); +void dma_disable_peripheral_increment_mode(uint32_t dma, uint8_t channel); +void dma_enable_circular_mode(uint32_t dma, uint8_t channel); +void dma_set_read_from_peripheral(uint32_t dma, uint8_t channel); +void dma_set_read_from_memory(uint32_t dma, uint8_t channel); +void dma_enable_transfer_error_interrupt(uint32_t dma, uint8_t channel); +void dma_disable_transfer_error_interrupt(uint32_t dma, uint8_t channel); +void dma_enable_half_transfer_interrupt(uint32_t dma, uint8_t channel); +void dma_disable_half_transfer_interrupt(uint32_t dma, uint8_t channel); +void dma_enable_transfer_complete_interrupt(uint32_t dma, uint8_t channel); +void dma_disable_transfer_complete_interrupt(uint32_t dma, uint8_t channel); +void dma_enable_channel(uint32_t dma, uint8_t channel); +void dma_disable_channel(uint32_t dma, uint8_t channel); +void dma_set_peripheral_address(uint32_t dma, uint8_t channel, + uint32_t address); +void dma_set_memory_address(uint32_t dma, uint8_t channel, uint32_t address); +void dma_set_number_of_data(uint32_t dma, uint8_t channel, uint16_t number); + +END_DECLS + +#endif +/** @cond */ +#else +#warning "dma_common_f13.h should not be included explicitly, only via dma.h" +#endif +/** @endcond */ + +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/common/exti_common_all.h b/libopencm3/include/libopencm3/stm32/common/exti_common_all.h new file mode 100644 index 0000000..317c267 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/exti_common_all.h @@ -0,0 +1,87 @@ +/** @addtogroup exti_defines + * + * @author @htmlonly © @endhtmlonly 2010 + * Mark Butler + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Mark Butler + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/** @cond */ +#if defined(LIBOPENCM3_EXTI_H) +/** @endcond */ +#ifndef LIBOPENCM3_EXTI_COMMON_ALL_H +#define LIBOPENCM3_EXTI_COMMON_ALL_H +/**@{*/ + +/* --- EXTI registers ------------------------------------------------------ */ + +#define EXTI_IMR MMIO32(EXTI_BASE + 0x00) +#define EXTI_EMR MMIO32(EXTI_BASE + 0x04) +#define EXTI_RTSR MMIO32(EXTI_BASE + 0x08) +#define EXTI_FTSR MMIO32(EXTI_BASE + 0x0c) +#define EXTI_SWIER MMIO32(EXTI_BASE + 0x10) +#define EXTI_PR MMIO32(EXTI_BASE + 0x14) + +/* EXTI number definitions */ +#define EXTI0 (1 << 0) +#define EXTI1 (1 << 1) +#define EXTI2 (1 << 2) +#define EXTI3 (1 << 3) +#define EXTI4 (1 << 4) +#define EXTI5 (1 << 5) +#define EXTI6 (1 << 6) +#define EXTI7 (1 << 7) +#define EXTI8 (1 << 8) +#define EXTI9 (1 << 9) +#define EXTI10 (1 << 10) +#define EXTI11 (1 << 11) +#define EXTI12 (1 << 12) +#define EXTI13 (1 << 13) +#define EXTI14 (1 << 14) +#define EXTI15 (1 << 15) +#define EXTI16 (1 << 16) +#define EXTI17 (1 << 17) +#define EXTI18 (1 << 18) +#define EXTI19 (1 << 19) + +/* Trigger types */ +enum exti_trigger_type { + EXTI_TRIGGER_RISING, + EXTI_TRIGGER_FALLING, + EXTI_TRIGGER_BOTH, +}; + +BEGIN_DECLS + +void exti_set_trigger(uint32_t extis, enum exti_trigger_type trig); +void exti_enable_request(uint32_t extis); +void exti_disable_request(uint32_t extis); +void exti_reset_request(uint32_t extis); +void exti_select_source(uint32_t exti, uint32_t gpioport); +uint32_t exti_get_flag_status(uint32_t exti); + +END_DECLS +/**@}*/ + +#endif +/** @cond */ +#else +#warning "exti_common_all.h should not be included directly, only via exti.h" +#endif +/** @endcond */ diff --git a/libopencm3/include/libopencm3/stm32/common/exti_common_l1f24.h b/libopencm3/include/libopencm3/stm32/common/exti_common_l1f24.h new file mode 100644 index 0000000..60f5c1b --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/exti_common_l1f24.h @@ -0,0 +1,45 @@ +/** @addtogroup exti_defines + * + * @author @htmlonly © @endhtmlonly 2010 + * Mark Butler + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Mark Butler + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/** @cond */ +#if defined(LIBOPENCM3_EXTI_H) +/** @endcond */ +#ifndef LIBOPENCM3_EXTI_COMMON_F24_H +#define LIBOPENCM3_EXTI_COMMON_F24_H +/**@{*/ + +#include + +/* EXTI number definitions */ +#define EXTI20 (1 << 20) +#define EXTI21 (1 << 21) +#define EXTI22 (1 << 22) +/**@}*/ + +#endif +/** @cond */ +#else +#warning "exti_common_f24.h should not be included directly, only via exti.h" +#endif +/** @endcond */ diff --git a/libopencm3/include/libopencm3/stm32/common/flash_common_f01.h b/libopencm3/include/libopencm3/stm32/common/flash_common_f01.h new file mode 100644 index 0000000..e765c3b --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/flash_common_f01.h @@ -0,0 +1,130 @@ +/** @addtogroup flash_defines + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2010 Mark Butler + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* + * For details see: + * PM0081 Programming manual: STM32F40xxx and STM32F41xxx Flash programming + * September 2011, Doc ID 018520 Rev 1 + * https://github.com/libopencm3/libopencm3-archive/blob/master/st_micro/DM00023388.pdf + */ + +/** @cond */ +#ifdef LIBOPENCM3_FLASH_H +/** @endcond */ +#ifndef LIBOPENCM3_FLASH_COMMON_F01_H +#define LIBOPENCM3_FLASH_COMMON_F01_H +/**@{*/ + +/* --- FLASH registers ----------------------------------------------------- */ + +#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) +#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) +#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) +#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) +#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) +#define FLASH_AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) +#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1C) +#define FLASH_WRPR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) +/* Only present in STM32F10x XL series */ +#define FLASH_KEYR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x44) +#define FLASH_SR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x4C) +#define FLASH_CR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x50) +#define FLASH_AR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x54) + +/* --- FLASH_OPTION bytes ------------------------------------------------- */ + +#define FLASH_OPTION_BYTE(i) MMIO16(INFO_BASE+0x0800 + (i)*2) + +/* --- FLASH_ACR values ---------------------------------------------------- */ + +#define FLASH_ACR_LATENCY_SHIFT 0 +#define FLASH_ACR_LATENCY 7 + +#define FLASH_ACR_PRFTBS (1 << 5) +#define FLASH_ACR_PRFTBE (1 << 4) + +/* --- FLASH_SR values ----------------------------------------------------- */ + +#define FLASH_SR_EOP (1 << 5) +#define FLASH_SR_WRPRTERR (1 << 4) +#define FLASH_SR_PGERR (1 << 2) +#define FLASH_SR_BSY (1 << 0) + +/* --- FLASH_CR values ----------------------------------------------------- */ + +#define FLASH_CR_EOPIE (1 << 12) +#define FLASH_CR_ERRIE (1 << 10) +#define FLASH_CR_OPTWRE (1 << 9) +#define FLASH_CR_LOCK (1 << 7) +#define FLASH_CR_STRT (1 << 6) +#define FLASH_CR_OPTER (1 << 5) +#define FLASH_CR_OPTPG (1 << 4) +#define FLASH_CR_MER (1 << 2) +#define FLASH_CR_PER (1 << 1) +#define FLASH_CR_PG (1 << 0) + +/* --- FLASH_OBR values ---------------------------------------------------- */ + +#define FLASH_OBR_RDPRT_SHIFT 1 +#define FLASH_OBR_OPTERR (1 << 0) + +/* --- FLASH Keys -----------------------------------------------------------*/ + +#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab) + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void flash_set_ws(uint32_t ws); +void flash_prefetch_buffer_enable(void); +void flash_prefetch_buffer_disable(void); +void flash_unlock(void); +void flash_lock(void); +void flash_clear_pgerr_flag(void); +void flash_clear_eop_flag(void); +void flash_clear_wrprterr_flag(void); +void flash_clear_bsy_flag(void); +void flash_clear_status_flags(void); +uint32_t flash_get_status_flags(void); +void flash_wait_for_last_operation(void); +void flash_program_word(uint32_t address, uint32_t data); +void flash_program_half_word(uint32_t address, uint16_t data); +void flash_erase_page(uint32_t page_address); +void flash_erase_all_pages(void); +void flash_unlock_option_bytes(void); +void flash_erase_option_bytes(void); +void flash_program_option_bytes(uint32_t address, uint16_t data); + +END_DECLS +/**@}*/ + +#endif +/** @cond */ +#else +#warning "flash_common_f01.h should not be included directly," +#warning "only via flash.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/flash_common_f234.h b/libopencm3/include/libopencm3/stm32/common/flash_common_f234.h new file mode 100644 index 0000000..a012cf6 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/flash_common_f234.h @@ -0,0 +1,93 @@ +/** @addtogroup flash_defines + * + * @author @htmlonly © @endhtmlonly 2010 + * Thomas Otto + * @author @htmlonly © @endhtmlonly 2010 + * Mark Butler + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2010 Mark Butler + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* + * For details see: + * PM0081 Programming manual: STM32F40xxx and STM32F41xxx Flash programming + * September 2011, Doc ID 018520 Rev 1 + * https://github.com/libopencm3/libopencm3-archive/blob/master/st_micro/DM00023388.pdf + */ + +/** @cond */ +#ifdef LIBOPENCM3_FLASH_H +/** @endcond */ +#ifndef LIBOPENCM3_FLASH_COMMON_F234_H +#define LIBOPENCM3_FLASH_COMMON_F234_H +/**@{*/ + +/* --- FLASH registers ----------------------------------------------------- */ + +#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) +#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) +#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) +#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) +#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) + +/* --- FLASH_ACR values ---------------------------------------------------- */ + +#define FLASH_ACR_LATENCY_0WS 0x00 +#define FLASH_ACR_LATENCY_1WS 0x01 +#define FLASH_ACR_LATENCY_2WS 0x02 +#define FLASH_ACR_LATENCY_3WS 0x03 +#define FLASH_ACR_LATENCY_4WS 0x04 +#define FLASH_ACR_LATENCY_5WS 0x05 +#define FLASH_ACR_LATENCY_6WS 0x06 +#define FLASH_ACR_LATENCY_7WS 0x07 + +/* --- FLASH_SR values ----------------------------------------------------- */ + +/* --- FLASH_CR values ----------------------------------------------------- */ + +/* --- FLASH Keys -----------------------------------------------------------*/ + +#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab) + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void flash_set_ws(uint32_t ws); +void flash_unlock(void); +void flash_lock(void); +void flash_clear_pgperr_flag(void); +void flash_clear_eop_flag(void); +void flash_clear_bsy_flag(void); +void flash_clear_status_flags(void); +void flash_wait_for_last_operation(void); + +END_DECLS +/**@}*/ + +#endif +/** @cond */ +#else +#warning "flash_common_f234.h should not be included direcitly," +#warning "only via flash.h" +#endif +/** @endcond */ diff --git a/libopencm3/include/libopencm3/stm32/common/flash_common_f24.h b/libopencm3/include/libopencm3/stm32/common/flash_common_f24.h new file mode 100644 index 0000000..b47329c --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/flash_common_f24.h @@ -0,0 +1,148 @@ +/** @addtogroup flash_defines + * + * @author @htmlonly © @endhtmlonly 2010 + * Thomas Otto + * @author @htmlonly © @endhtmlonly 2010 + * Mark Butler + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2010 Mark Butler + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* + * For details see: + * PM0081 Programming manual: STM32F40xxx and STM32F41xxx Flash programming + * September 2011, Doc ID 018520 Rev 1 + * https://github.com/libopencm3/libopencm3-archive/blob/master/st_micro/DM00023388.pdf + */ + +/** @cond */ +#ifdef LIBOPENCM3_FLASH_H +/** @endcond */ +#ifndef LIBOPENCM3_FLASH_COMMON_F24_H +#define LIBOPENCM3_FLASH_COMMON_F24_H +/**@{*/ + +#include + +/* --- FLASH registers ----------------------------------------------------- */ + +#define FLASH_OPTCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) + +/* --- FLASH_ACR values ---------------------------------------------------- */ + +#define FLASH_ACR_DCRST (1 << 12) +#define FLASH_ACR_ICRST (1 << 11) +#define FLASH_ACR_DCE (1 << 10) +#define FLASH_ACR_ICE (1 << 9) +#define FLASH_ACR_PRFTEN (1 << 8) + +/* --- FLASH_SR values ----------------------------------------------------- */ + +#define FLASH_SR_BSY (1 << 16) +#define FLASH_SR_PGSERR (1 << 7) +#define FLASH_SR_PGPERR (1 << 6) +#define FLASH_SR_PGAERR (1 << 5) +#define FLASH_SR_WRPERR (1 << 4) +#define FLASH_SR_OPERR (1 << 1) +#define FLASH_SR_EOP (1 << 0) + +/* --- FLASH_CR values ----------------------------------------------------- */ + +#define FLASH_CR_LOCK (1 << 31) +#define FLASH_CR_ERRIE (1 << 25) +#define FLASH_CR_EOPIE (1 << 24) +#define FLASH_CR_STRT (1 << 16) +#define FLASH_CR_MER (1 << 2) +#define FLASH_CR_SER (1 << 1) +#define FLASH_CR_PG (1 << 0) +#define FLASH_CR_SECTOR_0 (0x00 << 3) +#define FLASH_CR_SECTOR_1 (0x01 << 3) +#define FLASH_CR_SECTOR_2 (0x02 << 3) +#define FLASH_CR_SECTOR_3 (0x03 << 3) +#define FLASH_CR_SECTOR_4 (0x04 << 3) +#define FLASH_CR_SECTOR_5 (0x05 << 3) +#define FLASH_CR_SECTOR_6 (0x06 << 3) +#define FLASH_CR_SECTOR_7 (0x07 << 3) +#define FLASH_CR_SECTOR_8 (0x08 << 3) +#define FLASH_CR_SECTOR_9 (0x09 << 3) +#define FLASH_CR_SECTOR_10 (0x0a << 3) +#define FLASH_CR_SECTOR_11 (0x0b << 3) +#define FLASH_CR_PROGRAM_X8 (0x00 << 8) +#define FLASH_CR_PROGRAM_X16 (0x01 << 8) +#define FLASH_CR_PROGRAM_X32 (0x02 << 8) +#define FLASH_CR_PROGRAM_X64 (0x03 << 8) + +/* --- FLASH_OPTCR values -------------------------------------------------- */ + +/* FLASH_OPTCR[27:16]: nWRP */ +/* FLASH_OBR[15:8]: RDP */ +#define FLASH_OPTCR_NRST_STDBY (1 << 7) +#define FLASH_OPTCR_NRST_STOP (1 << 6) +#define FLASH_OPTCR_WDG_SW (1 << 5) +#define FLASH_OPTCR_OPTSTRT (1 << 1) +#define FLASH_OPTCR_OPTLOCK (1 << 0) +#define FLASH_OPTCR_BOR_LEVEL_3 (0x00 << 2) +#define FLASH_OPTCR_BOR_LEVEL_2 (0x01 << 2) +#define FLASH_OPTCR_BOR_LEVEL_1 (0x02 << 2) +#define FLASH_OPTCR_BOR_OFF (0x03 << 2) + +/* --- FLASH Keys -----------------------------------------------------------*/ + +#define FLASH_OPTKEYR_KEY1 ((uint32_t)0x08192a3b) +#define FLASH_OPTKEYR_KEY2 ((uint32_t)0x4c5d6e7f) + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void flash_unlock_option_bytes(void); +void flash_lock_option_bytes(void); +void flash_clear_pgserr_flag(void); +void flash_clear_wrperr_flag(void); +void flash_clear_pgaerr_flag(void); +void flash_dcache_enable(void); +void flash_dcache_disable(void); +void flash_icache_enable(void); +void flash_icache_disable(void); +void flash_prefetch_enable(void); +void flash_prefetch_disable(void); +void flash_dcache_reset(void); +void flash_icache_reset(void); +void flash_erase_all_sectors(uint32_t program_size); +void flash_erase_sector(uint8_t sector, uint32_t program_size); +void flash_program_double_word(uint32_t address, uint64_t data); +void flash_program_word(uint32_t address, uint32_t data); +void flash_program_half_word(uint32_t address, uint16_t data); +void flash_program_byte(uint32_t address, uint8_t data); +void flash_program(uint32_t address, uint8_t *data, uint32_t len); +void flash_program_option_bytes(uint32_t data); + +END_DECLS +/**@}*/ + +#endif +/** @cond */ +#else +#warning "flash_common_f24.h should not be included direcitly," +#warning "only via flash.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/gpio_common_all.h b/libopencm3/include/libopencm3/stm32/common/gpio_common_all.h new file mode 100644 index 0000000..fcfd31e --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/gpio_common_all.h @@ -0,0 +1,91 @@ +/** @addtogroup gpio_defines + * + * @author @htmlonly © @endhtmlonly 2011 + * Fergus Noble + * @author @htmlonly © @endhtmlonly 2012 + * Ken Sarkies + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * Copyright (C) 2012 Ken Sarkies + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H +The order of header inclusion is important. gpio.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#if defined(LIBOPENCM3_GPIO_H) +/** @endcond */ +#ifndef LIBOPENCM3_GPIO_COMMON_ALL_H +#define LIBOPENCM3_GPIO_COMMON_ALL_H + +/**@{*/ + +/* --- Convenience macros -------------------------------------------------- */ + +/* --- GPIO_LCKR values ---------------------------------------------------- */ + +#define GPIO_LCKK (1 << 16) +/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */ + +/* GPIO number definitions (for convenience) */ +/** @defgroup gpio_pin_id GPIO Pin Identifiers +@ingroup gpio_defines + +@{*/ +#define GPIO0 (1 << 0) +#define GPIO1 (1 << 1) +#define GPIO2 (1 << 2) +#define GPIO3 (1 << 3) +#define GPIO4 (1 << 4) +#define GPIO5 (1 << 5) +#define GPIO6 (1 << 6) +#define GPIO7 (1 << 7) +#define GPIO8 (1 << 8) +#define GPIO9 (1 << 9) +#define GPIO10 (1 << 10) +#define GPIO11 (1 << 11) +#define GPIO12 (1 << 12) +#define GPIO13 (1 << 13) +#define GPIO14 (1 << 14) +#define GPIO15 (1 << 15) +#define GPIO_ALL 0xffff +/**@}*/ + +BEGIN_DECLS + +void gpio_set(uint32_t gpioport, uint16_t gpios); +void gpio_clear(uint32_t gpioport, uint16_t gpios); +uint16_t gpio_get(uint32_t gpioport, uint16_t gpios); +void gpio_toggle(uint32_t gpioport, uint16_t gpios); +uint16_t gpio_port_read(uint32_t gpioport); +void gpio_port_write(uint32_t gpioport, uint16_t data); +void gpio_port_config_lock(uint32_t gpioport, uint16_t gpios); + +END_DECLS + +/**@}*/ +#endif +/** @cond */ +#else +#warning "gpio_common_all.h should not be included explicitly, only via gpio.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/gpio_common_f234.h b/libopencm3/include/libopencm3/stm32/common/gpio_common_f234.h new file mode 100644 index 0000000..e574a1b --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/gpio_common_f234.h @@ -0,0 +1,272 @@ +/** @addtogroup gpio_defines + * + * @author @htmlonly © @endhtmlonly 2011 + * Fergus Noble + * @author @htmlonly © @endhtmlonly 2012 + * Ken Sarkies + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * Copyright (C) 2012 Ken Sarkies + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H +The order of header inclusion is important. gpio.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_GPIO_H +/** @endcond */ +#ifndef LIBOPENCM3_GPIO_COMMON_F234_H +#define LIBOPENCM3_GPIO_COMMON_F234_H + +/**@{*/ + +#include + +/* GPIO port base addresses (for convenience) */ +/** @defgroup gpio_port_id GPIO Port IDs +@ingroup gpio_defines + +@{*/ +#define GPIOA GPIO_PORT_A_BASE +#define GPIOB GPIO_PORT_B_BASE +#define GPIOC GPIO_PORT_C_BASE +#define GPIOD GPIO_PORT_D_BASE +#define GPIOE GPIO_PORT_E_BASE +#define GPIOF GPIO_PORT_F_BASE + +/**@}*/ + +/* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------- */ + +/* Port mode register (GPIOx_MODER) */ +#define GPIO_MODER(port) MMIO32(port + 0x00) +#define GPIOA_MODER GPIO_MODER(GPIOA) +#define GPIOB_MODER GPIO_MODER(GPIOB) +#define GPIOC_MODER GPIO_MODER(GPIOC) +#define GPIOD_MODER GPIO_MODER(GPIOD) +#define GPIOE_MODER GPIO_MODER(GPIOE) +#define GPIOF_MODER GPIO_MODER(GPIOF) + +/* Port output type register (GPIOx_OTYPER) */ +#define GPIO_OTYPER(port) MMIO32(port + 0x04) +#define GPIOA_OTYPER GPIO_OTYPER(GPIOA) +#define GPIOB_OTYPER GPIO_OTYPER(GPIOB) +#define GPIOC_OTYPER GPIO_OTYPER(GPIOC) +#define GPIOD_OTYPER GPIO_OTYPER(GPIOD) +#define GPIOE_OTYPER GPIO_OTYPER(GPIOE) +#define GPIOF_OTYPER GPIO_OTYPER(GPIOF) + +/* Port output speed register (GPIOx_OSPEEDR) */ +#define GPIO_OSPEEDR(port) MMIO32(port + 0x08) +#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA) +#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB) +#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC) +#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD) +#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE) +#define GPIOF_OSPEEDR GPIO_OSPEEDR(GPIOF) + +/* Port pull-up/pull-down register (GPIOx_PUPDR) */ +#define GPIO_PUPDR(port) MMIO32(port + 0x0c) +#define GPIOA_PUPDR GPIO_PUPDR(GPIOA) +#define GPIOB_PUPDR GPIO_PUPDR(GPIOB) +#define GPIOC_PUPDR GPIO_PUPDR(GPIOC) +#define GPIOD_PUPDR GPIO_PUPDR(GPIOD) +#define GPIOE_PUPDR GPIO_PUPDR(GPIOE) +#define GPIOF_PUPDR GPIO_PUPDR(GPIOF) + +/* Port input data register (GPIOx_IDR) */ +#define GPIO_IDR(port) MMIO32(port + 0x10) +#define GPIOA_IDR GPIO_IDR(GPIOA) +#define GPIOB_IDR GPIO_IDR(GPIOB) +#define GPIOC_IDR GPIO_IDR(GPIOC) +#define GPIOD_IDR GPIO_IDR(GPIOD) +#define GPIOE_IDR GPIO_IDR(GPIOE) +#define GPIOF_IDR GPIO_IDR(GPIOF) + +/* Port output data register (GPIOx_ODR) */ +#define GPIO_ODR(port) MMIO32(port + 0x14) +#define GPIOA_ODR GPIO_ODR(GPIOA) +#define GPIOB_ODR GPIO_ODR(GPIOB) +#define GPIOC_ODR GPIO_ODR(GPIOC) +#define GPIOD_ODR GPIO_ODR(GPIOD) +#define GPIOE_ODR GPIO_ODR(GPIOE) +#define GPIOF_ODR GPIO_ODR(GPIOF) + +/* Port bit set/reset register (GPIOx_BSRR) */ +#define GPIO_BSRR(port) MMIO32(port + 0x18) +#define GPIOA_BSRR GPIO_BSRR(GPIOA) +#define GPIOB_BSRR GPIO_BSRR(GPIOB) +#define GPIOC_BSRR GPIO_BSRR(GPIOC) +#define GPIOD_BSRR GPIO_BSRR(GPIOD) +#define GPIOE_BSRR GPIO_BSRR(GPIOE) +#define GPIOF_BSRR GPIO_BSRR(GPIOF) + +/* Port configuration lock register (GPIOx_LCKR) */ +#define GPIO_LCKR(port) MMIO32(port + 0x1c) +#define GPIOA_LCKR GPIO_LCKR(GPIOA) +#define GPIOB_LCKR GPIO_LCKR(GPIOB) +#define GPIOC_LCKR GPIO_LCKR(GPIOC) +#define GPIOD_LCKR GPIO_LCKR(GPIOD) +#define GPIOE_LCKR GPIO_LCKR(GPIOE) +#define GPIOF_LCKR GPIO_LCKR(GPIOF) + +/* Alternate function low register (GPIOx_AFRL) */ +#define GPIO_AFRL(port) MMIO32(port + 0x20) +#define GPIOA_AFRL GPIO_AFRL(GPIOA) +#define GPIOB_AFRL GPIO_AFRL(GPIOB) +#define GPIOC_AFRL GPIO_AFRL(GPIOC) +#define GPIOD_AFRL GPIO_AFRL(GPIOD) +#define GPIOE_AFRL GPIO_AFRL(GPIOE) +#define GPIOF_AFRL GPIO_AFRL(GPIOF) + +/* Alternate function high register (GPIOx_AFRH) */ +#define GPIO_AFRH(port) MMIO32(port + 0x24) +#define GPIOA_AFRH GPIO_AFRH(GPIOA) +#define GPIOB_AFRH GPIO_AFRH(GPIOB) +#define GPIOC_AFRH GPIO_AFRH(GPIOC) +#define GPIOD_AFRH GPIO_AFRH(GPIOD) +#define GPIOE_AFRH GPIO_AFRH(GPIOE) +#define GPIOF_AFRH GPIO_AFRH(GPIOF) + +/* --- GPIOx_MODER values -------------------------------------------------- */ + +#define GPIO_MODE(n, mode) (mode << (2 * (n))) +#define GPIO_MODE_MASK(n) (0x3 << (2 * (n))) +/** @defgroup gpio_mode GPIO Pin Direction and Analog/Digital Mode +@ingroup gpio_defines +@{*/ +#define GPIO_MODE_INPUT 0x0 +#define GPIO_MODE_OUTPUT 0x1 +#define GPIO_MODE_AF 0x2 +#define GPIO_MODE_ANALOG 0x3 +/**@}*/ + +/* --- GPIOx_OTYPER values ------------------------------------------------- */ + +/** @defgroup gpio_output_type GPIO Output Pin Driver Type +@ingroup gpio_defines +@list Push Pull +@list Open Drain +@{*/ +#define GPIO_OTYPE_PP 0x0 +#define GPIO_OTYPE_OD 0x1 +/**@}*/ + +/* --- GPIOx_OSPEEDR values ------------------------------------------------ */ + +#define GPIO_OSPEED(n, speed) (speed << (2 * (n))) +#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n))) +/** @defgroup gpio_speed GPIO Output Pin Speed +@ingroup gpio_defines +@{*/ +#define GPIO_OSPEED_2MHZ 0x0 +#define GPIO_OSPEED_25MHZ 0x1 +#define GPIO_OSPEED_50MHZ 0x2 +#define GPIO_OSPEED_100MHZ 0x3 +/**@}*/ + +/* --- GPIOx_PUPDR values -------------------------------------------------- */ + +#define GPIO_PUPD(n, pupd) (pupd << (2 * (n))) +#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n))) +/** @defgroup gpio_pup GPIO Output Pin Pullup +@ingroup gpio_defines +@{*/ +#define GPIO_PUPD_NONE 0x0 +#define GPIO_PUPD_PULLUP 0x1 +#define GPIO_PUPD_PULLDOWN 0x2 +/**@}*/ + +/* --- GPIOx_IDR values ---------------------------------------------------- */ + +/* GPIOx_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */ + +/* --- GPIOx_ODR values ---------------------------------------------------- */ + +/* GPIOx_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */ + +/* --- GPIOx_BSRR values --------------------------------------------------- */ + +/* GPIOx_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */ +/* GPIOx_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */ + +/* --- GPIOx_LCKR values --------------------------------------------------- */ + +#define GPIO_LCKK (1 << 16) +/* GPIOx_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */ + +/* --- GPIOx_AFRL/H values ------------------------------------------------- */ + +/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */ +/* See datasheet table 6 (pg. 48) for alternate function mappings. */ + +#define GPIO_AFR(n, af) (af << ((n) * 4)) +#define GPIO_AFR_MASK(n) (0xf << ((n) * 4)) +/** @defgroup gpio_af_num Alternate Function Pin Selection +@ingroup gpio_defines +@{*/ +#define GPIO_AF0 0x0 +#define GPIO_AF1 0x1 +#define GPIO_AF2 0x2 +#define GPIO_AF3 0x3 +#define GPIO_AF4 0x4 +#define GPIO_AF5 0x5 +#define GPIO_AF6 0x6 +#define GPIO_AF7 0x7 +#define GPIO_AF8 0x8 +#define GPIO_AF9 0x9 +#define GPIO_AF10 0xa +#define GPIO_AF11 0xb +#define GPIO_AF12 0xc +#define GPIO_AF13 0xd +#define GPIO_AF14 0xe +#define GPIO_AF15 0xf +/**@}*/ + +/* Note: EXTI source selection is now in the SYSCFG peripheral. */ + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +/* + * Note: The F2 and F4 series have a completely new GPIO peripheral with + * different configuration options. Here we implement a different API partly to + * more closely match the peripheral capabilities and also to deliberately + * break compatibility with old F1 code so there is no confusion with similar + * sounding functions that have very different functionality. + */ + +void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, + uint16_t gpios); +void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, + uint16_t gpios); +void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint16_t gpios); + +END_DECLS +/**@}*/ +#endif +/** @cond */ +#else +#warning "gpio_common_f234.h should not be included explicitly, only via gpio.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/gpio_common_f24.h b/libopencm3/include/libopencm3/stm32/common/gpio_common_f24.h new file mode 100644 index 0000000..69e18c7 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/gpio_common_f24.h @@ -0,0 +1,111 @@ +/** @addtogroup gpio_defines + * + * @author @htmlonly © @endhtmlonly 2011 + * Fergus Noble + * @author @htmlonly © @endhtmlonly 2012 + * Ken Sarkies + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * Copyright (C) 2012 Ken Sarkies + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H +The order of header inclusion is important. gpio.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_GPIO_H +/** @endcond */ +#ifndef LIBOPENCM3_GPIO_COMMON_F24_H +#define LIBOPENCM3_GPIO_COMMON_F24_H + +/**@{*/ + +#include + +/* GPIO port base addresses (for convenience) */ +/** @defgroup gpio_port_id GPIO Port IDs +@ingroup gpio_defines + +@{*/ +#define GPIOG GPIO_PORT_G_BASE +#define GPIOH GPIO_PORT_H_BASE +#define GPIOI GPIO_PORT_I_BASE +/**@}*/ + +/* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------- */ + +/* Port mode register (GPIOx_MODER) */ +#define GPIOG_MODER GPIO_MODER(GPIOG) +#define GPIOH_MODER GPIO_MODER(GPIOH) +#define GPIOI_MODER GPIO_MODER(GPIOI) + +/* Port output type register (GPIOx_OTYPER) */ +#define GPIOG_OTYPER GPIO_OTYPER(GPIOG) +#define GPIOH_OTYPER GPIO_OTYPER(GPIOH) +#define GPIOI_OTYPER GPIO_OTYPER(GPIOI) + +/* Port output speed register (GPIOx_OSPEEDR) */ +#define GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG) +#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH) +#define GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI) + +/* Port pull-up/pull-down register (GPIOx_PUPDR) */ +#define GPIOG_PUPDR GPIO_PUPDR(GPIOG) +#define GPIOH_PUPDR GPIO_PUPDR(GPIOH) +#define GPIOI_PUPDR GPIO_PUPDR(GPIOI) + +/* Port input data register (GPIOx_IDR) */ +#define GPIOG_IDR GPIO_IDR(GPIOG) +#define GPIOH_IDR GPIO_IDR(GPIOH) +#define GPIOI_IDR GPIO_IDR(GPIOI) + +/* Port output data register (GPIOx_ODR) */ +#define GPIOG_ODR GPIO_ODR(GPIOG) +#define GPIOH_ODR GPIO_ODR(GPIOH) +#define GPIOI_ODR GPIO_ODR(GPIOI) + +/* Port bit set/reset register (GPIOx_BSRR) */ +#define GPIOG_BSRR GPIO_BSRR(GPIOG) +#define GPIOH_BSRR GPIO_BSRR(GPIOH) +#define GPIOI_BSRR GPIO_BSRR(GPIOI) + +/* Port configuration lock register (GPIOx_LCKR) */ +#define GPIOG_LCKR GPIO_LCKR(GPIOG) +#define GPIOH_LCKR GPIO_LCKR(GPIOH) +#define GPIOI_LCKR GPIO_LCKR(GPIOI) + +/* Alternate function low register (GPIOx_AFRL) */ +#define GPIOG_AFRL GPIO_AFRL(GPIOG) +#define GPIOH_AFRL GPIO_AFRL(GPIOH) +#define GPIOI_AFRL GPIO_AFRL(GPIOI) + +/* Alternate function high register (GPIOx_AFRH) */ +#define GPIOG_AFRH GPIO_AFRH(GPIOG) +#define GPIOH_AFRH GPIO_AFRH(GPIOH) +#define GPIOI_AFRH GPIO_AFRH(GPIOI) + +/**@}*/ +#endif +/** @cond */ +#else +#warning "gpio_common_f24.h should not be included explicitly, only via gpio.h" +#endif +/** @endcond */ diff --git a/libopencm3/include/libopencm3/stm32/common/hash_common_f24.h b/libopencm3/include/libopencm3/stm32/common/hash_common_f24.h new file mode 100644 index 0000000..6c43302 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/hash_common_f24.h @@ -0,0 +1,181 @@ +/** @addtogroup hash_defines + * + * @author @htmlonly © @endhtmlonly 2013 + * Mikhail Avkhimenia + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Mikhail Avkhimenia + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +/** @cond */ +#ifdef LIBOPENCM3_HASH_H +/** @endcond */ +#ifndef LIBOPENCM3_HASH_COMMON_F24_H +#define LIBOPENCM3_HASH_COMMON_F24_H + +/* --- Convenience macros -------------------------------------------------- */ + +/****************************************************************************/ +/** @defgroup hash_reg_base HASH register base addresses +@ingroup STM32F_hash_defines + +@{*/ +#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400) +#define HASH HASH_BASE +/**@}*/ + +/* --- HASH registers ------------------------------------------------------ */ + +/* HASH control register (HASH_CR) */ +#define HASH_CR MMIO32(HASH + 0x00) + +/* HASH data input register (HASH_DIR) */ +#define HASH_DIN MMIO32(HASH + 0x04) + +/* HASH start register (HASH_STR) */ +#define HASH_STR MMIO32(HASH + 0x08) + +/* HASH digest registers (HASH_HR[5]) */ +#define HASH_HR (&MMIO32(HASH + 0x0C)) /* x5 */ + +/* HASH interrupt enable register (HASH_IMR) */ +#define HASH_IMR MMIO32(HASH + 0x20) + +/* HASH status register (HASH_SR) */ +#define HASH_SR MMIO32(HASH + 0x28) + +/* HASH context swap registers (HASH_CSR[51]) */ +#define HASH_CSR (&MMIO32(HASH + 0xF8)) /* x51 */ + +/* --- HASH_CR values ------------------------------------------------------ */ + +/* INIT: Initialize message digest calculation */ +#define HASH_CR_INIT (1 << 2) + +/* DMAE: DMA enable */ +#define HASH_CR_DMAE (1 << 3) + +/* DATATYPE: Data type selection */ +/****************************************************************************/ +/** @defgroup hash_data_type HASH Data Type +@ingroup hash_defines + +@{*/ +#define HASH_DATA_32BIT (0 << 4) +#define HASH_DATA_16BIT (1 << 4) +#define HASH_DATA_8BIT (2 << 4) +#define HASH_DATA_BITSTRING (3 << 4) +/**@}*/ +#define HASH_CR_DATATYPE (3 << 4) + +/* MODE: Mode selection */ +/****************************************************************************/ +/** @defgroup hash_mode HASH Mode +@ingroup hash_defines + +@{*/ +#define HASH_MODE_HASH (0 << 6) +#define HASH_MODE_HMAC (1 << 6) +/**@}*/ +#define HASH_CR_MODE (1 << 6) + +/* ALGO: Algorithm selection */ +/****************************************************************************/ +/** @defgroup hash_algorithm HASH Algorithm +@ingroup hash_defines + +@{*/ +#define HASH_ALGO_SHA1 (0 << 7) +#define HASH_ALGO_MD5 (1 << 7) +/**@}*/ +#define HASH_CR_ALGO (1 << 7) + +/* NBW: Number of words already pushed */ +#define HASH_CR_NBW (15 << 8) + +/* DINNE: DIN(Data input register) not empty */ +#define HASH_CR_DINNE (1 << 12) + +/* LKEY: Long key selection */ +/****************************************************************************/ +/** @defgroup hash_key_length HASH Key length +@ingroup hash_defines + +@{*/ +#define HASH_KEY_SHORT (0 << 16) +#define HASH_KEY_LONG (1 << 16) +/**@}*/ +#define HASH_CR_LKEY (1 << 16) + +/* --- HASH_STR values ----------------------------------------------------- */ + +/* NBLW: Number of valid bits in the last word of the message in the bit string + */ +#define HASH_STR_NBW (31 << 0) + +/* DCAL: Digest calculation */ +#define HASH_STR_DCAL (1 << 8) + +/* --- HASH_IMR values ----------------------------------------------------- */ + +/* DINIE: Data input interrupt enable */ +#define HASH_IMR_DINIE (1 << 0) + +/* DCIE: Digest calculation completion interrupt enable */ +#define HASH_IMR_DCIE (1 << 1) + +/* --- HASH_SR values ------------------------------------------------------ */ + +/* DINIS: Data input interrupt status */ +#define HASH_SR_DINIS (1 << 0) + +/* DCIS: Digest calculation completion interrupt status */ +#define HASH_SR_DCIS (1 << 1) + +/* DMAS: DMA Status */ +#define HASH_SR_DMAS (1 << 2) + +/* BUSY: Busy bit */ +#define HASH_SR_BUSY (1 << 3) + +/* --- HASH function prototypes -------------------------------------------- */ + +BEGIN_DECLS + +void hash_set_mode(uint8_t mode); +void hash_set_algorithm(uint8_t algorithm); +void hash_set_data_type(uint8_t datatype); +void hash_set_key_length(uint8_t keylength); +void hash_set_last_word_valid_bits(uint8_t validbits); +void hash_init(void); +void hash_add_data(uint32_t data); +void hash_digest(void); +void hash_get_result(uint32_t *data); + +END_DECLS +/**@}*/ +#endif +/** @cond */ +#else +#warning "hash_common_f24.h should not be included explicitly, only via hash.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/i2c_common_all.h b/libopencm3/include/libopencm3/stm32/common/i2c_common_all.h new file mode 100644 index 0000000..0d8546c --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/i2c_common_all.h @@ -0,0 +1,401 @@ +/** @addtogroup i2c_defines + * + * @author @htmlonly © @endhtmlonly 2010 Thomas Otto + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H +The order of header inclusion is important. i2c.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#if defined(LIBOPENCM3_I2C_H) +/** @endcond */ +#ifndef LIBOPENCM3_I2C_COMMON_ALL_H +#define LIBOPENCM3_I2C_COMMON_ALL_H + +/**@{*/ + +/* --- Convenience macros -------------------------------------------------- */ + +/* I2C register base addresses (for convenience) */ +/****************************************************************************/ +/** @defgroup i2c_reg_base I2C register base address +@ingroup i2c_defines + +@{*/ +#define I2C1 I2C1_BASE +#define I2C2 I2C2_BASE +/**@}*/ + +/* --- I2C registers ------------------------------------------------------- */ + +/* Control register 1 (I2Cx_CR1) */ +#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00) +#define I2C1_CR1 I2C_CR1(I2C1) +#define I2C2_CR1 I2C_CR1(I2C2) + +/* Control register 2 (I2Cx_CR2) */ +#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04) +#define I2C1_CR2 I2C_CR2(I2C1) +#define I2C2_CR2 I2C_CR2(I2C2) + +/* Own address register 1 (I2Cx_OAR1) */ +#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08) +#define I2C1_OAR1 I2C_OAR1(I2C1) +#define I2C2_OAR1 I2C_OAR1(I2C2) + +/* Own address register 2 (I2Cx_OAR2) */ +#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c) +#define I2C1_OAR2 I2C_OAR2(I2C1) +#define I2C2_OAR2 I2C_OAR2(I2C2) + +/* Data register (I2Cx_DR) */ +#define I2C_DR(i2c_base) MMIO32(i2c_base + 0x10) +#define I2C1_DR I2C_DR(I2C1) +#define I2C2_DR I2C_DR(I2C2) + +/* Status register 1 (I2Cx_SR1) */ +#define I2C_SR1(i2c_base) MMIO32(i2c_base + 0x14) +#define I2C1_SR1 I2C_SR1(I2C1) +#define I2C2_SR1 I2C_SR1(I2C2) + +/* Status register 2 (I2Cx_SR2) */ +#define I2C_SR2(i2c_base) MMIO32(i2c_base + 0x18) +#define I2C1_SR2 I2C_SR2(I2C1) +#define I2C2_SR2 I2C_SR2(I2C2) + +/* Clock control register (I2Cx_CCR) */ +#define I2C_CCR(i2c_base) MMIO32(i2c_base + 0x1c) +#define I2C1_CCR I2C_CCR(I2C1) +#define I2C2_CCR I2C_CCR(I2C2) + +/* TRISE register (I2Cx_CCR) */ +#define I2C_TRISE(i2c_base) MMIO32(i2c_base + 0x20) +#define I2C1_TRISE I2C_TRISE(I2C1) +#define I2C2_TRISE I2C_TRISE(I2C2) + +/* --- I2Cx_CR1 values ----------------------------------------------------- */ + +/* SWRST: Software reset */ +#define I2C_CR1_SWRST (1 << 15) + +/* Note: Bit 14 is reserved, and forced to 0 by hardware. */ + +/* ALERT: SMBus alert */ +#define I2C_CR1_ALERT (1 << 13) + +/* PEC: Packet error checking */ +#define I2C_CR1_PEC (1 << 12) + +/* POS: Acknowledge / PEC position */ +#define I2C_CR1_POS (1 << 11) + +/* ACK: Acknowledge enable */ +#define I2C_CR1_ACK (1 << 10) + +/* STOP: STOP generation */ +#define I2C_CR1_STOP (1 << 9) + +/* START: START generation */ +#define I2C_CR1_START (1 << 8) + +/* NOSTRETCH: Clock stretching disable (slave mode) */ +#define I2C_CR1_NOSTRETCH (1 << 7) + +/* ENGC: General call enable */ +#define I2C_CR1_ENGC (1 << 6) + +/* ENPEC: Enable PEC */ +#define I2C_CR1_ENPEC (1 << 5) + +/* ENARP: ARP enable */ +#define I2C_CR1_ENARP (1 << 4) + +/* SMBTYPE: SMBus type */ +#define I2C_CR1_SMBTYPE (1 << 3) + +/* Note: Bit 2 is reserved, and forced to 0 by hardware. */ + +/* SMBUS: SMBus mode */ +#define I2C_CR1_SMBUS (1 << 1) + +/* PE: Peripheral enable */ +#define I2C_CR1_PE (1 << 0) + +/* --- I2Cx_CR2 values ----------------------------------------------------- */ + +/* Note: Bits [15:13] are reserved, and forced to 0 by hardware. */ + +/* LAST: DMA last transfer */ +#define I2C_CR2_LAST (1 << 12) + +/* DMAEN: DMA requests enable */ +#define I2C_CR2_DMAEN (1 << 11) + +/* ITBUFEN: Buffer interrupt enable */ +#define I2C_CR2_ITBUFEN (1 << 10) + +/* ITEVTEN: Event interrupt enable */ +#define I2C_CR2_ITEVTEN (1 << 9) + +/* ITERREN: Error interrupt enable */ +#define I2C_CR2_ITERREN (1 << 8) + +/* Note: Bits [7:6] are reserved, and forced to 0 by hardware. */ + +/* FREQ[5:0]: Peripheral clock frequency (valid values: 2-36 MHz, 2-42 MHz for + * STM32F4 respectivly) */ +/****************************************************************************/ +/** @defgroup i2c_clock I2C clock frequency settings +@ingroup i2c_defines + +@{*/ +#define I2C_CR2_FREQ_2MHZ 0x02 +#define I2C_CR2_FREQ_3MHZ 0x03 +#define I2C_CR2_FREQ_4MHZ 0x04 +#define I2C_CR2_FREQ_5MHZ 0x05 +#define I2C_CR2_FREQ_6MHZ 0x06 +#define I2C_CR2_FREQ_7MHZ 0x07 +#define I2C_CR2_FREQ_8MHZ 0x08 +#define I2C_CR2_FREQ_9MHZ 0x09 +#define I2C_CR2_FREQ_10MHZ 0x0a +#define I2C_CR2_FREQ_11MHZ 0x0b +#define I2C_CR2_FREQ_12MHZ 0x0c +#define I2C_CR2_FREQ_13MHZ 0x0d +#define I2C_CR2_FREQ_14MHZ 0x0e +#define I2C_CR2_FREQ_15MHZ 0x0f +#define I2C_CR2_FREQ_16MHZ 0x10 +#define I2C_CR2_FREQ_17MHZ 0x11 +#define I2C_CR2_FREQ_18MHZ 0x12 +#define I2C_CR2_FREQ_19MHZ 0x13 +#define I2C_CR2_FREQ_20MHZ 0x14 +#define I2C_CR2_FREQ_21MHZ 0x15 +#define I2C_CR2_FREQ_22MHZ 0x16 +#define I2C_CR2_FREQ_23MHZ 0x17 +#define I2C_CR2_FREQ_24MHZ 0x18 +#define I2C_CR2_FREQ_25MHZ 0x19 +#define I2C_CR2_FREQ_26MHZ 0x1a +#define I2C_CR2_FREQ_27MHZ 0x1b +#define I2C_CR2_FREQ_28MHZ 0x1c +#define I2C_CR2_FREQ_29MHZ 0x1d +#define I2C_CR2_FREQ_30MHZ 0x1e +#define I2C_CR2_FREQ_31MHZ 0x1f +#define I2C_CR2_FREQ_32MHZ 0x20 +#define I2C_CR2_FREQ_33MHZ 0x21 +#define I2C_CR2_FREQ_34MHZ 0x22 +#define I2C_CR2_FREQ_35MHZ 0x23 +#define I2C_CR2_FREQ_36MHZ 0x24 +#define I2C_CR2_FREQ_37MHZ 0x25 +#define I2C_CR2_FREQ_38MHZ 0x26 +#define I2C_CR2_FREQ_39MHZ 0x27 +#define I2C_CR2_FREQ_40MHZ 0x28 +#define I2C_CR2_FREQ_41MHZ 0x29 +#define I2C_CR2_FREQ_42MHZ 0x2a +/**@}*/ + +/* --- I2Cx_OAR1 values ---------------------------------------------------- */ + +/* ADDMODE: Addressing mode (slave mode) */ +#define I2C_OAR1_ADDMODE (1 << 15) +#define I2C_OAR1_ADDMODE_7BIT 0 +#define I2C_OAR1_ADDMODE_10BIT 1 + +/* Note: Bit 14 should always be kept at 1 by software! */ + +/* Note: Bits [13:10] are reserved, and forced to 0 by hardware. */ + +/* ADD: Address bits: [7:1] in 7-bit mode, bits [9:0] in 10-bit mode */ + +/* --- I2Cx_OAR2 values ---------------------------------------------------- */ + +/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ + +/* ADD2[7:1]: Interface address (bits [7:1] in dual addressing mode) */ + +/* ENDUAL: Dual addressing mode enable */ +#define I2C_OAR2_ENDUAL (1 << 0) + +/* --- I2Cx_DR values ------------------------------------------------------ */ + +/* Note: Bits [15:8] are reserved, and forced to 0 by hardware. */ + +/* DR[7:0] 8-bit data register */ + +/* --- I2Cx_SR1 values ----------------------------------------------------- */ + +/* SMBALERT: SMBus alert */ +#define I2C_SR1_SMBALERT (1 << 15) + +/* TIMEOUT: Timeout or Tlow Error */ +#define I2C_SR1_TIMEOUT (1 << 14) + +/* Note: Bit 13 is reserved, and forced to 0 by hardware. */ + +/* PECERR: PEC Error in reception */ +#define I2C_SR1_PECERR (1 << 12) + +/* OVR: Overrun/Underrun */ +#define I2C_SR1_OVR (1 << 11) + +/* AF: Acknowledge failure */ +#define I2C_SR1_AF (1 << 10) + +/* ARLO: Arbitration lost (master mode) */ +#define I2C_SR1_ARLO (1 << 9) + +/* BERR: Bus error */ +#define I2C_SR1_BERR (1 << 8) + +/* TxE: Data register empty (transmitters) */ +#define I2C_SR1_TxE (1 << 7) + +/* RxNE: Data register not empty (receivers) */ +#define I2C_SR1_RxNE (1 << 6) + +/* Note: Bit 5 is reserved, and forced to 0 by hardware. */ + +/* STOPF: STOP detection (slave mode) */ +#define I2C_SR1_STOPF (1 << 4) + +/* ADD10: 10-bit header sent (master mode) */ +#define I2C_SR1_ADD10 (1 << 3) + +/* BTF: Byte transfer finished */ +#define I2C_SR1_BTF (1 << 2) + +/* ADDR: Address sent (master mode) / address matched (slave mode) */ +#define I2C_SR1_ADDR (1 << 1) + +/* SB: Start bit (master mode) */ +#define I2C_SR1_SB (1 << 0) + +/* --- I2Cx_SR2 values ----------------------------------------------------- */ + +/* Bits [15:8]: PEC[7:0]: Packet error checking register */ + +/* DUALF: Dual flag (slave mode) */ +#define I2C_SR2_DUALF (1 << 7) + +/* SMBHOST: SMBus host header (slave mode) */ +#define I2C_SR2_SMBHOST (1 << 6) + +/* SMBDEFAULT: SMBus device default address (slave mode) */ +#define I2C_SR2_SMBDEFAULT (1 << 5) + +/* GENCALL: General call address (slave mode) */ +#define I2C_SR2_GENCALL (1 << 4) + +/* Note: Bit 3 is reserved, and forced to 0 by hardware. */ + +/* TRA: Transmitter / receiver */ +#define I2C_SR2_TRA (1 << 2) + +/* BUSY: Bus busy */ +#define I2C_SR2_BUSY (1 << 1) + +/* MSL: Master / slave */ +#define I2C_SR2_MSL (1 << 0) + +/* --- I2Cx_CCR values ----------------------------------------------------- */ + +/* F/S: I2C Master mode selection (fast / standard) */ +#define I2C_CCR_FS (1 << 15) + +/* DUTY: Fast Mode Duty Cycle */ +/** @defgroup i2c_duty_cycle I2C peripheral clock duty cycles +@ingroup i2c_defines + +@{*/ +#define I2C_CCR_DUTY (1 << 14) +#define I2C_CCR_DUTY_DIV2 0 +#define I2C_CCR_DUTY_16_DIV_9 1 +/**@}*/ + +/* Note: Bits [13:12] are reserved, and forced to 0 by hardware. */ + +/* + * Bits [11:0]: + * CCR[11:0]: Clock control register in Fast/Standard mode (master mode) + */ + +/* --- I2Cx_TRISE values --------------------------------------------------- */ + +/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */ + +/* + * Bits [5:0]: + * TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode) + */ + +/* --- I2C constant definitions -------------------------------------------- */ + +/****************************************************************************/ +/** @defgroup i2c_rw I2C Read/Write bit +@ingroup i2c_defines + +@{*/ +#define I2C_WRITE 0 +#define I2C_READ 1 +/**@}*/ + +/* --- I2C function prototypes---------------------------------------------- */ + +BEGIN_DECLS + +void i2c_reset(uint32_t i2c); +void i2c_peripheral_enable(uint32_t i2c); +void i2c_peripheral_disable(uint32_t i2c); +void i2c_send_start(uint32_t i2c); +void i2c_send_stop(uint32_t i2c); +void i2c_clear_stop(uint32_t i2c); +void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave); +void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave); +void i2c_set_clock_frequency(uint32_t i2c, uint8_t freq); +void i2c_send_data(uint32_t i2c, uint8_t data); +void i2c_set_fast_mode(uint32_t i2c); +void i2c_set_standard_mode(uint32_t i2c); +void i2c_set_ccr(uint32_t i2c, uint16_t freq); +void i2c_set_trise(uint32_t i2c, uint16_t trise); +void i2c_send_7bit_address(uint32_t i2c, uint8_t slave, uint8_t readwrite); +uint8_t i2c_get_data(uint32_t i2c); +void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt); +void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt); +void i2c_enable_ack(uint32_t i2c); +void i2c_disable_ack(uint32_t i2c); +void i2c_nack_next(uint32_t i2c); +void i2c_nack_current(uint32_t i2c); +void i2c_set_dutycycle(uint32_t i2c, uint32_t dutycycle); +void i2c_enable_dma(uint32_t i2c); +void i2c_disable_dma(uint32_t i2c); +void i2c_set_dma_last_transfer(uint32_t i2c); +void i2c_clear_dma_last_transfer(uint32_t i2c); + +END_DECLS + +#endif +/** @cond */ +#else +#warning "i2c_common_all.h should not be included explicitly, only via i2c.h" +#endif +/** @endcond */ +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/common/i2c_common_f24.h b/libopencm3/include/libopencm3/stm32/common/i2c_common_f24.h new file mode 100644 index 0000000..a056114 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/i2c_common_f24.h @@ -0,0 +1,51 @@ +/** @addtogroup i2c_defines + +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies + +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Ken Sarkies + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H +The order of header inclusion is important. i2c.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_I2C_H +/** @endcond */ +#ifndef LIBOPENCM3_I2C_COMMON_F24_H +#define LIBOPENCM3_I2C_COMMON_F24_H + +#include + +/**@{*/ + +#define I2C3 I2C3_BASE + +/**@}*/ + +#endif +/** @cond */ +#else +#warning "i2c_common_f24.h should not be included explicitly, only via i2c.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/iwdg_common_all.h b/libopencm3/include/libopencm3/stm32/common/iwdg_common_all.h new file mode 100644 index 0000000..7d915d6 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/iwdg_common_all.h @@ -0,0 +1,121 @@ +/** @addtogroup iwdg_defines + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto + +*/ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA IWDG.H +The order of header inclusion is important. iwdg.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_IWDG_H +/** @endcond */ +#ifndef LIBOPENCM3_IWDG_COMMON_ALL_H +#define LIBOPENCM3_IWDG_COMMON_ALL_H + +/**@{*/ + +/* --- IWDG registers ------------------------------------------------------ */ + +/* Key Register (IWDG_KR) */ +#define IWDG_KR MMIO32(IWDG_BASE + 0x00) + +/* Prescaler register (IWDG_PR) */ +#define IWDG_PR MMIO32(IWDG_BASE + 0x04) + +/* Reload register (IWDG_RLR) */ +#define IWDG_RLR MMIO32(IWDG_BASE + 0x08) + +/* Status register (IWDG_SR) */ +#define IWDG_SR MMIO32(IWDG_BASE + 0x0c) + +/* --- IWDG_KR values ------------------------------------------------------ */ + +/* Bits [31:16]: Reserved. */ + +/* KEY[15:0]: Key value (write-only, reads as 0x0000) */ +/** @defgroup iwdg_key IWDG Key Values +@ingroup STM32F_iwdg_defines + +@{*/ +#define IWDG_KR_RESET 0xaaaa +#define IWDG_KR_UNLOCK 0x5555 +#define IWDG_KR_START 0xcccc +/**@}*/ + +/* --- IWDG_PR values ------------------------------------------------------ */ + +/* Bits [31:3]: Reserved. */ + +/* PR[2:0]: Prescaler divider */ +#define IWDG_PR_LSB 0 +/** @defgroup iwdg_prediv IWDG prescaler divider +@ingroup STM32F_iwdg_defines + +@{*/ +#define IWDG_PR_DIV4 0x0 +#define IWDG_PR_DIV8 0x1 +#define IWDG_PR_DIV16 0x2 +#define IWDG_PR_DIV32 0x3 +#define IWDG_PR_DIV64 0x4 +#define IWDG_PR_DIV128 0x5 +#define IWDG_PR_DIV256 0x6 +/**@}*/ +/* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */ +/* #define IWDG_PR_DIV256 0x7 */ + +/* --- IWDG_RLR values ----------------------------------------------------- */ + +/* Bits [31:12]: Reserved. */ + +/* RL[11:0]: Watchdog counter reload value */ + +/* --- IWDG_SR values ------------------------------------------------------ */ + +/* Bits [31:2]: Reserved. */ + +/* RVU: Watchdog counter reload value update */ +#define IWDG_SR_RVU (1 << 1) + +/* PVU: Watchdog prescaler value update */ +#define IWDG_SR_PVU (1 << 0) + +/* --- IWDG function prototypes---------------------------------------------- */ + +BEGIN_DECLS + +void iwdg_start(void); +void iwdg_set_period_ms(uint32_t period); +bool iwdg_reload_busy(void); +bool iwdg_prescaler_busy(void); +void iwdg_reset(void); + +END_DECLS + +#endif +/** @cond */ +#else +#warning "iwdg_common_all.h should not be included explicitly, only via iwdg.h" +#endif +/** @endcond */ +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/common/pwr_common_all.h b/libopencm3/include/libopencm3/stm32/common/pwr_common_all.h new file mode 100644 index 0000000..56d2fe1 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/pwr_common_all.h @@ -0,0 +1,132 @@ +/** @addtogroup pwr_defines + +@author @htmlonly © @endhtmlonly 2010 Thomas Otto + +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PWR.H +The order of header inclusion is important. pwr.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_PWR_H +/** @endcond */ +#ifndef LIBOPENCM3_PWR_COMMON_ALL_H +#define LIBOPENCM3_PWR_COMMON_ALL_H + +/**@{*/ + +/* --- PWR registers ------------------------------------------------------- */ + +/* Power control register (PWR_CR) */ +#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00) + +/* Power control/status register (PWR_CSR) */ +#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04) + +/* --- PWR_CR values ------------------------------------------------------- */ + +/* Bits [31:9]: Reserved, must be kept at reset value. */ + +/* DBP: Disable backup domain write protection */ +#define PWR_CR_DBP (1 << 8) + +/* PLS[7:5]: PVD level selection */ +#define PWR_CR_PLS_LSB 5 +/** @defgroup pwr_pls PVD level selection +@ingroup STM32F_pwr_defines + +@{*/ +#define PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB) +#define PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB) +#define PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB) +#define PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB) +#define PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB) +#define PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB) +#define PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB) +#define PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB) +/**@}*/ +#define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB) + +/* PVDE: Power voltage detector enable */ +#define PWR_CR_PVDE (1 << 4) + +/* CSBF: Clear standby flag */ +#define PWR_CR_CSBF (1 << 3) + +/* CWUF: Clear wakeup flag */ +#define PWR_CR_CWUF (1 << 2) + +/* PDDS: Power down deepsleep */ +#define PWR_CR_PDDS (1 << 1) + +/* LPDS: Low-power deepsleep */ +#define PWR_CR_LPDS (1 << 0) + +/* --- PWR_CSR values ------------------------------------------------------ */ + +/* Bits [31:9]: Reserved, must be kept at reset value. */ + +/* EWUP: Enable WKUP pin */ +#define PWR_CSR_EWUP (1 << 8) + +/* Bits [7:3]: Reserved, must be kept at reset value. */ + +/* PVDO: PVD output */ +#define PWR_CSR_PVDO (1 << 2) + +/* SBF: Standby flag */ +#define PWR_CSR_SBF (1 << 1) + +/* WUF: Wakeup flag */ +#define PWR_CSR_WUF (1 << 0) + +/* --- PWR function prototypes ------------------------------------------- */ + +BEGIN_DECLS + +void pwr_disable_backup_domain_write_protect(void); +void pwr_enable_backup_domain_write_protect(void); +void pwr_enable_power_voltage_detect(uint32_t pvd_level); +void pwr_disable_power_voltage_detect(void); +void pwr_clear_standby_flag(void); +void pwr_clear_wakeup_flag(void); +void pwr_set_standby_mode(void); +void pwr_set_stop_mode(void); +void pwr_voltage_regulator_on_in_stop(void); +void pwr_voltage_regulator_low_power_in_stop(void); +void pwr_enable_wakeup_pin(void); +void pwr_disable_wakeup_pin(void); +bool pwr_voltage_high(void); +bool pwr_get_standby_flag(void); +bool pwr_get_wakeup_flag(void); + +END_DECLS + +/**@}*/ +#endif +/** @cond */ +#else +#warning "pwr_common_all.h should not be included explicitly, only via pwr.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/rcc_common_all.h b/libopencm3/include/libopencm3/stm32/common/rcc_common_all.h new file mode 100644 index 0000000..68511f1 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/rcc_common_all.h @@ -0,0 +1,61 @@ +/** @addtogroup rcc_defines + * + * @author @htmlonly © @endhtmlonly 2013 + * Frantisek Burian + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RCC.H + * The order of header inclusion is important. rcc.h defines the device + * specific enumerations before including this header file. + */ + +/** @cond */ +#ifdef LIBOPENCM3_RCC_H +/** @endcond */ + +#ifndef LIBOPENCM3_RCC_COMMON_ALL_H +#define LIBOPENCM3_RCC_COMMON_ALL_H + +/**@{*/ + +BEGIN_DECLS + +void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en); +void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en); +void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset); +void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset); + +void rcc_periph_clock_enable(enum rcc_periph_clken clken); +void rcc_periph_clock_disable(enum rcc_periph_clken clken); +void rcc_periph_reset_pulse(enum rcc_periph_rst rst); +void rcc_periph_reset_hold(enum rcc_periph_rst rst); +void rcc_periph_reset_release(enum rcc_periph_rst rst); + +END_DECLS +/**@}*/ + +#endif +/** @cond */ +#else +#warning "rcc_common_all.h should not be included explicitly, only via rcc.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/rng_common_f24.h b/libopencm3/include/libopencm3/stm32/common/rng_common_f24.h new file mode 100644 index 0000000..fc029af --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/rng_common_f24.h @@ -0,0 +1,71 @@ +/* + * This file is part of the libopencm3 project. + * + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RNG.H +The order of header inclusion is important. rng.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_RNG_H +/** @endcond */ +#ifndef LIBOPENCM3_RNG_COMMON_F24_H +#define LIBOPENCM3_RNG_COMMON_F24_H + +/* --- Random number generator registers ----------------------------------- */ + +/* Control register */ +#define RNG_CR MMIO32(RNG_BASE + 0x00) + +/* Status register */ +#define RNG_SR MMIO32(RNG_BASE + 0x04) + +/* Data register */ +#define RNG_DR MMIO32(RNG_BASE + 0x08) + +/* --- RNG_CR values ------------------------------------------------------- */ + +/* RNG ENABLE */ +#define RNG_CR_RNGEN (1 << 2) + +/* RNG interrupt enable */ +#define RNG_CR_IE (1 << 3) + +/* --- RNG_SR values ------------------------------------------------------- */ + +/* Data ready */ +#define RNG_SR_DRDY (1 << 0) + +/* Clock error current status */ +#define RNG_SR_CECS (1 << 1) + +/* Seed error current status */ +#define RNG_SR_SECS (1 << 2) + +/* Clock error interrupt status */ +#define RNG_SR_CEIS (1 << 5) + +/* Seed error interrupt status */ +#define RNG_SR_SEIS (1 << 6) + +#endif +/** @cond */ +#else +#warning "rng_common_f24.h should not be included explicitly, only via rng.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/rtc_common_l1f024.h b/libopencm3/include/libopencm3/stm32/common/rtc_common_l1f024.h new file mode 100644 index 0000000..677caf0 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/rtc_common_l1f024.h @@ -0,0 +1,347 @@ +/** @addtogroup rtc_defines + +@author @htmlonly © @endhtmlonly 2012 Karl Palsson + +*/ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* + * This covers the "version 2" RTC peripheral. This is completely different + * to the v1 RTC periph on the F1 series devices. It has BCD counters, with + * automatic leapyear corrections and daylight savings support. + * This peripheral is used on the F0, F2, F3, F4 and L1 devices, though some + * only support a subset. + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RTC.H +The order of header inclusion is important. rtc.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_RTC_H +/** @endcond */ +#ifndef LIBOPENCM3_RTC2_H +#define LIBOPENCM3_RTC2_H + +/**@{*/ + +/* RTC time register (RTC_TR) */ +#define RTC_TR MMIO32(RTC_BASE + 0x00) + +/* RTC date register (RTC_DR) */ +#define RTC_DR MMIO32(RTC_BASE + 0x04) + +/* RTC control register (RTC_CR) */ +#define RTC_CR MMIO32(RTC_BASE + 0x08) + +/* RTC initialization and status register (RTC_ISR) */ +#define RTC_ISR MMIO32(RTC_BASE + 0x0c) + +/* RTC prescaler register (RTC_PRER) */ +#define RTC_PRER MMIO32(RTC_BASE + 0x10) + +/* RTC wakeup timer register (RTC_WUTR) */ +#define RTC_WUTR MMIO32(RTC_BASE + 0x14) + +/* RTC calibration register (RTC_CALIBR) NB: see also RTC_CALR */ +#define RTC_CALIBR MMIO32(RTC_BASE + 0x18) + +/* RTC alarm X register (RTC_ALRMxR) */ +#define RTC_ALRMAR MMIO32(RTC_BASE + 0x1c) +#define RTC_ALRMBR MMIO32(RTC_BASE + 0x20) + +/* RTC write protection register (RTC_WPR)*/ +#define RTC_WPR MMIO32(RTC_BASE + 0x24) + +/* RTC sub second register (RTC_SSR) (high and med+ only) */ +#define RTC_SSR MMIO32(RTC_BASE + 0x28) + +/* RTC shift control register (RTC_SHIFTR) (high and med+ only) */ +#define RTC_SHIFTR MMIO32(RTC_BASE + 0x2c) + +/* RTC time stamp time register (RTC_TSTR) */ +#define RTC_TSTR MMIO32(RTC_BASE + 0x30) +/* RTC time stamp date register (RTC_TSDR) */ +#define RTC_TSDR MMIO32(RTC_BASE + 0x34) +/* RTC timestamp sub second register (RTC_TSSSR) (high and med+ only) */ +#define RTC_TSSSR MMIO32(RTC_BASE + 0x38) + +/* RTC calibration register (RTC_CALR) (high and med+ only) */ +#define RTC_CALR MMIO32(RTC_BASE + 0x3c) + +/* RTC tamper and alternate function configuration register (RTC_TAFCR) */ +#define RTC_TAFCR MMIO32(RTC_BASE + 0x40) + +/* RTC alarm X sub second register (RTC_ALRMxSSR) (high and med+ only) */ +#define RTC_ALRMASSR MMIO32(RTC_BASE + 0x44) +#define RTC_ALRMBSSR MMIO32(RTC_BASE + 0x48) + +/* RTC backup registers (RTC_BKPxR) */ +#define RTC_BKP_BASE (RTC_BASE + 0x50) +#define RTC_BKPXR(reg) MMIO32(RTC_BKP_BASE + (4*reg)) + + +/* RTC time register (RTC_TR) ----------------------------------- */ +/* Note: Bits [31:23], 15, and 7 are reserved, and must be kept at reset value. + */ +#define RTC_TR_PM (1 << 22) /* AM/PM notation */ +#define RTC_TR_HT_SHIFT (20) /* Hour tens in BCD format shift */ +#define RTC_TR_HT_MASK (0x3) /* Hour tens in BCD format mask */ +#define RTC_TR_HU_SHIFT (16) /* Hour units in BCD format shift */ +#define RTC_TR_HU_MASK (0xf) /* Hour units in BCD format mask */ +#define RTC_TR_MNT_SHIFT (12) /* Minute tens in BCD format shift */ +#define RTC_TR_MNT_MASK (0x7) /* Minute tens in BCD format mask */ +#define RTC_TR_MNU_SHIFT (8) /* Minute units in BCD format shift */ +#define RTC_TR_MNU_MASK (0xf) /* Minute units in BCD format mask */ +#define RTC_TR_ST_SHIFT (4) /* Second tens in BCD format shift */ +#define RTC_TR_ST_MASK (0x7) /* Second tens in BCD format mask */ +#define RTC_TR_SU_SHIFT (0) /* Second units in BCD format shift */ +#define RTC_TR_SU_MASK (0xf) /* Second units in BCD format mask */ + +/* RTC date register (RTC_DR) ----------------------------------- */ +/* Note: Bits [31:24] and [7:6] are reserved, and must be kept at reset value. + */ +#define RTC_DR_YT_SHIFT (20) /* Year tens in BCD format shift */ +#define RTC_DR_YT_MASK (0xf) /* Year tens in BCD format mask */ +#define RTC_DR_YU_SHIFT (16) /* Year units in BCD format shift */ +#define RTC_DR_YU_MASK (0xf) /* Year units in BCD format mask */ +#define RTC_DR_WDU_SHIFT (13) /* Weekday units shift */ +#define RTC_DR_WDU_MASK (0x7) /* Weekday units mask */ +#define RTC_DR_MT (1<<12) /* Month tens in BCD format shift */ +#define RTC_DR_MT_SHIFT (12) /* Month tens in BCD format mask */ +#define RTC_DR_MU_SHIFT (8) /* Month units in BCD format shift */ +#define RTC_DR_MU_MASK (0xf) /* Month units in BCD format mask */ +#define RTC_DR_DT_SHIFT (4) /* Date tens in BCD format shift */ +#define RTC_DR_DT_MASK (0x3) /* Date tens in BCD format mask */ +#define RTC_DR_DU_SHIFT (0) /* Date units in BCD format shift */ +#define RTC_DR_DU_MASK (0xf) /* Date units in BCD format mask */ + +/* RTC control register (RTC_CR) -------------------------------- */ +/* Note: Bits [31:24] are reserved, and must be kept at reset value. */ +/* Note: Bits 7, 6 and 4 of this register can be written in initialization mode + * only (RTC_ISR/INITF = 1). + */ +/* Note: Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit + * = 0 and RTC_ISR WUTWF bit = 1. + */ +#define RTC_CR_COE (1<<23) /* RTC_CR_COE: Calibration output enable */ + +/* RTC_CR_OSEL: Output selection values */ +/* Note: These bits are used to select the flag to be routed to AFO_ALARM RTC + * output + */ +#define RTC_CR_OSEL_SHIFT 21 +#define RTC_CR_OSEL_MASK (0x3) +#define RTC_CR_OSEL_DISABLED (0x0) +#define RTC_CR_OSEL_ALARMA (0x1) +#define RTC_CR_OSEL_ALARMB (0x2) +#define RTC_CR_OSEL_WAKEUP (0x3) + +#define RTC_CR_POL (1<<20) /* RTC_CR_POL: Output polarity */ +#define RTC_CR_COSEL (1<<19) /* RTC_CR_COSEL: Calibration output + selection */ +#define RTC_CR_BKP (1<<18) /* RTC_CR_BKP: Backup */ +#define RTC_CR_SUB1H (1<<17) /* RTC_CR_SUB1H: Subtract 1 hour + (winter time change) */ +#define RTC_CR_ADD1H (1<<16) /* RTC_CR_ADD1H: Add 1 hour (summer + time change) */ +#define RTC_CR_TSIE (1<<15) /* RTC_CR_TSIE: Timestamp interrupt + enable */ +#define RTC_CR_WUTIE (1<<14) /* RTC_CR_WUTIE: Wakeup timer + interrupt enable */ +#define RTC_CR_ALRBIE (1<<13) /* RTC_CR_ALRBIE: Alarm B interrupt + enable */ +#define RTC_CR_ALRAIE (1<<12) /* RTC_CR_ALRAIE: Alarm A interrupt + enable */ +#define RTC_CR_TSE (1<<11) /* RTC_CR_TSE: Time stamp enable */ +#define RTC_CR_WUTE (1<<10) /* RTC_CR_WUTE: Wakeup timer enable */ +#define RTC_CR_ALRBE (1<<9) /* RTC_CR_ALRBIE: Alarm B enable */ +#define RTC_CR_ALRAE (1<<8) /* RTC_CR_ALRAE: Alarm A enable */ +#define RTC_CR_DCE (1<<7) /* RTC_CR_DCE: Course digital + calibration enable */ +#define RTC_CR_FMT (1<<6) /* RTC_CR_FMT: Hour format */ +#define RTC_CR_BYPSHAD (1<<5) /* RTC_CR_BYPSHAD: Bypass the shadow + registers */ +#define RTC_CR_REFCKON (1<<4) /* RTC_CR_REFCKON: Reference clock + detection enable */ +#define RTC_CR_TSEDGE (1<<3) /* RTC_CR_TSEDGE: Timestamp event + active edge */ + +/* RTC_CR_WUCKSEL: Wakeup clock selection */ +#define RTC_CR_WUCLKSEL_SHIFT (0) +#define RTC_CR_WUCLKSEL_MASK (0x7) +#define RTC_CR_WUCLKSEL_RTC_DIV16 (0x0) +#define RTC_CR_WUCLKSEL_RTC_DIV8 (0x1) +#define RTC_CR_WUCLKSEL_RTC_DIV4 (0x2) +#define RTC_CR_WUCLKSEL_RTC_DIV2 (0x3) +#define RTC_CR_WUCLKSEL_SPRE (0x4) +#define RTC_CR_WUCLKSEL_SPRE_216 (0x6) + +/* RTC initialization and status register (RTC_ISR) ------------- */ +/* Note: Bits [31:17] and [15] are reserved, and must be kept at reset value. */ +/* Note: This register is write protected (except for RTC_ISR[13:8] bits). */ +#define RTC_ISR_RECALPF (1<<16) /* RECALPF: Recalib pending flag */ +#define RTC_ISR_TAMP3F (1<<15) /* TAMP3F: TAMPER3 detection flag + (not on F4)*/ +#define RTC_ISR_TAMP2F (1<<14) /* TAMP2F: TAMPER2 detection flag */ +#define RTC_ISR_TAMP1F (1<<13) /* TAMP1F: TAMPER detection flag */ +#define RTC_ISR_TSOVF (1<<12) /* TSOVF: Timestamp overflow flag */ +#define RTC_ISR_TSF (1<<11) /* TSF: Timestamp flag */ +#define RTC_ISR_WUTF (1<<10) /* WUTF: Wakeup timer flag */ +#define RTC_ISR_ALRBF (1<<9) /* ALRBF: Alarm B flag */ +#define RTC_ISR_ALRAF (1<<8) /* ALRAF: Alarm A flag */ +#define RTC_ISR_INIT (1<<7) /* INIT: Initialization mode */ +#define RTC_ISR_INITF (1<<6) /* INITF: Initialization flag */ +#define RTC_ISR_RSF (1<<5) /* RSF: Registers sync flag */ +#define RTC_ISR_INITS (1<<4) /* INITS: Init status flag */ +#define RTC_ISR_SHPF (1<<3) /* SHPF: Shift operation pending */ +#define RTC_ISR_WUTWF (1<<2) /* WUTWF: Wakeup timer write flag */ +#define RTC_ISR_ALRBWF (1<<1) /* ALRBWF: Alarm B write flag */ +#define RTC_ISR_ALRAWF (1<<0) /* ALRAWF: Alarm A write flag */ + +/* RTC prescaler register (RTC_PRER) ---------------------------- */ +#define RTC_PRER_PREDIV_A_SHIFT (16) /* Async prescaler factor shift */ +#define RTC_PRER_PREDIV_A_MASK (0x7f) /* Async prescaler factor mask */ +#define RTC_PRER_PREDIV_S_SHIFT (0) /* Sync prescaler factor shift */ +#define RTC_PRER_PREDIV_S_MASK (0x7fff) /* Sync prescaler factor mask */ + +/* RTC calibration register (RTC_CALIBR) ------------------------ */ +/* FIXME - TODO */ + +/* RTC Alarm register ------------------------------------------- */ +/* Note: Applies to RTC_ALRMAR and RTC_ALRMBR */ +#define RTC_ALRMXR_MSK4 (1<<31) +#define RTC_ALRMXR_WDSEL (1<<30) +#define RTC_ALRMXR_DT_SHIFT (28) +#define RTC_ALRMXR_DT_MASK (0x3) +#define RTC_ALRMXR_DU_SHIFT (24) +#define RTC_ALRMXR_DU_MASK (0xf) +#define RTC_ALRMXR_MSK3 (1<<23) +#define RTC_ALRMXR_PM (1<<22) +#define RTC_ALRMXR_HT_SHIFT (20) +#define RTC_ALRMXR_HT_MASK (0x3) +#define RTC_ALRMXR_HU_SHIFT (16) +#define RTC_ALRMXR_HU_MASK (0xf) +#define RTC_ALRMXR_MSK2 (1<<15) +#define RTC_ALRMXR_MNT_SHIFT (12) +#define RTC_ALRMXR_MNT_MASK (0x7) +#define RTC_ALRMXR_MNU_SHIFT (8) +#define RTC_ALRMXR_MNU_MASK (0xf) +#define RTC_ALRMXR_MSK1 (1<<7) +#define RTC_ALRMXR_ST_SHIFT (4) +#define RTC_ALRMXR_ST_MASK (0x7) +#define RTC_ALRMXR_SU_SHIFT (0) +#define RTC_ALRMXR_SU_MASK (0xf) + +/* RTC shift control register (RTC_SHIFTR) */ +/* FIXME - TODO */ + +/* RTC time stamp time register (RTC_TSTR) ---------------------- */ +#define RTC_TSTR_PM (1<<22) +#define RTC_TSTR_HT_SHIFT (20) +#define RTC_TSTR_HT_MASK (0x3) +#define RTC_TSTR_HU_SHIFT (16) +#define RTC_TSTR_HU_MASK (0xf) +#define RTC_TSTR_MNT_SHIFT (12) +#define RTC_TSTR_MNT_MASK (0x7) +#define RTC_TSTR_MNU_SHIFT (8) +#define RTC_TSTR_MNU_MASK (0xf) +#define RTC_TSTR_ST_SHIFT (4) +#define RTC_TSTR_ST_MASK (0x7) +#define RTC_TSTR_SU_SHIFT (0) +#define RTC_TSTR_SU_MASK (0xf) + +/* RTC time stamp date register (RTC_TSDR) ---------------------- */ +#define RTC_TSDR_WDU_SHIFT (13) +#define RTC_TSDR_WDU_MASK (0x7) +#define RTC_TSDR_MT (1<<12) +#define RTC_TSDR_MU_SHIFT (8) +#define RTC_TSDR_MU_MASK (0xf) +#define RTC_TSDR_DT_SHIFT (4) +#define RTC_TSDR_DT_MASK (0x3) +#define RTC_TSDR_DU_SHIFT (0) +#define RTC_TSDR_DU_MASK (0xf) + +/* RTC calibration register (RTC_CALR) -------------------------- */ +/* FIXME - TODO */ + +/* RTC tamper and alternate function configuration register (RTC_TAFCR) --- */ +#define RTC_TAFCR_ALARMOUTTYPE (1<<18) +#define RTC_TAFCR_TAMPPUDIS (1<<15) + +#define RTC_TAFCR_TAMPPRCH_SHIFT (13) +#define RTC_TAFCR_TAMPPRCH_MASK (0x3) +#define RTC_TAFCR_TAMPPRCH_1RTC (0x0) +#define RTC_TAFCR_TAMPPRCH_2RTC (0x1) +#define RTC_TAFCR_TAMPPRCH_4RTC (0x2) +#define RTC_TAFCR_TAMPPRCH_8RTC (0x3) + +#define RTC_TAFCR_TAMPFLT_SHIFT (11) +#define RTC_TAFCR_TAMPFLT_MASK (0x3) +#define RTC_TAFCR_TAMPFLT_EDGE1 (0x0) +#define RTC_TAFCR_TAMPFLT_EDGE2 (0x1) +#define RTC_TAFCR_TAMPFLT_EDGE4 (0x2) +#define RTC_TAFCR_TAMPFLT_EDGE8 (0x3) + +#define RTC_TAFCR_TAMPFREQ_SHIFT (8) +#define RTC_TAFCR_TAMPFREQ_MASK (0x7) +#define RTC_TAFCR_TAMPFREQ_RTCDIV32K (0x0) +#define RTC_TAFCR_TAMPFREQ_RTCDIV16K (0x1) +#define RTC_TAFCR_TAMPFREQ_RTCDIV8K (0x2) +#define RTC_TAFCR_TAMPFREQ_RTCDIV4K (0x3) +#define RTC_TAFCR_TAMPFREQ_RTCDIV2K (0x4) +#define RTC_TAFCR_TAMPFREQ_RTCDIV1K (0x5) +#define RTC_TAFCR_TAMPFREQ_RTCDIV512 (0x6) +#define RTC_TAFCR_TAMPFREQ_RTCDIV256 (0x7) + +#define RTC_TAFCR_TAMPTS (1<<7) +#define RTC_TAFCR_TAMP3TRG (1<<6) +#define RTC_TAFCR_TAMP3E (1<<5) +#define RTC_TAFCR_TAMP2TRG (1<<4) +#define RTC_TAFCR_TAMP2E (1<<3) +#define RTC_TAFCR_TAMPIE (1<<2) +#define RTC_TAFCR_TAMP1TRG (1<<1) +#define RTC_TAFCR_TAMP1E (1<<0) + +/* RTC alarm X sub second register */ +/* FIXME - TODO */ + + + +BEGIN_DECLS + +void rtc_set_prescaler(uint32_t sync, uint32_t async); +void rtc_wait_for_synchro(void); +void rtc_lock(void); +void rtc_unlock(void); +void rtc_set_wakeup_time(uint16_t wkup_time, uint8_t rtc_cr_wucksel); +void rtc_clear_wakeup_flag(void); + +END_DECLS +/**@}*/ + +#endif /* RTC2_H */ +/** @cond */ +#else +#warning "rtc_common_bcd.h should not be included explicitly, only via rtc.h" +#endif +/** @endcond */ + + diff --git a/libopencm3/include/libopencm3/stm32/common/spi_common_all.h b/libopencm3/include/libopencm3/stm32/common/spi_common_all.h new file mode 100644 index 0000000..a0d2571 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/spi_common_all.h @@ -0,0 +1,405 @@ +/** @addtogroup spi_defines + * + * @author @htmlonly © @endhtmlonly 2009 Uwe Hermann + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H +The order of header inclusion is important. spi.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#if defined(LIBOPENCM3_SPI_H) +/** @endcond */ +#ifndef LIBOPENCM3_SPI_COMMON_ALL_H +#define LIBOPENCM3_SPI_COMMON_ALL_H + +/**@{*/ + +/* Registers can be accessed as 16bit or 32bit values. */ + +/* --- Convenience macros -------------------------------------------------- */ + +/****************************************************************************/ +/** @defgroup spi_reg_base SPI Register base address +@ingroup spi_defines + +@{*/ +#define SPI1 SPI1_BASE +#define SPI2 SPI2_I2S_BASE +#define SPI3 SPI3_I2S_BASE +#define SPI4 SPI4_BASE +#define SPI5 SPI5_BASE +#define SPI6 SPI6_BASE +/**@}*/ + +/* --- SPI registers ------------------------------------------------------- */ + +/* Control register 1 (SPIx_CR1) */ +/* Note: Not used in I2S mode. */ +#define SPI_CR1(spi_base) MMIO32(spi_base + 0x00) +#define SPI1_CR1 SPI_CR1(SPI1_BASE) +#define SPI2_CR1 SPI_CR1(SPI2_I2S_BASE) +#define SPI3_CR1 SPI_CR1(SPI3_I2S_BASE) + +/* Control register 2 (SPIx_CR2) */ +#define SPI_CR2(spi_base) MMIO32(spi_base + 0x04) +#define SPI1_CR2 SPI_CR2(SPI1_BASE) +#define SPI2_CR2 SPI_CR2(SPI2_I2S_BASE) +#define SPI3_CR2 SPI_CR2(SPI3_I2S_BASE) + +/* Status register (SPIx_SR) */ +#define SPI_SR(spi_base) MMIO32(spi_base + 0x08) +#define SPI1_SR SPI_SR(SPI1_BASE) +#define SPI2_SR SPI_SR(SPI2_I2S_BASE) +#define SPI3_SR SPI_SR(SPI3_I2S_BASE) + +/* Data register (SPIx_DR) */ +#define SPI_DR(spi_base) MMIO32(spi_base + 0x0c) +#define SPI1_DR SPI_DR(SPI1_BASE) +#define SPI2_DR SPI_DR(SPI2_I2S_BASE) +#define SPI3_DR SPI_DR(SPI3_I2S_BASE) + +/* CRC polynomial register (SPIx_CRCPR) */ +/* Note: Not used in I2S mode. */ +#define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10) +#define SPI1_CRCPR SPI_CRCPR(SPI1_BASE) +#define SPI2_CRCPR SPI_CRCPR(SPI2_I2S_BASE) +#define SPI3_CRCPR SPI_CRCPR(SPI3_I2S_BASE) + +/* RX CRC register (SPIx_RXCRCR) */ +/* Note: Not used in I2S mode. */ +#define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14) +#define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE) +#define SPI2_RXCRCR SPI_RXCRCR(SPI2_I2S_BASE) +#define SPI3_RXCRCR SPI_RXCRCR(SPI3_I2S_BASE) + +/* TX CRC register (SPIx_RXCRCR) */ +/* Note: Not used in I2S mode. */ +#define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18) +#define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE) +#define SPI2_TXCRCR SPI_TXCRCR(SPI2_I2S_BASE) +#define SPI3_TXCRCR SPI_TXCRCR(SPI3_I2S_BASE) + +/* I2S configuration register (SPIx_I2SCFGR) */ +#define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c) +#define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE) +#define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_I2S_BASE) +#define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_I2S_BASE) + +/* I2S prescaler register (SPIx_I2SPR) */ +#define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20) +#define SPI1_I2SPR SPI_I2SPR(SPI1_BASE) +#define SPI2_I2SPR SPI_I2SPR(SPI2_I2S_BASE) +#define SPI3_I2SPR SPI_I2SPR(SPI3_I2S_BASE) + +/* --- SPI_CR1 values ------------------------------------------------------ */ + +/* Note: None of the CR1 bits are used in I2S mode. */ + +/* BIDIMODE: Bidirectional data mode enable */ +#define SPI_CR1_BIDIMODE_2LINE_UNIDIR (0 << 15) +#define SPI_CR1_BIDIMODE_1LINE_BIDIR (1 << 15) +#define SPI_CR1_BIDIMODE (1 << 15) + +/* BIDIOE: Output enable in bidirectional mode */ +#define SPI_CR1_BIDIOE (1 << 14) + +/* CRCEN: Hardware CRC calculation enable */ +#define SPI_CR1_CRCEN (1 << 13) + +/* CRCNEXT: Transmit CRC next */ +#define SPI_CR1_CRCNEXT (1 << 12) + +/* RXONLY: Receive only */ +#define SPI_CR1_RXONLY (1 << 10) + +/* SSM: Software slave management */ +#define SPI_CR1_SSM (1 << 9) + +/* SSI: Internal slave select */ +#define SPI_CR1_SSI (1 << 8) + +/* LSBFIRST: Frame format */ +/****************************************************************************/ +/** @defgroup spi_lsbfirst SPI lsb/msb first +@ingroup spi_defines + +@{*/ +#define SPI_CR1_MSBFIRST (0 << 7) +#define SPI_CR1_LSBFIRST (1 << 7) +/**@}*/ + +/* SPE: SPI enable */ +#define SPI_CR1_SPE (1 << 6) + +/* BR[2:0]: Baud rate control */ +/****************************************************************************/ +/** @defgroup spi_baudrate SPI peripheral baud rates +@ingroup spi_defines + +@{*/ +#define SPI_CR1_BAUDRATE_FPCLK_DIV_2 (0x00 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_4 (0x01 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_8 (0x02 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_16 (0x03 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_32 (0x04 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_64 (0x05 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_128 (0x06 << 3) +#define SPI_CR1_BAUDRATE_FPCLK_DIV_256 (0x07 << 3) +/**@}*/ +/****************************************************************************/ +/** @defgroup spi_br_pre SPI peripheral baud rate prescale values +@ingroup spi_defines + +@{*/ +#define SPI_CR1_BR_FPCLK_DIV_2 0x0 +#define SPI_CR1_BR_FPCLK_DIV_4 0x1 +#define SPI_CR1_BR_FPCLK_DIV_8 0x2 +#define SPI_CR1_BR_FPCLK_DIV_16 0x3 +#define SPI_CR1_BR_FPCLK_DIV_32 0x4 +#define SPI_CR1_BR_FPCLK_DIV_64 0x5 +#define SPI_CR1_BR_FPCLK_DIV_128 0x6 +#define SPI_CR1_BR_FPCLK_DIV_256 0x7 +/**@}*/ + +/* MSTR: Master selection */ +#define SPI_CR1_MSTR (1 << 2) + +/* CPOL: Clock polarity */ +/****************************************************************************/ +/** @defgroup spi_cpol SPI clock polarity +@ingroup spi_defines + +@{*/ +#define SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE (0 << 1) +#define SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE (1 << 1) +/**@}*/ +#define SPI_CR1_CPOL (1 << 1) + +/* CPHA: Clock phase */ +/****************************************************************************/ +/** @defgroup spi_cpha SPI clock phase +@ingroup spi_defines + +@{*/ +#define SPI_CR1_CPHA_CLK_TRANSITION_1 (0 << 0) +#define SPI_CR1_CPHA_CLK_TRANSITION_2 (1 << 0) +/**@}*/ +#define SPI_CR1_CPHA (1 << 0) + +/* --- SPI_CR2 values ------------------------------------------------------ */ + +/* Bits [15:8]: Reserved. Forced to 0 by hardware. Used on F3. */ + +/* TXEIE: Tx buffer empty interrupt enable */ +#define SPI_CR2_TXEIE (1 << 7) + +/* RXNEIE: Rx buffer not empty interrupt enable */ +#define SPI_CR2_RXNEIE (1 << 6) + +/* ERRIE: Error interrupt enable */ +#define SPI_CR2_ERRIE (1 << 5) + +/* Bits [4:3]: Reserved. Forced to 0 by hardware. */ + +/* SSOE: SS output enable */ +/* Note: Not used in I2S mode. */ +#define SPI_CR2_SSOE (1 << 2) + +/* TXDMAEN: Tx buffer DMA enable */ +#define SPI_CR2_TXDMAEN (1 << 1) + +/* RXDMAEN: Rx buffer DMA enable */ +#define SPI_CR2_RXDMAEN (1 << 0) + +/* --- SPI_SR values ------------------------------------------------------- */ + +/* Bits [15:8]: Reserved. Forced to 0 by hardware. Used on F3. */ + +/* BSY: Busy flag */ +#define SPI_SR_BSY (1 << 7) + +/* OVR: Overrun flag */ +#define SPI_SR_OVR (1 << 6) + +/* MODF: Mode fault */ +/* Note: Not used in I2S mode. */ +#define SPI_SR_MODF (1 << 5) + +/* CRCERR: CRC error flag */ +/* Note: Not used in I2S mode. */ +#define SPI_SR_CRCERR (1 << 4) + +/* UDR: Underrun flag */ +/* Note: Not used in SPI mode. */ +#define SPI_SR_UDR (1 << 3) + +/* CHSIDE: Channel side */ +/* Note: Not used in SPI mode. No meaning in PCM mode. */ +#define SPI_SR_CHSIDE (1 << 2) + +/* TXE: Transmit buffer empty */ +#define SPI_SR_TXE (1 << 1) + +/* RXNE: Receive buffer not empty */ +#define SPI_SR_RXNE (1 << 0) + +/* --- SPI_DR values ------------------------------------------------------- */ + +/* SPI_DR[15:0]: Data Register. */ + +/* --- SPI_CRCPR values ---------------------------------------------------- */ + +/* Note: Not used in I2S mode. */ +/* SPI_CRCPR [15:0]: CRC Polynomial Register. */ + +/* --- SPI_RXCRCR values --------------------------------------------------- */ + +/* Note: Not used in I2S mode. */ +/* SPI_RXCRCR [15:0]: RX CRC Register. */ + +/* --- SPI_TXCRCR values --------------------------------------------------- */ + +/* Note: Not used in I2S mode. */ +/* SPI_TXCRCR [15:0]: TX CRC Register. */ + +/* --- SPI_I2SCFGR values -------------------------------------------------- */ + +/* Note: None of these bits are used in SPI mode. */ + +/* Bits [15:12]: Reserved. Forced to 0 by hardware. */ + +/* I2SMOD: I2S mode selection */ +#define SPI_I2SCFGR_I2SMOD (1 << 11) + +/* I2SE: I2S enable */ +#define SPI_I2SCFGR_I2SE (1 << 10) + +/* I2SCFG[9:8]: I2S configuration mode */ +#define SPI_I2SCFGR_I2SCFG_LSB 8 +#define SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT 0x0 +#define SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE 0x1 +#define SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT 0x2 +#define SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE 0x3 + +/* PCMSYNC: PCM frame synchronization */ +#define SPI_I2SCFGR_PCMSYNC (1 << 7) + +/* Bit 6: Reserved. Forced to 0 by hardware. */ + +/* I2SSTD[5:4]: I2S standard selection */ +#define SPI_I2SCFGR_I2SSTD_LSB 4 +#define SPI_I2SCFGR_I2SSTD_I2S_PHILLIPS 0x0 +#define SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED 0x1 +#define SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED 0x2 +#define SPI_I2SCFGR_I2SSTD_PCM 0x3 + +/* CKPOL: Steady state clock polarity */ +#define SPI_I2SCFGR_CKPOL (1 << 3) + +/* DATLEN[2:1]: Data length to be transferred */ +#define SPI_I2SCFGR_DATLEN_LSB 1 +#define SPI_I2SCFGR_DATLEN_16BIT 0x0 +#define SPI_I2SCFGR_DATLEN_24BIT 0x1 +#define SPI_I2SCFGR_DATLEN_32BIT 0x2 + +/* CHLEN: Channel length */ +#define SPI_I2SCFGR_CHLEN (1 << 0) + +/* --- SPI_I2SPR values ---------------------------------------------------- */ + +/* Note: None of these bits are used in SPI mode. */ + +/* Bits [15:10]: Reserved. Forced to 0 by hardware. */ + +/* MCKOE: Master clock output enable */ +#define SPI_I2SPR_MCKOE (1 << 9) + +/* ODD: Odd factor for the prescaler */ +#define SPI_I2SPR_ODD (1 << 8) + +/* I2SDIV[7:0]: I2S linear prescaler */ +/* 0 and 1 are forbidden values */ + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void spi_reset(uint32_t spi_peripheral); +int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha, + uint32_t dff, uint32_t lsbfirst); +void spi_enable(uint32_t spi); +void spi_disable(uint32_t spi); +uint16_t spi_clean_disable(uint32_t spi); +void spi_write(uint32_t spi, uint16_t data); +void spi_send(uint32_t spi, uint16_t data); +uint16_t spi_read(uint32_t spi); +uint16_t spi_xfer(uint32_t spi, uint16_t data); +void spi_set_bidirectional_mode(uint32_t spi); +void spi_set_unidirectional_mode(uint32_t spi); +void spi_set_bidirectional_receive_only_mode(uint32_t spi); +void spi_set_bidirectional_transmit_only_mode(uint32_t spi); +void spi_enable_crc(uint32_t spi); +void spi_disable_crc(uint32_t spi); +void spi_set_next_tx_from_buffer(uint32_t spi); +void spi_set_next_tx_from_crc(uint32_t spi); +void spi_set_dff_8bit(uint32_t spi); +void spi_set_dff_16bit(uint32_t spi); +void spi_set_full_duplex_mode(uint32_t spi); +void spi_set_receive_only_mode(uint32_t spi); +void spi_disable_software_slave_management(uint32_t spi); +void spi_enable_software_slave_management(uint32_t spi); +void spi_set_nss_high(uint32_t spi); +void spi_set_nss_low(uint32_t spi); +void spi_send_lsb_first(uint32_t spi); +void spi_send_msb_first(uint32_t spi); +void spi_set_baudrate_prescaler(uint32_t spi, uint8_t baudrate); +void spi_set_master_mode(uint32_t spi); +void spi_set_slave_mode(uint32_t spi); +void spi_set_clock_polarity_1(uint32_t spi); +void spi_set_clock_polarity_0(uint32_t spi); +void spi_set_clock_phase_1(uint32_t spi); +void spi_set_clock_phase_0(uint32_t spi); +void spi_enable_tx_buffer_empty_interrupt(uint32_t spi); +void spi_disable_tx_buffer_empty_interrupt(uint32_t spi); +void spi_enable_rx_buffer_not_empty_interrupt(uint32_t spi); +void spi_disable_rx_buffer_not_empty_interrupt(uint32_t spi); +void spi_enable_error_interrupt(uint32_t spi); +void spi_disable_error_interrupt(uint32_t spi); +void spi_enable_ss_output(uint32_t spi); +void spi_disable_ss_output(uint32_t spi); +void spi_enable_tx_dma(uint32_t spi); +void spi_disable_tx_dma(uint32_t spi); +void spi_enable_rx_dma(uint32_t spi); +void spi_disable_rx_dma(uint32_t spi); + +END_DECLS + +/**@}*/ + +#endif +/** @cond */ +#else +#warning "spi_common_all.h should not be included explicitly, only via spi.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/spi_common_f03.h b/libopencm3/include/libopencm3/stm32/common/spi_common_f03.h new file mode 100644 index 0000000..69813d8 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/spi_common_f03.h @@ -0,0 +1,124 @@ +/** @addtogroup spi_defines + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H + * The order of header inclusion is important. spi.h includes the device + * specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_SPI_H +/** @endcond */ +#ifndef LIBOPENCM3_SPI_COMMON_F03_H +#define LIBOPENCM3_SPI_COMMON_F03_H + +/**@{*/ + +#include + +/* + * This file extends the common stm32 version with defintions only + * applicable to the STM32F0/F3 series of devices + */ + +#define SPI_DR8(spi_base) MMIO8(spi_base + 0x0c) +#define SPI1_DR8 SPI_DR8(SPI1_BASE) +#define SPI2_DR8 SPI_DR8(SPI2_I2S_BASE) +#define SPI3_DR8 SPI_DR8(SPI3_I2S_BASE) + +/* DFF: Data frame format */ +/****************************************************************************/ +/** @defgroup spi_dff SPI data frame format + * @ingroup spi_defines + * + * @{*/ + +#define SPI_CR1_CRCL_8BIT (0 << 11) +#define SPI_CR1_CRCL_16BIT (1 << 11) +/**@}*/ +#define SPI_CR1_CRCL (1 << 11) + +/* --- SPI_CR2 values ------------------------------------------------------ */ + +/* LDMA_TX: Last DMA transfer for transmission */ +#define SPI_CR2_LDMA_TX (1 << 14) + +/* LDMA_RX: Last DMA transfer for reception */ +#define SPI_CR2_LDMA_RX (1 << 13) + +/* FRXTH: FIFO reception threshold */ +#define SPI_CR2_FRXTH (1 << 12) + +/* DS [3:0]: Data size */ +/* 0x0 - 0x2 NOT USED */ +#define SPI_CR2_DS_4BIT (0x3 << 8) +#define SPI_CR2_DS_5BIT (0x4 << 8) +#define SPI_CR2_DS_6BIT (0x5 << 8) +#define SPI_CR2_DS_7BIT (0x6 << 8) +#define SPI_CR2_DS_8BIT (0x7 << 8) +#define SPI_CR2_DS_9BIT (0x8 << 8) +#define SPI_CR2_DS_10BIT (0x9 << 8) +#define SPI_CR2_DS_11BIT (0xA << 8) +#define SPI_CR2_DS_12BIT (0xB << 8) +#define SPI_CR2_DS_13BIT (0xC << 8) +#define SPI_CR2_DS_14BIT (0xD << 8) +#define SPI_CR2_DS_15BIT (0xE << 8) +#define SPI_CR2_DS_16BIT (0xF << 8) +#define SPI_CR2_DS_MASK (0xF << 8) + +/* NSSP: NSS pulse management */ +#define SPI_CR2_NSSP (1 << 3) + +/* --- SPI_SR values ------------------------------------------------------- */ + +/* FTLVL[1:0]: FIFO Transmission Level */ +#define SPI_SR_FTLVL_FIFO_EMPTY (0x0 << 11) +#define SPI_SR_FTLVL_QUARTER_FIFO (0x1 << 11) +#define SPI_SR_FTLVL_HALF_FIFO (0x2 << 11) +#define SPI_SR_FTLVL_FIFO_FULL (0x3 << 11) + +/* FRLVL[1:0]: FIFO Reception Level */ +#define SPI_SR_FRLVL_FIFO_EMPTY (0x0 << 9) +#define SPI_SR_FRLVL_QUARTER_FIFO (0x1 << 9) +#define SPI_SR_FRLVL_HALF_FIFO (0x2 << 9) +#define SPI_SR_FRLVL_FIFO_FULL (0x3 << 9) + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void spi_set_crcl_8bit(uint32_t spi); +void spi_set_crcl_16bit(uint32_t spi); +void spi_set_data_size(uint32_t spi, uint16_t data_s); +void spi_fifo_reception_threshold_8bit(uint32_t spi); +void spi_fifo_reception_threshold_16bit(uint32_t spi); +void spi_i2s_mode_spi_mode(uint32_t spi); +void spi_send8(uint32_t spi, uint8_t data); +uint8_t spi_read8(uint32_t spi); + +END_DECLS + +#endif +/** @cond */ +#else +#warning "spi_common_f03.h should not be included explicitly, only via spi.h" +#endif +/** @endcond */ +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/common/spi_common_f24.h b/libopencm3/include/libopencm3/stm32/common/spi_common_f24.h new file mode 100644 index 0000000..f894626 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/spi_common_f24.h @@ -0,0 +1,66 @@ +/** @addtogroup spi_defines + +@author @htmlonly © @endhtmlonly 2011 Fergus Noble + +*/ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H +The order of header inclusion is important. spi.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_SPI_H +/** @endcond */ +#ifndef LIBOPENCM3_SPI_COMMON_F24_H +#define LIBOPENCM3_SPI_COMMON_F24_H + +/**@{*/ + +#include + +/* + * This file extends the common STM32 version with definitions only + * applicable to the STM32F2/4 series of devices. + */ + +/* Note, these values are also on the F0, but other parts are _not_ */ + +/* --- SPI_CR2 values ------------------------------------------------------ */ + +/* FRF: Frame format */ +/* Note: Not used in I2S mode. */ +#define SPI_CR2_FRF (1 << 4) +#define SPI_CR2_FRF_MOTOROLA_MODE (0 << 4) +#define SPI_CR2_FRF_TI_MODE (1 << 4) + +/* --- SPI_SR values ------------------------------------------------------- */ + +/* TIFRFE: TI frame format error */ +#define SPI_SR_TIFRFE (1 << 8) + +#endif +/** @cond */ +#else +#warning "spi_common_f24.h should not be included explicitly, only via spi.h" +#endif +/** @endcond */ +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/common/spi_common_l1f124.h b/libopencm3/include/libopencm3/stm32/common/spi_common_l1f124.h new file mode 100644 index 0000000..ddfe612 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/spi_common_l1f124.h @@ -0,0 +1,65 @@ +/** @addtogroup spi_defines + +@author @htmlonly © @endhtmlonly 2011 Fergus Noble + +*/ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H +The order of header inclusion is important. spi.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_SPI_H +/** @endcond */ +#ifndef LIBOPENCM3_SPI_COMMON_L1F124_H +#define LIBOPENCM3_SPI_COMMON_L1F124_H + +/**@{*/ + +#include + +/* + * This file extends the common STM32 version with definitions only + * applicable to the STM32L1/F1/2/4 series of devices. + */ + +/* DFF: Data frame format */ +/****************************************************************************/ +/** @defgroup spi_dff SPI data frame format +@ingroup spi_defines + +@{*/ + +#define SPI_CR1_DFF_8BIT (0 << 11) +#define SPI_CR1_DFF_16BIT (1 << 11) + +/**@}*/ + +#define SPI_CR1_DFF (1 << 11) + +#endif +/** @cond */ +#else +#warning "spi_common_l1f124.h should not be included explicitly, only via spi.h" +#endif +/** @endcond */ +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/common/syscfg_common_l1f234.h b/libopencm3/include/libopencm3/stm32/common/syscfg_common_l1f234.h new file mode 100644 index 0000000..2b41c95 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/syscfg_common_l1f234.h @@ -0,0 +1,61 @@ +/** @addtogroup syscfg_defines + * + * @author @htmlonly © @endhtmlonly 2011 + * Fergus Noble + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H +The order of header inclusion is important. spi.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#if defined(LIBOPENCM3_SYSCFG_H) +/** @endcond */ +#ifndef LIBOPENCM3_SYSCFG_COMMON_L1F234_H +#define LIBOPENCM3_SYSCFG_COMMON_L1F234_H + +/**@{*/ + +/* --- SYSCFG registers ---------------------------------------------------- */ + +#define SYSCFG_MEMRM MMIO32(SYSCFG_BASE + 0x00) + +#define SYSCFG_PMC MMIO32(SYSCFG_BASE + 0x04) + +/* External interrupt configuration registers [0..3] (SYSCFG_EXTICR[1..4]) */ +#define SYSCFG_EXTICR(i) MMIO32(SYSCFG_BASE + 0x08 + (i)*4) +#define SYSCFG_EXTICR1 SYSCFG_EXTICR(0) +#define SYSCFG_EXTICR2 SYSCFG_EXTICR(1) +#define SYSCFG_EXTICR3 SYSCFG_EXTICR(2) +#define SYSCFG_EXTICR4 SYSCFG_EXTICR(3) + +#define SYSCFG_CMPCR MMIO32(SYSCFG_BASE + 0x20) + +#endif +/**@}*/ + +/** @cond */ +#else +#warning "syscfg_common_l1f234.h should not be included explicitly," +#warning "only via syscfg.h" +#endif +/** @endcond */ diff --git a/libopencm3/include/libopencm3/stm32/common/timer_common_all.h b/libopencm3/include/libopencm3/stm32/common/timer_common_all.h new file mode 100644 index 0000000..9725d64 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/timer_common_all.h @@ -0,0 +1,1129 @@ +/** @addtogroup timer_defines + * + * @author @htmlonly © @endhtmlonly 2009 Piotr Esden-Tempski + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Piotr Esden-Tempski + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA TIMER.H +The order of header inclusion is important. timer.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#if defined(LIBOPENCM3_TIMER_H) +/** @endcond */ +#ifndef LIBOPENCM3_TIMER_COMMON_H +#define LIBOPENCM3_TIMER_COMMON_H + +/* --- Convenience macros -------------------------------------------------- */ + +/* Timer register base addresses (for convenience) */ +/****************************************************************************/ +/** @defgroup tim_reg_base Timer register base addresses +@ingroup timer_defines + +@{*/ +#define TIM1 TIM1_BASE +#define TIM2 TIM2_BASE +#define TIM3 TIM3_BASE +#if defined(TIM4_BASE) +#define TIM4 TIM4_BASE +#endif +#define TIM5 TIM5_BASE +#define TIM6 TIM6_BASE +#define TIM7 TIM7_BASE +#if defined(TIM8_BASE) +# define TIM8 TIM8_BASE +#endif +/**@}*/ + +/* --- Timer registers ----------------------------------------------------- */ + +/* Control register 1 (TIMx_CR1) */ +#define TIM_CR1(tim_base) MMIO32(tim_base + 0x00) +#define TIM1_CR1 TIM_CR1(TIM1) +#define TIM2_CR1 TIM_CR1(TIM2) +#define TIM3_CR1 TIM_CR1(TIM3) +#define TIM4_CR1 TIM_CR1(TIM4) +#define TIM5_CR1 TIM_CR1(TIM5) +#define TIM6_CR1 TIM_CR1(TIM6) +#define TIM7_CR1 TIM_CR1(TIM7) +#define TIM8_CR1 TIM_CR1(TIM8) + +/* Control register 2 (TIMx_CR2) */ +#define TIM_CR2(tim_base) MMIO32(tim_base + 0x04) +#define TIM1_CR2 TIM_CR2(TIM1) +#define TIM2_CR2 TIM_CR2(TIM2) +#define TIM3_CR2 TIM_CR2(TIM3) +#define TIM4_CR2 TIM_CR2(TIM4) +#define TIM5_CR2 TIM_CR2(TIM5) +#define TIM6_CR2 TIM_CR2(TIM6) +#define TIM7_CR2 TIM_CR2(TIM7) +#define TIM8_CR2 TIM_CR2(TIM8) + +/* Slave mode control register (TIMx_SMCR) */ +#define TIM_SMCR(tim_base) MMIO32(tim_base + 0x08) +#define TIM1_SMCR TIM_SMCR(TIM1) +#define TIM2_SMCR TIM_SMCR(TIM2) +#define TIM3_SMCR TIM_SMCR(TIM3) +#define TIM4_SMCR TIM_SMCR(TIM4) +#define TIM5_SMCR TIM_SMCR(TIM5) +#define TIM8_SMCR TIM_SMCR(TIM8) + +/* DMA/Interrupt enable register (TIMx_DIER) */ +#define TIM_DIER(tim_base) MMIO32(tim_base + 0x0C) +#define TIM1_DIER TIM_DIER(TIM1) +#define TIM2_DIER TIM_DIER(TIM2) +#define TIM3_DIER TIM_DIER(TIM3) +#define TIM4_DIER TIM_DIER(TIM4) +#define TIM5_DIER TIM_DIER(TIM5) +#define TIM6_DIER TIM_DIER(TIM6) +#define TIM7_DIER TIM_DIER(TIM7) +#define TIM8_DIER TIM_DIER(TIM8) + +/* Status register (TIMx_SR) */ +#define TIM_SR(tim_base) MMIO32(tim_base + 0x10) +#define TIM1_SR TIM_SR(TIM1) +#define TIM2_SR TIM_SR(TIM2) +#define TIM3_SR TIM_SR(TIM3) +#define TIM4_SR TIM_SR(TIM4) +#define TIM5_SR TIM_SR(TIM5) +#define TIM6_SR TIM_SR(TIM6) +#define TIM7_SR TIM_SR(TIM7) +#define TIM8_SR TIM_SR(TIM8) + +/* Event generation register (TIMx_EGR) */ +#define TIM_EGR(tim_base) MMIO32(tim_base + 0x14) +#define TIM1_EGR TIM_EGR(TIM1) +#define TIM2_EGR TIM_EGR(TIM2) +#define TIM3_EGR TIM_EGR(TIM3) +#define TIM4_EGR TIM_EGR(TIM4) +#define TIM5_EGR TIM_EGR(TIM5) +#define TIM6_EGR TIM_EGR(TIM6) +#define TIM7_EGR TIM_EGR(TIM7) +#define TIM8_EGR TIM_EGR(TIM8) + +/* Capture/compare mode register 1 (TIMx_CCMR1) */ +#define TIM_CCMR1(tim_base) MMIO32(tim_base + 0x18) +#define TIM1_CCMR1 TIM_CCMR1(TIM1) +#define TIM2_CCMR1 TIM_CCMR1(TIM2) +#define TIM3_CCMR1 TIM_CCMR1(TIM3) +#define TIM4_CCMR1 TIM_CCMR1(TIM4) +#define TIM5_CCMR1 TIM_CCMR1(TIM5) +#define TIM8_CCMR1 TIM_CCMR1(TIM8) + +/* Capture/compare mode register 2 (TIMx_CCMR2) */ +#define TIM_CCMR2(tim_base) MMIO32(tim_base + 0x1C) +#define TIM1_CCMR2 TIM_CCMR2(TIM1) +#define TIM2_CCMR2 TIM_CCMR2(TIM2) +#define TIM3_CCMR2 TIM_CCMR2(TIM3) +#define TIM4_CCMR2 TIM_CCMR2(TIM4) +#define TIM5_CCMR2 TIM_CCMR2(TIM5) +#define TIM8_CCMR2 TIM_CCMR2(TIM8) + +/* Capture/compare enable register (TIMx_CCER) */ +#define TIM_CCER(tim_base) MMIO32(tim_base + 0x20) +#define TIM1_CCER TIM_CCER(TIM1) +#define TIM2_CCER TIM_CCER(TIM2) +#define TIM3_CCER TIM_CCER(TIM3) +#define TIM4_CCER TIM_CCER(TIM4) +#define TIM5_CCER TIM_CCER(TIM5) +#define TIM8_CCER TIM_CCER(TIM8) + +/* Counter (TIMx_CNT) */ +#define TIM_CNT(tim_base) MMIO32(tim_base + 0x24) +#define TIM1_CNT TIM_CNT(TIM1) +#define TIM2_CNT TIM_CNT(TIM2) +#define TIM3_CNT TIM_CNT(TIM3) +#define TIM4_CNT TIM_CNT(TIM4) +#define TIM5_CNT TIM_CNT(TIM5) +#define TIM6_CNT TIM_CNT(TIM6) +#define TIM7_CNT TIM_CNT(TIM7) +#define TIM8_CNT TIM_CNT(TIM8) + +/* Prescaler (TIMx_PSC) */ +#define TIM_PSC(tim_base) MMIO32(tim_base + 0x28) +#define TIM1_PSC TIM_PSC(TIM1) +#define TIM2_PSC TIM_PSC(TIM2) +#define TIM3_PSC TIM_PSC(TIM3) +#define TIM4_PSC TIM_PSC(TIM4) +#define TIM5_PSC TIM_PSC(TIM5) +#define TIM6_PSC TIM_PSC(TIM6) +#define TIM7_PSC TIM_PSC(TIM7) +#define TIM8_PSC TIM_PSC(TIM8) + +/* Auto-reload register (TIMx_ARR) */ +#define TIM_ARR(tim_base) MMIO32(tim_base + 0x2C) +#define TIM1_ARR TIM_ARR(TIM1) +#define TIM2_ARR TIM_ARR(TIM2) +#define TIM3_ARR TIM_ARR(TIM3) +#define TIM4_ARR TIM_ARR(TIM4) +#define TIM5_ARR TIM_ARR(TIM5) +#define TIM6_ARR TIM_ARR(TIM6) +#define TIM7_ARR TIM_ARR(TIM7) +#define TIM8_ARR TIM_ARR(TIM8) + +/* Repetition counter register (TIMx_RCR) */ +#define TIM_RCR(tim_base) MMIO32(tim_base + 0x30) +#define TIM1_RCR TIM_RCR(TIM1) +#define TIM8_RCR TIM_RCR(TIM8) + +/* Capture/compare register 1 (TIMx_CCR1) */ +#define TIM_CCR1(tim_base) MMIO32(tim_base + 0x34) +#define TIM1_CCR1 TIM_CCR1(TIM1) +#define TIM2_CCR1 TIM_CCR1(TIM2) +#define TIM3_CCR1 TIM_CCR1(TIM3) +#define TIM4_CCR1 TIM_CCR1(TIM4) +#define TIM5_CCR1 TIM_CCR1(TIM5) +#define TIM8_CCR1 TIM_CCR1(TIM8) + +/* Capture/compare register 2 (TIMx_CCR2) */ +#define TIM_CCR2(tim_base) MMIO32(tim_base + 0x38) +#define TIM1_CCR2 TIM_CCR2(TIM1) +#define TIM2_CCR2 TIM_CCR2(TIM2) +#define TIM3_CCR2 TIM_CCR2(TIM3) +#define TIM4_CCR2 TIM_CCR2(TIM4) +#define TIM5_CCR2 TIM_CCR2(TIM5) +#define TIM8_CCR2 TIM_CCR2(TIM8) + +/* Capture/compare register 3 (TIMx_CCR3) */ +#define TIM_CCR3(tim_base) MMIO32(tim_base + 0x3C) +#define TIM1_CCR3 TIM_CCR3(TIM1) +#define TIM2_CCR3 TIM_CCR3(TIM2) +#define TIM3_CCR3 TIM_CCR3(TIM3) +#define TIM4_CCR3 TIM_CCR3(TIM4) +#define TIM5_CCR3 TIM_CCR3(TIM5) +#define TIM8_CCR3 TIM_CCR3(TIM8) + +/* Capture/compare register 4 (TIMx_CCR4) */ +#define TIM_CCR4(tim_base) MMIO32(tim_base + 0x40) +#define TIM1_CCR4 TIM_CCR4(TIM1) +#define TIM2_CCR4 TIM_CCR4(TIM2) +#define TIM3_CCR4 TIM_CCR4(TIM3) +#define TIM4_CCR4 TIM_CCR4(TIM4) +#define TIM5_CCR4 TIM_CCR4(TIM5) +#define TIM8_CCR4 TIM_CCR4(TIM8) + +/* Break and dead-time register (TIMx_BDTR) */ +#define TIM_BDTR(tim_base) MMIO32(tim_base + 0x44) +#define TIM1_BDTR TIM_BDTR(TIM1) +#define TIM8_BDTR TIM_BDTR(TIM8) + +/* DMA control register (TIMx_DCR) */ +#define TIM_DCR(tim_base) MMIO32(tim_base + 0x48) +#define TIM1_DCR TIM_DCR(TIM1) +#define TIM2_DCR TIM_DCR(TIM2) +#define TIM3_DCR TIM_DCR(TIM3) +#define TIM4_DCR TIM_DCR(TIM4) +#define TIM5_DCR TIM_DCR(TIM5) +#define TIM8_DCR TIM_DCR(TIM8) + +/* DMA address for full transfer (TIMx_DMAR) */ +#define TIM_DMAR(tim_base) MMIO32(tim_base + 0x4C) +#define TIM1_DMAR TIM_DMAR(TIM1) +#define TIM2_DMAR TIM_DMAR(TIM2) +#define TIM3_DMAR TIM_DMAR(TIM3) +#define TIM4_DMAR TIM_DMAR(TIM4) +#define TIM5_DMAR TIM_DMAR(TIM5) +#define TIM8_DMAR TIM_DMAR(TIM8) + +/* --- TIMx_CR1 values ----------------------------------------------------- */ + +/****************************************************************************/ +/** @defgroup tim_x_cr1_cdr TIMx_CR1 CKD[1:0] Clock Division Ratio +@ingroup timer_defines + +@{*/ +/* CKD[1:0]: Clock division */ +#define TIM_CR1_CKD_CK_INT (0x0 << 8) +#define TIM_CR1_CKD_CK_INT_MUL_2 (0x1 << 8) +#define TIM_CR1_CKD_CK_INT_MUL_4 (0x2 << 8) +#define TIM_CR1_CKD_CK_INT_MASK (0x3 << 8) +/**@}*/ + +/* ARPE: Auto-reload preload enable */ +#define TIM_CR1_ARPE (1 << 7) + +/* CMS[1:0]: Center-aligned mode selection */ +/****************************************************************************/ +/** @defgroup tim_x_cr1_cms TIMx_CR1 CMS[1:0]: Center-aligned Mode Selection +@ingroup timer_defines + +@{*/ +#define TIM_CR1_CMS_EDGE (0x0 << 5) +#define TIM_CR1_CMS_CENTER_1 (0x1 << 5) +#define TIM_CR1_CMS_CENTER_2 (0x2 << 5) +#define TIM_CR1_CMS_CENTER_3 (0x3 << 5) +#define TIM_CR1_CMS_MASK (0x3 << 5) +/**@}*/ + +/* DIR: Direction */ +/****************************************************************************/ +/** @defgroup tim_x_cr1_dir TIMx_CR1 DIR: Direction +@ingroup timer_defines + +@{*/ +#define TIM_CR1_DIR_UP (0 << 4) +#define TIM_CR1_DIR_DOWN (1 << 4) +/**@}*/ + +/* OPM: One pulse mode */ +#define TIM_CR1_OPM (1 << 3) + +/* URS: Update request source */ +#define TIM_CR1_URS (1 << 2) + +/* UDIS: Update disable */ +#define TIM_CR1_UDIS (1 << 1) + +/* CEN: Counter enable */ +#define TIM_CR1_CEN (1 << 0) + +/* --- TIMx_CR2 values ----------------------------------------------------- */ + +/****************************************************************************/ +/** @defgroup tim_x_cr2_ois TIMx_CR2_OIS: Force Output Idle State Control Values +@ingroup timer_defines + +@{*/ +/* OIS4:*//** Output idle state 4 (OC4 output) */ +#define TIM_CR2_OIS4 (1 << 14) + +/* OIS3N:*//** Output idle state 3 (OC3N output) */ +#define TIM_CR2_OIS3N (1 << 13) + +/* OIS3:*//** Output idle state 3 (OC3 output) */ +#define TIM_CR2_OIS3 (1 << 12) + +/* OIS2N:*//** Output idle state 2 (OC2N output) */ +#define TIM_CR2_OIS2N (1 << 11) + +/* OIS2:*//** Output idle state 2 (OC2 output) */ +#define TIM_CR2_OIS2 (1 << 10) + +/* OIS1N:*//** Output idle state 1 (OC1N output) */ +#define TIM_CR2_OIS1N (1 << 9) + +/* OIS1:*//** Output idle state 1 (OC1 output) */ +#define TIM_CR2_OIS1 (1 << 8) +#define TIM_CR2_OIS_MASK (0x7f << 8) +/**@}*/ + +/* TI1S: TI1 selection */ +#define TIM_CR2_TI1S (1 << 7) + +/* MMS[2:0]: Master mode selection */ +/****************************************************************************/ +/** @defgroup tim_mastermode TIMx_CR2 MMS[6:4]: Master Mode Selection +@ingroup timer_defines + +@{*/ +#define TIM_CR2_MMS_RESET (0x0 << 4) +#define TIM_CR2_MMS_ENABLE (0x1 << 4) +#define TIM_CR2_MMS_UPDATE (0x2 << 4) +#define TIM_CR2_MMS_COMPARE_PULSE (0x3 << 4) +#define TIM_CR2_MMS_COMPARE_OC1REF (0x4 << 4) +#define TIM_CR2_MMS_COMPARE_OC2REF (0x5 << 4) +#define TIM_CR2_MMS_COMPARE_OC3REF (0x6 << 4) +#define TIM_CR2_MMS_COMPARE_OC4REF (0x7 << 4) +#define TIM_CR2_MMS_MASK (0x7 << 4) +/**@}*/ + +/* CCDS: Capture/compare DMA selection */ +#define TIM_CR2_CCDS (1 << 3) + +/* CCUS: Capture/compare control update selection */ +#define TIM_CR2_CCUS (1 << 2) + +/* CCPC: Capture/compare preload control */ +#define TIM_CR2_CCPC (1 << 0) + +/* --- TIMx_SMCR values ---------------------------------------------------- */ + +/* ETP: External trigger polarity */ +#define TIM_SMCR_ETP (1 << 15) + +/* ECE: External clock enable */ +#define TIM_SMCR_ECE (1 << 14) + +/* ETPS[1:0]: External trigger prescaler */ +#define TIM_SMCR_ETPS_OFF (0x0 << 12) +#define TIM_SMCR_ETPS_ETRP_DIV_2 (0x1 << 12) +#define TIM_SMCR_ETPS_ETRP_DIV_4 (0x2 << 12) +#define TIM_SMCR_ETPS_ETRP_DIV_8 (0x3 << 12) +#define TIM_SMCR_ETPS_MASK (0X3 << 12) + +/* ETF[3:0]: External trigger filter */ +#define TIM_SMCR_ETF_OFF (0x0 << 8) +#define TIM_SMCR_ETF_CK_INT_N_2 (0x1 << 8) +#define TIM_SMCR_ETF_CK_INT_N_4 (0x2 << 8) +#define TIM_SMCR_ETF_CK_INT_N_8 (0x3 << 8) +#define TIM_SMCR_ETF_DTS_DIV_2_N_6 (0x4 << 8) +#define TIM_SMCR_ETF_DTS_DIV_2_N_8 (0x5 << 8) +#define TIM_SMCR_ETF_DTS_DIV_4_N_6 (0x6 << 8) +#define TIM_SMCR_ETF_DTS_DIV_4_N_8 (0x7 << 8) +#define TIM_SMCR_ETF_DTS_DIV_8_N_6 (0x8 << 8) +#define TIM_SMCR_ETF_DTS_DIV_8_N_8 (0x9 << 8) +#define TIM_SMCR_ETF_DTS_DIV_16_N_5 (0xA << 8) +#define TIM_SMCR_ETF_DTS_DIV_16_N_6 (0xB << 8) +#define TIM_SMCR_ETF_DTS_DIV_16_N_8 (0xC << 8) +#define TIM_SMCR_ETF_DTS_DIV_32_N_5 (0xD << 8) +#define TIM_SMCR_ETF_DTS_DIV_32_N_6 (0xE << 8) +#define TIM_SMCR_ETF_DTS_DIV_32_N_8 (0xF << 8) +#define TIM_SMCR_ETF_MASK (0xF << 8) + +/* MSM: Master/slave mode */ +#define TIM_SMCR_MSM (1 << 7) + +/* TS[2:0]: Trigger selection */ +/** @defgroup tim_ts TS Trigger selection +@ingroup timer_defines + +@{*/ +/** Internal Trigger 0 (ITR0) */ +#define TIM_SMCR_TS_ITR0 (0x0 << 4) +/** Internal Trigger 1 (ITR1) */ +#define TIM_SMCR_TS_ITR1 (0x1 << 4) +/** Internal Trigger 2 (ITR2) */ +#define TIM_SMCR_TS_ITR2 (0x2 << 4) +/** Internal Trigger 3 (ITR3) */ +#define TIM_SMCR_TS_ITR3 (0x3 << 4) +/** TI1 Edge Detector (TI1F_ED) */ +#define TIM_SMCR_TS_IT1F_ED (0x4 << 4) +/** Filtered Timer Input 1 (TI1FP1) */ +#define TIM_SMCR_TS_IT1FP1 (0x5 << 4) +/** Filtered Timer Input 2 (TI1FP2) */ +#define TIM_SMCR_TS_IT1FP2 (0x6 << 4) +/** External Trigger input (ETRF) */ +#define TIM_SMCR_TS_ETRF (0x7 << 4) +#define TIM_SMCR_TS_MASK (0x7 << 4) +/**@}*/ + +/* SMS[2:0]: Slave mode selection */ +/** @defgroup tim_sms SMS Slave mode selection +@ingroup timer_defines + +@{*/ +/** Slave mode disabled */ +#define TIM_SMCR_SMS_OFF (0x0 << 0) +/** Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 +level. */ +#define TIM_SMCR_SMS_EM1 (0x1 << 0) +/** Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 +level. */ +#define TIM_SMCR_SMS_EM2 (0x2 << 0) +/** Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges +depending on the level of the complementary input. */ +#define TIM_SMCR_SMS_EM3 (0x3 << 0) +/** Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes + * the counter and generates an update of the registers. + */ +#define TIM_SMCR_SMS_RM (0x4 << 0) +/** Gated Mode - The counter clock is enabled when the trigger input (TRGI) is + * high. + */ +#define TIM_SMCR_SMS_GM (0x5 << 0) +/** Trigger Mode - The counter starts at a rising edge of the trigger TRGI. */ +#define TIM_SMCR_SMS_TM (0x6 << 0) +/** External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock + * the counter. + */ +#define TIM_SMCR_SMS_ECM1 (0x7 << 0) +#define TIM_SMCR_SMS_MASK (0x7 << 0) +/**@}*/ + +/* --- TIMx_DIER values ---------------------------------------------------- */ + +/****************************************************************************/ +/** @defgroup tim_irq_enable TIMx_DIER Timer DMA and Interrupt Enable Values +@ingroup timer_defines + +@{*/ +/* TDE:*//** Trigger DMA request enable */ +#define TIM_DIER_TDE (1 << 14) + +/* COMDE:*//** COM DMA request enable */ +#define TIM_DIER_COMDE (1 << 13) + +/* CC4DE:*//** Capture/Compare 4 DMA request enable */ +#define TIM_DIER_CC4DE (1 << 12) + +/* CC3DE:*//** Capture/Compare 3 DMA request enable */ +#define TIM_DIER_CC3DE (1 << 11) + +/* CC2DE:*//** Capture/Compare 2 DMA request enable */ +#define TIM_DIER_CC2DE (1 << 10) + +/* CC1DE:*//** Capture/Compare 1 DMA request enable */ +#define TIM_DIER_CC1DE (1 << 9) + +/* UDE*//**: Update DMA request enable */ +#define TIM_DIER_UDE (1 << 8) + +/* BIE:*//** Break interrupt enable */ +#define TIM_DIER_BIE (1 << 7) + +/* TIE:*//** Trigger interrupt enable */ +#define TIM_DIER_TIE (1 << 6) + +/* COMIE:*//** COM interrupt enable */ +#define TIM_DIER_COMIE (1 << 5) + +/* CC4IE:*//** Capture/compare 4 interrupt enable */ +#define TIM_DIER_CC4IE (1 << 4) + +/* CC3IE:*//** Capture/compare 3 interrupt enable */ +#define TIM_DIER_CC3IE (1 << 3) + +/* CC2IE:*//** Capture/compare 2 interrupt enable */ +#define TIM_DIER_CC2IE (1 << 2) + +/* CC1IE:*//** Capture/compare 1 interrupt enable */ +#define TIM_DIER_CC1IE (1 << 1) + +/* UIE:*//** Update interrupt enable */ +#define TIM_DIER_UIE (1 << 0) +/**@}*/ + +/* --- TIMx_SR values ------------------------------------------------------ */ +/****************************************************************************/ +/** @defgroup tim_sr_values TIMx_SR Timer Status Register Flags +@ingroup timer_defines + +@{*/ + +/* CC4OF:*//** Capture/compare 4 overcapture flag */ +#define TIM_SR_CC4OF (1 << 12) + +/* CC3OF:*//** Capture/compare 3 overcapture flag */ +#define TIM_SR_CC3OF (1 << 11) + +/* CC2OF:*//** Capture/compare 2 overcapture flag */ +#define TIM_SR_CC2OF (1 << 10) + +/* CC1OF:*//** Capture/compare 1 overcapture flag */ +#define TIM_SR_CC1OF (1 << 9) + +/* BIF:*//** Break interrupt flag */ +#define TIM_SR_BIF (1 << 7) + +/* TIF:*//** Trigger interrupt flag */ +#define TIM_SR_TIF (1 << 6) + +/* COMIF:*//** COM interrupt flag */ +#define TIM_SR_COMIF (1 << 5) + +/* CC4IF:*//** Capture/compare 4 interrupt flag */ +#define TIM_SR_CC4IF (1 << 4) + +/* CC3IF:*//** Capture/compare 3 interrupt flag */ +#define TIM_SR_CC3IF (1 << 3) + +/* CC2IF:*//** Capture/compare 2 interrupt flag */ +#define TIM_SR_CC2IF (1 << 2) + +/* CC1IF:*//** Capture/compare 1 interrupt flag */ +#define TIM_SR_CC1IF (1 << 1) + +/* UIF:*//** Update interrupt flag */ +#define TIM_SR_UIF (1 << 0) +/**@}*/ + +/* --- TIMx_EGR values ----------------------------------------------------- */ + +/****************************************************************************/ +/** @defgroup tim_event_gen TIMx_EGR Timer Event Generator Values +@ingroup timer_defines + +@{*/ + +/* BG:*//** Break generation */ +#define TIM_EGR_BG (1 << 7) + +/* TG:*//** Trigger generation */ +#define TIM_EGR_TG (1 << 6) + +/* COMG:*//** Capture/compare control update generation */ +#define TIM_EGR_COMG (1 << 5) + +/* CC4G:*//** Capture/compare 4 generation */ +#define TIM_EGR_CC4G (1 << 4) + +/* CC3G:*//** Capture/compare 3 generation */ +#define TIM_EGR_CC3G (1 << 3) + +/* CC2G:*//** Capture/compare 2 generation */ +#define TIM_EGR_CC2G (1 << 2) + +/* CC1G:*//** Capture/compare 1 generation */ +#define TIM_EGR_CC1G (1 << 1) + +/* UG:*//** Update generation */ +#define TIM_EGR_UG (1 << 0) +/**@}*/ + +/* --- TIMx_CCMR1 values --------------------------------------------------- */ + +/* --- Output compare mode --- */ + +/* OC2CE: Output compare 2 clear enable */ +#define TIM_CCMR1_OC2CE (1 << 15) + +/* OC2M[2:0]: Output compare 2 mode */ +#define TIM_CCMR1_OC2M_FROZEN (0x0 << 12) +#define TIM_CCMR1_OC2M_ACTIVE (0x1 << 12) +#define TIM_CCMR1_OC2M_INACTIVE (0x2 << 12) +#define TIM_CCMR1_OC2M_TOGGLE (0x3 << 12) +#define TIM_CCMR1_OC2M_FORCE_LOW (0x4 << 12) +#define TIM_CCMR1_OC2M_FORCE_HIGH (0x5 << 12) +#define TIM_CCMR1_OC2M_PWM1 (0x6 << 12) +#define TIM_CCMR1_OC2M_PWM2 (0x7 << 12) +#define TIM_CCMR1_OC2M_MASK (0x7 << 12) + +/* OC2PE: Output compare 2 preload enable */ +#define TIM_CCMR1_OC2PE (1 << 11) + +/* OC2FE: Output compare 2 fast enable */ +#define TIM_CCMR1_OC2FE (1 << 10) + +/* CC2S[1:0]: Capture/compare 2 selection */ +/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in + * TIMx_CCER). */ +#define TIM_CCMR1_CC2S_OUT (0x0 << 8) +#define TIM_CCMR1_CC2S_IN_TI2 (0x1 << 8) +#define TIM_CCMR1_CC2S_IN_TI1 (0x2 << 8) +#define TIM_CCMR1_CC2S_IN_TRC (0x3 << 8) +#define TIM_CCMR1_CC2S_MASK (0x3 << 8) + +/* OC1CE: Output compare 1 clear enable */ +#define TIM_CCMR1_OC1CE (1 << 7) + +/* OC1M[2:0]: Output compare 1 mode */ +#define TIM_CCMR1_OC1M_FROZEN (0x0 << 4) +#define TIM_CCMR1_OC1M_ACTIVE (0x1 << 4) +#define TIM_CCMR1_OC1M_INACTIVE (0x2 << 4) +#define TIM_CCMR1_OC1M_TOGGLE (0x3 << 4) +#define TIM_CCMR1_OC1M_FORCE_LOW (0x4 << 4) +#define TIM_CCMR1_OC1M_FORCE_HIGH (0x5 << 4) +#define TIM_CCMR1_OC1M_PWM1 (0x6 << 4) +#define TIM_CCMR1_OC1M_PWM2 (0x7 << 4) +#define TIM_CCMR1_OC1M_MASK (0x7 << 4) + +/* OC1PE: Output compare 1 preload enable */ +#define TIM_CCMR1_OC1PE (1 << 3) + +/* OC1FE: Output compare 1 fast enable */ +#define TIM_CCMR1_OC1FE (1 << 2) + +/* CC1S[1:0]: Capture/compare 1 selection */ +/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in + * TIMx_CCER). */ +#define TIM_CCMR1_CC1S_OUT (0x0 << 0) +#define TIM_CCMR1_CC1S_IN_TI2 (0x2 << 0) +#define TIM_CCMR1_CC1S_IN_TI1 (0x1 << 0) +#define TIM_CCMR1_CC1S_IN_TRC (0x3 << 0) +#define TIM_CCMR1_CC1S_MASK (0x3 << 0) + +/* --- Input capture mode --- */ + +/* IC2F[3:0]: Input capture 2 filter */ +#define TIM_CCMR1_IC2F_OFF (0x0 << 12) +#define TIM_CCMR1_IC2F_CK_INT_N_2 (0x1 << 12) +#define TIM_CCMR1_IC2F_CK_INT_N_4 (0x2 << 12) +#define TIM_CCMR1_IC2F_CK_INT_N_8 (0x3 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_2_N_6 (0x4 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_2_N_8 (0x5 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_4_N_6 (0x6 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_4_N_8 (0x7 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_8_N_6 (0x8 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_8_N_8 (0x9 << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_16_N_5 (0xA << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_16_N_6 (0xB << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_16_N_8 (0xC << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_32_N_5 (0xD << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_32_N_6 (0xE << 12) +#define TIM_CCMR1_IC2F_DTF_DIV_32_N_8 (0xF << 12) +#define TIM_CCMR1_IC2F_MASK (0xF << 12) + +/* IC2PSC[1:0]: Input capture 2 prescaler */ +#define TIM_CCMR1_IC2PSC_OFF (0x0 << 10) +#define TIM_CCMR1_IC2PSC_2 (0x1 << 10) +#define TIM_CCMR1_IC2PSC_4 (0x2 << 10) +#define TIM_CCMR1_IC2PSC_8 (0x3 << 10) +#define TIM_CCMR1_IC2PSC_MASK (0x3 << 10) + +/* IC1F[3:0]: Input capture 1 filter */ +#define TIM_CCMR1_IC1F_OFF (0x0 << 4) +#define TIM_CCMR1_IC1F_CK_INT_N_2 (0x1 << 4) +#define TIM_CCMR1_IC1F_CK_INT_N_4 (0x2 << 4) +#define TIM_CCMR1_IC1F_CK_INT_N_8 (0x3 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_2_N_6 (0x4 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_2_N_8 (0x5 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_4_N_6 (0x6 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_4_N_8 (0x7 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_8_N_6 (0x8 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_8_N_8 (0x9 << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_16_N_5 (0xA << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_16_N_6 (0xB << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_16_N_8 (0xC << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_32_N_5 (0xD << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_32_N_6 (0xE << 4) +#define TIM_CCMR1_IC1F_DTF_DIV_32_N_8 (0xF << 4) +#define TIM_CCMR1_IC1F_MASK (0xF << 4) + +/* IC1PSC[1:0]: Input capture 1 prescaler */ +#define TIM_CCMR1_IC1PSC_OFF (0x0 << 2) +#define TIM_CCMR1_IC1PSC_2 (0x1 << 2) +#define TIM_CCMR1_IC1PSC_4 (0x2 << 2) +#define TIM_CCMR1_IC1PSC_8 (0x3 << 2) +#define TIM_CCMR1_IC1PSC_MASK (0x3 << 2) + +/* --- TIMx_CCMR2 values --------------------------------------------------- */ + +/* --- Output compare mode --- */ + +/* OC4CE: Output compare 4 clear enable */ +#define TIM_CCMR2_OC4CE (1 << 15) + +/* OC4M[2:0]: Output compare 4 mode */ +#define TIM_CCMR2_OC4M_FROZEN (0x0 << 12) +#define TIM_CCMR2_OC4M_ACTIVE (0x1 << 12) +#define TIM_CCMR2_OC4M_INACTIVE (0x2 << 12) +#define TIM_CCMR2_OC4M_TOGGLE (0x3 << 12) +#define TIM_CCMR2_OC4M_FORCE_LOW (0x4 << 12) +#define TIM_CCMR2_OC4M_FORCE_HIGH (0x5 << 12) +#define TIM_CCMR2_OC4M_PWM1 (0x6 << 12) +#define TIM_CCMR2_OC4M_PWM2 (0x7 << 12) +#define TIM_CCMR2_OC4M_MASK (0x7 << 12) + +/* OC4PE: Output compare 4 preload enable */ +#define TIM_CCMR2_OC4PE (1 << 11) + +/* OC4FE: Output compare 4 fast enable */ +#define TIM_CCMR2_OC4FE (1 << 10) + +/* CC4S[1:0]: Capture/compare 4 selection */ +/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in + * TIMx_CCER). */ +#define TIM_CCMR2_CC4S_OUT (0x0 << 8) +#define TIM_CCMR2_CC4S_IN_TI2 (0x1 << 8) +#define TIM_CCMR2_CC4S_IN_TI1 (0x2 << 8) +#define TIM_CCMR2_CC4S_IN_TRC (0x3 << 8) +#define TIM_CCMR2_CC4S_MASK (0x3 << 8) + +/* OC3CE: Output compare 3 clear enable */ +#define TIM_CCMR2_OC3CE (1 << 7) + +/* OC3M[2:0]: Output compare 3 mode */ +#define TIM_CCMR2_OC3M_FROZEN (0x0 << 4) +#define TIM_CCMR2_OC3M_ACTIVE (0x1 << 4) +#define TIM_CCMR2_OC3M_INACTIVE (0x2 << 4) +#define TIM_CCMR2_OC3M_TOGGLE (0x3 << 4) +#define TIM_CCMR2_OC3M_FORCE_LOW (0x4 << 4) +#define TIM_CCMR2_OC3M_FORCE_HIGH (0x5 << 4) +#define TIM_CCMR2_OC3M_PWM1 (0x6 << 4) +#define TIM_CCMR2_OC3M_PWM2 (0x7 << 4) +#define TIM_CCMR2_OC3M_MASK (0x7 << 4) + +/* OC3PE: Output compare 3 preload enable */ +#define TIM_CCMR2_OC3PE (1 << 3) + +/* OC3FE: Output compare 3 fast enable */ +#define TIM_CCMR2_OC3FE (1 << 2) + +/* CC3S[1:0]: Capture/compare 3 selection */ +/* Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in + * TIMx_CCER). */ +#define TIM_CCMR2_CC3S_OUT (0x0 << 0) +#define TIM_CCMR2_CC3S_IN_TI2 (0x1 << 0) +#define TIM_CCMR2_CC3S_IN_TI1 (0x2 << 0) +#define TIM_CCMR2_CC3S_IN_TRC (0x3 << 0) +#define TIM_CCMR2_CC3S_MASK (0x3 << 0) + +/* --- Input capture mode --- */ + +/* IC4F[3:0]: Input capture 4 filter */ +#define TIM_CCMR2_IC4F_OFF (0x0 << 12) +#define TIM_CCMR2_IC4F_CK_INT_N_2 (0x1 << 12) +#define TIM_CCMR2_IC4F_CK_INT_N_4 (0x2 << 12) +#define TIM_CCMR2_IC4F_CK_INT_N_8 (0x3 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_2_N_6 (0x4 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_2_N_8 (0x5 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_4_N_6 (0x6 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_4_N_8 (0x7 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_8_N_6 (0x8 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_8_N_8 (0x9 << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_16_N_5 (0xA << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_16_N_6 (0xB << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_16_N_8 (0xC << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_32_N_5 (0xD << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_32_N_6 (0xE << 12) +#define TIM_CCMR2_IC4F_DTF_DIV_32_N_8 (0xF << 12) +#define TIM_CCMR2_IC4F_MASK (0xF << 12) + +/* IC4PSC[1:0]: Input capture 4 prescaler */ +#define TIM_CCMR2_IC4PSC_OFF (0x0 << 10) +#define TIM_CCMR2_IC4PSC_2 (0x1 << 10) +#define TIM_CCMR2_IC4PSC_4 (0x2 << 10) +#define TIM_CCMR2_IC4PSC_8 (0x3 << 10) +#define TIM_CCMR2_IC4PSC_MASK (0x3 << 10) + +/* IC3F[3:0]: Input capture 3 filter */ +#define TIM_CCMR2_IC3F_OFF (0x0 << 4) +#define TIM_CCMR2_IC3F_CK_INT_N_2 (0x1 << 4) +#define TIM_CCMR2_IC3F_CK_INT_N_4 (0x2 << 4) +#define TIM_CCMR2_IC3F_CK_INT_N_8 (0x3 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_2_N_6 (0x4 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_2_N_8 (0x5 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_4_N_6 (0x6 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_4_N_8 (0x7 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_8_N_6 (0x8 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_8_N_8 (0x9 << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_16_N_5 (0xA << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_16_N_6 (0xB << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_16_N_8 (0xC << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_32_N_5 (0xD << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_32_N_6 (0xE << 4) +#define TIM_CCMR2_IC3F_DTF_DIV_32_N_8 (0xF << 4) +#define TIM_CCMR2_IC3F_MASK (0xF << 4) + +/* IC3PSC[1:0]: Input capture 3 prescaler */ +#define TIM_CCMR2_IC3PSC_OFF (0x0 << 2) +#define TIM_CCMR2_IC3PSC_2 (0x1 << 2) +#define TIM_CCMR2_IC3PSC_4 (0x2 << 2) +#define TIM_CCMR2_IC3PSC_8 (0x3 << 2) +#define TIM_CCMR2_IC3PSC_MASK (0x3 << 2) + +/* --- TIMx_CCER values ---------------------------------------------------- */ + +/* CC4P: Capture/compare 4 output polarity */ +#define TIM_CCER_CC4P (1 << 13) + +/* CC4E: Capture/compare 4 output enable */ +#define TIM_CCER_CC4E (1 << 12) + +/* CC3NP: Capture/compare 3 complementary output polarity */ +#define TIM_CCER_CC3NP (1 << 11) + +/* CC3NE: Capture/compare 3 complementary output enable */ +#define TIM_CCER_CC3NE (1 << 10) + +/* CC3P: Capture/compare 3 output polarity */ +#define TIM_CCER_CC3P (1 << 9) + +/* CC3E: Capture/compare 3 output enable */ +#define TIM_CCER_CC3E (1 << 8) + +/* CC2NP: Capture/compare 2 complementary output polarity */ +#define TIM_CCER_CC2NP (1 << 7) + +/* CC2NE: Capture/compare 2 complementary output enable */ +#define TIM_CCER_CC2NE (1 << 6) + +/* CC2P: Capture/compare 2 output polarity */ +#define TIM_CCER_CC2P (1 << 5) + +/* CC2E: Capture/compare 2 output enable */ +#define TIM_CCER_CC2E (1 << 4) + +/* CC1NP: Capture/compare 1 complementary output polarity */ +#define TIM_CCER_CC1NP (1 << 3) + +/* CC1NE: Capture/compare 1 complementary output enable */ +#define TIM_CCER_CC1NE (1 << 2) + +/* CC1P: Capture/compare 1 output polarity */ +#define TIM_CCER_CC1P (1 << 1) + +/* CC1E: Capture/compare 1 output enable */ +#define TIM_CCER_CC1E (1 << 0) + +/* --- TIMx_CNT values ----------------------------------------------------- */ + +/* CNT[15:0]: Counter value */ + +/* --- TIMx_PSC values ----------------------------------------------------- */ + +/* PSC[15:0]: Prescaler value */ + +/* --- TIMx_ARR values ----------------------------------------------------- */ + +/* ARR[15:0]: Prescaler value */ + +/* --- TIMx_RCR values ----------------------------------------------------- */ + +/* REP[15:0]: Repetition counter value */ + +/* --- TIMx_CCR1 values ---------------------------------------------------- */ + +/* CCR1[15:0]: Capture/compare 1 value */ + +/* --- TIMx_CCR2 values ---------------------------------------------------- */ + +/* CCR2[15:0]: Capture/compare 2 value */ + +/* --- TIMx_CCR3 values ---------------------------------------------------- */ + +/* CCR3[15:0]: Capture/compare 3 value */ + +/* --- TIMx_CCR4 values ---------------------------------------------------- */ + +/* CCR4[15:0]: Capture/compare 4 value */ + +/* --- TIMx_BDTR values ---------------------------------------------------- */ + +/* MOE: Main output enable */ +#define TIM_BDTR_MOE (1 << 15) + +/* AOE: Automatic output enable */ +#define TIM_BDTR_AOE (1 << 14) + +/* BKP: Break polarity */ +#define TIM_BDTR_BKP (1 << 13) + +/* BKE: Break enable */ +#define TIM_BDTR_BKE (1 << 12) + +/* OSSR: Off-state selection of run mode */ +#define TIM_BDTR_OSSR (1 << 11) + +/* OSSI: Off-state selection of idle mode */ +#define TIM_BDTR_OSSI (1 << 10) + +/* LOCK[1:0]: Lock configuration */ +/****************************************************************************/ +/** @defgroup tim_lock TIM_BDTR_LOCK Timer Lock Values +@ingroup timer_defines + +@{*/ +#define TIM_BDTR_LOCK_OFF (0x0 << 8) +#define TIM_BDTR_LOCK_LEVEL_1 (0x1 << 8) +#define TIM_BDTR_LOCK_LEVEL_2 (0x2 << 8) +#define TIM_BDTR_LOCK_LEVEL_3 (0x3 << 8) +#define TIM_BDTR_LOCK_MASK (0x3 << 8) +/**@}*/ + +/* DTG[7:0]: Dead-time generator set-up */ +#define TIM_BDTR_DTG_MASK 0x00FF + +/* --- TIMx_DCR values ----------------------------------------------------- */ + +/* DBL[4:0]: DMA burst length */ +#define TIM_BDTR_DBL_MASK (0x1F << 8) + +/* DBA[4:0]: DMA base address */ +#define TIM_BDTR_DBA_MASK (0x1F << 0) + +/* --- TIMx_DMAR values ---------------------------------------------------- */ + +/* DMAB[15:0]: DMA register for burst accesses */ + +/* --- TIMx convenience defines -------------------------------------------- */ + +/** Output Compare channel designators */ +enum tim_oc_id { + TIM_OC1 = 0, + TIM_OC1N, + TIM_OC2, + TIM_OC2N, + TIM_OC3, + TIM_OC3N, + TIM_OC4, +}; + +/** Output Compare mode designators */ +enum tim_oc_mode { + TIM_OCM_FROZEN, + TIM_OCM_ACTIVE, + TIM_OCM_INACTIVE, + TIM_OCM_TOGGLE, + TIM_OCM_FORCE_LOW, + TIM_OCM_FORCE_HIGH, + TIM_OCM_PWM1, + TIM_OCM_PWM2, +}; + +/** Input Capture channel designators */ +enum tim_ic_id { + TIM_IC1, + TIM_IC2, + TIM_IC3, + TIM_IC4, +}; + +/** Input Capture input filter. The frequency used to sample the +input and the number of events needed to validate an output transition. + +TIM_IC_CK_INT_N_x No division from the Deadtime and Sampling Clock frequency +(DTF), filter length x +TIM_IC_DTF_DIV_y_N_x Division by y from the DTF, filter length x + */ +enum tim_ic_filter { + TIM_IC_OFF, + TIM_IC_CK_INT_N_2, + TIM_IC_CK_INT_N_4, + TIM_IC_CK_INT_N_8, + TIM_IC_DTF_DIV_2_N_6, + TIM_IC_DTF_DIV_2_N_8, + TIM_IC_DTF_DIV_4_N_6, + TIM_IC_DTF_DIV_4_N_8, + TIM_IC_DTF_DIV_8_N_6, + TIM_IC_DTF_DIV_8_N_8, + TIM_IC_DTF_DIV_16_N_5, + TIM_IC_DTF_DIV_16_N_6, + TIM_IC_DTF_DIV_16_N_8, + TIM_IC_DTF_DIV_32_N_5, + TIM_IC_DTF_DIV_32_N_6, + TIM_IC_DTF_DIV_32_N_8, +}; + +/** Input Capture input prescaler. + +TIM_IC_PSC_x Input capture is done every x events*/ +enum tim_ic_psc { + TIM_IC_PSC_OFF, + TIM_IC_PSC_2, + TIM_IC_PSC_4, + TIM_IC_PSC_8, +}; + +/** Input Capture input source. + +The direction of the channel (input/output) as well as the input used. + */ +enum tim_ic_input { + TIM_IC_OUT = 0, + TIM_IC_IN_TI1 = 1, + TIM_IC_IN_TI2 = 2, + TIM_IC_IN_TRC = 3, + TIM_IC_IN_TI3 = 5, + TIM_IC_IN_TI4 = 6, +}; + +/** Slave external trigger polarity */ +enum tim_et_pol { + TIM_ET_RISING, + TIM_ET_FALLING, +}; + +/* --- TIM function prototypes --------------------------------------------- */ + +BEGIN_DECLS + +void timer_reset(uint32_t timer_peripheral); +void timer_enable_irq(uint32_t timer_peripheral, uint32_t irq); +void timer_disable_irq(uint32_t timer_peripheral, uint32_t irq); +bool timer_interrupt_source(uint32_t timer_peripheral, uint32_t flag); +bool timer_get_flag(uint32_t timer_peripheral, uint32_t flag); +void timer_clear_flag(uint32_t timer_peripheral, uint32_t flag); +void timer_set_mode(uint32_t timer_peripheral, uint32_t clock_div, + uint32_t alignment, uint32_t direction); +void timer_set_clock_division(uint32_t timer_peripheral, uint32_t clock_div); +void timer_enable_preload(uint32_t timer_peripheral); +void timer_disable_preload(uint32_t timer_peripheral); +void timer_set_alignment(uint32_t timer_peripheral, uint32_t alignment); +void timer_direction_up(uint32_t timer_peripheral); +void timer_direction_down(uint32_t timer_peripheral); +void timer_one_shot_mode(uint32_t timer_peripheral); +void timer_continuous_mode(uint32_t timer_peripheral); +void timer_update_on_any(uint32_t timer_peripheral); +void timer_update_on_overflow(uint32_t timer_peripheral); +void timer_enable_update_event(uint32_t timer_peripheral); +void timer_disable_update_event(uint32_t timer_peripheral); +void timer_enable_counter(uint32_t timer_peripheral); +void timer_disable_counter(uint32_t timer_peripheral); +void timer_set_output_idle_state(uint32_t timer_peripheral, uint32_t outputs); +void timer_reset_output_idle_state(uint32_t timer_peripheral, uint32_t outputs); +void timer_set_ti1_ch123_xor(uint32_t timer_peripheral); +void timer_set_ti1_ch1(uint32_t timer_peripheral); +void timer_set_master_mode(uint32_t timer_peripheral, uint32_t mode); +void timer_set_dma_on_compare_event(uint32_t timer_peripheral); +void timer_set_dma_on_update_event(uint32_t timer_peripheral); +void timer_enable_compare_control_update_on_trigger(uint32_t timer_peripheral); +void timer_disable_compare_control_update_on_trigger(uint32_t timer_peripheral); +void timer_enable_preload_complementry_enable_bits(uint32_t timer_peripheral); +void timer_disable_preload_complementry_enable_bits(uint32_t timer_peripheral); +void timer_set_prescaler(uint32_t timer_peripheral, uint32_t value); +void timer_set_repetition_counter(uint32_t timer_peripheral, uint32_t value); +void timer_set_period(uint32_t timer_peripheral, uint32_t period); +void timer_enable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id); +void timer_disable_oc_clear(uint32_t timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_fast_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_slow_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id, + enum tim_oc_mode oc_mode); +void timer_enable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id); +void timer_disable_oc_preload(uint32_t timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_polarity_high(uint32_t timer_peripheral, + enum tim_oc_id oc_id); +void timer_set_oc_polarity_low(uint32_t timer_peripheral, enum tim_oc_id oc_id); +void timer_enable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id); +void timer_disable_oc_output(uint32_t timer_peripheral, enum tim_oc_id oc_id); +void timer_set_oc_idle_state_set(uint32_t timer_peripheral, + enum tim_oc_id oc_id); +void timer_set_oc_idle_state_unset(uint32_t timer_peripheral, + enum tim_oc_id oc_id); +void timer_set_oc_value(uint32_t timer_peripheral, enum tim_oc_id oc_id, + uint32_t value); +void timer_enable_break_main_output(uint32_t timer_peripheral); +void timer_disable_break_main_output(uint32_t timer_peripheral); +void timer_enable_break_automatic_output(uint32_t timer_peripheral); +void timer_disable_break_automatic_output(uint32_t timer_peripheral); +void timer_set_break_polarity_high(uint32_t timer_peripheral); +void timer_set_break_polarity_low(uint32_t timer_peripheral); +void timer_enable_break(uint32_t timer_peripheral); +void timer_disable_break(uint32_t timer_peripheral); +void timer_set_enabled_off_state_in_run_mode(uint32_t timer_peripheral); +void timer_set_disabled_off_state_in_run_mode(uint32_t timer_peripheral); +void timer_set_enabled_off_state_in_idle_mode(uint32_t timer_peripheral); +void timer_set_disabled_off_state_in_idle_mode(uint32_t timer_peripheral); +void timer_set_break_lock(uint32_t timer_peripheral, uint32_t lock); +void timer_set_deadtime(uint32_t timer_peripheral, uint32_t deadtime); +void timer_generate_event(uint32_t timer_peripheral, uint32_t event); +uint32_t timer_get_counter(uint32_t timer_peripheral); +void timer_set_counter(uint32_t timer_peripheral, uint32_t count); + +void timer_ic_set_filter(uint32_t timer, enum tim_ic_id ic, + enum tim_ic_filter flt); +void timer_ic_set_prescaler(uint32_t timer, enum tim_ic_id ic, + enum tim_ic_psc psc); +void timer_ic_set_input(uint32_t timer, enum tim_ic_id ic, + enum tim_ic_input in); +void timer_ic_enable(uint32_t timer, enum tim_ic_id ic); +void timer_ic_disable(uint32_t timer, enum tim_ic_id ic); + +void timer_slave_set_filter(uint32_t timer, enum tim_ic_filter flt); +void timer_slave_set_prescaler(uint32_t timer, enum tim_ic_psc psc); +void timer_slave_set_polarity(uint32_t timer, enum tim_et_pol pol); +void timer_slave_set_mode(uint32_t timer, uint8_t mode); +void timer_slave_set_trigger(uint32_t timer, uint8_t trigger); + +END_DECLS + +#endif +/** @cond */ +#else +#warning "timer_common_all.h should not be included directly, only via timer.h" +#endif +/** @endcond */ +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/common/timer_common_f24.h b/libopencm3/include/libopencm3/stm32/common/timer_common_f24.h new file mode 100644 index 0000000..67ba593 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/timer_common_f24.h @@ -0,0 +1,114 @@ +/** @addtogroup timer_defines + +@author @htmlonly © @endhtmlonly 2011 Fergus Noble + +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA TIMER.H +The order of header inclusion is important. timer.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_TIMER_H +/** @endcond */ +#ifndef LIBOPENCM3_TIMER_COMMON_F24_H +#define LIBOPENCM3_TIMER_COMMON_F24_H + +#include + +/* + * TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide: + * CNT, ARR, CCR1, CCR2, CCR3, CCR4 + */ + +/* Timer 2/5 option register (TIMx_OR) */ +#define TIM_OR(tim_base) MMIO32(tim_base + 0x50) +#define TIM2_OR TIM_OR(TIM2) +#define TIM5_OR TIM_OR(TIM5) + +/* --- TIM2_OR values ---------------------------------------------------- */ + +/* ITR1_RMP */ +/****************************************************************************/ +/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal +Trigger 1 Remap + +Only available in F2 and F4 series. +@ingroup timer_defines + +@{*/ +/** Internal Trigger 1 remapped to timer 8 trigger out */ +#define TIM2_OR_ITR1_RMP_TIM8_TRGOU (0x0 << 10) +/** Internal Trigger 1 remapped to PTP trigger out */ +#define TIM2_OR_ITR1_RMP_PTP (0x1 << 10) +/** Internal Trigger 1 remapped to USB OTG FS SOF */ +#define TIM2_OR_ITR1_RMP_OTG_FS_SOF (0x2 << 10) +/** Internal Trigger 1 remapped to USB OTG HS SOF */ +#define TIM2_OR_ITR1_RMP_OTG_HS_SOF (0x3 << 10) +/**@}*/ +#define TIM2_OR_ITR1_RMP_MASK (0x3 << 10) + +/* --- TIM5_OR values ---------------------------------------------------- */ + +/* ITR4_RMP */ +/****************************************************************************/ +/** @defgroup tim5_opt_trigger_remap TIM5_OR Timer 5 Option Register Internal Trigger 4 Remap + +Only available in F2 and F4 series. +@ingroup timer_defines + +@{*/ +/** Internal Trigger 4 remapped to GPIO (see reference manual) */ +#define TIM5_OR_TI4_RMP_GPIO (0x0 << 6) +/** Internal Trigger 4 remapped to LSI internal clock */ +#define TIM5_OR_TI4_RMP_LSI (0x1 << 6) +/** Internal Trigger 4 remapped to LSE internal clock */ +#define TIM5_OR_TI4_RMP_LSE (0x2 << 6) +/** Internal Trigger 4 remapped to RTC output event */ +#define TIM5_OR_TI4_RMP_RTC (0x3 << 6) +/**@}*/ +#define TIM5_OR_TI4_RMP_MASK (0x3 << 6) + +/** Input Capture input polarity */ +enum tim_ic_pol { + TIM_IC_RISING, + TIM_IC_FALLING, + TIM_IC_BOTH, +}; + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void timer_set_option(uint32_t timer_peripheral, uint32_t option); +void timer_ic_set_polarity(uint32_t timer, enum tim_ic_id ic, + enum tim_ic_pol pol); + +END_DECLS + +#endif +/** @cond */ +#else +#warning "timer_common_f24.h should not be included directly, only via timer.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/common/usart_common_all.h b/libopencm3/include/libopencm3/stm32/common/usart_common_all.h new file mode 100644 index 0000000..6eafdfd --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/usart_common_all.h @@ -0,0 +1,141 @@ +/** @addtogroup usart_defines + * + * @author @htmlonly © @endhtmlonly 2009 Uwe Hermann + * + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H +The order of header inclusion is important. usart.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#if defined(LIBOPENCM3_USART_H) +/** @endcond */ +#ifndef LIBOPENCM3_USART_COMMON_ALL_H +#define LIBOPENCM3_USART_COMMON_ALL_H + +/* --- Convenience macros -------------------------------------------------- */ + +/****************************************************************************/ +/** @defgroup usart_reg_base USART register base addresses +@ingroup STM32F_usart_defines + +@{*/ +#define USART1 USART1_BASE +#define USART2 USART2_BASE +#define USART3 USART3_BASE +/**@}*/ +#define UART4 UART4_BASE +#define UART5 UART5_BASE + +/* --- Convenience defines ------------------------------------------------- */ + +/* CR1_PCE / CR1_PS combined values */ +/****************************************************************************/ +/** @defgroup usart_cr1_parity USART Parity Selection +@ingroup STM32F_usart_defines + +@{*/ +#define USART_PARITY_NONE 0x00 +#define USART_PARITY_EVEN USART_CR1_PCE +#define USART_PARITY_ODD (USART_CR1_PS | USART_CR1_PCE) +/**@}*/ +#define USART_PARITY_MASK (USART_CR1_PS | USART_CR1_PCE) + +/* CR1_TE/CR1_RE combined values */ +/****************************************************************************/ +/** @defgroup usart_cr1_mode USART Tx/Rx Mode Selection +@ingroup STM32F_usart_defines + +@{*/ +#define USART_MODE_RX USART_CR1_RE +#define USART_MODE_TX USART_CR1_TE +#define USART_MODE_TX_RX (USART_CR1_RE | USART_CR1_TE) +/**@}*/ +#define USART_MODE_MASK (USART_CR1_RE | USART_CR1_TE) + +/****************************************************************************/ +/** @defgroup usart_cr2_stopbits USART Stop Bit Selection +@ingroup STM32F_usart_defines + +@{*/ +#define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */ +#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* .5 stop bit */ +#define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */ +#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bit*/ +/**@}*/ + +/* CR3_CTSE/CR3_RTSE combined values */ +/****************************************************************************/ +/** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection +@ingroup STM32F_usart_defines + +@{*/ +#define USART_FLOWCONTROL_NONE 0x00 +#define USART_FLOWCONTROL_RTS USART_CR3_RTSE +#define USART_FLOWCONTROL_CTS USART_CR3_CTSE +#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) +/**@}*/ +#define USART_FLOWCONTROL_MASK (USART_CR3_RTSE | USART_CR3_CTSE) + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void usart_set_baudrate(uint32_t usart, uint32_t baud); +void usart_set_databits(uint32_t usart, uint32_t bits); +void usart_set_stopbits(uint32_t usart, uint32_t stopbits); +void usart_set_parity(uint32_t usart, uint32_t parity); +void usart_set_mode(uint32_t usart, uint32_t mode); +void usart_set_flow_control(uint32_t usart, uint32_t flowcontrol); +void usart_enable(uint32_t usart); +void usart_disable(uint32_t usart); +void usart_send(uint32_t usart, uint16_t data); +uint16_t usart_recv(uint32_t usart); +void usart_wait_send_ready(uint32_t usart); +void usart_wait_recv_ready(uint32_t usart); +void usart_send_blocking(uint32_t usart, uint16_t data); +uint16_t usart_recv_blocking(uint32_t usart); +void usart_enable_rx_dma(uint32_t usart); +void usart_disable_rx_dma(uint32_t usart); +void usart_enable_tx_dma(uint32_t usart); +void usart_disable_tx_dma(uint32_t usart); +void usart_enable_rx_interrupt(uint32_t usart); +void usart_disable_rx_interrupt(uint32_t usart); +void usart_enable_tx_interrupt(uint32_t usart); +void usart_disable_tx_interrupt(uint32_t usart); +void usart_enable_error_interrupt(uint32_t usart); +void usart_disable_error_interrupt(uint32_t usart); +bool usart_get_flag(uint32_t usart, uint32_t flag); +bool usart_get_interrupt_source(uint32_t usart, uint32_t flag); + +END_DECLS + +#endif +/** @cond */ +#else +#warning "usart_common_all.h should not be included directly, only via usart.h" +#endif +/** @endcond */ +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/common/usart_common_f124.h b/libopencm3/include/libopencm3/stm32/common/usart_common_f124.h new file mode 100644 index 0000000..0bb8514 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/usart_common_f124.h @@ -0,0 +1,288 @@ +/** @addtogroup usart_defines + +@author @htmlonly © @endhtmlonly 2009 Uwe Hermann + +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H +The order of header inclusion is important. usart.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#if defined(LIBOPENCM3_USART_H) +/** @endcond */ +#ifndef LIBOPENCM3_USART_COMMON_F124_H +#define LIBOPENCM3_USART_COMMON_F124_H + +#include + +/* --- USART registers ----------------------------------------------------- */ + +/* Status register (USARTx_SR) */ +#define USART_SR(usart_base) MMIO32(usart_base + 0x00) +#define USART1_SR USART_SR(USART1_BASE) +#define USART2_SR USART_SR(USART2_BASE) +#define USART3_SR USART_SR(USART3_BASE) +#define UART4_SR USART_SR(UART4_BASE) +#define UART5_SR USART_SR(UART5_BASE) + +/* Data register (USARTx_DR) */ +#define USART_DR(usart_base) MMIO32(usart_base + 0x04) +#define USART1_DR USART_DR(USART1_BASE) +#define USART2_DR USART_DR(USART2_BASE) +#define USART3_DR USART_DR(USART3_BASE) +#define UART4_DR USART_DR(UART4_BASE) +#define UART5_DR USART_DR(UART5_BASE) + +/* Baud rate register (USARTx_BRR) */ +#define USART_BRR(usart_base) MMIO32(usart_base + 0x08) +#define USART1_BRR USART_BRR(USART1_BASE) +#define USART2_BRR USART_BRR(USART2_BASE) +#define USART3_BRR USART_BRR(USART3_BASE) +#define UART4_BRR USART_BRR(UART4_BASE) +#define UART5_BRR USART_BRR(UART5_BASE) + +/* Control register 1 (USARTx_CR1) */ +#define USART_CR1(usart_base) MMIO32(usart_base + 0x0c) +#define USART1_CR1 USART_CR1(USART1_BASE) +#define USART2_CR1 USART_CR1(USART2_BASE) +#define USART3_CR1 USART_CR1(USART3_BASE) +#define UART4_CR1 USART_CR1(UART4_BASE) +#define UART5_CR1 USART_CR1(UART5_BASE) + +/* Control register 2 (USARTx_CR2) */ +#define USART_CR2(usart_base) MMIO32(usart_base + 0x10) +#define USART1_CR2 USART_CR2(USART1_BASE) +#define USART2_CR2 USART_CR2(USART2_BASE) +#define USART3_CR2 USART_CR2(USART3_BASE) +#define UART4_CR2 USART_CR2(UART4_BASE) +#define UART5_CR2 USART_CR2(UART5_BASE) + +/* Control register 3 (USARTx_CR3) */ +#define USART_CR3(usart_base) MMIO32(usart_base + 0x14) +#define USART1_CR3 USART_CR3(USART1_BASE) +#define USART2_CR3 USART_CR3(USART2_BASE) +#define USART3_CR3 USART_CR3(USART3_BASE) +#define UART4_CR3 USART_CR3(UART4_BASE) +#define UART5_CR3 USART_CR3(UART5_BASE) + +/* Guard time and prescaler register (USARTx_GTPR) */ +#define USART_GTPR(usart_base) MMIO32(usart_base + 0x18) +#define USART1_GTPR USART_GTPR(USART1_BASE) +#define USART2_GTPR USART_GTPR(USART2_BASE) +#define USART3_GTPR USART_GTPR(USART3_BASE) +#define UART4_GTPR USART_GTPR(UART4_BASE) +#define UART5_GTPR USART_GTPR(UART5_BASE) + +/* --- USART_SR values ----------------------------------------------------- */ +/****************************************************************************/ +/** @defgroup usart_sr_flags USART Status register Flags +@ingroup STM32F_usart_defines + +@{*/ + +/** CTS: CTS flag */ +/** @note: undefined on UART4 and UART5 */ +#define USART_SR_CTS (1 << 9) + +/** LBD: LIN break detection flag */ +#define USART_SR_LBD (1 << 8) + +/** TXE: Transmit data buffer empty */ +#define USART_SR_TXE (1 << 7) + +/** TC: Transmission complete */ +#define USART_SR_TC (1 << 6) + +/** RXNE: Read data register not empty */ +#define USART_SR_RXNE (1 << 5) + +/** IDLE: Idle line detected */ +#define USART_SR_IDLE (1 << 4) + +/** ORE: Overrun error */ +#define USART_SR_ORE (1 << 3) + +/** NE: Noise error flag */ +#define USART_SR_NE (1 << 2) + +/** FE: Framing error */ +#define USART_SR_FE (1 << 1) + +/** PE: Parity error */ +#define USART_SR_PE (1 << 0) +/**@}*/ + +/* --- USART_DR values ----------------------------------------------------- */ + +/* USART_DR[8:0]: DR[8:0]: Data value */ +#define USART_DR_MASK 0x1FF + +/* --- USART_BRR values ---------------------------------------------------- */ + +/* DIV_Mantissa[11:0]: mantissa of USARTDIV */ +#define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4) +/* DIV_Fraction[3:0]: fraction of USARTDIV */ +#define USART_BRR_DIV_FRACTION_MASK 0xF + +/* --- USART_CR1 values ---------------------------------------------------- */ + +/* UE: USART enable */ +#define USART_CR1_UE (1 << 13) + +/* M: Word length */ +#define USART_CR1_M (1 << 12) + +/* WAKE: Wakeup method */ +#define USART_CR1_WAKE (1 << 11) + +/* PCE: Parity control enable */ +#define USART_CR1_PCE (1 << 10) + +/* PS: Parity selection */ +#define USART_CR1_PS (1 << 9) + +/* PEIE: PE interrupt enable */ +#define USART_CR1_PEIE (1 << 8) + +/* TXEIE: TXE interrupt enable */ +#define USART_CR1_TXEIE (1 << 7) + +/* TCIE: Transmission complete interrupt enable */ +#define USART_CR1_TCIE (1 << 6) + +/* RXNEIE: RXNE interrupt enable */ +#define USART_CR1_RXNEIE (1 << 5) + +/* IDLEIE: IDLE interrupt enable */ +#define USART_CR1_IDLEIE (1 << 4) + +/* TE: Transmitter enable */ +#define USART_CR1_TE (1 << 3) + +/* RE: Receiver enable */ +#define USART_CR1_RE (1 << 2) + +/* RWU: Receiver wakeup */ +#define USART_CR1_RWU (1 << 1) + +/* SBK: Send break */ +#define USART_CR1_SBK (1 << 0) + +/* --- USART_CR2 values ---------------------------------------------------- */ + +/* LINEN: LIN mode enable */ +#define USART_CR2_LINEN (1 << 14) + +/* STOP[13:12]: STOP bits */ +#define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */ +#define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */ +#define USART_CR2_STOPBITS_2 (0x02 << 12) /* 2 stop bits */ +#define USART_CR2_STOPBITS_1_5 (0x03 << 12) /* 1.5 stop bits */ +#define USART_CR2_STOPBITS_MASK (0x03 << 12) +#define USART_CR2_STOPBITS_SHIFT 12 + +/* CLKEN: Clock enable */ +#define USART_CR2_CLKEN (1 << 11) + +/* CPOL: Clock polarity */ +#define USART_CR2_CPOL (1 << 10) + +/* CPHA: Clock phase */ +#define USART_CR2_CPHA (1 << 9) + +/* LBCL: Last bit clock pulse */ +#define USART_CR2_LBCL (1 << 8) + +/* LBDIE: LIN break detection interrupt enable */ +#define USART_CR2_LBDIE (1 << 6) + +/* LBDL: LIN break detection length */ +#define USART_CR2_LBDL (1 << 5) + +/* ADD[3:0]: Address of the usart node */ +#define USART_CR2_ADD_MASK 0xF + +/* --- USART_CR3 values ---------------------------------------------------- */ + +/* CTSIE: CTS interrupt enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_CTSIE (1 << 10) + +/* CTSE: CTS enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_CTSE (1 << 9) + +/* RTSE: RTS enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_RTSE (1 << 8) + +/* DMAT: DMA enable transmitter */ +/* Note: N/A on UART5 */ +#define USART_CR3_DMAT (1 << 7) + +/* DMAR: DMA enable receiver */ +/* Note: N/A on UART5 */ +#define USART_CR3_DMAR (1 << 6) + +/* SCEN: Smartcard mode enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_SCEN (1 << 5) + +/* NACK: Smartcard NACK enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_NACK (1 << 4) + +/* HDSEL: Half-duplex selection */ +#define USART_CR3_HDSEL (1 << 3) + +/* IRLP: IrDA low-power */ +#define USART_CR3_IRLP (1 << 2) + +/* IREN: IrDA mode enable */ +#define USART_CR3_IREN (1 << 1) + +/* EIE: Error interrupt enable */ +#define USART_CR3_EIE (1 << 0) + +/* --- USART_GTPR values --------------------------------------------------- */ + +/* GT[7:0]: Guard time value */ +/* Note: N/A on UART4 & UART5 */ +#define USART_GTPR_GT_MASK (0xFF << 8) + +/* PSC[7:0]: Prescaler value */ +/* Note: N/A on UART4/5 */ +#define USART_GTPR_PSC_MASK 0xFF + +/* TODO */ /* Note to Uwe: what needs to be done here? */ + +#endif +/** @cond */ +#else +#warning "usart_common_all.h should not be included directly, only via usart.h" +#endif +/** @endcond */ +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/common/usart_common_f24.h b/libopencm3/include/libopencm3/stm32/common/usart_common_f24.h new file mode 100644 index 0000000..e8d9f7f --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/common/usart_common_f24.h @@ -0,0 +1,98 @@ +/** @addtogroup usart_defines + +@author @htmlonly © @endhtmlonly 2011 Uwe Hermann +@author @htmlonly © @endhtmlonly 2011 Stephen Caudle + +*/ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * Copyright (C) 2011 Stephen Caudle + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H +The order of header inclusion is important. usart.h includes the device +specific memorymap.h header before including this header file.*/ + +/** @cond */ +#ifdef LIBOPENCM3_USART_H +/** @endcond */ +#ifndef LIBOPENCM3_USART_COMMON_F24_H +#define LIBOPENCM3_USART_COMMON_F24_H + +#include + +/* --- Convenience macros -------------------------------------------------- */ + +#define USART6 USART6_BASE +#define UART7 UART7_BASE +#define UART8 UART8_BASE + +/* --- USART registers ----------------------------------------------------- */ + +/* Status register (USARTx_SR) */ +#define USART6_SR USART_SR(USART6_BASE) +#define UART7_SR USART_SR(UART7) +#define UART8_SR USART_SR(UART8) + +/* Data register (USARTx_DR) */ +#define USART6_DR USART_DR(USART6_BASE) +#define UART7_DR USART_DR(UART7) +#define UART8_DR USART_DR(UART8) + +/* Baud rate register (USARTx_BRR) */ +#define USART6_BRR USART_BRR(USART6_BASE) +#define UART7_BRR USART_BRR(UART7) +#define UART8_BRR USART_BRR(UART8) + +/* Control register 1 (USARTx_CR1) */ +#define USART6_CR1 USART_CR1(USART6_BASE) +#define UART7_CR1 USART_CR1(UART7) +#define UART8_CR1 USART_CR1(UART8) + +/* Control register 2 (USARTx_CR2) */ +#define USART6_CR2 USART_CR2(USART6_BASE) +#define UART7_CR2 USART_CR2(UART7) +#define UART8_CR2 USART_CR2(UART8) + +/* Control register 3 (USARTx_CR3) */ +#define USART6_CR3 USART_CR3(USART6_BASE) +#define UART7_CR3 USART_CR3(UART7) +#define UART8_CR3 USART_CR3(UART8) + +/* Guard time and prescaler register (USARTx_GTPR) */ +#define USART6_GTPR USART_GTPR(USART6_BASE) +#define UART7_GTPR USART_GTPR(UART7) +#define UART8_GTPR USART_GTPR(UART8) + +/* --- USART_CR1 values ---------------------------------------------------- */ + +/* OVER8: Oversampling mode */ +#define USART_CR1_OVER8 (1 << 15) + +/* --- USART_CR3 values ---------------------------------------------------- */ + +/* ONEBIT: One sample bit method enable */ +#define USART_CR3_ONEBIT (1 << 11) + +#endif +/** @cond */ +#else +#warning "usart_common_f24.h should not be included directly, only via usart.h" +#endif +/** @endcond */ + diff --git a/libopencm3/include/libopencm3/stm32/comparator.h b/libopencm3/include/libopencm3/stm32/comparator.h new file mode 100644 index 0000000..b372e22 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/comparator.h @@ -0,0 +1,28 @@ +/* This provides unification of code over STM32F subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#if defined(STM32F0) +# include +#else +# error "stm32 family not defined." +#endif + diff --git a/libopencm3/include/libopencm3/stm32/crc.h b/libopencm3/include/libopencm3/stm32/crc.h new file mode 100644 index 0000000..469124f --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/crc.h @@ -0,0 +1,38 @@ +/* This provides unification of code over STM32F subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#if defined(STM32F0) +# include +#elif defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F3) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." +#endif + diff --git a/libopencm3/include/libopencm3/stm32/crs.h b/libopencm3/include/libopencm3/stm32/crs.h new file mode 100644 index 0000000..d75a624 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/crs.h @@ -0,0 +1,28 @@ +/* This provides unification of code over STM32F subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#if defined(STM32F0) +# include +#else +# error "stm32 family not defined." +#endif + diff --git a/libopencm3/include/libopencm3/stm32/crypto.h b/libopencm3/include/libopencm3/stm32/crypto.h new file mode 100644 index 0000000..575032d --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/crypto.h @@ -0,0 +1,30 @@ +/* This provides unification of code over STM32F subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#if defined(STM32F2) +# include +#elif defined(STM32F4) +# include +#else +# error "CRYPTO processor is supported only" \ + "in stm32f2xx, stm32f41xx, stm32f42xx and stm32f43xx family." +#endif diff --git a/libopencm3/include/libopencm3/stm32/dac.h b/libopencm3/include/libopencm3/stm32/dac.h new file mode 100644 index 0000000..0e18605 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/dac.h @@ -0,0 +1,38 @@ +/* This provides unification of code over STM32F subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#if defined(STM32F0) +# include +#elif defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F3) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." +#endif + diff --git a/libopencm3/include/libopencm3/stm32/dbgmcu.h b/libopencm3/include/libopencm3/stm32/dbgmcu.h new file mode 100644 index 0000000..cb4c5f6 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/dbgmcu.h @@ -0,0 +1,72 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_STM32_DBGMCU_H +#define LIBOPENCM3_STM32_DBGMCU_H + +#include +#include + +/* --- DBGMCU registers ---------------------------------------------------- */ + +/* Debug MCU IDCODE register (DBGMCU_IDCODE) */ +#define DBGMCU_IDCODE MMIO32(DBGMCU_BASE + 0x00) + +/* Debug MCU configuration register (DBGMCU_CR) */ +/* Note: Only 32bit access supported. */ +#define DBGMCU_CR MMIO32(DBGMCU_BASE + 0x04) + +/* --- DBGMCU_IDCODE values ------------------------------------------------ */ + +#define DBGMCU_IDCODE_DEV_ID_MASK 0x00000fff +#define DBGMCU_IDCODE_REV_ID_MASK 0xffff0000 + +/* --- DBGMCU_CR values ---------------------------------------------------- */ + +/* Bit 31: Reserved. */ + +/* Bits [24:22]: Reserved, must be kept cleared. */ + +/* Bits [4:3]: Reserved. */ + +#define DBGMCU_CR_SLEEP 0x00000001 +#define DBGMCU_CR_STOP 0x00000002 +#define DBGMCU_CR_STANDBY 0x00000004 +#define DBGMCU_CR_TRACE_IOEN 0x00000020 +#define DBGMCU_CR_TRACE_MODE_MASK 0x000000C0 +#define DBGMCU_CR_TRACE_MODE_ASYNC 0x00000000 +#define DBGMCU_CR_TRACE_MODE_SYNC_1 0x00000040 +#define DBGMCU_CR_TRACE_MODE_SYNC_2 0x00000080 +#define DBGMCU_CR_TRACE_MODE_SYNC_4 0x000000C0 +#define DBGMCU_CR_IWDG_STOP 0x00000100 +#define DBGMCU_CR_WWDG_STOP 0x00000200 +#define DBGMCU_CR_TIM1_STOP 0x00000400 +#define DBGMCU_CR_TIM2_STOP 0x00000800 +#define DBGMCU_CR_TIM3_STOP 0x00001000 +#define DBGMCU_CR_TIM4_STOP 0x00002000 +#define DBGMCU_CR_CAN1_STOP 0x00004000 +#define DBGMCU_CR_I2C1_SMBUS_TIMEOUT 0x00008000 +#define DBGMCU_CR_I2C2_SMBUS_TIMEOUT 0x00010000 +#define DBGMCU_CR_TIM8_STOP 0x00020000 +#define DBGMCU_CR_TIM5_STOP 0x00040000 +#define DBGMCU_CR_TIM6_STOP 0x00080000 +#define DBGMCU_CR_TIM7_STOP 0x00100000 +#define DBGMCU_CR_CAN2_STOP 0x00200000 + +#endif diff --git a/libopencm3/include/libopencm3/stm32/desig.h b/libopencm3/include/libopencm3/stm32/desig.h new file mode 100644 index 0000000..53d0cf3 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/desig.h @@ -0,0 +1,57 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DESIG_H +#define LIBOPENCM3_DESIG_H + +#include +#include + +/* --- Device Electronic Signature -------------------------------- */ + +/* Flash size register */ +#define DESIG_FLASH_SIZE MMIO16(DESIG_FLASH_SIZE_BASE + 0x00) + +BEGIN_DECLS + +/** + * Read the on board flash size + * @return flash size in KB + */ +uint16_t desig_get_flash_size(void); + +/** + * Read the full 96 bit unique identifier + * Note: ST specifies that bits 31..16 are _also_ reserved for future use + * @param result pointer to at least 3xuint32_ts (96 bits) + */ +void desig_get_unique_id(uint32_t result[]); + +/** + * Read the full 96 bit unique identifier and return it as a + * zero-terminated string + * @param string memory region to write the result to + 8 @param string_len the size of string in bytes + */ +void desig_get_unique_id_as_string(char *string, + unsigned int string_len); + +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/stm32/dma.h b/libopencm3/include/libopencm3/stm32/dma.h new file mode 100644 index 0000000..dd2880b --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/dma.h @@ -0,0 +1,38 @@ +/* This provides unification of code over STM32F subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#if defined(STM32F0) +# include +#elif defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F3) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." +#endif + diff --git a/libopencm3/include/libopencm3/stm32/ethernet.h b/libopencm3/include/libopencm3/stm32/ethernet.h new file mode 100644 index 0000000..73ff728 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/ethernet.h @@ -0,0 +1,27 @@ +/* This provides unification of code over STM32F subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#if defined(STM32F1) +# include +#elif defined(STM32F4) +# include +#else +# error "stm32 family not defined." +#endif + diff --git a/libopencm3/include/libopencm3/stm32/exti.h b/libopencm3/include/libopencm3/stm32/exti.h new file mode 100644 index 0000000..96cf771 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/exti.h @@ -0,0 +1,40 @@ +/* This provides unification of code over STM32F subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Piotr Esden-Tempski + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#if defined(STM32F0) +# include +#elif defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F3) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f0/adc.h b/libopencm3/include/libopencm3/stm32/f0/adc.h new file mode 100644 index 0000000..c76fefb --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/adc.h @@ -0,0 +1,352 @@ +/** @defgroup adc_defines ADC Defines + * + * @brief Defined Constants and Types for the STM32F0xx Analog to Digital + * Converter + * + * @ingroup STM32F0xx_defines + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_ADC_H +#define LIBOPENCM3_ADC_H + +/*****************************************************************************/ +/* Module definitions */ +/*****************************************************************************/ + +/** @defgroup adc_reg_base ADC register base addresses + * @ingroup adc_defines + * + *@{*/ +#define ADC ADC_BASE +#define ADC1 ADC_BASE/* for API compatibility */ +/**@}*/ + +/*****************************************************************************/ +/* Register definitions */ +/*****************************************************************************/ + +/* ADC interrupt and status register */ +#define ADC_ISR(base) MMIO32(base + 0x00) +#define ADC1_ISR ADC_ISR(ADC) + +/* Interrupt Enable Register */ +#define ADC_IER(base) MMIO32(base + 0x04) +#define ADC1_IER ADC_IER(ADC) + +/* Control Register */ +#define ADC_CR(base) MMIO32(base + 0x08) +#define ADC1_CR ADC_CR(ADC) + + +/* Configuration Register 1 */ +#define ADC_CFGR1(base) MMIO32(base + 0x0C) +#define ADC1_CFGR1 ADC_CFGR1(ADC) + + +/* Configuration Register 2 */ +#define ADC_CFGR2(base) MMIO32(base + 0x10) +#define ADC1_CFGR2 ADC_CFGR2(ADC) + + +/* Sample Time Register 1 */ +#define ADC_SMPR(base) MMIO32(base + 0x14) +#define ADC1_SMPR ADC_SMPR(ADC) + + +/* Watchdog Threshold Register */ +#define ADC_TR(base) MMIO32(base + 0x20) +#define ADC1_TR ADC_TR(ADC) + + +/* Channel Select Register */ +#define ADC_CHSELR(base) MMIO32(base + 0x28) +#define ADC1_CHSELR ADC_CHSELR(ADC) + + +/* Regular Data Register */ +#define ADC_DR(base) MMIO32(base + 0x40) +#define ADC1_DR ADC_DR(ADC) + + +/* Regular Data Register */ +#define ADC_CCR MMIO32(ADC_BASE + 0x308) + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +/* ADC_ISR Values -----------------------------------------------------------*/ + +#define ADC_ISR_AWD (1 << 7) +#define ADC_ISR_OVR (1 << 4) +#define ADC_ISR_EOSEQ (1 << 3) +#define ADC_ISR_EOC (1 << 2) +#define ADC_ISR_EOSMP (1 << 1) +#define ADC_ISR_ADRDY (1 << 0) + +/* ADC_IER Values -----------------------------------------------------------*/ + +#define ADC_IER_AWDIE (1 << 7) +#define ADC_IER_OVRIE (1 << 4) +#define ADC_IER_EOSEQIE (1 << 3) +#define ADC_IER_EOCIE (1 << 2) +#define ADC_IER_EOSMPIE (1 << 1) +#define ADC_IER_ADRDYIE (1 << 0) + +/* ADC_CR Values ------------------------------------------------------------*/ + +#define ADC_CR_ADCAL (1 << 31) +#define ADC_CR_ADSTP (1 << 4) +#define ADC_CR_ADSTART (1 << 2) +#define ADC_CR_ADDIS (1 << 1) +#define ADC_CR_ADEN (1 << 0) + +/* ADC_CFGR1 Values ---------------------------------------------------------*/ + +#define ADC_CFGR1_AWDCH_SHIFT 26 +#define ADC_CFGR1_AWDCH (0x1F << ADC_CFGR1_AWDCH_SHIFT) +#define ADC_CFGR1_AWDCH_VAL(x) ((x) << ADC_CFGR1_AWDCH_SHIFT) + +#define ADC_CFGR1_AWDEN (1 << 23) +#define ADC_CFGR1_AWDSGL (1 << 22) +#define ADC_CFGR1_DISCEN (1 << 16) +#define ADC_CFGR1_AUTOFF (1 << 15) +#define ADC_CFGR1_WAIT (1 << 14) +#define ADC_CFGR1_CONT (1 << 13) +#define ADC_CFGR1_OVRMOD (1 << 12) + +#define ADC_CFGR1_EXTEN_SHIFT 10 +#define ADC_CFGR1_EXTEN (3 << ADC_CFGR1_EXTEN_SHIFT) +#define ADC_CFGR1_EXTEN_DISABLE (0 << ADC_CFGR1_EXTEN_SHIFT) +#define ADC_CFGR1_EXTEN_RISING (1 << ADC_CFGR1_EXTEN_SHIFT) +#define ADC_CFGR1_EXTEN_FALLING (2 << ADC_CFGR1_EXTEN_SHIFT) +#define ADC_CFGR1_EXTEN_BOTH (3 << ADC_CFGR1_EXTEN_SHIFT) + +#define ADC_CFGR1_EXTSEL_SHIFT 6 +#define ADC_CFGR1_EXTSEL (7 << ADC_CFGR1_EXTSEL_SHIFT) +#define ADC_CFGR1_EXTSEL_VAL(x) ((x) << ADC_CFGR1_EXTSEL_SHIFT) + +#define ADC_CFGR1_ALIGN (1 << 5) + +#define ADC_CFGR1_RES_SHIFT 3 +#define ADC_CFGR1_RES (3 << ADC_CFGR1_RES_SHIFT) +#define ADC_CFGR1_RES_12_BIT (0 << ADC_CFGR1_RES_SHIFT) +#define ADC_CFGR1_RES_10_BIT (1 << ADC_CFGR1_RES_SHIFT) +#define ADC_CFGR1_RES_8_BIT (2 << ADC_CFGR1_RES_SHIFT) +#define ADC_CFGR1_RES_6_BIT (3 << ADC_CFGR1_RES_SHIFT) + +#define ADC_CFGR1_SCANDIR (1 << 2) +#define ADC_CFGR1_DMACFG (1 << 1) +#define ADC_CFGR1_DMAEN (1 << 0) + +/* ADC_CFGR2 Values ---------------------------------------------------------*/ + +#define ADC_CFGR2_CKMODE_SHIFT 30 +#define ADC_CFGR2_CKMODE (3 << ADC_CFGR2_CKMODE_SHIFT) +#define ADC_CFGR2_CKMODE_CK_ADC (0 << ADC_CFGR2_CKMODE_SHIFT) +#define ADC_CFGR2_CKMODE_PCLK_DIV2 (1 << ADC_CFGR2_CKMODE_SHIFT) +#define ADC_CFGR2_CKMODE_PCLK_DIV4 (2 << ADC_CFGR2_CKMODE_SHIFT) + +/* ADC_SMPR Values ----------------------------------------------------------*/ + +#define ADC_SMPR_SMP_SHIFT 0 +#define ADC_SMPR_SMP (7 << ADC_SMPR_SMP_SHIFT) +#define ADC_SMPR_SMP_001DOT5 (0 << ADC_SMPR_SMP_SHIFT) +#define ADC_SMPR_SMP_007DOT5 (1 << ADC_SMPR_SMP_SHIFT) +#define ADC_SMPR_SMP_013DOT5 (2 << ADC_SMPR_SMP_SHIFT) +#define ADC_SMPR_SMP_028DOT5 (3 << ADC_SMPR_SMP_SHIFT) +#define ADC_SMPR_SMP_041DOT5 (4 << ADC_SMPR_SMP_SHIFT) +#define ADC_SMPR_SMP_055DOT5 (5 << ADC_SMPR_SMP_SHIFT) +#define ADC_SMPR_SMP_071DOT5 (6 << ADC_SMPR_SMP_SHIFT) +#define ADC_SMPR_SMP_239DOT5 (7 << ADC_SMPR_SMP_SHIFT) + +/* ADC_TR Values ------------------------------------------------------------*/ + +#define ADC_TR_LT_SHIFT 0 +#define ADC_TR_LT (0xFFF << ADC_TR_LT_SHIFT) +#define ADC_TR_LT_VAL(x) ((x) << ADC_TR_LT_SHIFT) + +#define ADC_TR_HT_SHIFT 16 +#define ADC_TR_HT (0xFFF << ADC_TR_HT_SHIFT) +#define ADC_TR_HT_VAL(x) ((x) << ADC_TR_HT_SHIFT) + +/* ADC_CHSELR Values --------------------------------------------------------*/ + +#define ADC_CHSELR_CHSEL(x) (1 << (x)) + +/* ADC_DR Values ------------------------------------------------------------*/ + +#define ADC_DR_DATA 0xFFFF + +/* ADC_CCR Values -----------------------------------------------------------*/ + +#define ADC_CCR_VBATEN (1 << 24) +#define ADC_CCR_TSEN (1 << 23) +#define ADC_CCR_VREFEN (1 << 22) + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +/** @defgroup adc_api_res ADC resolutions + * @ingroup adc_defines + * + *@{*/ +#define ADC_RESOLUTION_12BIT ADC_CFGR1_RES_12_BIT +#define ADC_RESOLUTION_10BIT ADC_CFGR1_RES_10_BIT +#define ADC_RESOLUTION_8BIT ADC_CFGR1_RES_8_BIT +#define ADC_RESOLUTION_6BIT ADC_CFGR1_RES_6_BIT +/**@}*/ + +/** @defgroup adc_api_smptime ADC sampling time + * @ingroup adc_defines + * + *@{*/ +#define ADC_SMPTIME_001DOT5 ADC_SMPR_SMP_001DOT5 +#define ADC_SMPTIME_007DOT5 ADC_SMPR_SMP_007DOT5 +#define ADC_SMPTIME_013DOT5 ADC_SMPR_SMP_013DOT5 +#define ADC_SMPTIME_028DOT5 ADC_SMPR_SMP_028DOT5 +#define ADC_SMPTIME_041DOT5 ADC_SMPR_SMP_041DOT5 +#define ADC_SMPTIME_055DOT5 ADC_SMPR_SMP_055DOT5 +#define ADC_SMPTIME_071DOT5 ADC_SMPR_SMP_071DOT5 +#define ADC_SMPTIME_239DOT5 ADC_SMPR_SMP_239DOT5 +/**@}*/ + +/** @defgroup adc_api_clksource ADC clock source + * @ingroup adc_defines + * + *@{*/ +#define ADC_CLKSOURCE_ADC ADC_CFGR2_CKMODE_CK_ADC +#define ADC_CLKSOURCE_PCLK_DIV2 ADC_CFGR2_CKMODE_PCLK_DIV2 +#define ADC_CLKSOURCE_PCLK_DIV4 ADC_CFGR2_CKMODE_PCLK_DIV4 +/**@}*/ + +/** @defgroup adc_channel ADC Channel Numbers + * @ingroup adc_defines + * + *@{*/ +#define ADC_CHANNEL0 0x00 +#define ADC_CHANNEL1 0x01 +#define ADC_CHANNEL2 0x02 +#define ADC_CHANNEL3 0x03 +#define ADC_CHANNEL4 0x04 +#define ADC_CHANNEL5 0x05 +#define ADC_CHANNEL6 0x06 +#define ADC_CHANNEL7 0x07 +#define ADC_CHANNEL8 0x08 +#define ADC_CHANNEL9 0x09 +#define ADC_CHANNEL10 0x0A +#define ADC_CHANNEL11 0x0B +#define ADC_CHANNEL12 0x0C +#define ADC_CHANNEL13 0x0D +#define ADC_CHANNEL14 0x0E +#define ADC_CHANNEL15 0x0F +#define ADC_CHANNEL_TEMP 0x10 +#define ADC_CHANNEL_VREF 0x11 +#define ADC_CHANNEL_VBAT 0x12 +/**@}*/ + +/** @defgroup adc_api_opmode ADC Operation Modes + * @ingroup adc_defines + * + *@{*/ +enum adc_opmode { + ADC_MODE_SEQUENTIAL, + ADC_MODE_SCAN, + ADC_MODE_SCAN_INFINITE, +}; +/**@}*/ + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + + +BEGIN_DECLS + +/* Operation mode API */ +void adc_set_continuous_conversion_mode(uint32_t adc); +void adc_set_single_conversion_mode(uint32_t adc); +void adc_enable_discontinuous_mode(uint32_t adc); +void adc_disable_discontinuous_mode(uint32_t adc); +void adc_set_operation_mode(uint32_t adc, enum adc_opmode opmode); + +/* Trigger API */ +void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, + uint32_t polarity); +void adc_disable_external_trigger_regular(uint32_t adc); + +/* Conversion API */ +void adc_start_conversion_regular(uint32_t adc); +bool adc_eoc(uint32_t adc); +uint32_t adc_read_regular(uint32_t adc); + +/* Interrupt configuration */ +void adc_enable_watchdog_interrupt(uint32_t adc); +void adc_disable_watchdog_interrupt(uint32_t adc); +bool adc_get_watchdog_flag(uint32_t adc); +void adc_clear_watchdog_flag(uint32_t adc); +void adc_enable_overrun_interrupt(uint32_t adc); +void adc_disable_overrun_interrupt(uint32_t adc); +bool adc_get_overrun_flag(uint32_t adc); +void adc_clear_overrun_flag(uint32_t adc); +void adc_enable_eoc_sequence_interrupt(uint32_t adc); +void adc_disable_eoc_sequence_interrupt(uint32_t adc); +bool adc_get_eoc_sequence_flag(uint32_t adc); +void adc_enable_eoc_interrupt(uint32_t adc); +void adc_disable_eoc_interrupt(uint32_t adc); + +/* Basic configuration */ +void adc_power_off(uint32_t adc); +void adc_power_on(uint32_t adc); +void adc_set_clk_source(uint32_t adc, uint32_t source); +void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]); +void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time); +void adc_set_resolution(uint32_t adc, uint16_t resolution); +void adc_set_left_aligned(uint32_t adc); +void adc_set_right_aligned(uint32_t adc); +void adc_enable_dma(uint32_t adc); +void adc_disable_dma(uint32_t adc); +void adc_enable_temperature_sensor(void); +void adc_disable_temperature_sensor(void); +void adc_enable_vref_sensor(void); +void adc_disable_vref_sensor(void); +void adc_enable_vbat_sensor(void); +void adc_disable_vbat_sensor(void); +void adc_calibrate_start(uint32_t adc); +void adc_calibrate_wait_finish(uint32_t adc); + +/* Analog Watchdog */ +void adc_enable_analog_watchdog_on_all_channels(uint32_t adc); +void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t chan); +void adc_disable_analog_watchdog(uint32_t adc); +void adc_set_watchdog_high_threshold(uint32_t adc, uint8_t threshold); +void adc_set_watchdog_low_threshold(uint32_t adc, uint8_t threshold); + +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/cec.h b/libopencm3/include/libopencm3/stm32/f0/cec.h new file mode 100644 index 0000000..2193a97 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/cec.h @@ -0,0 +1,125 @@ +/** @defgroup CEC_defines CEC Defines + * + * @brief Defined Constants and Types for the STM32F0xx HDMI-CEC + * + * @ingroup STM32F0xx_defines + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CEC_H +#define LIBOPENCM3_CEC_H +/**@{*/ + +/*****************************************************************************/ +/* Module definitions */ +/*****************************************************************************/ + +#define CEC CEC_BASE + +/*****************************************************************************/ +/* Register definitions */ +/*****************************************************************************/ + +#define CEC_CR MMIO32(CEC_BASE + 0x00) +#define CEC_CFGR MMIO32(CEC_BASE + 0x04) +#define CEC_TXDR MMIO32(CEC_BASE + 0x08) +#define CEC_RXDR MMIO32(CEC_BASE + 0x0c) +#define CEC_ISR MMIO32(CEC_BASE + 0x10) +#define CEC_IER MMIO32(CEC_BASE + 0x14) + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +/* CEC_CR Values ------------------------------------------------------------*/ + +#define CEC_CR_TXEOM (1 << 2) +#define CEC_CR_TXSOM (1 << 1) +#define CEC_CR_CECEN (1 << 0) + +/* CEC_CFGR Values ----------------------------------------------------------*/ + +#define CEC_CFGR_LSTN (1 << 31) + +#define CEC_CFGR_OAR_SHIFT 16 +#define CEC_CFGR_OAR (0x3FFF << CEC_CFGR_OAR_SHIFT) + +#define CEC_CFGR_SFTOPT (1 << 8) +#define CEC_CFGR_BRDNOGEN (1 << 7) +#define CEC_CFGR_LBPEGEN (1 << 6) +#define CEC_CFGR_BREGEN (1 << 5) +#define CEC_CFGR_BRESTP (1 << 4) +#define CEC_CFGR_RXTOL (1 << 3) + +#define CEC_CFGR_SFT_SHIFT 0 +#define CEC_CFGR_SFT (7 >> CEC_CFGR_SFT_SHIFT) + +/* CEC_ISR Values -----------------------------------------------------------*/ + +#define CEC_ISR_TXACKE (1 << 12) +#define CEC_ISR_TXERR (1 << 11) +#define CEC_ISR_TXUDR (1 << 10) +#define CEC_ISR_TXEND (1 << 9) +#define CEC_ISR_TXBR (1 << 8) +#define CEC_ISR_ARBLST (1 << 7) +#define CEC_ISR_RXACKE (1 << 6) +#define CEC_ISR_LBPE (1 << 5) +#define CEC_ISR_SBPE (1 << 4) +#define CEC_ISR_BRE (1 << 3) +#define CEC_ISR_RXOVR (1 << 2) +#define CEC_ISR_RXEND (1 << 1) +#define CEC_ISR_RXBR (1 << 0) + +/* CEC_IER Values -----------------------------------------------------------*/ + +#define CEC_IER_TXACKIE (1 << 12) +#define CEC_IER_TXERRIE (1 << 11) +#define CEC_IER_TXUDRIE (1 << 10) +#define CEC_IER_TXENDIE (1 << 9) +#define CEC_IER_TXBRIE (1 << 8) +#define CEC_IER_ARBLSTIE (1 << 7) +#define CEC_IER_RXACKIE (1 << 6) +#define CEC_IER_LBPEIE (1 << 5) +#define CEC_IER_SBPEIE (1 << 4) +#define CEC_IER_BREIE (1 << 3) +#define CEC_IER_RXOVRIE (1 << 2) +#define CEC_IER_RXENDIE (1 << 1) +#define CEC_IER_RXBRIE (1 << 0) + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + +BEGIN_DECLS + +END_DECLS +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/comparator.h b/libopencm3/include/libopencm3/stm32/f0/comparator.h new file mode 100644 index 0000000..78db9cf --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/comparator.h @@ -0,0 +1,124 @@ +/** @defgroup comp_defines COMP Defines + * + * @brief libopencm3 Defined Constants and Types for the STM32F0xx + * Comparator module + * + * @ingroup STM32F0xx_defines + * + * @version 1.0.0 + * + * @date 29 Jun 2013 + * + *LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_COMP_H +#define LIBOPENCM3_COMP_H +/**@{*/ + +/*****************************************************************************/ +/* Module definitions */ +/*****************************************************************************/ + +#define COMP1 0 +#define COMP2 1 + +/*****************************************************************************/ +/* Register definitions */ +/*****************************************************************************/ + +#define COMP_CSR(i) MMIO16(SYSCFG_COMP_BASE + 0x1c + (i)*2) +#define COMP_CSR1 COMP_CSR(COMP1) +#define COMP_CSR2 COMP_CSR(COMP2) + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +/* COMP_CSR Values ----------------------------------------------------------*/ + +#define COMP_CSR_LOCK (1 << 15) +#define COMP_CSR_OUT (1 << 14) + +#define COMP_CSR_HYST_SHIFT 12 +#define COMP_CSR_HYST (3 << COMP_CSR_HYST_SHIFT) +#define COMP_CSR_HYST_NO (0 << COMP_CSR_HYST_SHIFT) +#define COMP_CSR_HYST_LOW (1 << COMP_CSR_HYST_SHIFT) +#define COMP_CSR_HYST_MED (2 << COMP_CSR_HYST_SHIFT) +#define COMP_CSR_HYST_HIGH (3 << COMP_CSR_HYST_SHIFT) + +#define COMP_CSR_POL (1 << 11) + +#define COMP_CSR_OUTSEL_SHIFT 8 +#define COMP_CSR_OUTSEL (7 << COMP_CSR_OUTSEL_SHIFT) +#define COMP_CSR_OUTSEL_NONE (0 << COMP_CSR_OUTSEL_SHIFT) +#define COMP_CSR_OUTSEL_TIM1_BRK (1 << COMP_CSR_OUTSEL_SHIFT) +#define COMP_CSR_OUTSEL_TIM1_IC1 (2 << COMP_CSR_OUTSEL_SHIFT) +#define COMP_CSR_OUTSEL_TIM1_OCRCLR (3 << COMP_CSR_OUTSEL_SHIFT) +#define COMP_CSR_OUTSEL_TIM2_IC4 (4 << COMP_CSR_OUTSEL_SHIFT) +#define COMP_CSR_OUTSEL_TIM2_OCRCLR (5 << COMP_CSR_OUTSEL_SHIFT) +#define COMP_CSR_OUTSEL_TIM3_IC1 (6 << COMP_CSR_OUTSEL_SHIFT) +#define COMP_CSR_OUTSEL_TIM3_OCRCLR (7 << COMP_CSR_OUTSEL_SHIFT) + +#define COMP_CSR_WINDWEN (1 << 23) + +#define COMP_CSR_INSEL_SHIFT 4 +#define COMP_CSR_INSEL (7 << COMP_CSR_INSEL_SHIFT) +#define COMP_CSR_INSEL_1_4_VREFINT (0 << COMP_CSR_INSEL_SHIFT) +#define COMP_CSR_INSEL_2_4_VREFINT (1 << COMP_CSR_INSEL_SHIFT) +#define COMP_CSR_INSEL_3_4_VREFINT (2 << COMP_CSR_INSEL_SHIFT) +#define COMP_CSR_INSEL_4_4_VREFINT (3 << COMP_CSR_INSEL_SHIFT) +#define COMP_CSR_INSEL_VREFINT (3 << COMP_CSR_INSEL_SHIFT) +#define COMP_CSR_INSEL_INM4 (4 << COMP_CSR_INSEL_SHIFT) +#define COMP_CSR_INSEL_INM5 (5 << COMP_CSR_INSEL_SHIFT) +#define COMP_CSR_INSEL_INM6 (6 << COMP_CSR_INSEL_SHIFT) + +#define COMP_CSR_SPEED_SHIFT 2 +#define COMP_CSR_SPEED (3 << COMP_CSR_SPEED_SHIFT) +#define COMP_CSR_SPEED_HIGH (0 << COMP_CSR_SPEED_SHIFT) +#define COMP_CSR_SPEED_MED (1 << COMP_CSR_SPEED_SHIFT) +#define COMP_CSR_SPEED_LOW (2 << COMP_CSR_SPEED_SHIFT) +#define COMP_CSR_SPEED_VERYLOW (3 << COMP_CSR_SPEED_SHIFT) + +#define COMP_CSR_SW1 (1 << 1) +#define COMP_CSR_EN (1 << 0) + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + +BEGIN_DECLS + +void comp_enable(uint8_t id); +void comp_disable(uint8_t id); +void comp_select_input(uint8_t id, uint32_t input); +void comp_select_output(uint8_t id, uint32_t output); +void comp_select_hyst(uint8_t id, uint32_t hyst); +void comp_select_speed(uint8_t id, uint32_t speed); + +END_DECLS +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/crc.h b/libopencm3/include/libopencm3/stm32/f0/crc.h new file mode 100644 index 0000000..34d8a89 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/crc.h @@ -0,0 +1,89 @@ +/** @defgroup crc_defines CRC Defines + * + * @brief libopencm3 Defined Constants and Types for the STM32F1xx CRC + * Generator + * + * @ingroup STM32F0xx_defines + * + * @version 1.0.0 + * + * @date 29 Jun 2013 + * + *LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CRC_H +#define LIBOPENCM3_CRC_H +/**@{*/ + +#include + +/*****************************************************************************/ +/* Module definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Register definitions */ +/*****************************************************************************/ + +/* Initial CRC Value */ +#define CRC_INIT MMIO32(CRC_BASE + 0x10) + +/* CRC Polynomial */ +#define CRC_POL MMIO32(CRC_BASE + 0x14) + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +#define CRC_CR_REV_OUT (1 << 7) + +#define CRC_CR_REV_IN_SHIFT 5 +#define CRC_CR_REV_IN (3 << CRC_CR_REV_IN_SHIFT) +#define CRC_CR_REV_IN_NONE (0 << CRC_CR_REV_IN_SHIFT) +#define CRC_CR_REV_IN_BYTE (1 << CRC_CR_REV_IN_SHIFT) +#define CRC_CR_REV_IN_HALF (2 << CRC_CR_REV_IN_SHIFT) +#define CRC_CR_REV_IN_WORD (3 << CRC_CR_REV_IN_SHIFT) + +#define CRC_CR_POLYSIZE_SHIFT 3 +#define CRC_CR_POLYSIZE (3 << CRC_CR_POLYSIZE_SHIFT) +#define CRC_CR_POLYSIZE_32BIT (0 << CRC_CR_POLYSIZE_SHIFT) +#define CRC_CR_POLYSIZE_16BIT (1 << CRC_CR_POLYSIZE_SHIFT) +#define CRC_CR_POLYSIZE_8BIT (2 << CRC_CR_POLYSIZE_SHIFT) +#define CRC_CR_POLYSIZE_7BIT (3 << CRC_CR_POLYSIZE_SHIFT) + +/* Default polynomial */ +#define CRC_POL_DEFAULT 0x04C11DB7 + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + +BEGIN_DECLS + +END_DECLS +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/crs.h b/libopencm3/include/libopencm3/stm32/f0/crs.h new file mode 100644 index 0000000..b65610c --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/crs.h @@ -0,0 +1,131 @@ +/** @defgroup CRS_defines CRS Defines + * + * @brief Defined Constants and Types for the STM32F0xx Clock Recovery + * + * @ingroup STM32F0xx_defines + * + * @version 1.0.0 + * + * @date 5 Feb 2014 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2014 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CRS_H +#define LIBOPENCM3_CRS_H +/**@{*/ + +/*****************************************************************************/ +/* Module definitions */ +/*****************************************************************************/ + +#define CRS CRS_BASE + +/*****************************************************************************/ +/* Register definitions */ +/*****************************************************************************/ + +#define CRS_CR MMIO32(CRS_BASE + 0x00) +#define CRS_CFGR MMIO32(CRS_BASE + 0x04) +#define CRS_ISR MMIO32(CRS_BASE + 0x08) +#define CRS_ICR MMIO32(CRS_BASE + 0x0c) + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +/* CEC_CR Values ------------------------------------------------------------*/ + +#define CRS_CR_TRIM_SHIFT 8 +#define CRS_CR_TRIM (0x3F << CRS_CR_TRIM_SHIFT) + +#define CRS_CR_SWSYNC (1 << 7) +#define CRS_CR_AUTOTRIMEN (1 << 6) +#define CRS_CR_CEN (1 << 5) +#define CRS_CR_ESYNCIE (1 << 3) +#define CRS_CR_ERRIE (1 << 2) +#define CRS_CR_SYNCWARNIE (1 << 1) +#define CRS_CR_SYNCOKIE (1 << 0) + +/* CEC_CFGR Values ----------------------------------------------------------*/ + +#define CRS_CFGR_SYNCPOL (1 << 31) + +#define CRS_CFGR_SYNCSRC_SHIFT 28 +#define CRS_CFGR_SYNCSRC (3 << CRS_CFGR_SYNCSRC_SHIFT) +#define CRS_CFGR_SYNCSRC_GPIO (0 << CRS_CFGR_SYNCSRC_SHIFT) +#define CRS_CFGR_SYNCSRC_LSE (1 << CRS_CFGR_SYNCSRC_SHIFT) +#define CRS_CFGR_SYNCSRC_USB_SOF (2 << CRS_CFGR_SYNCSRC_SHIFT) + +#define CRS_CFGR_SYNCDIV_SHIFT 24 +#define CRS_CFGR_SYNCDIV (7 << CRS_CFGR_SYNCDIV_SHIFT) +#define CRS_CFGR_SYNCDIV_NODIV (0 << CRS_CFGR_SYNCDIV_SHIFT) +#define CRS_CFGR_SYNCDIV_DIV2 (1 << CRS_CFGR_SYNCDIV_SHIFT) +#define CRS_CFGR_SYNCDIV_DIV4 (2 << CRS_CFGR_SYNCDIV_SHIFT) +#define CRS_CFGR_SYNCDIV_DIV8 (3 << CRS_CFGR_SYNCDIV_SHIFT) +#define CRS_CFGR_SYNCDIV_DIV16 (4 << CRS_CFGR_SYNCDIV_SHIFT) +#define CRS_CFGR_SYNCDIV_DIV32 (5 << CRS_CFGR_SYNCDIV_SHIFT) +#define CRS_CFGR_SYNCDIV_DIV64 (6 << CRS_CFGR_SYNCDIV_SHIFT) +#define CRS_CFGR_SYNCDIV_DIV128 (7 << CRS_CFGR_SYNCDIV_SHIFT) + +#define CRS_CFGR_FELIM_SHIFT 16 +#define CRS_CFGR_FELIM (0xFF << CRS_CFGR_FELIM_SHIFT) +#define CRS_CFGR_FELIM_VAL(x) ((x) << CRS_CFGR_FELIM_SHIFT) + +#define CRS_CFGR_RELOAD_SHIFT 0 +#define CRS_CFGR_RELOAD (0xFFFF << CRS_CFGR_RELOAD_SHIFT) +#define CRS_CFGR_RELOAD_VAL(x) ((x) << CRS_CFGR_RELOAD_SHIFT) + +/* CEC_ISR Values -----------------------------------------------------------*/ + +#define CRS_ISR_FECAP_SHIFT 16 +#define CRS_ISR_FECAP (0xFFFF << CRS_ISR_FECAP_SHIFT) + +#define CRS_ISR_FEDIR (1 << 15) +#define CRS_ISR_TRIMOVF (1 << 10) +#define CRS_ISR_SYNCMISS (1 << 9) +#define CRS_ISR_SYNCERR (1 << 8) +#define CRS_ISR_ESYNCF (1 << 3) +#define CRS_ISR_ERRF (1 << 2) +#define CRS_ISR_SYNCWARNF (1 << 1) +#define CRS_ISR_SYNCOOKF (1 << 0) + +/* CEC_ICR Values -----------------------------------------------------------*/ + +#define CRS_ICR_ESYNCC (1 << 3) +#define CRS_ICR_ERRC (1 << 2) +#define CRS_ICR_SYNCWARNC (1 << 1) +#define CRS_ICR_SYNCOKC (1 << 0) + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + +BEGIN_DECLS + +END_DECLS +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/dac.h b/libopencm3/include/libopencm3/stm32/f0/dac.h new file mode 100644 index 0000000..7f54484 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/dac.h @@ -0,0 +1,117 @@ +/** @defgroup dac_defines DAC Defines + * + * @brief Defined Constants and Types for the STM32F0xx Digital to Analog + * Converter + * + * @ingroup STM32F0xx_defines + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DAC_H +#define LIBOPENCM3_DAC_H + +#include + +/*****************************************************************************/ +/* Module definitions */ +/*****************************************************************************/ + +#define DAC DAC_BASE + +/*****************************************************************************/ +/* Register definitions */ +/*****************************************************************************/ + +#define DAC_CR MMIO32(DAC_BASE + 0x00) +#define DAC_SWTRIGR MMIO32(DAC_BASE + 0x04) +#define DAC_DHR12R1 MMIO32(DAC_BASE + 0x08) +#define DAC_DHR12L1 MMIO32(DAC_BASE + 0x0C) +#define DAC_DHR8R1 MMIO32(DAC_BASE + 0x10) +#define DAC_DOR1 MMIO32(DAC_BASE + 0x2C) +#define DAC_SR MMIO32(DAC_BASE + 0x34) + + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +/* DAC_CR Values ------------------------------------------------------------*/ + +#define DAC_CR_DMAUDRIE1 (1 << 13) +#define DAC_CR_DMAEN1 (1 << 12) + +#define DAC_CR_TSEL1_SHIFT 3 +#define DAC_CR_TSEL1 (7 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_TIM6_TRGO (0 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_TIM8_TRGO (1 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_TIM7_TRGO (2 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_TIM5_TRGO (3 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_TIM2_TRGO (4 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_TIM4_TRGO (5 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_EXT_9 (6 << DAC_CR_TSEL1_SHIFT) +#define DAC_CR_TSEL1_SWTRG (7 << DAC_CR_TSEL1_SHIFT) + +#define DAC_CR_TEN1 (1 << 2) +#define DAC_CR_BOFF1 (1 << 1) +#define DAC_CR_EN1 (1 << 0) + +/* DAC_SWTRIGR Values -------------------------------------------------------*/ + +#define DAC_SWTRIGR_SWTRIG1 (1 << 0) + +/* DAC_DHR12R1 Values -------------------------------------------------------*/ + +#define DAC_DHR12R1_DACC1DHR 0xFFF + +/* DAC_DHR12L1 Values -------------------------------------------------------*/ + +#define DAC_DHR12L1_DACC1DHR (0xFFF << 4) + +/* DAC_DHR8R1 Values --------------------------------------------------------*/ + +#define DAC_DHR8R1_DACC1DHR 0xFF + +/* DAC_DOR1 Values ----------------------------------------------------------*/ + +#define DAC_DOR1_DACC1DOR 0xFFF + +/* DAC_SR Values ------------------------------------------------------------*/ + +#define DAC_SR_DMAUDR1 (1 << 13) + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + +BEGIN_DECLS + +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/dma.h b/libopencm3/include/libopencm3/stm32/f0/dma.h new file mode 100644 index 0000000..42b4687 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/dma.h @@ -0,0 +1,37 @@ +/** @defgroup dma_defines DMA Defines + * + * @ingroup STM32F0xx_defines + * + * @brief Defined Constants and Types for the STM32F0xx DMA Controller + * + * @version 1.0.0 + * + * @date 10 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DMA_H +#define LIBOPENCM3_DMA_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f0/doc-stm32f0.h b/libopencm3/include/libopencm3/stm32/f0/doc-stm32f0.h new file mode 100644 index 0000000..fc26c50 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/doc-stm32f0.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 STM32F0 + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * API documentation for ST Microelectronics STM32F0 Cortex M0 series. + * + * LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup STM32F0xx STM32F0xx + * Libraries for ST Microelectronics STM32F0xx series. + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ + +/** @defgroup STM32F0xx_defines STM32F0xx Defines + * + * @brief Defined Constants and Types for the STM32F0xx series + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ + diff --git a/libopencm3/include/libopencm3/stm32/f0/exti.h b/libopencm3/include/libopencm3/stm32/f0/exti.h new file mode 100644 index 0000000..3a99f5b --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/exti.h @@ -0,0 +1,40 @@ +/** @defgroup exti_defines EXTI Defines + * + * @brief Defined Constants and Types for the STM32F0xx External Interrupts + * + * + * @ingroup STM32F0xx_defines + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EXTI_H +#define LIBOPENCM3_EXTI_H +/**@{*/ + +#include +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/flash.h b/libopencm3/include/libopencm3/stm32/f0/flash.h new file mode 100644 index 0000000..58e9ea6 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/flash.h @@ -0,0 +1,116 @@ +/** @defgroup flash_defines FLASH Defines + * + * @brief Defined Constants and Types for the STM32F0xx Flash memory + * + * @ingroup STM32F0xx_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2013 + * Frantisek Burian + * + * @date 14 January 2014 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_FLASH_H +#define LIBOPENCM3_FLASH_H +/**@{*/ + +#include + +/* --- FLASH_OPTION values ------------------------------------------------- */ + +/** @defgroup flash_options Option Byte Addresses +@ingroup flash_defines +@{*/ +#define FLASH_OPTION_BYTE_0 FLASH_OPTION_BYTE(0) +#define FLASH_OPTION_BYTE_1 FLASH_OPTION_BYTE(1) +#define FLASH_OPTION_BYTE_2 FLASH_OPTION_BYTE(2) +#define FLASH_OPTION_BYTE_3 FLASH_OPTION_BYTE(3) +#define FLASH_OPTION_BYTE_4 FLASH_OPTION_BYTE(4) +#define FLASH_OPTION_BYTE_5 FLASH_OPTION_BYTE(5) +/**@}*/ + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +/* --- FLASH_ACR values ---------------------------------------------------- */ + +/** @defgroup flash_latency FLASH Wait States +@ingroup flash_defines +@{*/ +#define FLASH_ACR_LATENCY_000_024MHZ 0 +#define FLASH_ACR_LATENCY_024_048MHZ 1 +#define FLASH_ACR_LATENCY_0WS 0 +#define FLASH_ACR_LATENCY_1WS 1 +/**@}*/ + +/* --- FLASH_SR values ----------------------------------------------------- */ + +#define FLASH_SR_EOP (1 << 5) +#define FLASH_SR_WRPRTERR (1 << 4) +#define FLASH_SR_PGERR (1 << 2) +#define FLASH_SR_BSY (1 << 0) + +/* --- FLASH_CR values ----------------------------------------------------- */ + +#define FLASH_CR_OBL_LAUNCH (1 << 13) + +/* --- FLASH_OBR values ---------------------------------------------------- */ + +#define FLASH_OBR_DATA1_SHIFT 24 +#define FLASH_OBR_DATA1 (0xFF << FLASH_OBR_DATA1_SHIFT) +#define FLASH_OBR_DATA0_SHIFT 16 +#define FLASH_OBR_DATA0 (0xFF << FLASH_OBR_DATA0_SHIFT) + +#define FLASH_OBR_RAM_PARITY_CHECK (1 << 14) +#define FLASH_OBR_VDDA_MONITOR (1 << 13) +#define FLASH_OBR_NBOOT1 (1 << 12) +#define FLASH_OBR_NRST_STDBY (1 << 10) +#define FLASH_OBR_NRST_STOP (1 << 9) +#define FLASH_OBR_WDG_SW (1 << 8) +#define FLASH_OBR_RDPRT (3 << FLASH_OBR_RDPRT_SHIFT) +#define FLASH_OBR_RDPRT_L0 (0 << FLASH_OBR_RDPRT_SHIFT) +#define FLASH_OBR_RDPRT_L1 (1 << FLASH_OBR_RDPRT_SHIFT) +#define FLASH_OBR_RDPRT_L2 (3 << FLASH_OBR_RDPRT_SHIFT) + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +/* Read protection option byte protection level setting */ +#define FLASH_RDP_L0 ((uint8_t)0xaa) +#define FLASH_RDP_L1 ((uint8_t)0xf0) /* any value */ +#define FLASH_RDP_L2 ((uint8_t)0xcc) + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + +BEGIN_DECLS + +END_DECLS +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/gpio.h b/libopencm3/include/libopencm3/stm32/f0/gpio.h new file mode 100644 index 0000000..cfef358 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/gpio.h @@ -0,0 +1,75 @@ +/** @defgroup gpio_defines GPIO Defines + * + * @brief Defined Constants and Types for the STM32F0xx General Purpose I/O + * + * @ingroup STM32F0xx_defines + * + * @version 1.0.0 + * + * @date 1 July 2012 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_GPIO_H +#define LIBOPENCM3_GPIO_H + +#include + +/*****************************************************************************/ +/* Module definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Register definitions */ +/*****************************************************************************/ + +#define GPIO_BRR(port) MMIO32(port + 0x24) +#define GPIOA_BRR GPIO_BRR(GPIOA) +#define GPIOB_BRR GPIO_BRR(GPIOB) +#define GPIOC_BRR GPIO_BRR(GPIOC) +#define GPIOD_BRR GPIO_BRR(GPIOD) +#define GPIOF_BRR GPIO_BRR(GPIOF) + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +/** @defgroup gpio_speed GPIO Output Pin Speed +@ingroup gpio_defines +@{*/ +#define GPIO_OSPEED_LOW 0x0 +#define GPIO_OSPEED_MED 0x1 +#define GPIO_OSPEED_HIGH 0x3 +/**@}*/ + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + +BEGIN_DECLS + +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/i2c.h b/libopencm3/include/libopencm3/stm32/f0/i2c.h new file mode 100644 index 0000000..06ff2dd --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/i2c.h @@ -0,0 +1,256 @@ +/** @defgroup i2c_defines I2C Defines + * + * @brief Defined Constants and Types for the STM32F0xx I2C + * + * @ingroup STM32F0xx_defines + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_I2C_H +#define LIBOPENCM3_I2C_H + +/*****************************************************************************/ +/* Module definitions */ +/*****************************************************************************/ + +#define I2C1 I2C1_BASE +#define I2C2 I2C2_BASE + +/*****************************************************************************/ +/* Register definitions */ +/*****************************************************************************/ + +#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00) +#define I2C1_CR1 I2C_CR1(I2C1) +#define I2C2_CR1 I2C_CR1(I2C2) + +#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04) +#define I2C1_CR2 I2C_CR2(I2C1) +#define I2C2_CR2 I2C_CR2(I2C2) + +#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08) +#define I2C1_OAR1 I2C_OAR1(I2C1) +#define I2C2_OAR1 I2C_OAR1(I2C2) + +#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c) +#define I2C1_OAR2 I2C_OAR2(I2C1) +#define I2C2_OAR2 I2C_OAR2(I2C2) + +#define I2C_TIMINGR(i2c_base) MMIO32(i2c_base + 0x10) +#define I2C1_TIMINGR I2C_TIMINGR(I2C1) +#define I2C2_TIMINGR I2C_TIMINGR(I2C2) + +#define I2C_TIMEOUTR(i2c_base) MMIO32(i2c_base + 0x14) +#define I2C1_TIMEOUTR I2C_TIMEOUTR(I2C1) +#define I2C2_TIMEOUTR I2C_TIMEOUTR(I2C2) + +#define I2C_ISR(i2c_base) MMIO32(i2c_base + 0x18) +#define I2C1_ISR I2C_ISR(I2C1) +#define I2C2_ISR I2C_ISR(I2C2) + +#define I2C_ICR(i2c_base) MMIO32(i2c_base + 0x1C) +#define I2C1_ICR I2C_ICR(I2C1) +#define I2C2_ICR I2C_ICR(I2C2) + +#define I2C_PECR(i2c_base) MMIO8(i2c_base + 0x20) +#define I2C1_PECR I2C_PECR(I2C1) +#define I2C2_PECR I2C_PECR(I2C2) + +#define I2C_RXDR(i2c_base) MMIO8(i2c_base + 0x24) +#define I2C1_RXDR I2C_RXDR(I2C1) +#define I2C2_RXDR I2C_RXDR(I2C2) + +#define I2C_TXDR(i2c_base) MMIO8(i2c_base + 0x28) +#define I2C1_TXDR I2C_TXDR(I2C1) +#define I2C2_TXDR I2C_TXDR(I2C2) + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +/* I2C_CR1 values ---------------------------------------------------------- */ + +#define I2C_CR1_PECEN (1 << 23) +#define I2C_CR1_ALERTEN (1 << 22) +#define I2C_CR1_SMBDEN (1 << 21) +#define I2C_CR1_SMBHEN (1 << 20) +#define I2C_CR1_GCEN (1 << 19) +#define I2C_CR1_WUPEN (1 << 18) +#define I2C_CR1_NOSTRETCH (1 << 17) +#define I2C_CR1_SBC (1 << 16) +#define I2C_CR1_RXDMAEN (1 << 15) +#define I2C_CR1_TXDMAEN (1 << 14) +#define I2C_CR1_ANFOFF (1 << 12) + +#define I2C_CR1_DNF_SHIFT 8 +#define I2C_CR1_DNF (0x0F << I2C_CR1_DNF_SHIFT) +#define I2C_CR1_DNF_VAL(x) ((x) << I2C_CR1_DNF_SHIFT) + +#define I2C_CR1_ERRIE (1 << 7) +#define I2C_CR1_TCIE (1 << 6) +#define I2C_CR1_STOPIE (1 << 5) +#define I2C_CR1_NACKIE (1 << 4) +#define I2C_CR1_ADDRIE (1 << 3) +#define I2C_CR1_RXIE (1 << 2) +#define I2C_CR1_TXIE (1 << 1) +#define I2C_CR1_PE (1 << 0) + +/* I2C_CR2 values ---------------------------------------------------------- */ + +#define I2C_CR2_PECBYTE (1 << 26) +#define I2C_CR2_AUTOEND (1 << 25) +#define I2C_CR2_RELOAD (1 << 24) + +#define I2C_CR2_NBYTES_SHIFT 16 +#define I2C_CR2_NBYTES (0xFF << I2C_CR2_NBYTES_SHIFT) +#define I2C_CR2_NBYTES_VAL(x) ((x) << I2C_CR2_NBYTES_SHIFT) + +#define I2C_CR2_NACK (1 << 15) +#define I2C_CR2_STOP (1 << 14) +#define I2C_CR2_START (1 << 13) +#define I2C_CR2_HEAD10R (1 << 12) +#define I2C_CR2_ADD10 (1 << 11) +#define I2C_CR2_RD_WRN (1 << 10) + +#define I2C_CR2_SADD_SHIFT 0 +#define I2C_CR2_SADD (0x3FF << I2C_CR2_SADD_SHIFT) +#define I2C_CR2_SADD_VAL(x) ((x) << I2C_CR2_SADD_SHIFT) + +/* I2C_OAR1 values --------------------------------------------------------- */ + +#define I2C_OAR1_OA1EN (1 << 15) +#define I2C_OAR1_OA1MODE (1 << 10) + +#define I2C_OAR1_OA1_SHIFT 0 +#define I2C_OAR1_OA1 (0x3FF << I2C_OAR1_OA1_SHIFT) +#define I2C_OAR1_OA1_VAL(x) ((x) << I2C_OAR1_OA1_SHIFT) + +/* I2C_OAR2 values --------------------------------------------------------- */ + +#define I2C_OAR2_OA1EN (1 << 15) + +#define I2C_OAR2_OA2MSK_SHIFT 8 +#define I2C_OAR2_OA2MSK (7 << I2C_OAR2_OA2MSK_SHIFT) +#define I2C_OAR2_OA2MSK_NOMASK (0 << I2C_OAR2_OA2MSK_SHIFT) +#define I2C_OAR2_OA2MSK_1_BIT (1 << I2C_OAR2_OA2MSK_SHIFT) +#define I2C_OAR2_OA2MSK_2_BIT (2 << I2C_OAR2_OA2MSK_SHIFT) +#define I2C_OAR2_OA2MSK_3_BIT (3 << I2C_OAR2_OA2MSK_SHIFT) +#define I2C_OAR2_OA2MSK_4_BIT (4 << I2C_OAR2_OA2MSK_SHIFT) +#define I2C_OAR2_OA2MSK_5_BIT (5 << I2C_OAR2_OA2MSK_SHIFT) +#define I2C_OAR2_OA2MSK_6_BIT (6 << I2C_OAR2_OA2MSK_SHIFT) +#define I2C_OAR2_OA2MSK_ALL (7 << I2C_OAR2_OA2MSK_SHIFT) + +#define I2C_OAR2_OA2_SHIFT 1 +#define I2C_OAR2_OA2 (0x7F << I2C_OAR2_OA2_SHIFT) +#define I2C_OAR2_OA2_VAL(x) ((x) << I2C_OAR2_OA2_SHIFT) + +/* I2C_TIMINGR values ------------------------------------------------------ */ + +#define I2C_TIMINGR_PRESC_SHIFT 28 +#define I2C_TIMINGR_PRESC (0x0F << I2C_TIMINGR_PRESC_SHIFT) +#define I2C_TIMINGR_PRESC_VAL(x) ((x) << I2C_TIMINGR_PRESC_SHIFT) + +#define I2C_TIMINGR_SCLDEL_SHIFT 20 +#define I2C_TIMINGR_SCLDEL (0x0F << I2C_TIMINGR_SCLDEL_SHIFT) +#define I2C_TIMINGR_SCLDEL_VAL(x) ((x) << I2C_TIMINGR_SCLDEL_SHIFT) + +#define I2C_TIMINGR_SDADEL_SHIFT 16 +#define I2C_TIMINGR_SDADEL (0x0F << I2C_TIMINGR_SDADEL_SHIFT) +#define I2C_TIMINGR_SDADEL_VAL(x) ((x) << I2C_TIMINGR_SDADEL_SHIFT) + +#define I2C_TIMINGR_SCLH_SHIFT 8 +#define I2C_TIMINGR_SCLH (0xFF << I2C_TIMINGR_SCLH_SHIFT) +#define I2C_TIMINGR_SCLH_VAL(x) ((x) << I2C_TIMINGR_SCLH_SHIFT) + +#define I2C_TIMINGR_SCLL_SHIFT 0 +#define I2C_TIMINGR_SCLL (0xFF << I2C_TIMINGR_SCLL_SHIFT) +#define I2C_TIMINGR_SCLL_VAL(x) ((x) << I2C_TIMINGR_SCLL_SHIFT) + +/* I2C_TIMEOUTR values ----------------------------------------------------- */ + +#define I2C_TIMEOUTR_TETXEN (1 << 31) + +#define I2C_TIMEOUTR_TIMEOUTB_SHIFT 16 +#define I2C_TIMEOUTR_TIMEOUTB (0xFFF << I2C_TIMEOUTR_TIMEOUTB_SHIFT) +#define I2C_TIMEOUTR_TIMEOUTB_VAL(x) ((x) << I2C_TIMEOUTR_TIMEOUTB_SHIFT) + +#define I2C_TIMEOUTR_TIMOUTEN (1 << 15) +#define I2C_TIMEOUTR_TIDLE (1 << 12) + +#define I2C_TIMEOUTR_TIMEOUTA_SHIFT 0 +#define I2C_TIMEOUTR_TIMEOUTA (0xFFF << I2C_TIMEOUTR_TIMEOUTA_SHIFT) +#define I2C_TIMEOUTR_TIMEOUTA_VAL(x) ((x) << I2C_TIMEOUTR_TIMEOUTA_SHIFT) + +/* I2C_ISR values ---------------------------------------------------------- */ + +#define I2C_ISR_ADDCODE_SHIFT 17 +#define I2C_ISR_ADDCODE (0x7F << I2C_ISR_ADDCODE_SHIFT) +#define I2C_ISR_ADDCODE_VAL(x) ((x) << I2C_ISR_ADDCODE_SHIFT) +#define I2C_ISR_ADDCODE_VALG(reg) (((reg) & I2C_ISR_ADDCODE) >> \ + I2C_ISR_ADDCODE_SHIFT) + +#define I2C_ISR_DIR (1 << 16) +#define I2C_ISR_BUSY (1 << 15) +#define I2C_ISR_ALERT (1 << 13) +#define I2C_ISR_TIMEOUT (1 << 12) +#define I2C_ISR_PECERR (1 << 11) +#define I2C_ISR_OVR (1 << 10) +#define I2C_ISR_ARLO (1 << 9) +#define I2C_ISR_BERR (1 << 8) +#define I2C_ISR_TCR (1 << 7) +#define I2C_ISR_TC (1 << 6) +#define I2C_ISR_STOPF (1 << 5) +#define I2C_ISR_NACKF (1 << 4) +#define I2C_ISR_ADDR (1 << 3) +#define I2C_ISR_RXNE (1 << 2) +#define I2C_ISR_TXIS (1 << 1) +#define I2C_ISR_TXE (1 << 0) + +/* I2C_ICR values ---------------------------------------------------------- */ + +#define I2C_ICR_ALERTCF (1 << 13) +#define I2C_ICR_TIMEOUTCF (1 << 12) +#define I2C_ICR_PECCF (1 << 11) +#define I2C_ICR_OVRCF (1 << 10) +#define I2C_ICR_ARLOCF (1 << 9) +#define I2C_ICR_BERRCF (1 << 8) +#define I2C_ICR_STOPCF (1 << 5) +#define I2C_ICR_NACKCF (1 << 4) +#define I2C_ICR_ADDRCF (1 << 3) + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + +BEGIN_DECLS + +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/irq.json b/libopencm3/include/libopencm3/stm32/f0/irq.json new file mode 100644 index 0000000..8a407dc --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/irq.json @@ -0,0 +1,39 @@ +{ + "irqs": [ + "wwdg", + "pvd", + "rtc", + "flash", + "rcc", + "exti0_1", + "exti2_3", + "exti4_15", + "tsc", + "dma1_channel1", + "dma1_channel2_3", + "dma1_channel4_5", + "adc_comp", + "tim1_brk_up_trg_com", + "tim1_cc", + "tim2", + "tim3", + "tim6_dac", + "tim7", + "tim14", + "tim15", + "tim16", + "tim17", + "i2c1", + "i2c2", + "spi1", + "spi2", + "usart1", + "usart2", + "usart3_4", + "cec_can", + "usb" + ], + "partname_humanreadable": "STM32 F0 series", + "partname_doxygen": "STM32F0", + "includeguard": "LIBOPENCM3_STM32_F0_NVIC_H" +} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/stm32/f0/iwdg.h b/libopencm3/include/libopencm3/stm32/f0/iwdg.h new file mode 100644 index 0000000..be9dc5a --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/iwdg.h @@ -0,0 +1,70 @@ +/** @defgroup iwdg_defines IWDG Defines + * + * @brief Defined Constants and Types for the STM32F0xx Independent Watchdog + * Timer + * + * @ingroup STM32F0xx_defines + * + * @version 1.0.0 + * + * @date 18 August 2012 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_IWDG_H +#define LIBOPENCM3_IWDG_H + +#include + +/*****************************************************************************/ +/* Module definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Register definitions */ +/*****************************************************************************/ + +/* Key Register (IWDG_WINR) */ +#define IWDG_WINR MMIO32(IWDG_BASE + 0x10) + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +/* --- IWDG_SR values ------------------------------------------------------ */ + +/* WVU: Watchdog counter window value update */ +#define IWDG_SR_WVU (1 << 2) + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + +BEGIN_DECLS + +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/memorymap.h b/libopencm3/include/libopencm3/stm32/f0/memorymap.h new file mode 100644 index 0000000..4802b0f --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/memorymap.h @@ -0,0 +1,116 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * .. based on file from F4. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_MEMORYMAP_H +#define LIBOPENCM3_MEMORYMAP_H + +#include + +/* --- STM32 specific peripheral definitions ------------------------------- */ + +/* Memory map for all buses */ +#define FLASH_BASE (0x08000000U) +#define PERIPH_BASE (0x40000000U) +#define INFO_BASE (0x1ffff000U) +#define PERIPH_BASE_APB (PERIPH_BASE + 0x00000000) +#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x00020000) +#define PERIPH_BASE_AHB2 (PERIPH_BASE + 0x08000000) + +/* Register boundary addresses */ + +/* APB1 */ +#define TIM2_BASE (PERIPH_BASE_APB + 0x0000) +#define TIM3_BASE (PERIPH_BASE_APB + 0x0400) + +#define TIM6_BASE (PERIPH_BASE_APB + 0x1000) +#define TIM7_BASE (PERIPH_BASE_APB + 0x1400) + +#define TIM14_BASE (PERIPH_BASE_APB + 0x2000) +/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ +#define RTC_BASE (PERIPH_BASE_APB + 0x2800) +#define WWDG_BASE (PERIPH_BASE_APB + 0x2c00) +#define IWDG_BASE (PERIPH_BASE_APB + 0x3000) +/* PERIPH_BASE_APB + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ +#define SPI2_BASE (PERIPH_BASE_APB + 0x3800) +/* PERIPH_BASE_APB + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ +#define USART2_BASE (PERIPH_BASE_APB + 0x4400) +#define USART3_BASE (PERIPH_BASE_APB + 0x4800) +#define USART4_BASE (PERIPH_BASE_APB + 0x4C00) + +#define I2C1_BASE (PERIPH_BASE_APB + 0x5400) +#define I2C2_BASE (PERIPH_BASE_APB + 0x5800) +#define USB_DEV_FS_BASE (PERIPH_BASE_APB + 0x5C00) +/* USB_PMA_BASE already defined in usb.h */ +#define BX_CAN1_BASE (PERIPH_BASE_APB + 0x6400) + +#define CRS_BASE (PERIPH_BASE_APB + 0x6C00) +#define POWER_CONTROL_BASE (PERIPH_BASE_APB + 0x7000) +#define DAC_BASE (PERIPH_BASE_APB + 0x7400) +#define CEC_BASE (PERIPH_BASE_APB + 0x7800) + +#define SYSCFG_COMP_BASE (PERIPH_BASE_APB + 0x10000) +#define EXTI_BASE (PERIPH_BASE_APB + 0x10400) + +#define ADC_BASE (PERIPH_BASE_APB + 0x12400) +#define TIM1_BASE (PERIPH_BASE_APB + 0x12C00) +#define SPI1_I2S1_BASE (PERIPH_BASE_APB + 0x13000) + +#define USART1_BASE (PERIPH_BASE_APB + 0x13800) +#define TIM15_BASE (PERIPH_BASE_APB + 0x14000) +#define TIM16_BASE (PERIPH_BASE_APB + 0x14400) +#define TIM17_BASE (PERIPH_BASE_APB + 0x14800) + +#define DBGMCU_BASE (PERIPH_BASE_APB + 0x15800) + +/* AHB1 */ +#define DMA_BASE (PERIPH_BASE_AHB1 + 0x0000) +/* DMA is the name in the F0 refman, but all other stm32's use DMA1 */ +#define DMA1_BASE DMA_BASE + +#define RCC_BASE (PERIPH_BASE_AHB1 + 0x1000) + +#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000) + +#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) + +#define TSC_BASE (PERIPH_BASE_AHB1 + 0x4000) + +/* AHB2 */ +#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000) +#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400) +#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800) +#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0C00) +#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000) +#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400) + +/* Device Electronic Signature */ +#define DESIG_FLASH_SIZE_BASE (0x1FFFF7CCU) +#define DESIG_UNIQUE_ID_BASE (0x1FFFF7ACU) +#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) +#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) +#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8) + +/* ST provided factory calibration values @ 3.3V */ +#define ST_VREFINT_CAL MMIO16(0x1FFFF7BA) +#define ST_TSENSE_CAL1_30C MMIO16(0x1FFFF7B8) +#define ST_TSENSE_CAL2_110 MMIO16(0x1FFFF7C2) + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/pwr.h b/libopencm3/include/libopencm3/stm32/f0/pwr.h new file mode 100644 index 0000000..e0706b6 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/pwr.h @@ -0,0 +1,67 @@ +/** @defgroup pwr_defines PWR Defines + * + * @brief Defined Constants and Types for the STM32F0xx PWR Control + * + * @ingroup STM32F0xx_defines + * + * @version 1.0.0 + * + * @date 5 December 2012 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_PWR_H +#define LIBOPENCM3_PWR_H + +#include + +/*****************************************************************************/ +/* Module definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Register definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +/* EWUP: Enable WKUP2 pin */ +#define PWR_CSR_EWUP2 (1 << 9) + +/* EWUP: Enable WKUP1 pin */ +#define PWR_CSR_EWUP1 (1 << 8) + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + +BEGIN_DECLS + +END_DECLS + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f0/rcc.h b/libopencm3/include/libopencm3/stm32/f0/rcc.h new file mode 100644 index 0000000..39de15e --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/rcc.h @@ -0,0 +1,524 @@ +/** @defgroup rcc_defines RCC Defines + * + * @brief Defined Constants and Types for the STM32F0xx Reset and Clock +Control + * + * @ingroup STM32F0xx_defines + * + * @author @htmlonly © @endhtmlonly 2013 + * Frantisek Burian + * + * @version 1.0.0 + * + * @date 29 Jun 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ +/**@{*/ + +#ifndef LIBOPENCM3_RCC_H +#define LIBOPENCM3_RCC_H + +/*****************************************************************************/ +/* Module definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Register definitions */ +/*****************************************************************************/ + +#define RCC_CR MMIO32(RCC_BASE + 0x00) +#define RCC_CFGR MMIO32(RCC_BASE + 0x04) +#define RCC_CIR MMIO32(RCC_BASE + 0x08) +#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c) +#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10) +#define RCC_AHBENR MMIO32(RCC_BASE + 0x14) +#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18) +#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c) +#define RCC_BDCR MMIO32(RCC_BASE + 0x20) +#define RCC_CSR MMIO32(RCC_BASE + 0x24) +#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) +#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) +#define RCC_CFGR3 MMIO32(RCC_BASE + 0x30) +#define RCC_CR2 MMIO32(RCC_BASE + 0x34) + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +/* --- RCC_CR values ------------------------------------------------------- */ + +#define RCC_CR_PLLRDY (1 << 25) +#define RCC_CR_PLLON (1 << 24) +#define RCC_CR_CSSON (1 << 19) +#define RCC_CR_HSEBYP (1 << 18) +#define RCC_CR_HSERDY (1 << 17) +#define RCC_CR_HSEON (1 << 16) +#define RCC_CR_HSICAL_SHIFT 8 +#define RCC_CR_HSICAL (0xFF << RCC_CR_HSICAL_SHIFT) +#define RCC_CR_HSITRIM_SHIFT 3 +#define RCC_CR_HSITRIM (0x1F << RCC_CR_HSITRIM_SHIFT) +#define RCC_CR_HSIRDY (1 << 1) +#define RCC_CR_HSION (1 << 0) + +/* --- RCC_CFGR values ----------------------------------------------------- */ + +#define RCC_CFGR_PLLNODIV (1 << 31) + +#define RCC_CFGR_MCOPRE_SHIFT 28 +#define RCC_CFGR_MCOPRE (7 << RCC_CFGR_MCOPRE_SHIFT) +#define RCC_CFGR_MCOPRE_DIV1 (0 << RCC_CFGR_MCOPRE_SHIFT) +#define RCC_CFGR_MCOPRE_DIV2 (1 << RCC_CFGR_MCOPRE_SHIFT) +#define RCC_CFGR_MCOPRE_DIV4 (2 << RCC_CFGR_MCOPRE_SHIFT) +#define RCC_CFGR_MCOPRE_DIV8 (3 << RCC_CFGR_MCOPRE_SHIFT) +#define RCC_CFGR_MCOPRE_DIV16 (4 << RCC_CFGR_MCOPRE_SHIFT) +#define RCC_CFGR_MCOPRE_DIV32 (5 << RCC_CFGR_MCOPRE_SHIFT) +#define RCC_CFGR_MCOPRE_DIV64 (6 << RCC_CFGR_MCOPRE_SHIFT) +#define RCC_CFGR_MCOPRE_DIV128 (7 << RCC_CFGR_MCOPRE_SHIFT) + +#define RCC_CFGR_MCO_SHIFT 24 +#define RCC_CFGR_MCO (15 << RCC_CFGR_MCO_SHIFT) +#define RCC_CFGR_MCO_NOCLK (0 << RCC_CFGR_MCO_SHIFT) +#define RCC_CFGR_MCO_HSI14 (1 << RCC_CFGR_MCO_SHIFT) +#define RCC_CFGR_MCO_LSI (2 << RCC_CFGR_MCO_SHIFT) +#define RCC_CFGR_MCO_LSE (3 << RCC_CFGR_MCO_SHIFT) +#define RCC_CFGR_MCO_SYSCLK (4 << RCC_CFGR_MCO_SHIFT) +#define RCC_CFGR_MCO_HSI (5 << RCC_CFGR_MCO_SHIFT) +#define RCC_CFGR_MCO_HSE (6 << RCC_CFGR_MCO_SHIFT) +#define RCC_CFGR_MCO_PLL (7 << RCC_CFGR_MCO_SHIFT) +#define RCC_CFGR_MCO_HSI48 (8 << RCC_CFGR_MCO_SHIFT)/*f07*/ + +#define RCC_CFGR_PLLMUL_SHIFT 18 +#define RCC_CFGR_PLLMUL (0x0F << RCC_CFGR_PLLMUL_SHIFT) +#define RCC_CFGR_PLLMUL_MUL2 (0x00 << RCC_CFGR_PLLMUL_SHIFT) +#define RCC_CFGR_PLLMUL_MUL3 (0x01 << RCC_CFGR_PLLMUL_SHIFT) +#define RCC_CFGR_PLLMUL_MUL4 (0x02 << RCC_CFGR_PLLMUL_SHIFT) +#define RCC_CFGR_PLLMUL_MUL5 (0x03 << RCC_CFGR_PLLMUL_SHIFT) +#define RCC_CFGR_PLLMUL_MUL6 (0x04 << RCC_CFGR_PLLMUL_SHIFT) +#define RCC_CFGR_PLLMUL_MUL7 (0x05 << RCC_CFGR_PLLMUL_SHIFT) +#define RCC_CFGR_PLLMUL_MUL8 (0x06 << RCC_CFGR_PLLMUL_SHIFT) +#define RCC_CFGR_PLLMUL_MUL9 (0x07 << RCC_CFGR_PLLMUL_SHIFT) +#define RCC_CFGR_PLLMUL_MUL10 (0x08 << RCC_CFGR_PLLMUL_SHIFT) +#define RCC_CFGR_PLLMUL_MUL11 (0x09 << RCC_CFGR_PLLMUL_SHIFT) +#define RCC_CFGR_PLLMUL_MUL12 (0x0A << RCC_CFGR_PLLMUL_SHIFT) +#define RCC_CFGR_PLLMUL_MUL13 (0x0B << RCC_CFGR_PLLMUL_SHIFT) +#define RCC_CFGR_PLLMUL_MUL14 (0x0C << RCC_CFGR_PLLMUL_SHIFT) +#define RCC_CFGR_PLLMUL_MUL15 (0x0D << RCC_CFGR_PLLMUL_SHIFT) +#define RCC_CFGR_PLLMUL_MUL16 (0x0E << RCC_CFGR_PLLMUL_SHIFT) + +#define RCC_CFGR_PLLXTPRE (1<<17) +#define RCC_CFGR_PLLSRC (1<<16) +#define RCC_CFGR_PLLSRC0 (1<<15) +#define RCC_CFGR_ADCPRE (1<<14) + + +#define RCC_CFGR_PPRE_SHIFT 8 +#define RCC_CFGR_PPRE (7 << RCC_CFGR_PPRE_SHIFT) +#define RCC_CFGR_PPRE_NODIV (0 << RCC_CFGR_PPRE_SHIFT) +#define RCC_CFGR_PPRE_DIV2 (4 << RCC_CFGR_PPRE_SHIFT) +#define RCC_CFGR_PPRE_DIV4 (5 << RCC_CFGR_PPRE_SHIFT) +#define RCC_CFGR_PPRE_DIV8 (6 << RCC_CFGR_PPRE_SHIFT) +#define RCC_CFGR_PPRE_DIV16 (7 << RCC_CFGR_PPRE_SHIFT) + +#define RCC_CFGR_HPRE_SHIFT 4 +#define RCC_CFGR_HPRE (0xf << RCC_CFGR_HPRE_SHIFT) +#define RCC_CFGR_HPRE_NODIV (0x0 << RCC_CFGR_HPRE_SHIFT) +#define RCC_CFGR_HPRE_DIV2 (0x8 << RCC_CFGR_HPRE_SHIFT) +#define RCC_CFGR_HPRE_DIV4 (0x9 << RCC_CFGR_HPRE_SHIFT) +#define RCC_CFGR_HPRE_DIV8 (0xa << RCC_CFGR_HPRE_SHIFT) +#define RCC_CFGR_HPRE_DIV16 (0xb << RCC_CFGR_HPRE_SHIFT) +#define RCC_CFGR_HPRE_DIV64 (0xc << RCC_CFGR_HPRE_SHIFT) +#define RCC_CFGR_HPRE_DIV128 (0xd << RCC_CFGR_HPRE_SHIFT) +#define RCC_CFGR_HPRE_DIV256 (0xe << RCC_CFGR_HPRE_SHIFT) +#define RCC_CFGR_HPRE_DIV512 (0xf << RCC_CFGR_HPRE_SHIFT) + +#define RCC_CFGR_SWS_SHIFT 2 +#define RCC_CFGR_SWS (3 << RCC_CFGR_SWS_SHIFT) +#define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) +#define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT) +#define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT) +#define RCC_CFGR_SWS_HSI48 (3 << RCC_CFGR_SWS_SHIFT) + +#define RCC_CFGR_SW_SHIFT 0 +#define RCC_CFGR_SW (3 << RCC_CFGR_SW_SHIFT) +#define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) +#define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT) +#define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT) +#define RCC_CFGR_SW_HSI48 (3 << RCC_CFGR_SW_SHIFT) + +/* --- RCC_CIR values ------------------------------------------------------ */ + +#define RCC_CIR_CSSC (1 << 23) +#define RCC_CIR_HSI48RDYC (1 << 22) +#define RCC_CIR_HSI14RDYC (1 << 21) +#define RCC_CIR_PLLRDYC (1 << 20) +#define RCC_CIR_HSERDYC (1 << 19) +#define RCC_CIR_HSIRDYC (1 << 18) +#define RCC_CIR_LSERDYC (1 << 17) +#define RCC_CIR_LSIRDYC (1 << 16) +#define RCC_CIR_HSI48RDYIE (1 << 14) +#define RCC_CIR_HSI14RDYIE (1 << 13) +#define RCC_CIR_PLLRDYIE (1 << 12) +#define RCC_CIR_HSERDYIE (1 << 11) +#define RCC_CIR_HSIRDYIE (1 << 10) +#define RCC_CIR_LSERDYIE (1 << 9) +#define RCC_CIR_LSIRDYIE (1 << 8) +#define RCC_CIR_CSSF (1 << 7) +#define RCC_CIR_HSI48RDYF (1 << 6) +#define RCC_CIR_HSI14RDYF (1 << 5) +#define RCC_CIR_PLLRDYF (1 << 4) +#define RCC_CIR_HSERDYF (1 << 3) +#define RCC_CIR_HSIRDYF (1 << 2) +#define RCC_CIR_LSERDYF (1 << 1) +#define RCC_CIR_LSIRDYF (1 << 0) + +/* --- RCC_APB2RSTR values ------------------------------------------------- */ + +#define RCC_APB2RSTR_DBGMCURST (1 << 22) +#define RCC_APB2RSTR_TIM17RST (1 << 18) +#define RCC_APB2RSTR_TIM16RST (1 << 17) +#define RCC_APB2RSTR_TIM15RST (1 << 16) +#define RCC_APB2RSTR_USART1RST (1 << 14) +#define RCC_APB2RSTR_SPI1RST (1 << 12) +#define RCC_APB2RSTR_TIM1RST (1 << 11) +#define RCC_APB2RSTR_ADCRST (1 << 9) +#define RCC_APB2RSTR_SYSCFGRST (1 << 0) + +/* --- RCC_APB1RSTR values ------------------------------------------------- */ + +#define RCC_APB1RSTR_CECRST (1 << 30) +#define RCC_APB1RSTR_DACRST (1 << 29) +#define RCC_APB1RSTR_PWRRST (1 << 28) +#define RCC_APB1RSTR_CRSRST (1 << 27) +#define RCC_APB1RSTR_CANRST (1 << 25) +#define RCC_APB1RSTR_USBRST (1 << 23) +#define RCC_APB1RSTR_I2C2RST (1 << 22) +#define RCC_APB1RSTR_I2C1RST (1 << 21) +#define RCC_APB1RSTR_USART4RST (1 << 19) +#define RCC_APB1RSTR_USART3RST (1 << 18) +#define RCC_APB1RSTR_USART2RST (1 << 17) +#define RCC_APB1RSTR_SPI2RST (1 << 14) +#define RCC_APB1RSTR_WWDGRST (1 << 11) +#define RCC_APB1RSTR_TIM14RST (1 << 8) +#define RCC_APB1RSTR_TIM7RST (1 << 5) +#define RCC_APB1RSTR_TIM6RST (1 << 4) +#define RCC_APB1RSTR_TIM3RST (1 << 1) +#define RCC_APB1RSTR_TIM2RST (1 << 0) + +/* --- RCC_AHBENR values --------------------------------------------------- */ + +#define RCC_AHBENR_TSCEN (1 << 24) +#define RCC_AHBENR_GPIOFEN (1 << 22) +#define RCC_AHBENR_GPIOEEN (1 << 21) +#define RCC_AHBENR_GPIODEN (1 << 20) +#define RCC_AHBENR_GPIOCEN (1 << 19) +#define RCC_AHBENR_GPIOBEN (1 << 18) +#define RCC_AHBENR_GPIOAEN (1 << 17) +#define RCC_AHBENR_CRCEN (1 << 6) +#define RCC_AHBENR_FLTFEN (1 << 4) +#define RCC_AHBENR_SRAMEN (1 << 2) +#define RCC_AHBENR_DMAEN (1 << 0) + +/* --- RCC_APB2ENR values -------------------------------------------------- */ + +#define RCC_APB2ENR_DBGMCUEN (1 << 22) +#define RCC_APB2ENR_TIM17EN (1 << 18) +#define RCC_APB2ENR_TIM16EN (1 << 17) +#define RCC_APB2ENR_TIM15EN (1 << 16) +#define RCC_APB2ENR_USART1EN (1 << 14) +#define RCC_APB2ENR_SPI1EN (1 << 12) +#define RCC_APB2ENR_TIM1EN (1 << 11) +#define RCC_APB2ENR_ADCEN (1 << 9) +#define RCC_APB2ENR_SYSCFGCOMPEN (1 << 0) + +/* --- RCC_APB1ENR values -------------------------------------------------- */ + +#define RCC_APB1ENR_CECEN (1 << 30) +#define RCC_APB1ENR_DACEN (1 << 29) +#define RCC_APB1ENR_PWREN (1 << 28) +#define RCC_APB1ENR_CRSEN (1 << 27) +#define RCC_APB1ENR_CANEN (1 << 25) +#define RCC_APB1ENR_USBEN (1 << 23) +#define RCC_APB1ENR_I2C2EN (1 << 22) +#define RCC_APB1ENR_I2C1EN (1 << 21) +#define RCC_APB1ENR_USART4EN (1 << 19) +#define RCC_APB1ENR_USART3EN (1 << 18) +#define RCC_APB1ENR_USART2EN (1 << 17) +#define RCC_APB1ENR_SPI2EN (1 << 14) +#define RCC_APB1ENR_WWDGEN (1 << 11) +#define RCC_APB1ENR_TIM14EN (1 << 8) +#define RCC_APB1ENR_TIM7EN (1 << 5) +#define RCC_APB1ENR_TIM6EN (1 << 4) +#define RCC_APB1ENR_TIM3EN (1 << 1) +#define RCC_APB1ENR_TIM2EN (1 << 0) + +/* --- RCC_BDCR values ----------------------------------------------------- */ + +#define RCC_BDCR_BDRST (1 << 16) +#define RCC_BDCR_RTCEN (1 << 15) +#define RCC_BDCR_RTCSEL_SHIFT 8 +#define RCC_BDCR_RTCSEL (3 << RCC_BDCR_RTCSEL_SHIFT) +#define RCC_BDCR_RTCSEL_NOCLK (0 << RCC_BDCR_RTCSEL_SHIFT) +#define RCC_BDCR_RTCSEL_LSE (1 << RCC_BDCR_RTCSEL_SHIFT) +#define RCC_BDCR_RTCSEL_LSI (2 << RCC_BDCR_RTCSEL_SHIFT) +#define RCC_BDCR_RTCSEL_HSE (3 << RCC_BDCR_RTCSEL_SHIFT) +#define RCC_BDCR_LSEDRV_SHIFT 3 +#define RCC_BDCR_LSEDRV (3 << RCC_BDCR_LSEDRV_SHIFT) +#define RCC_BDCR_LSEDRV_LOW (0 << RCC_BDCR_LSEDRV_SHIFT) +#define RCC_BDCR_LSEDRV_MEDLO (1 << RCC_BDCR_LSEDRV_SHIFT) +#define RCC_BDCR_LSEDRV_MEDHI (2 << RCC_BDCR_LSEDRV_SHIFT) +#define RCC_BDCR_LSEDRV_HIGH (3 << RCC_BDCR_LSEDRV_SHIFT) +#define RCC_BDCR_LSEBYP (1 << 2) +#define RCC_BDCR_LSERDY (1 << 1) +#define RCC_BDCR_LSEON (1 << 0) + +/* --- RCC_CSR values ------------------------------------------------------ */ + +#define RCC_CSR_LPWRRSTF (1 << 31) +#define RCC_CSR_WWDGRSTF (1 << 30) +#define RCC_CSR_IWDGRSTF (1 << 29) +#define RCC_CSR_SFTRSTF (1 << 28) +#define RCC_CSR_PORRSTF (1 << 27) +#define RCC_CSR_PINRSTF (1 << 26) +#define RCC_CSR_OBLRSTF (1 << 25) +#define RCC_CSR_RMVF (1 << 24) +#define RCC_CSR_V18PWRRSTF (1 << 23) +#define RCC_CSR_LSIRDY (1 << 1) +#define RCC_CSR_LSION (1 << 0) + +/* --- RCC_AHBRSTR values -------------------------------------------------- */ + +#define RCC_AHBRSTR_TSCRST (1 << 24) +#define RCC_AHBRSTR_IOPFRST (1 << 22) +#define RCC_AHBRSTR_IOPERST (1 << 21) +#define RCC_AHBRSTR_IOPDRST (1 << 20) +#define RCC_AHBRSTR_IOPCRST (1 << 19) +#define RCC_AHBRSTR_IOPBRST (1 << 18) +#define RCC_AHBRSTR_IOPARST (1 << 17) + + +/* --- RCC_CFGR2 values ---------------------------------------------------- */ + +#define RCC_CFGR2_PREDIV 0xf +#define RCC_CFGR2_PREDIV_NODIV 0x0 +#define RCC_CFGR2_PREDIV_DIV2 0x1 +#define RCC_CFGR2_PREDIV_DIV3 0x2 +#define RCC_CFGR2_PREDIV_DIV4 0x3 +#define RCC_CFGR2_PREDIV_DIV5 0x4 +#define RCC_CFGR2_PREDIV_DIV6 0x5 +#define RCC_CFGR2_PREDIV_DIV7 0x6 +#define RCC_CFGR2_PREDIV_DIV8 0x7 +#define RCC_CFGR2_PREDIV_DIV9 0x8 +#define RCC_CFGR2_PREDIV_DIV10 0x9 +#define RCC_CFGR2_PREDIV_DIV11 0xa +#define RCC_CFGR2_PREDIV_DIV12 0xb +#define RCC_CFGR2_PREDIV_DIV13 0xc +#define RCC_CFGR2_PREDIV_DIV14 0xd +#define RCC_CFGR2_PREDIV_DIV15 0xe +#define RCC_CFGR2_PREDIV_DIV16 0xf + +/* --- RCC_CFGR3 values ---------------------------------------------------- */ + +#define RCC_CFGR3_USART2SW_SHIFT 16 +#define RCC_CFGR3_USART2SW (3 << RCC_CFGR3_USART2SW_SHIFT) +#define RCC_CFGR3_USART2SW_PCLK (0 << RCC_CFGR3_USART2SW_SHIFT) +#define RCC_CFGR3_USART2SW_SYSCLK (1 << RCC_CFGR3_USART2SW_SHIFT) +#define RCC_CFGR3_USART2SW_LSE (2 << RCC_CFGR3_USART2SW_SHIFT) +#define RCC_CFGR3_USART2SW_HSI (3 << RCC_CFGR3_USART2SW_SHIFT) + +#define RCC_CFGR3_ADCSW (1 << 8) +#define RCC_CFGR3_USBSW (1 << 7) +#define RCC_CFGR3_CECSW (1 << 6) +#define RCC_CFGR3_I2C1SW (1 << 4) + +#define RCC_CFGR3_USART1SW_SHIFT 0 +#define RCC_CFGR3_USART1SW (3 << RCC_CFGR3_USART1SW_SHIFT) +#define RCC_CFGR3_USART1SW_PCLK (0 << RCC_CFGR3_USART1SW_SHIFT) +#define RCC_CFGR3_USART1SW_SYSCLK (1 << RCC_CFGR3_USART1SW_SHIFT) +#define RCC_CFGR3_USART1SW_LSE (2 << RCC_CFGR3_USART1SW_SHIFT) +#define RCC_CFGR3_USART1SW_HSI (3 << RCC_CFGR3_USART1SW_SHIFT) + +/* --- RCC_CFGR3 values ---------------------------------------------------- */ + +#define RCC_CR2_HSI48CAL_SHIFT 24 +#define RCC_CR2_HSI48CAL (0xFF << RCC_CR2_HSI48CAL_SHIFT) +#define RCC_CR2_HSI48RDY (1 << 17) +#define RCC_CR2_HSI48ON (1 << 16) +#define RCC_CR2_HSI14CAL_SHIFT 8 +#define RCC_CR2_HSI14CAL (0xFF << RCC_CR2_HSI14CAL_SHIFT) +#define RCC_CR2_HSI14TRIM_SHIFT 3 +#define RCC_CR2_HSI14TRIM (31 << RCC_CR2_HSI14TRIM_SHIFT) +#define RCC_CR2_HSI14DIS (1 << 2) +#define RCC_CR2_HSI14RDY (1 << 1) +#define RCC_CR2_HSI14ON (1 << 0) + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +/* --- Variable definitions ------------------------------------------------ */ +extern uint32_t rcc_core_frequency; +extern uint32_t rcc_ppre_frequency; + +enum rcc_osc { + HSI14, HSI, HSE, PLL, LSI, LSE, HSI48 +}; + +#define _REG_BIT(base, bit) (((base) << 5) + (bit)) + +enum rcc_periph_clken { + /* AHB peripherals */ + RCC_DMA = _REG_BIT(0x14, 0), + RCC_SRAM = _REG_BIT(0x14, 2), + RCC_FLTIF = _REG_BIT(0x14, 4), + RCC_CRC = _REG_BIT(0x14, 6), + RCC_GPIOA = _REG_BIT(0x14, 17), + RCC_GPIOB = _REG_BIT(0x14, 18), + RCC_GPIOC = _REG_BIT(0x14, 19), + RCC_GPIOD = _REG_BIT(0x14, 20), + RCC_GPIOE = _REG_BIT(0x14, 21), + RCC_GPIOF = _REG_BIT(0x14, 22), + RCC_TSC = _REG_BIT(0x14, 24), + + /* APB2 peripherals */ + RCC_SYSCFG_COMP = _REG_BIT(0x18, 0), + RCC_ADC = _REG_BIT(0x18, 9), + RCC_TIM1 = _REG_BIT(0x18, 11), + RCC_SPI1 = _REG_BIT(0x18, 12), + RCC_USART1 = _REG_BIT(0x18, 14), + RCC_TIM15 = _REG_BIT(0x18, 16), + RCC_TIM16 = _REG_BIT(0x18, 17), + RCC_TIM17 = _REG_BIT(0x18, 18), + RCC_DBGMCU = _REG_BIT(0x18, 22), + + /* APB1 peripherals */ + RCC_TIM2 = _REG_BIT(0x1C, 0), + RCC_TIM3 = _REG_BIT(0x1C, 1), + RCC_TIM6 = _REG_BIT(0x1C, 4), + RCC_TIM7 = _REG_BIT(0x1C, 5), + RCC_TIM14 = _REG_BIT(0x1C, 8), + RCC_WWDG = _REG_BIT(0x1C, 11), + RCC_SPI2 = _REG_BIT(0x1C, 14), + RCC_USART2 = _REG_BIT(0x1C, 17), + RCC_USART3 = _REG_BIT(0x1C, 18), + RCC_USART4 = _REG_BIT(0x1C, 19), + RCC_I2C1 = _REG_BIT(0x1C, 21), + RCC_I2C2 = _REG_BIT(0x1C, 22), + RCC_USB = _REG_BIT(0x1C, 23), + RCC_CAN = _REG_BIT(0x1C, 25), + RCC_CRS = _REG_BIT(0x1C, 27), + RCC_PWR = _REG_BIT(0x1C, 28), + RCC_DAC = _REG_BIT(0x1C, 29), + RCC_CEC = _REG_BIT(0x1C, 30), + + /* Advanced peripherals */ + RCC_RTC = _REG_BIT(0x20, 15),/* BDCR[15] */ +}; + +enum rcc_periph_rst { + /* APB2 peripherals */ + RST_SYSCFG = _REG_BIT(0x0C, 0), + RST_ADC = _REG_BIT(0x0C, 9), + RST_TIM1 = _REG_BIT(0x0C, 11), + RST_SPI1 = _REG_BIT(0x0C, 12), + RST_USART1 = _REG_BIT(0x0C, 14), + RST_TIM15 = _REG_BIT(0x0C, 16), + RST_TIM16 = _REG_BIT(0x0C, 17), + RST_TIM17 = _REG_BIT(0x0C, 18), + RST_DBGMCU = _REG_BIT(0x0C, 22), + + /* APB1 peripherals */ + RST_TIM2 = _REG_BIT(0x10, 0), + RST_TIM3 = _REG_BIT(0x10, 1), + RST_TIM6 = _REG_BIT(0x10, 4), + RST_TIM7 = _REG_BIT(0x10, 5), + RST_TIM14 = _REG_BIT(0x10, 8), + RST_WWDG = _REG_BIT(0x10, 11), + RST_SPI2 = _REG_BIT(0x10, 14), + RST_USART2 = _REG_BIT(0x10, 17), + RST_USART3 = _REG_BIT(0x10, 18), + RST_USART4 = _REG_BIT(0x10, 19), + RST_I2C1 = _REG_BIT(0x10, 21), + RST_I2C2 = _REG_BIT(0x10, 22), + RST_USB = _REG_BIT(0x10, 23), + RST_CAN = _REG_BIT(0x10, 25), + RST_CRS = _REG_BIT(0x10, 27), + RST_PWR = _REG_BIT(0x10, 28), + RST_DAC = _REG_BIT(0x10, 29), + RST_CEC = _REG_BIT(0x10, 30), + + /* Advanced peripherals */ + RST_BACKUPDOMAIN = _REG_BIT(0x20, 16),/* BDCR[16] */ + + /* AHB peripherals */ + RST_GPIOA = _REG_BIT(0x28, 17), + RST_GPIOB = _REG_BIT(0x28, 18), + RST_GPIOC = _REG_BIT(0x28, 19), + RST_GPIOD = _REG_BIT(0x28, 20), + RST_GPIOE = _REG_BIT(0x28, 21), + RST_GPIOF = _REG_BIT(0x28, 22), + RST_TSC = _REG_BIT(0x28, 24), +}; +#undef _REG_BIT + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + +BEGIN_DECLS + +void rcc_osc_ready_int_clear(enum rcc_osc osc); +void rcc_osc_ready_int_enable(enum rcc_osc osc); +void rcc_osc_ready_int_disable(enum rcc_osc osc); +int rcc_osc_ready_int_flag(enum rcc_osc osc); +void rcc_wait_for_osc_ready(enum rcc_osc osc); +void rcc_osc_on(enum rcc_osc osc); +void rcc_osc_off(enum rcc_osc osc); +void rcc_osc_bypass_enable(enum rcc_osc osc); +void rcc_osc_bypass_disable(enum rcc_osc osc); +void rcc_css_enable(void); +void rcc_css_disable(void); +void rcc_css_int_clear(void); +int rcc_css_int_flag(void); +void rcc_set_sysclk_source(enum rcc_osc clk); +void rcc_set_pll_multiplication_factor(uint32_t mul); +void rcc_set_ppre(uint32_t ppre); +void rcc_set_hpre(uint32_t hpre); +void rcc_set_prediv(uint32_t prediv); +void rcc_set_mco(uint32_t mcosrc); +enum rcc_osc rcc_system_clock_source(void); +void rcc_clock_setup_in_hsi_out_8mhz(void); +void rcc_clock_setup_in_hsi_out_16mhz(void); +void rcc_clock_setup_in_hsi_out_24mhz(void); +void rcc_clock_setup_in_hsi_out_32mhz(void); +void rcc_clock_setup_in_hsi_out_40mhz(void); +void rcc_clock_setup_in_hsi_out_48mhz(void); +void rcc_periph_clock_enable(enum rcc_periph_clken periph); +void rcc_periph_clock_disable(enum rcc_periph_clken periph); +void rcc_periph_reset_pulse(enum rcc_periph_rst periph); +void rcc_periph_reset_hold(enum rcc_periph_rst periph); +void rcc_periph_reset_release(enum rcc_periph_rst periph); + +END_DECLS + +#endif +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/f0/rtc.h b/libopencm3/include/libopencm3/stm32/f0/rtc.h new file mode 100644 index 0000000..8a99c24 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/rtc.h @@ -0,0 +1,36 @@ +/** @defgroup rtc_defines RTC Defines + * + * @brief Defined Constants and Types for the STM32F0xx RTC + * + * @ingroup STM32F0xx_defines + * + * @version 1.0.0 + * + * @date 5 December 2012 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_RTC_H +#define LIBOPENCM3_RTC_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/spi.h b/libopencm3/include/libopencm3/stm32/f0/spi.h new file mode 100644 index 0000000..773743e --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/spi.h @@ -0,0 +1,36 @@ +/** @defgroup spi_defines SPI Defines + * + * @brief Defined Constants and Types for the STM32F0xx SPI + * + * @ingroup STM32F0xx_defines + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_SPI_H +#define LIBOPENCM3_SPI_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/syscfg.h b/libopencm3/include/libopencm3/stm32/f0/syscfg.h new file mode 100644 index 0000000..1084543 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/syscfg.h @@ -0,0 +1,110 @@ +/** @defgroup syscfg_defines SYSCFG Defines + * + * @brief Defined Constants and Types for the STM32F0xx System Config + * + * @ingroup STM32F0xx_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2013 + * Frantisek Burian + * + * @date 13 January 2014 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_SYSCFG_H +#define LIBOPENCM3_SYSCFG_H +/**@{*/ + +/*****************************************************************************/ +/* Module definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Register definitions */ +/*****************************************************************************/ + +#define SYSCFG_CFGR1 MMIO32(SYSCFG_COMP_BASE + 0x00) +#define SYSCFG_EXTICR(i) MMIO32(SYSCFG_COMP_BASE + 0x08 + (i)*4) +#define SYSCFG_EXTICR1 SYSCFG_EXTICR(0) +#define SYSCFG_EXTICR2 SYSCFG_EXTICR(1) +#define SYSCFG_EXTICR3 SYSCFG_EXTICR(2) +#define SYSCFG_EXTICR4 SYSCFG_EXTICR(3) +#define SYSCFG_CFGR2 MMIO32(SYSCFG_COMP_BASE + 0x18) + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +/* SYSCFG_CFGR1 Values -- ---------------------------------------------------*/ + +#define SYSCFG_CFGR1_MEM_MODE_SHIFT 0 +#define SYSCFG_CFGR1_MEM_MODE (3 << SYSCFG_CFGR1_MEM_MODE_SHIFT) +#define SYSCFG_CFGR1_MEM_MODE_FLASH (0 << SYSCFG_CFGR1_MEM_MODE_SHIFT) +#define SYSCFG_CFGR1_MEM_MODE_SYSTEM (1 << SYSCFG_CFGR1_MEM_MODE_SHIFT) +#define SYSCFG_CFGR1_MEM_MODE_SRAM (3 << SYSCFG_CFGR1_MEM_MODE_SHIFT) + +#define SYSCFG_CFGR1_ADC_DMA_RMP (1 << 8) +#define SYSCFG_CFGR1_USART1_TX_DMA_RMP (1 << 9) +#define SYSCFG_CFGR1_USART1_RX_DMA_RMP (1 << 10) +#define SYSCFG_CFGR1_TIM16_DMA_RMP (1 << 11) +#define SYSCFG_CFGR1_TIM17_DMA_RMP (1 << 12) + +#define SYSCFG_CFGR1_I2C_PB6_FMPLUS (1 << 16) +#define SYSCFG_CFGR1_I2C_PB7_FMPLUS (1 << 17) +#define SYSCFG_CFGR1_I2C_PB8_FMPLUS (1 << 18) +#define SYSCFG_CFGR1_I2C_PB9_FMPLUS (1 << 19) +#define SYSCFG_CFGR1_I2C1_FMPLUS (1 << 20) +#define SYSCFG_CFGR1_I2C_PA9_FMPLUS (1 << 22) +#define SYSCFG_CFGR1_I2C_PA10_FMPLUS (1 << 23) + +/* SYSCFG_EXTICR Values -- --------------------------------------------------*/ + +#define SYSCFG_EXTICR_SKIP 4 +#define SYSCFG_EXTICR_GPIOA 0 +#define SYSCFG_EXTICR_GPIOB 1 +#define SYSCFG_EXTICR_GPIOC 2 +#define SYSCFG_EXTICR_GPIOD 3 +#define SYSCFG_EXTICR_GPIOF 5 + +/* SYSCFG_CFGR2 Values -- ---------------------------------------------------*/ + +#define SYSCFG_CFGR2_LOCKUP_LOCK (1 << 0) +#define SYSCFG_CFGR2_SRAM_PARITY_LOCK (1 << 1) +#define SYSCFG_CFGR2_PVD_LOCK (1 << 2) +#define SYSCFG_CFGR2_SRAM_PEF (1 << 8) + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + +BEGIN_DECLS + +END_DECLS +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/timer.h b/libopencm3/include/libopencm3/stm32/f0/timer.h new file mode 100644 index 0000000..eac50c2 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/timer.h @@ -0,0 +1,37 @@ +/** @defgroup timer_defines Timers Defines + * + * @brief Defined Constants and Types for the STM32F0xx Timers + * + * @ingroup STM32F0xx_defines + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_TIMER_H +#define LIBOPENCM3_TIMER_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/tsc.h b/libopencm3/include/libopencm3/stm32/f0/tsc.h new file mode 100644 index 0000000..fbd65b4 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/tsc.h @@ -0,0 +1,159 @@ +/** @defgroup tsc_defines TSC Defines + * + * @brief Defined Constants and Types for the STM32F0xx Touch Sensor + * + * @ingroup STM32F0xx_defines + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_TSC_H +#define LIBOPENCM3_TSC_H +/**@{*/ + +/*****************************************************************************/ +/* Module definitions */ +/*****************************************************************************/ + +#define TSC TSC_BASE + +/*****************************************************************************/ +/* Register definitions */ +/*****************************************************************************/ + +#define TSC_CR MMIO32(TSC_BASE + 0x00) +#define TSC_IER MMIO32(TSC_BASE + 0x04) +#define TSC_ICR MMIO32(TSC_BASE + 0x08) +#define TSC_ISR MMIO32(TSC_BASE + 0x0c) +#define TSC_IOHCR MMIO32(TSC_BASE + 0x10) +#define TSC_IOASCR MMIO32(TSC_BASE + 0x18) +#define TSC_IOSCR MMIO32(TSC_BASE + 0x20) +#define TSC_IOCCR MMIO32(TSC_BASE + 0x28) +#define TSC_IOGCSR MMIO32(TSC_BASE + 0x30) +#define TSC_IOGxCR(x) MMIO8(TSC_BASE + 0x34 + (x)*4) + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +/* TSC_CR Values ------------------------------------------------------------*/ + +#define TSC_CR_CTPH_SHIFT 28 +#define TSC_CR_CTPH (0xF << TSC_CR_CTPH_SHIFT) + +#define TSC_CR_CTPL_SHIFT 24 +#define TSC_CR_CTPL (0x0F << TSC_CR_CTPL_SHIFT) + +#define TSC_CR_SSD_SHIFT 17 +#define TSC_CR_SSD (0x7F << TSC_CR_SSD_SHIFT) + +#define TSC_CR_SSE (1 << 16) +#define TSC_CR_SSPSC (1 << 15) + +#define TSC_CR_PGPSC_SHIFT 12 +#define TSC_CR_PGPSC (7 << TSC_CR_PGPSC_SHIFT) + +#define TSC_CR_MCV_SHIFT 5 +#define TSC_CR_MCV (7 << TSC_CR_MCV_SHIFT) + +#define TSC_CR_IODEF (1 << 4) +#define TSC_CR_SYNCPOL (1 << 3) +#define TSC_CR_AM (1 << 2) +#define TSC_CR_START (1 << 1) +#define TSC_CR_TSCE (1 << 0) + +/* TSC_IER Values -----------------------------------------------------------*/ + +#define TSC_IER_MCEIE (1 << 1) +#define TSC_IER_EOAIE (1 << 0) + +/* TSC_ICR Values -----------------------------------------------------------*/ + +#define TSC_ICR_MCEIC (1 << 1) +#define TSC_ICR_EOAIC (1 << 0) + +/* TSC_ISR Values -----------------------------------------------------------*/ + +#define TSC_ISR_MCEF (1 << 1) +#define TSC_ISR_EOAF (1 << 0) + +/* TSC_IOHCR Values ---------------------------------------------------------*/ + +/* Bit helper g = [1..6] io = [1..4] */ +#define TSC_IOBIT_VAL(g, io) ((1 << ((io)-1)) << (((g)-1)*4)) + +#define TSC_IOHCR_G1(io) TSC_IOBIT_VAL(1, io) +#define TSC_IOHCR_G2(io) TSC_IOBIT_VAL(2, io) +#define TSC_IOHCR_G3(io) TSC_IOBIT_VAL(3, io) +#define TSC_IOHCR_G4(io) TSC_IOBIT_VAL(4, io) +#define TSC_IOHCR_G5(io) TSC_IOBIT_VAL(5, io) +#define TSC_IOHCR_G6(io) TSC_IOBIT_VAL(6, io) + +/* TSC_IOASCR Values --------------------------------------------------------*/ + +#define TSC_IOASCR_G1(io) TSC_IOBIT_VAL(1, io) +#define TSC_IOASCR_G2(io) TSC_IOBIT_VAL(2, io) +#define TSC_IOASCR_G3(io) TSC_IOBIT_VAL(3, io) +#define TSC_IOASCR_G4(io) TSC_IOBIT_VAL(4, io) +#define TSC_IOASCR_G5(io) TSC_IOBIT_VAL(5, io) +#define TSC_IOASCR_G6(io) TSC_IOBIT_VAL(6, io) + +/* TSC_IOSCR Values ---------------------------------------------------------*/ + +#define TSC_IOSCR_G1(io) TSC_IOBIT_VAL(1, io) +#define TSC_IOSCR_G2(io) TSC_IOBIT_VAL(2, io) +#define TSC_IOSCR_G3(io) TSC_IOBIT_VAL(3, io) +#define TSC_IOSCR_G4(io) TSC_IOBIT_VAL(4, io) +#define TSC_IOSCR_G5(io) TSC_IOBIT_VAL(5, io) +#define TSC_IOSCR_G6(io) TSC_IOBIT_VAL(6, io) + +/* TSC_IOCCR Values ---------------------------------------------------------*/ + +#define TSC_IOCCR_G1(io) TSC_IOBIT_VAL(1, io) +#define TSC_IOCCR_G2(io) TSC_IOBIT_VAL(2, io) +#define TSC_IOCCR_G3(io) TSC_IOBIT_VAL(3, io) +#define TSC_IOCCR_G4(io) TSC_IOBIT_VAL(4, io) +#define TSC_IOCCR_G5(io) TSC_IOBIT_VAL(5, io) +#define TSC_IOCCR_G6(io) TSC_IOBIT_VAL(6, io) + +/* TSC_IOGCSR Values --------------------------------------------------------*/ + +#define TSC_IOGCSR_GxE(x) (1 << ((x)-1)) +#define TSC_IOGCSR_GxS(x) (1 << ((x)+15)) + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + +BEGIN_DECLS + +END_DECLS +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f0/usart.h b/libopencm3/include/libopencm3/stm32/f0/usart.h new file mode 100644 index 0000000..8dba683 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f0/usart.h @@ -0,0 +1,343 @@ +/** @defgroup usart_defines USART Defines + * + * @brief Defined Constants and Types for the STM32F0xx USART + * + * @ingroup STM32F0xx_defines + * + * @version 1.0.0 + * + * @date 2 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_USART_H +#define LIBOPENCM3_USART_H + +/*****************************************************************************/ +/* Module definitions */ +/*****************************************************************************/ + +#define USART1 USART1_BASE +#define USART2 USART2_BASE +#define USART3 USART3_BASE +#define USART4 USART4_BASE + +/*****************************************************************************/ +/* Register definitions */ +/*****************************************************************************/ + +#define USART_CR1(usart_base) MMIO32(usart_base + 0x00) +#define USART1_CR1 USART_CR1(USART1_BASE) +#define USART2_CR1 USART_CR1(USART2_BASE) +#define USART3_CR1 USART_CR1(USART3_BASE) +#define USART4_CR1 USART_CR1(USART4_BASE) + +#define USART_CR2(usart_base) MMIO32(usart_base + 0x04) +#define USART1_CR2 USART_CR2(USART1_BASE) +#define USART2_CR2 USART_CR2(USART2_BASE) +#define USART3_CR2 USART_CR2(USART3_BASE) +#define USART4_CR2 USART_CR2(USART4_BASE) + +#define USART_CR3(usart_base) MMIO32(usart_base + 0x08) +#define USART1_CR3 USART_CR3(USART1_BASE) +#define USART2_CR3 USART_CR3(USART2_BASE) +#define USART3_CR3 USART_CR3(USART3_BASE) +#define USART4_CR3 USART_CR3(USART4_BASE) + +#define USART_BRR(usart_base) MMIO32(usart_base + 0x0c) +#define USART1_BRR USART_BRR(USART1_BASE) +#define USART2_BRR USART_BRR(USART2_BASE) +#define USART3_BRR USART_BRR(USART3_BASE) +#define USART4_BRR USART_BRR(USART4_BASE) + +#define USART_GTPR(usart_base) MMIO32(usart_base + 0x10) +#define USART1_GTPR USART_GTPR(USART1_BASE) +#define USART2_GTPR USART_GTPR(USART2_BASE) +#define USART3_GTPR USART_GTPR(USART3_BASE) +#define USART4_GTPR USART_GTPR(USART4_BASE) + +#define USART_RTOR(usart_base) MMIO32(usart_base + 0x14) +#define USART1_RTOR USART_RTOR(USART1_BASE) +#define USART2_RTOR USART_RTOR(USART2_BASE) +#define USART3_RTOR USART_RTOR(USART3_BASE) +#define USART4_RTOR USART_RTOR(USART4_BASE) + +#define USART_RQR(usart_base) MMIO32(usart_base + 0x18) +#define USART1_RQR USART_RQR(USART1_BASE) +#define USART2_RQR USART_RQR(USART2_BASE) +#define USART3_RQR USART_RQR(USART3_BASE) +#define USART4_RQR USART_RQR(USART4_BASE) + +#define USART_ISR(usart_base) MMIO32(usart_base + 0x1c) +#define USART1_ISR USART_ISR(USART1_BASE) +#define USART2_ISR USART_ISR(USART2_BASE) +#define USART3_ISR USART_ISR(USART3_BASE) +#define USART4_ISR USART_ISR(USART4_BASE) + +#define USART_ICR(usart_base) MMIO32(usart_base + 0x20) +#define USART1_ICR USART_ICR(USART1_BASE) +#define USART2_ICR USART_ICR(USART2_BASE) +#define USART3_ICR USART_ICR(USART3_BASE) +#define USART4_ICR USART_ICR(USART4_BASE) + +#define USART_RDR(usart_base) MMIO8(usart_base + 0x24) +#define USART1_RDR USART_RDR(USART1_BASE) +#define USART2_RDR USART_RDR(USART2_BASE) +#define USART3_RDR USART_RDR(USART3_BASE) +#define USART4_RDR USART_RDR(USART4_BASE) + +#define USART_TDR(usart_base) MMIO8(usart_base + 0x28) +#define USART1_TDR USART_TDR(USART1_BASE) +#define USART2_TDR USART_TDR(USART2_BASE) +#define USART3_TDR USART_TDR(USART3_BASE) +#define USART4_TDR USART_TDR(USART4_BASE) + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +/* USART_CR1 Values ---------------------------------------------------------*/ + +#define USART_CR1_M1 (1 << 28) /* F07x */ +#define USART_CR1_EOBIE (1 << 27) +#define USART_CR1_RTOIE (1 << 26) + +#define USART_CR1_DEAT_SHIFT 21 +#define USART_CR1_DEAT (0x1F << USART_CR1_DEAT_SHIFT) +#define USART_CR1_DEAT_VAL(x) ((x) << USART_CR1_DEAT_SHIFT) + +#define USART_CR1_DEDT_SHIFT 16 +#define USART_CR1_DEDT (0x1F << USART_CR1_DEDT_SHIFT) +#define USART_CR1_DEDT_VAL(x) ((x) << USART_CR1_DEDT_SHIFT) + +#define USART_CR1_OVER8 (1 << 15) +#define USART_CR1_CMIE (1 << 14) +#define USART_CR1_MME (1 << 13) +#define USART_CR1_M (1 << 12) /* Obsolete, please use M0 */ +#define USART_CR1_M0 (1 << 12) +#define USART_CR1_WAKE (1 << 11) +#define USART_CR1_PCE (1 << 10) +#define USART_CR1_PS (1 << 9) +#define USART_CR1_PEIE (1 << 8) +#define USART_CR1_TXEIE (1 << 7) +#define USART_CR1_TCIE (1 << 6) +#define USART_CR1_RXNEIE (1 << 5) +#define USART_CR1_IDLEIE (1 << 4) +#define USART_CR1_TE (1 << 3) +#define USART_CR1_RE (1 << 2) +#define USART_CR1_UESM (1 << 1) +#define USART_CR1_UE (1 << 0) + +/* USART_CR2 Values ---------------------------------------------------------*/ + +#define USART_CR2_ADD_SHIFT 24 +#define USART_CR2_ADD (0xFF << USART_CR2_ADD_SHIFT) +#define USART_CR2_ADD_VAL(x) ((x) << USART_CR2_ADD_SHIFT) + +#define USART_CR2_RTOEN (1 << 23) + +#define USART_CR2_ABRMOD_SHIFT 21 +#define USART_CR2_ABRMOD (3 << USART_CR2_ABRMOD_SHIFT) +#define USART_CR2_ABRMOD_STARTBIT (0 << USART_CR2_ABRMOD_SHIFT) +#define USART_CR2_ABRMOD_FALLTOFALL (1 << USART_CR2_ABRMOD_SHIFT) + +#define USART_CR2_ABREN (1 << 20) +#define USART_CR2_MSBFIRST (1 << 19) +#define USART_CR2_DATAINV (1 << 18) +#define USART_CR2_TXINV (1 << 17) +#define USART_CR2_RXINV (1 << 16) +#define USART_CR2_SWAP (1 << 15) +#define USART_CR2_LINEN (1 << 14) + +#define USART_CR2_STOP_SHIFT 12 +#define USART_CR2_STOP (3 << USART_CR2_STOP_SHIFT) +#define USART_CR2_STOP_1_0BIT (0 << USART_CR2_STOP_SHIFT) +#define USART_CR2_STOP_2_0BIT (2 << USART_CR2_STOP_SHIFT) +#define USART_CR2_STOP_1_5BIT (3 << USART_CR2_STOP_SHIFT) + +#define USART_CR2_CLKEN (1 << 11) +#define USART_CR2_CPOL (1 << 10) +#define USART_CR2_CPHA (1 << 9) +#define USART_CR2_LBCL (1 << 8) +#define USART_CR2_LBIDE (1 << 6) +#define USART_CR2_LBDL (1 << 5) +#define USART_CR2_ADDM (1 << 4) /* Obsolete, use ADDM7 */ +#define USART_CR2_ADDM7 (1 << 4) + +/* USART_CR3 Values ---------------------------------------------------------*/ + +#define USART_CR3_WUFIE (1 << 22) + +#define USART_CR3_WUS_SHIFT 20 +#define USART_CR3_WUS (3 << USART_CR3_WUS_SHIFT) +#define USART_CR3_WUS_ADDRMATCH (0 << USART_CR3_WUS_SHIFT) +#define USART_CR3_WUS_STARTBIT (2 << USART_CR3_WUS_SHIFT) +#define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) + +#define USART_CR3_SCARCNT_SHIFT 17 +#define USART_CR3_SCARCNT (7 << USART_CR3_SCARCNT_SHIFT) +#define USART_CR3_SCARCNT_DISABLE (0 << USART_CR3_SCARCNT_SHIFT) +#define USART_CR3_SCARCNT_VAL(x) ((x) << USART_CR3_SCARCNT_SHIFT) + +#define USART_CR3_DEP (1 << 15) +#define USART_CR3_DEM (1 << 14) +#define USART_CR3_DDRE (1 << 13) +#define USART_CR3_OVRDIS (1 << 12) +#define USART_CR3_ONEBIT (1 << 11) +#define USART_CR3_CTSIE (1 << 10) +#define USART_CR3_CTSE (1 << 9) +#define USART_CR3_RTSE (1 << 8) +#define USART_CR3_DMAT (1 << 7) +#define USART_CR3_DMAR (1 << 6) +#define USART_CR3_SCEN (1 << 5) +#define USART_CR3_NACK (1 << 4) +#define USART_CR3_HDSEL (1 << 3) +#define USART_CR3_IRLP (1 << 2) +#define USART_CR3_IREN (1 << 1) +#define USART_CR3_EIE (1 << 0) + +/* USART_GTPR Values --------------------------------------------------------*/ + +#define USART_GTPR_GT_SHIFT 8 +#define USART_GTPR_GT (0xFF << USART_GTPR_GT_SHIFT) +#define USART_GTPR_GT_VAL(x) ((x) << USART_GTPR_GT_SHIFT) + +#define USART_GTPR_PSC_SHIFT 0 +#define USART_GTPR_PSC (0xFF << USART_GTPR_PSC_SHIFT) +#define USART_GTPR_PSC_VAL(x) ((x) << USART_GTPR_PSC_SHIFT) + + +/* USART_RTOR Values --------------------------------------------------------*/ + +#define USART_RTOR_BLEN_SHIFT 24 +#define USART_RTOR_BLEN (0xFF << USART_RTOR_BLEN_SHIFT) +#define USART_RTOR_BLEN_VAL(x) ((x) << USART_RTOR_BLEN_SHIFT) + +#define USART_RTOR_RTO_SHIFT 0 +#define USART_RTOR_RTO (0xFF << USART_RTOR_RTO_SHIFT) +#define USART_RTOR_RTO_VAL(x) ((x) << USART_RTOR_RTO_SHIFT) + +/* USART_RQR Values ---------------------------------------------------------*/ + +#define USART_RQR_TXFRQ (1 << 4) +#define USART_RQR_RXFRQ (1 << 3) +#define USART_RQR_MMRQ (1 << 2) +#define USART_RQR_SBKRQ (1 << 1) +#define USART_RQR_ABRRQ (1 << 0) + +/* USART_ISR Values ---------------------------------------------------------*/ + +#define USART_ISR_REACK (1 << 22) +#define USART_ISR_TEACK (1 << 21) +#define USART_ISR_WUF (1 << 20) +#define USART_ISR_RWU (1 << 19) +#define USART_ISR_SBKF (1 << 18) +#define USART_ISR_CMF (1 << 17) +#define USART_ISR_BUSY (1 << 16) +#define USART_ISR_ABRF (1 << 15) +#define USART_ISR_ABRE (1 << 14) +#define USART_ISR_EOBF (1 << 12) +#define USART_ISR_RTOF (1 << 11) +#define USART_ISR_CTS (1 << 10) +#define USART_ISR_CTSIF (1 << 9) +#define USART_ISR_LBDF (1 << 8) +#define USART_ISR_TXE (1 << 7) +#define USART_ISR_TC (1 << 6) +#define USART_ISR_RXNE (1 << 5) +#define USART_ISR_IDLE (1 << 4) +#define USART_ISR_ORE (1 << 3) +#define USART_ISR_NF (1 << 2) +#define USART_ISR_FE (1 << 1) +#define USART_ISR_PE (1 << 0) + +/* USART_ICR Values ---------------------------------------------------------*/ + +#define USART_ICR_WUCF (1 << 20) +#define USART_ICR_CMCF (1 << 17) +#define USART_ICR_EOBCF (1 << 12) +#define USART_ICR_RTOCF (1 << 11) +#define USART_ICR_CTSCF (1 << 9) +#define USART_ICR_LBDCF (1 << 8) +#define USART_ICR_TCCF (1 << 6) +#define USART_ICR_IDLECF (1 << 4) +#define USART_ICR_ORECF (1 << 3) +#define USART_ICR_NCF (1 << 2) +#define USART_ICR_FECF (1 << 1) +#define USART_ICR_PECF (1 << 0) + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +#define USART_PARITY (USART_CR1_PCE | USART_CR1_PS) +#define USART_PARITY_NONE (0) +#define USART_PARITY_EVEN (USART_CR1_PCE) +#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) + +#define USART_MODE (USART_CR1_TE | USART_CR1_RE) +#define USART_MODE_NONE (0) +#define USART_MODE_RX (USART_CR1_RE) +#define USART_MODE_TX (USART_CR1_TE) +#define USART_MODE_TX_RX (USART_CR1_TE | USART_CR1_RE) + +#define USART_FLOWCONTROL (USART_CR3_RTSE | USART_CR3_CTSE) +#define USART_FLOWCONTROL_NONE (0) +#define USART_FLOWCONTROL_RTS (USART_CR3_RTSE) +#define USART_FLOWCONTROL_CTS (USART_CR3_CTSE) +#define USART_FLOWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) + +/*****************************************************************************/ +/* API Functions */ +/*****************************************************************************/ + +BEGIN_DECLS + +void usart_set_baudrate(uint32_t usart, uint32_t baud); +void usart_set_databits(uint32_t usart, uint32_t bits); +void usart_set_stopbits(uint32_t usart, uint32_t stopbits); +void usart_set_parity(uint32_t usart, uint32_t parity); +void usart_set_mode(uint32_t usart, uint32_t mode); +void usart_set_flow_control(uint32_t usart, uint32_t flowcontrol); +void usart_enable(uint32_t usart); +void usart_disable(uint32_t usart); +void usart_send(uint32_t usart, uint8_t data); +uint8_t usart_recv(uint32_t usart); +void usart_wait_send_ready(uint32_t usart); +void usart_wait_recv_ready(uint32_t usart); +void usart_send_blocking(uint32_t usart, uint8_t data); +uint8_t usart_recv_blocking(uint32_t usart); +void usart_enable_rx_dma(uint32_t usart); +void usart_disable_rx_dma(uint32_t usart); +void usart_enable_tx_dma(uint32_t usart); +void usart_disable_tx_dma(uint32_t usart); +void usart_enable_rx_interrupt(uint32_t usart); +void usart_disable_rx_interrupt(uint32_t usart); +void usart_enable_tx_interrupt(uint32_t usart); +void usart_disable_tx_interrupt(uint32_t usart); +void usart_enable_error_interrupt(uint32_t usart); +void usart_disable_error_interrupt(uint32_t usart); +bool usart_get_flag(uint32_t usart, uint32_t flag); +bool usart_get_interrupt_source(uint32_t usart, uint32_t flag); + +END_DECLS + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f1/adc.h b/libopencm3/include/libopencm3/stm32/f1/adc.h new file mode 100644 index 0000000..ec7cabc --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f1/adc.h @@ -0,0 +1,420 @@ +/** @defgroup adc_defines ADC Defines + +@brief Defined Constants and Types for the STM32F1xx Analog to Digital +Converters + +@ingroup STM32F1xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2009 +Edward Cheeseman + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Edward Cheeseman + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#ifndef LIBOPENCM3_ADC_H +#define LIBOPENCM3_ADC_H + +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ +#define ADC_JOFR1(block) MMIO32(block + 0x14) +#define ADC_JOFR2(block) MMIO32(block + 0x18) +#define ADC_JOFR3(block) MMIO32(block + 0x1c) +#define ADC_JOFR4(block) MMIO32(block + 0x20) + +/* ADC watchdog high threshold register (ADC_HTR) */ +#define ADC_HTR(block) MMIO32(block + 0x24) + +/* ADC watchdog low threshold register (ADC_LTR) */ +#define ADC_LTR(block) MMIO32(block + 0x28) + +/* ADC regular sequence register 1 (ADC_SQR1) */ +#define ADC_SQR1(block) MMIO32(block + 0x2c) + +/* ADC regular sequence register 2 (ADC_SQR2) */ +#define ADC_SQR2(block) MMIO32(block + 0x30) + +/* ADC regular sequence register 3 (ADC_SQR3) */ +#define ADC_SQR3(block) MMIO32(block + 0x34) + +/* ADC injected sequence register (ADC_JSQR) */ +#define ADC_JSQR(block) MMIO32(block + 0x38) + +/* ADC injected data register x (ADC_JDRx) (x=1..4) */ +#define ADC_JDR1(block) MMIO32(block + 0x3c) +#define ADC_JDR2(block) MMIO32(block + 0x40) +#define ADC_JDR3(block) MMIO32(block + 0x44) +#define ADC_JDR4(block) MMIO32(block + 0x48) + +/* ADC regular data register (ADC_DR) */ +#define ADC_DR(block) MMIO32(block + 0x4c) + +/* --- ADC Channels ------------------------------------------------------- */ +#define ADC_CHANNEL_TEMP ADC_CHANNEL16 +#define ADC_CHANNEL_VREFINT ADC_CHANNEL17 + + +/* --- ADC_CR1 values ------------------------------------------------------ */ + +/* Note: Bits [21:20] are reserved, and must be kept at reset value. */ + +/* DUALMOD[3:0]: Dual mode selection. (ADC1 only) */ +/* Legend: + * IND: Independent mode. + * CRSISM: Combined regular simultaneous + injected simultaneous mode. + * CRSATM: Combined regular simultaneous + alternate trigger mode. + * CISFIM: Combined injected simultaneous + fast interleaved mode. + * CISSIM: Combined injected simultaneous + slow interleaved mode. + * ISM: Injected simultaneous mode only. + * RSM: Regular simultaneous mode only. + * FIM: Fast interleaved mode only. + * SIM: Slow interleaved mode only. + * ATM: Alternate trigger mode only. + */ +/****************************************************************************/ +/* ADC_CR1 DUALMOD[3:0] ADC Mode Selection */ +/** @defgroup adc_cr1_dualmod ADC Mode Selection +@ingroup adc_defines + +@{*/ +/** Independent (non-dual) mode */ +#define ADC_CR1_DUALMOD_IND (0x0 << 16) +/** Combined regular simultaneous + injected simultaneous mode. */ +#define ADC_CR1_DUALMOD_CRSISM (0x1 << 16) +/** Combined regular simultaneous + alternate trigger mode. */ +#define ADC_CR1_DUALMOD_CRSATM (0x2 << 16) +/** Combined injected simultaneous + fast interleaved mode. */ +#define ADC_CR1_DUALMOD_CISFIM (0x3 << 16) +/** Combined injected simultaneous + slow interleaved mode. */ +#define ADC_CR1_DUALMOD_CISSIM (0x4 << 16) +/** Injected simultaneous mode only. */ +#define ADC_CR1_DUALMOD_ISM (0x5 << 16) +/** Regular simultaneous mode only. */ +#define ADC_CR1_DUALMOD_RSM (0x6 << 16) +/** Fast interleaved mode only. */ +#define ADC_CR1_DUALMOD_FIM (0x7 << 16) +/** Slow interleaved mode only. */ +#define ADC_CR1_DUALMOD_SIM (0x8 << 16) +/** Alternate trigger mode only. */ +#define ADC_CR1_DUALMOD_ATM (0x9 << 16) +/**@}*/ +#define ADC_CR1_DUALMOD_MASK (0xF << 16) +#define ADC_CR1_DUALMOD_SHIFT 16 + +#define ADC_CR1_AWDCH_MAX 17 + +/* --- ADC_CR2 values ------------------------------------------------------ */ + +/* TSVREFE: */ /** Temperature sensor and V_REFINT enable. (ADC1 only!) */ +#define ADC_CR2_TSVREFE (1 << 23) + +/* SWSTART: */ /** Start conversion of regular channels. */ +#define ADC_CR2_SWSTART (1 << 22) + +/* JSWSTART: */ /** Start conversion of injected channels. */ +#define ADC_CR2_JSWSTART (1 << 21) + +/* EXTTRIG: */ /** External trigger conversion mode for regular channels. */ +#define ADC_CR2_EXTTRIG (1 << 20) + +/* EXTSEL[2:0]: External event select for regular group. */ +/* The following are only valid for ADC1 and ADC2. */ +/****************************************************************************/ +/* ADC_CR2 EXTSEL[2:0] ADC Trigger Identifier for ADC1 and ADC2 */ +/** @defgroup adc_trigger_regular_12 ADC Trigger Identifier for ADC1 and ADC2 +@ingroup adc_defines + +@{*/ +/** Timer 1 Compare Output 1 */ +#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 17) +/** Timer 1 Compare Output 2 */ +#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 17) +/** Timer 1 Compare Output 3 */ +#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17) +/** Timer 2 Compare Output 2 */ +#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 17) +/** Timer 3 Trigger Output */ +#define ADC_CR2_EXTSEL_TIM3_TRGO (0x4 << 17) +/** Timer 4 Compare Output 4 */ +#define ADC_CR2_EXTSEL_TIM4_CC4 (0x5 << 17) +/** External Interrupt 11 */ +#define ADC_CR2_EXTSEL_EXTI11 (0x6 << 17) +/** Software Trigger */ +#define ADC_CR2_EXTSEL_SWSTART (0x7 << 17) +/**@}*/ + +/* The following are only valid for ADC3 */ +/****************************************************************************/ +/* ADC_CR2 EXTSEL[2:0] ADC Trigger Identifier for ADC3 */ +/** @defgroup adc_trigger_regular_3 ADC Trigger Identifier for ADC3 +@ingroup adc_defines + +@{*/ +/** Timer 2 Compare Output 1 */ +#define ADC_CR2_EXTSEL_TIM3_CC1 (0x0 << 17) +/** Timer 2 Compare Output 3 */ +#define ADC_CR2_EXTSEL_TIM2_CC3 (0x1 << 17) +/** Timer 1 Compare Output 3 */ +#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 17) +/** Timer 8 Compare Output 1 */ +#define ADC_CR2_EXTSEL_TIM8_CC1 (0x3 << 17) +/** Timer 8 Trigger Output */ +#define ADC_CR2_EXTSEL_TIM8_TRGO (0x4 << 17) +/** Timer 5 Compare Output 1 */ +#define ADC_CR2_EXTSEL_TIM5_CC1 (0x5 << 17) +/** Timer 5 Compare Output 3 */ +#define ADC_CR2_EXTSEL_TIM5_CC3 (0x6 << 17) +/**@}*/ + +#define ADC_CR2_EXTSEL_MASK (0x7 << 17) +#define ADC_CR2_EXTSEL_SHIFT 17 + +/* Note: Bit 16 is reserved, must be kept at reset value. */ + +/* JEXTTRIG: External trigger conversion mode for injected channels. */ +#define ADC_CR2_JEXTTRIG (1 << 15) + +/* JEXTSEL[2:0]: External event selection for injected group. */ +/* The following are only valid for ADC1 and ADC2. */ +/****************************************************************************/ +/* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC1 and ADC2 */ +/** @defgroup adc_trigger_injected_12 ADC Injected Trigger Identifier for ADC1 +and ADC2 +@ingroup adc_defines + +@{*/ +/** Timer 1 Trigger Output */ +#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12) +/** Timer 1 Compare Output 4 */ +#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12) +/** Timer 2 Trigger Output */ +#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x2 << 12) +/** Timer 2 Compare Output 1 */ +#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x3 << 12) +/** Timer 3 Compare Output 4 */ +#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x4 << 12) +/** Timer 4 Trigger Output */ +#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x5 << 12) +/** External Interrupt 15 */ +#define ADC_CR2_JEXTSEL_EXTI15 (0x6 << 12) +/** Injected Software Trigger */ +#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */ +/**@}*/ + +/* The following are the different meanings for ADC3 only. */ +/****************************************************************************/ +/* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC3 */ +/** @defgroup adc_trigger_injected_3 ADC Injected Trigger Identifier for ADC3 +@ingroup adc_defines + +@{*/ +/** Timer 1 Trigger Output */ +#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x0 << 12) +/** Timer 1 Compare Output 4 */ +#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x1 << 12) +/** Timer 4 Compare Output 3 */ +#define ADC_CR2_JEXTSEL_TIM4_CC3 (0x2 << 12) +/** Timer 8 Compare Output 2 */ +#define ADC_CR2_JEXTSEL_TIM8_CC2 (0x3 << 12) +/** Timer 8 Compare Output 4 */ +#define ADC_CR2_JEXTSEL_TIM8_CC4 (0x4 << 12) +/** Timer 5 Trigger Output */ +#define ADC_CR2_JEXTSEL_TIM5_TRGO (0x5 << 12) +/** Timer 5 Compare Output 4 */ +#define ADC_CR2_JEXTSEL_TIM5_CC4 (0x6 << 12) +/** Injected Software Trigger */ +#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */ +/**@}*/ + +#define ADC_CR2_JEXTSEL_MASK (0x7 << 12) +#define ADC_CR2_JEXTSEL_SHIFT 12 + +/* ALIGN: Data alignment. */ +#define ADC_CR2_ALIGN_RIGHT (0 << 11) +#define ADC_CR2_ALIGN_LEFT (1 << 11) +#define ADC_CR2_ALIGN (1 << 11) + +/* Note: Bits [10:9] are reserved and must be kept at reset value. */ + +/* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */ +#define ADC_CR2_DMA (1 << 8) + +/* Note: Bits [7:4] are reserved and must be kept at reset value. */ + +/* RSTCAL: Reset calibration. */ +#define ADC_CR2_RSTCAL (1 << 3) + +/* CAL: A/D Calibration. */ +#define ADC_CR2_CAL (1 << 2) + +/* CONT: Continous conversion. */ +#define ADC_CR2_CONT (1 << 1) + +/* ADON: A/D converter On/Off. */ +/* Note: If any other bit in this register apart from ADON is changed at the + * same time, then conversion is not triggered. This is to prevent triggering + * an erroneous conversion. + * Conclusion: Must be separately written. + */ +#define ADC_CR2_ADON (1 << 0) + +/* --- ADC_SMPR1 values ---------------------------------------------------- */ +#define ADC_SMPR1_SMP17_LSB 21 +#define ADC_SMPR1_SMP16_LSB 18 +#define ADC_SMPR1_SMP15_LSB 15 +#define ADC_SMPR1_SMP14_LSB 12 +#define ADC_SMPR1_SMP13_LSB 9 +#define ADC_SMPR1_SMP12_LSB 6 +#define ADC_SMPR1_SMP11_LSB 3 +#define ADC_SMPR1_SMP10_LSB 0 +#define ADC_SMPR1_SMP17_MSK (0x7 << ADC_SMP17_LSB) +#define ADC_SMPR1_SMP16_MSK (0x7 << ADC_SMP16_LSB) +#define ADC_SMPR1_SMP15_MSK (0x7 << ADC_SMP15_LSB) +#define ADC_SMPR1_SMP14_MSK (0x7 << ADC_SMP14_LSB) +#define ADC_SMPR1_SMP13_MSK (0x7 << ADC_SMP13_LSB) +#define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMP12_LSB) +#define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMP11_LSB) +#define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMP10_LSB) + +/* --- ADC_SMPR2 values ---------------------------------------------------- */ + +#define ADC_SMPR2_SMP9_LSB 27 +#define ADC_SMPR2_SMP8_LSB 24 +#define ADC_SMPR2_SMP7_LSB 21 +#define ADC_SMPR2_SMP6_LSB 18 +#define ADC_SMPR2_SMP5_LSB 15 +#define ADC_SMPR2_SMP4_LSB 12 +#define ADC_SMPR2_SMP3_LSB 9 +#define ADC_SMPR2_SMP2_LSB 6 +#define ADC_SMPR2_SMP1_LSB 3 +#define ADC_SMPR2_SMP0_LSB 0 +#define ADC_SMPR2_SMP9_MSK (0x7 << ADC_SMP9_LSB) +#define ADC_SMPR2_SMP8_MSK (0x7 << ADC_SMP8_LSB) +#define ADC_SMPR2_SMP7_MSK (0x7 << ADC_SMP7_LSB) +#define ADC_SMPR2_SMP6_MSK (0x7 << ADC_SMP6_LSB) +#define ADC_SMPR2_SMP5_MSK (0x7 << ADC_SMP5_LSB) +#define ADC_SMPR2_SMP4_MSK (0x7 << ADC_SMP4_LSB) +#define ADC_SMPR2_SMP3_MSK (0x7 << ADC_SMP3_LSB) +#define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMP2_LSB) +#define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMP1_LSB) +#define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMP0_LSB) + +/* --- ADC_SMPRx values --------------------------------------------------- */ +/****************************************************************************/ +/* ADC_SMPRG ADC Sample Time Selection for Channels */ +/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels +@ingroup adc_defines + +@{*/ +#define ADC_SMPR_SMP_1DOT5CYC 0x0 +#define ADC_SMPR_SMP_7DOT5CYC 0x1 +#define ADC_SMPR_SMP_13DOT5CYC 0x2 +#define ADC_SMPR_SMP_28DOT5CYC 0x3 +#define ADC_SMPR_SMP_41DOT5CYC 0x4 +#define ADC_SMPR_SMP_55DOT5CYC 0x5 +#define ADC_SMPR_SMP_71DOT5CYC 0x6 +#define ADC_SMPR_SMP_239DOT5CYC 0x7 +/**@}*/ + + +/* --- ADC_SQR1 values ----------------------------------------------------- */ + +#define ADC_SQR_MAX_CHANNELS_REGULAR 16 + +#define ADC_SQR1_SQ16_LSB 15 +#define ADC_SQR1_SQ15_LSB 10 +#define ADC_SQR1_SQ14_LSB 5 +#define ADC_SQR1_SQ13_LSB 0 +#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB) +#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB) +#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB) +#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB) +#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB) + +/* --- ADC_SQR2 values ----------------------------------------------------- */ + +#define ADC_SQR2_SQ12_LSB 25 +#define ADC_SQR2_SQ11_LSB 20 +#define ADC_SQR2_SQ10_LSB 15 +#define ADC_SQR2_SQ9_LSB 10 +#define ADC_SQR2_SQ8_LSB 5 +#define ADC_SQR2_SQ7_LSB 0 +#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB) +#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB) +#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB) +#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB) +#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB) +#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB) + +/* --- ADC_SQR3 values ----------------------------------------------------- */ + +#define ADC_SQR3_SQ6_LSB 25 +#define ADC_SQR3_SQ5_LSB 20 +#define ADC_SQR3_SQ4_LSB 15 +#define ADC_SQR3_SQ3_LSB 10 +#define ADC_SQR3_SQ2_LSB 5 +#define ADC_SQR3_SQ1_LSB 0 +#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB) +#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB) +#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB) +#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB) +#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB) +#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB) + +/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ + +#define ADC_JDATA_LSB 0 +#define ADC_DATA_LSB 0 +#define ADC_ADC2DATA_LSB 16 /* ADC1 only (dual mode) */ +#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB) +#define ADC_DATA_MSK (0xffff << ADC_DA) +#define ADC_ADC2DATA_MSK (0xffff << ADC_ADC2DATA_LSB) + /* ADC1 only (dual mode) */ + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void adc_start_conversion_direct(uint32_t adc); +void adc_set_single_channel(uint32_t adc, uint8_t channel); +void adc_set_dual_mode(uint32_t mode); +void adc_enable_temperature_sensor(uint32_t adc); +void adc_disable_temperature_sensor(uint32_t adc); +void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger); +void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger); +void adc_reset_calibration(uint32_t adc); +void adc_calibration(uint32_t adc); +void adc_on(uint32_t adc) + LIBOPENCM3_DEPRECATED("will be removed in the first release"); + +END_DECLS + +#endif +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/f1/bkp.h b/libopencm3/include/libopencm3/stm32/f1/bkp.h new file mode 100644 index 0000000..3d36a1f --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f1/bkp.h @@ -0,0 +1,205 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_BKP_H +#define LIBOPENCM3_BKP_H + +/* --- BKP registers ------------------------------------------------------- */ + +/* Backup data register 1 (BKP_DR1) */ +#define BKP_DR1 MMIO32(BACKUP_REGS_BASE + 0x04) + +/* Backup data register 2 (BKP_DR2) */ +#define BKP_DR2 MMIO32(BACKUP_REGS_BASE + 0x08) + +/* Backup data register 3 (BKP_DR3) */ +#define BKP_DR3 MMIO32(BACKUP_REGS_BASE + 0x0C) + +/* Backup data register 4 (BKP_DR4) */ +#define BKP_DR4 MMIO32(BACKUP_REGS_BASE + 0x10) + +/* Backup data register 5 (BKP_DR5) */ +#define BKP_DR5 MMIO32(BACKUP_REGS_BASE + 0x14) + +/* Backup data register 6 (BKP_DR6) */ +#define BKP_DR6 MMIO32(BACKUP_REGS_BASE + 0x18) + +/* Backup data register 7 (BKP_DR7) */ +#define BKP_DR7 MMIO32(BACKUP_REGS_BASE + 0x1C) + +/* Backup data register 8 (BKP_DR8) */ +#define BKP_DR8 MMIO32(BACKUP_REGS_BASE + 0x20) + +/* Backup data register 9 (BKP_DR9) */ +#define BKP_DR9 MMIO32(BACKUP_REGS_BASE + 0x24) + +/* Backup data register 10 (BKP_DR10) */ +#define BKP_DR10 MMIO32(BACKUP_REGS_BASE + 0x28) + +/* RTC clock calibration register (BKP_RTCCR) */ +#define BKP_RTCCR MMIO32(BACKUP_REGS_BASE + 0x2C) + +/* Backup control register (BKP_CR) */ +#define BKP_CR MMIO32(BACKUP_REGS_BASE + 0x30) + +/* Backup control/status register (BKP_CSR) */ +#define BKP_CSR MMIO32(BACKUP_REGS_BASE + 0x34) + +/* Backup data register 11 (BKP_DR11) */ +#define BKP_DR11 MMIO32(BACKUP_REGS_BASE + 0x40) + +/* Backup data register 12 (BKP_DR12) */ +#define BKP_DR12 MMIO32(BACKUP_REGS_BASE + 0x44) + +/* Backup data register 13 (BKP_DR13) */ +#define BKP_DR13 MMIO32(BACKUP_REGS_BASE + 0x48) + +/* Backup data register 14 (BKP_DR14) */ +#define BKP_DR14 MMIO32(BACKUP_REGS_BASE + 0x4C) + +/* Backup data register 15 (BKP_DR15) */ +#define BKP_DR15 MMIO32(BACKUP_REGS_BASE + 0x50) + +/* Backup data register 16 (BKP_DR16) */ +#define BKP_DR16 MMIO32(BACKUP_REGS_BASE + 0x54) + +/* Backup data register 17 (BKP_DR17) */ +#define BKP_DR17 MMIO32(BACKUP_REGS_BASE + 0x58) + +/* Backup data register 18 (BKP_DR18) */ +#define BKP_DR18 MMIO32(BACKUP_REGS_BASE + 0x5C) + +/* Backup data register 19 (BKP_DR19) */ +#define BKP_DR19 MMIO32(BACKUP_REGS_BASE + 0x60) + +/* Backup data register 20 (BKP_DR20) */ +#define BKP_DR20 MMIO32(BACKUP_REGS_BASE + 0x64) + +/* Backup data register 21 (BKP_DR21) */ +#define BKP_DR21 MMIO32(BACKUP_REGS_BASE + 0x68) + +/* Backup data register 22 (BKP_DR22) */ +#define BKP_DR22 MMIO32(BACKUP_REGS_BASE + 0x6C) + +/* Backup data register 23 (BKP_DR23) */ +#define BKP_DR23 MMIO32(BACKUP_REGS_BASE + 0x70) + +/* Backup data register 24 (BKP_DR24) */ +#define BKP_DR24 MMIO32(BACKUP_REGS_BASE + 0x74) + +/* Backup data register 25 (BKP_DR25) */ +#define BKP_DR25 MMIO32(BACKUP_REGS_BASE + 0x78) + +/* Backup data register 26 (BKP_DR26) */ +#define BKP_DR26 MMIO32(BACKUP_REGS_BASE + 0x7C) + +/* Backup data register 27 (BKP_DR27) */ +#define BKP_DR27 MMIO32(BACKUP_REGS_BASE + 0x80) + +/* Backup data register 28 (BKP_DR28) */ +#define BKP_DR28 MMIO32(BACKUP_REGS_BASE + 0x84) + +/* Backup data register 29 (BKP_DR29) */ +#define BKP_DR29 MMIO32(BACKUP_REGS_BASE + 0x88) + +/* Backup data register 30 (BKP_DR30) */ +#define BKP_DR30 MMIO32(BACKUP_REGS_BASE + 0x8C) + +/* Backup data register 31 (BKP_DR31) */ +#define BKP_DR31 MMIO32(BACKUP_REGS_BASE + 0x90) + +/* Backup data register 32 (BKP_DR32) */ +#define BKP_DR32 MMIO32(BACKUP_REGS_BASE + 0x94) + +/* Backup data register 33 (BKP_DR33) */ +#define BKP_DR33 MMIO32(BACKUP_REGS_BASE + 0x98) + +/* Backup data register 34 (BKP_DR34) */ +#define BKP_DR34 MMIO32(BACKUP_REGS_BASE + 0x9C) + +/* Backup data register 35 (BKP_DR35) */ +#define BKP_DR35 MMIO32(BACKUP_REGS_BASE + 0xA0) + +/* Backup data register 36 (BKP_DR36) */ +#define BKP_DR36 MMIO32(BACKUP_REGS_BASE + 0xA4) + +/* Backup data register 37 (BKP_DR37) */ +#define BKP_DR37 MMIO32(BACKUP_REGS_BASE + 0xA8) + +/* Backup data register 38 (BKP_DR38) */ +#define BKP_DR38 MMIO32(BACKUP_REGS_BASE + 0xAC) + +/* Backup data register 39 (BKP_DR39) */ +#define BKP_DR39 MMIO32(BACKUP_REGS_BASE + 0xB0) + +/* Backup data register 40 (BKP_DR40) */ +#define BKP_DR40 MMIO32(BACKUP_REGS_BASE + 0xB4) + +/* Backup data register 41 (BKP_DR41) */ +#define BKP_DR41 MMIO32(BACKUP_REGS_BASE + 0xB8) + +/* Backup data register 42 (BKP_DR42) */ +#define BKP_DR42 MMIO32(BACKUP_REGS_BASE + 0xBC) + +/* --- BKP_RTCCR values ---------------------------------------------------- */ + +/* ASOS: Alarm or second output selection */ +#define BKP_RTCCR_ASOS (1 << 9) + +/* ASOE: Alarm or second output enable */ +#define BKP_RTCCR_ASOE (1 << 8) + +/* CCO: Calibration clock output */ +#define BKP_RTCCR_CCO (1 << 7) + +/* CAL[6:0]: Calibration value */ +#define BKP_RTCCR_CAL_LSB 0 + +/* --- BKP_CR values ------------------------------------------------------- */ + +/* TPAL: TAMPER pin active level */ +#define BKP_CR_TAL (1 << 1) + +/* TPE: TAMPER pin enable */ +#define BKP_CR_TPE (1 << 0) + +/* --- BKP_CSR values ------------------------------------------------------ */ + +/* TIF: Tamper interrupt flag */ +#define BKP_CSR_TIF (1 << 9) + +/* TEF: Tamper event flag */ +#define BKP_CSR_TEF (1 << 8) + +/* TPIE: TAMPER pin interrupt enable */ +#define BKP_CSR_TPIE (1 << 2) + +/* CTI: Clear tamper interrupt */ +#define BKP_CSR_CTI (1 << 1) + +/* CTE: Clear tamper event */ +#define BKP_CSR_CTE (1 << 0) + +/* --- BKP_DRx values ------------------------------------------------------ */ + +/* Bits[15:0]: Backup data */ + +/* --- BKP function prototypes --------------------------------------------- */ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f1/crc.h b/libopencm3/include/libopencm3/stm32/f1/crc.h new file mode 100644 index 0000000..a35bf49 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f1/crc.h @@ -0,0 +1,38 @@ +/** @defgroup crc_defines CRC Defines + +@brief libopencm3 Defined Constants and Types for the STM32F1xx CRC +Generator + +@ingroup STM32F1xx_defines + +@version 1.0.0 + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CRC_H +#define LIBOPENCM3_CRC_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f1/dac.h b/libopencm3/include/libopencm3/stm32/f1/dac.h new file mode 100644 index 0000000..145df73 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f1/dac.h @@ -0,0 +1,37 @@ +/** @defgroup dac_defines DAC Defines + +@brief Defined Constants and Types for the STM32F1xx DAC + +@ingroup STM32F1xx_defines + +@version 1.0.0 + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DAC_H +#define LIBOPENCM3_DAC_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f1/dma.h b/libopencm3/include/libopencm3/stm32/f1/dma.h new file mode 100644 index 0000000..ac73090 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f1/dma.h @@ -0,0 +1,37 @@ +/** @defgroup dma_defines DMA Defines + +@ingroup STM32F1xx_defines + +@brief Defined Constants and Types for the STM32F1xx DMA Controller + +@version 1.0.0 + +@date 30 November 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DMA_H +#define LIBOPENCM3_DMA_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f1/doc-stm32f1.h b/libopencm3/include/libopencm3/stm32/f1/doc-stm32f1.h new file mode 100644 index 0000000..4e1407e --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f1/doc-stm32f1.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 STM32F1 + +@version 1.0.0 + +@date 7 September 2012 + +API documentation for ST Microelectronics STM32F1 Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup STM32F1xx STM32F1xx +Libraries for ST Microelectronics STM32F1xx series. + +@version 1.0.0 + +@date 7 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup STM32F1xx_defines STM32F1xx Defines + +@brief Defined Constants and Types for the STM32F1xx series + +@version 1.0.0 + +@date 7 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/libopencm3/include/libopencm3/stm32/f1/ethernet.h b/libopencm3/include/libopencm3/stm32/f1/ethernet.h new file mode 100644 index 0000000..5598cce --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f1/ethernet.h @@ -0,0 +1,210 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#ifndef LIBOPENCM3_ETHERNET_H +#define LIBOPENCM3_ETHERNET_H + +/* Ethernet MAC registers */ +#define ETH_MACCR MMIO32(ETHERNET_BASE + 0x00) +#define ETH_MACFFR MMIO32(ETHERNET_BASE + 0x04) +#define ETH_MACHTHR MMIO32(ETHERNET_BASE + 0x08) +#define ETH_MACHTLR MMIO32(ETHERNET_BASE + 0x0C) +#define ETH_MACMIIAR MMIO32(ETHERNET_BASE + 0x10) +#define ETH_MACMIIDR MMIO32(ETHERNET_BASE + 0x14) +#define ETH_MACFCR MMIO32(ETHERNET_BASE + 0x18) +#define ETH_MACVLANTR MMIO32(ETHERNET_BASE + 0x1C) +#define ETH_MACRWUFFR MMIO32(ETHERNET_BASE + 0x28) +#define ETH_MACPMTCSR MMIO32(ETHERNET_BASE + 0x2C) +#define ETH_MACSR MMIO32(ETHERNET_BASE + 0x38) +#define ETH_MACIMR MMIO32(ETHERNET_BASE + 0x3C) +#define ETH_MACA0HR MMIO32(ETHERNET_BASE + 0x40) +#define ETH_MACA0LR MMIO32(ETHERNET_BASE + 0x44) +#define ETH_MACA1HR MMIO32(ETHERNET_BASE + 0x48) +#define ETH_MACA1LR MMIO32(ETHERNET_BASE + 0x4C) +#define ETH_MACA2HR MMIO32(ETHERNET_BASE + 0x50) +#define ETH_MACA2LR MMIO32(ETHERNET_BASE + 0x54) +#define ETH_MACA3HR MMIO32(ETHERNET_BASE + 0x58) +#define ETH_MACA3LR MMIO32(ETHERNET_BASE + 0x5C) + +/* Ethernet MMC registers */ +#define ETH_MMCCR MMIO32(ETHERNET_BASE + 0x100) +#define ETH_MMCRIR MMIO32(ETHERNET_BASE + 0x104) +#define ETH_MMCTIR MMIO32(ETHERNET_BASE + 0x108) +#define ETH_MMCRIMR MMIO32(ETHERNET_BASE + 0x10C) +#define ETH_MMCTIMR MMIO32(ETHERNET_BASE + 0x110) +#define ETH_MMCTGFSCCR MMIO32(ETHERNET_BASE + 0x14C) +#define ETH_MMCTGFMSCCR MMIO32(ETHERNET_BASE + 0x150) +#define ETH_MMCTGFCR MMIO32(ETHERNET_BASE + 0x168) +#define ETH_MMCRFCECR MMIO32(ETHERNET_BASE + 0x194) +#define ETH_MMCRFAECR MMIO32(ETHERNET_BASE + 0x198) +#define ETH_MMCRGUFCR MMIO32(ETHERNET_BASE + 0x1C4) + +/* Ethrenet IEEE 1588 time stamp registers */ +#define ETH_PTPTSCR MMIO32(ETHERNET_BASE + 0x700) +#define ETH_PTPSSIR MMIO32(ETHERNET_BASE + 0x704) +#define ETH_PTPTSHR MMIO32(ETHERNET_BASE + 0x708) +#define ETH_PTPTSLR MMIO32(ETHERNET_BASE + 0x70C) +#define ETH_PTPTSHUR MMIO32(ETHERNET_BASE + 0x710) +#define ETH_PTPTSLUR MMIO32(ETHERNET_BASE + 0x714) +#define ETH_PTPTSAR MMIO32(ETHERNET_BASE + 0x718) +#define ETH_PTPTTHR MMIO32(ETHERNET_BASE + 0x71C) +#define ETH_PTPTTLR MMIO32(ETHERNET_BASE + 0x720) + +/* Ethernet DMA registers */ +#define ETH_DMABMR MMIO32(ETHERNET_BASE + 0x1000) +#define ETH_DMATPDR MMIO32(ETHERNET_BASE + 0x1004) +#define ETH_DMARPDR MMIO32(ETHERNET_BASE + 0x1008) +#define ETH_DMARDLAR MMIO32(ETHERNET_BASE + 0x100C) +#define ETH_DMATDLAR MMIO32(ETHERNET_BASE + 0x1010) +#define ETH_DMATDLAR MMIO32(ETHERNET_BASE + 0x1010) +#define ETH_DMASR MMIO32(ETHERNET_BASE + 0x1014) +#define ETH_DMAOMR MMIO32(ETHERNET_BASE + 0x1018) +#define ETH_DMAIER MMIO32(ETHERNET_BASE + 0x101C) +#define ETH_DMAMFBOCR MMIO32(ETHERNET_BASE + 0x1020) +#define ETH_DMACHTDR MMIO32(ETHERNET_BASE + 0x1048) +#define ETH_DMACHRDR MMIO32(ETHERNET_BASE + 0x104C) +#define ETH_DMACHTBAR MMIO32(ETHERNET_BASE + 0x1050) +#define ETH_DMACHRBAR MMIO32(ETHERNET_BASE + 0x1054) + +/* Ethernet MAC Register bit definitions */ +/* Ethernet MAC configuration register ETH_MACCR bits */ +#define ETH_MACCR_RE 0x00000004 +#define ETH_MACCR_TE 0x00000008 +#define ETH_MACCR_DC 0x00000010 +#define ETH_MACCR_BL 0x00000060 +#define ETH_MACCR_APCS 0x00000080 +#define ETH_MACCR_RD 0x00000200 +#define ETH_MACCR_IPCO 0x00000400 +#define ETH_MACCR_DM 0x00000800 +#define ETH_MACCR_LM 0x00001000 +#define ETH_MACCR_ROD 0x00002000 +#define ETH_MACCR_FES 0x00004000 +#define ETH_MACCR_CSD 0x00010000 +#define ETH_MACCR_IFG 0x000E0000 +#define ETH_MACCR_JD 0x00400000 +#define ETH_MACCR_WD 0x00800000 + +/* Ethernet MAC frame filter register ETH_MACFFR bits */ +#define ETH_MACFFR_PM 0x00000001 +#define ETH_MACFFR_HU 0x00000002 +#define ETH_MACFFR_HM 0x00000004 +#define ETH_MACFFR_DAIF 0x00000008 +#define ETH_MACFFR_PAM 0x00000010 +#define ETH_MACFFR_BFD 0x00000020 +#define ETH_MACFFR_PCF 0x000000C0 +#define ETH_MACFFR_SAIF 0x00000100 +#define ETH_MACFFR_SAF 0x00000200 +#define ETH_MACFFR_HPF 0x00000400 +#define ETH_MACFFR_PA 0x80000000 + +/* Ethernet MAC MII address register ETH_MACMIIAR bits */ +#define ETH_MACMIIAR_MB 0x0001 +#define ETH_MACMIIAR_MW 0x0002 +/* Clock Range for MDC frequency */ +#define ETH_MACMIIAR_CR_MASK 0x001C +#define ETH_MACMIIAR_CR_HCLK_DIV_42 0x0000 /* For HCLK 60-72 MHz */ +#define ETH_MACMIIAR_CR_HCLK_DIV_16 0x0008 /* For HCLK 20-35 MHz */ +#define ETH_MACMIIAR_CR_HCLK_DIV_24 0x000C /* For HCLK 35-60 MHz */ +#define ETH_MACMIIAR_MR 0x07C0 +#define ETH_MACMIIAR_PA 0xF800 + +/* Ethernet MAC flow control register ETH_MACFCR bits */ +#define ETH_MACFCR_FCB 0x00000001 +#define ETH_MACFCR_BPA 0x00000001 +#define ETH_MACFCR_TFCE 0x00000002 +#define ETH_MACFCR_RFCE 0x00000004 +#define ETH_MACFCR_UPFD 0x00000008 +#define ETH_MACFCR_PLT 0x00000030 +#define ETH_MACFCR_ZQPD 0x00000080 +#define ETH_MACFCR_PT 0xFFFF0000 + +/* Ethernet MAC interrupt status register ETH_MACSR bits */ +#define ETH_MACSR_PMTS 0x0008 +#define ETH_MACSR_MMCS 0x0010 +#define ETH_MACSR_MMCRS 0x0020 +#define ETH_MACSR_MMCTS 0x0040 +#define ETH_MACSR_TSTS 0x0200 + +/* Ethernet MAC interrupt mask register ETH_MACIMR bits */ +#define ETH_MACIMR_PMTIM 0x0008 +#define ETH_MACIMR_TSTIM 0x0200 + +/* Ethernet DMA Register bit definitions */ +/* Ethernet DMA bus mode register ETH_DMABMR bits */ +#define ETH_DMABMR_SR 0x00000001 +#define ETH_DMABMR_DA 0x00000002 +#define ETH_DMABMR_DSL_MASK 0x0000007C +#define ETH_DMABMR_PBL_MASK 0x00003F00 +#define ETH_DMABMR_RTPR_MASK 0x0000C000 +#define ETH_DMABMR_RTPR_1TO1 0x00000000 +#define ETH_DMABMR_RTPR_2TO1 0x00004000 +#define ETH_DMABMR_RTPR_3TO1 0x00008000 +#define ETH_DMABMR_RTPR_4TO1 0x0000C000 +#define ETH_DMABMR_FB 0x00010000 +#define ETH_DMABMR_RDP_MASK 0x007E0000 +#define ETH_DMABMR_USP 0x00800000 +#define ETH_DMABMR_FPM 0x01000000 +#define ETH_DMABMR_AAB 0x02000000 + +/* Ethernet DMA operation mode register ETH_DMAOMR bits */ +#define ETH_DMAOMR_SR 0x00000002 +#define ETH_DMAOMR_OSF 0x00000004 +#define ETH_DMAOMR_RTC_MASK 0x00000018 +#define ETH_DMAOMR_RTC_64 0x00000000 +#define ETH_DMAOMR_RTC_32 0x00000008 +#define ETH_DMAOMR_RTC_96 0x00000010 +#define ETH_DMAOMR_RTC_128 0x00000018 +#define ETH_DMAOMR_FUGF 0x00000040 +#define ETH_DMAOMR_FEF 0x00000080 +#define ETH_DMAOMR_ST 0x00002000 +#define ETH_DMAOMR_TTC_MASK 0x0001C000 +#define ETH_DMAOMR_FTF 0x00100000 +#define ETH_DMAOMR_TSF 0x00200000 +#define ETH_DMAOMR_DFRF 0x01000000 +#define ETH_DMAOMR_RSF 0x02000000 +#define ETH_DMAOMR_DTCEFD 0x04000000 + +/* Ethernet DMA interrupt enable register ETH_DMAIER bits */ +#define ETH_DMAIER_TIE 0x00000001 +#define ETH_DMAIER_TPSIE 0x00000002 +#define ETH_DMAIER_TBUIE 0x00000004 +#define ETH_DMAIER_TJTIE 0x00000008 +#define ETH_DMAIER_ROIE 0x00000010 +#define ETH_DMAIER_TUIE 0x00000020 +#define ETH_DMAIER_RIE 0x00000040 +#define ETH_DMAIER_RBUIE 0x00000080 +#define ETH_DMAIER_RPSIE 0x00000100 +#define ETH_DMAIER_RWTIE 0x00000200 +#define ETH_DMAIER_ETIE 0x00000400 +#define ETH_DMAIER_FBEIE 0x00002000 +#define ETH_DMAIER_ERIE 0x00004000 +#define ETH_DMAIER_AISE 0x00008000 +#define ETH_DMAIER_NSIE 0x00010000 + +BEGIN_DECLS + +void eth_smi_write(uint8_t phy, uint8_t reg, uint16_t data); +uint16_t eth_smi_read(uint8_t phy, uint8_t reg); + +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f1/exti.h b/libopencm3/include/libopencm3/stm32/f1/exti.h new file mode 100644 index 0000000..1088210 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f1/exti.h @@ -0,0 +1,41 @@ +/** @defgroup exti_defines EXTI Defines + * + * @brief Defined Constants and Types for the STM32F1xx External Interrupts + * + * + * @ingroup STM32F1xx_defines + * + * @author @htmlonly © @endhtmlonly 2013 + * Piotr Esden-Tempski + * + * @version 1.0.0 + * + * @date 14 January 2014 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Piotr Esden-Tempski + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EXTI_H +#define LIBOPENCM3_EXTI_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f1/flash.h b/libopencm3/include/libopencm3/stm32/f1/flash.h new file mode 100644 index 0000000..f7ba402 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f1/flash.h @@ -0,0 +1,120 @@ +/** @defgroup flash_defines FLASH Defines + * + * @ingroup STM32F1xx_defines + * + * @brief Defined Constants and Types for the STM32F1xx FLASH Memory + * + * @version 1.0.0 + * + * @date 14 January 2014 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2010 Mark Butler + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* + * For details see: + * PM0075 programming manual: STM32F10xxx Flash programming + * August 2010, Doc ID 17863 Rev 1 + * https://github.com/libopencm3/libopencm3-archive/blob/master/st_micro/CD00283419.pdf + */ + +#ifndef LIBOPENCM3_FLASH_H +#define LIBOPENCM3_FLASH_H + +/**@{*/ + +#include + +/* --- FLASH_OPTION bytes ------------------------------------------------- */ + +/** @defgroup flash_options Option Byte Addresses +@ingroup flash_defines +@{*/ +#define FLASH_OPTION_BYTE_0 FLASH_OPTION_BYTE(0) +#define FLASH_OPTION_BYTE_1 FLASH_OPTION_BYTE(1) +#define FLASH_OPTION_BYTE_2 FLASH_OPTION_BYTE(2) +#define FLASH_OPTION_BYTE_3 FLASH_OPTION_BYTE(3) +#define FLASH_OPTION_BYTE_4 FLASH_OPTION_BYTE(4) +#define FLASH_OPTION_BYTE_5 FLASH_OPTION_BYTE(5) +#define FLASH_OPTION_BYTE_6 FLASH_OPTION_BYTE(6) +#define FLASH_OPTION_BYTE_7 FLASH_OPTION_BYTE(7) +/**@}*/ + +/*****************************************************************************/ +/* Register values */ +/*****************************************************************************/ + +/* --- FLASH_ACR values ---------------------------------------------------- */ + +/** @defgroup flash_latency FLASH Wait States +@ingroup flash_defines +@{*/ +#define FLASH_ACR_LATENCY_0WS 0x00 +#define FLASH_ACR_LATENCY_1WS 0x01 +#define FLASH_ACR_LATENCY_2WS 0x02 +/**@}*/ +#define FLASH_ACR_HLFCYA (1 << 3) + +/* --- FLASH_SR values ----------------------------------------------------- */ + +#define FLASH_SR_EOP (1 << 5) +#define FLASH_SR_WRPRTERR (1 << 4) +#define FLASH_SR_PGERR (1 << 2) +#define FLASH_SR_BSY (1 << 0) + +/* --- FLASH_CR values ----------------------------------------------------- */ + +/* --- FLASH_OBR values ---------------------------------------------------- */ + +/* FLASH_OBR[25:18]: Data1 */ +/* FLASH_OBR[17:10]: Data0 */ +#define FLASH_OBR_NRST_STDBY (1 << 4) +#define FLASH_OBR_NRST_STOP (1 << 3) +#define FLASH_OBR_WDG_SW (1 << 2) +#define FLASH_OBR_RDPRT_EN (1 << FLASH_OBR_RDPRT_SHIFT) + +/*****************************************************************************/ +/* API definitions */ +/*****************************************************************************/ + +/* Read protection option byte protection enable key */ +#define FLASH_RDP_KEY ((uint16_t)0x00a5) + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void flash_halfcycle_enable(void); +void flash_halfcycle_disable(void); +void flash_unlock_upper(void); +void flash_lock_upper(void); +void flash_clear_pgerr_flag_upper(void); +void flash_clear_eop_flag_upper(void); +void flash_clear_wrprterr_flag_upper(void); +void flash_clear_bsy_flag_upper(void); + +END_DECLS + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f1/gpio.h b/libopencm3/include/libopencm3/stm32/f1/gpio.h new file mode 100644 index 0000000..9fc8990 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f1/gpio.h @@ -0,0 +1,955 @@ +/** @defgroup gpio_defines GPIO Defines + +@brief Defined Constants and Types for the STM32F1xx General Purpose I/O + +@ingroup STM32F1xx_defines + +@version 1.0.0 + +@date 1 July 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2012 Piotr Esden-Tempski + * Copyright (C) 2012 Ken Sarkies + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#ifndef LIBOPENCM3_GPIO_H +#define LIBOPENCM3_GPIO_H + +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* GPIO port base addresses (for convenience) */ +/** @defgroup gpio_port_id GPIO Port IDs +@ingroup gpio_defines + +@{*/ +/* GPIO port base addresses (for convenience) */ +#define GPIOA GPIO_PORT_A_BASE +#define GPIOB GPIO_PORT_B_BASE +#define GPIOC GPIO_PORT_C_BASE +#define GPIOD GPIO_PORT_D_BASE +#define GPIOE GPIO_PORT_E_BASE +#define GPIOF GPIO_PORT_F_BASE +#define GPIOG GPIO_PORT_G_BASE +/**@}*/ + +/* --- Alternate function GPIOs -------------------------------------------- */ + +/* Default alternate functions of some pins (with and without remapping) */ + +/* CAN1 / CAN GPIO */ +#define GPIO_CAN1_RX GPIO11 /* PA11 */ +#define GPIO_CAN1_TX GPIO12 /* PA12 */ +#define GPIO_CAN_RX GPIO_CAN1_RX /* Alias */ +#define GPIO_CAN_TX GPIO_CAN1_TX /* Alias */ + +#define GPIO_CAN_PB_RX GPIO8 /* PB8 */ +#define GPIO_CAN_PB_TX GPIO9 /* PB9 */ +#define GPIO_CAN1_PB_RX GPIO_CAN_PB_RX /* Alias */ +#define GPIO_CAN1_PB_TX GPIO_CAN_PB_TX /* Alias */ + +#define GPIO_CAN_PD_RX GPIO0 /* PD0 */ +#define GPIO_CAN_PD_TX GPIO1 /* PD1 */ +#define GPIO_CAN1_PD_RX GPIO_CAN_PD_RX /* Alias */ +#define GPIO_CAN1_PD_TX GPIO_CAN_PD_TX /* Alias */ + +/* CAN1 / CAN BANK */ +#define GPIO_BANK_CAN1_RX GPIOA /* PA11 */ +#define GPIO_BANK_CAN1_TX GPIOA /* PA12 */ +#define GPIO_BANK_CAN_RX GPIO_BANK_CAN1_RX /* Alias */ +#define GPIO_BANK_CAN_TX GPIO_BANK_CAN1_TX /* Alias */ + +#define GPIO_BANK_CAN_PB_RX GPIOB /* PB8 */ +#define GPIO_BANK_CAN_PB_TX GPIOB /* PB9 */ +#define GPIO_BANK_CAN1_PB_RX GPIO_BANK_CAN_PB_RX /* Alias */ +#define GPIO_BANK_CAN1_PB_TX GPIO_BANK_CAN_PB_TX /* Alias */ + +#define GPIO_BANK_CAN_PD_RX GPIOD /* PD0 */ +#define GPIO_BANK_CAN_PD_TX GPIOD /* PD1 */ +#define GPIO_BANK_CAN1_PD_RX GPIO_BANK_CAN_PD_RX /* Alias */ +#define GPIO_BANK_CAN1_PD_TX GPIO_BANK_CAN_PD_TX /* Alias */ + +/* CAN2 GPIO */ +#define GPIO_CAN2_RX GPIO12 /* PB12 */ +#define GPIO_CAN2_TX GPIO13 /* PB13 */ + +#define GPIO_CAN2_RE_RX GPIO5 /* PB5 */ +#define GPIO_CAN2_RE_TX GPIO6 /* PB6 */ + +/* CAN2 BANK */ +#define GPIO_BANK_CAN2_RX GPIOB /* PB12 */ +#define GPIO_BANK_CAN2_TX GPIOB /* PB13 */ + +#define GPIO_BANK_CAN2_RE_RX GPIOB /* PB5 */ +#define GPIO_BANK_CAN2_RE_TX GPIOB /* PB6 */ + +/* JTAG/SWD GPIO */ +#define GPIO_JTMS_SWDIO GPIO13 /* PA13 */ +#define GPIO_JTCK_SWCLK GPIO14 /* PA14 */ +#define GPIO_JTDI GPIO15 /* PA15 */ +#define GPIO_JTDO_TRACESWO GPIO3 /* PB3 */ +#define GPIO_JNTRST GPIO4 /* PB4 */ +#define GPIO_TRACECK GPIO2 /* PE2 */ +#define GPIO_TRACED0 GPIO3 /* PE3 */ +#define GPIO_TRACED1 GPIO4 /* PE4 */ +#define GPIO_TRACED2 GPIO5 /* PE5 */ +#define GPIO_TRACED3 GPIO6 /* PE6 */ + +/* JTAG/SWD BANK */ +#define GPIO_BANK_JTMS_SWDIO GPIOA /* PA13 */ +#define GPIO_BANK_JTCK_SWCLK GPIOA /* PA14 */ +#define GPIO_BANK_JTDI GPIOA /* PA15 */ +#define GPIO_BANK_JTDO_TRACESWO GPIOB /* PB3 */ +#define GPIO_BANK_JNTRST GPIOB /* PB4 */ +#define GPIO_BANK_TRACECK GPIOE /* PE2 */ +#define GPIO_BANK_TRACED0 GPIOE /* PE3 */ +#define GPIO_BANK_TRACED1 GPIOE /* PE4 */ +#define GPIO_BANK_TRACED2 GPIOE /* PE5 */ +#define GPIO_BANK_TRACED3 GPIOE /* PE6 */ + +/* Timer5 GPIO */ +#define GPIO_TIM5_CH1 GPIO0 /* PA0 */ +#define GPIO_TIM5_CH2 GPIO1 /* PA1 */ +#define GPIO_TIM5_CH3 GPIO2 /* PA2 */ +#define GPIO_TIM5_CH4 GPIO3 /* PA3 */ + +/* Timer5 BANK */ +#define GPIO_BANK_TIM5_CH1 GPIOA /* PA0 */ +#define GPIO_BANK_TIM5_CH2 GPIOA /* PA1 */ +#define GPIO_BANK_TIM5_CH3 GPIOA /* PA2 */ +#define GPIO_BANK_TIM5_CH4 GPIOA /* PA3 */ +#define GPIO_BANK_TIM5 GPIOA + +/* Timer4 GPIO */ +#define GPIO_TIM4_CH1 GPIO6 /* PB6 */ +#define GPIO_TIM4_CH2 GPIO7 /* PB7 */ +#define GPIO_TIM4_CH3 GPIO8 /* PB8 */ +#define GPIO_TIM4_CH4 GPIO9 /* PB9 */ + +#define GPIO_TIM4_RE_CH1 GPIO12 /* PD12 */ +#define GPIO_TIM4_RE_CH2 GPIO13 /* PD13 */ +#define GPIO_TIM4_RE_CH3 GPIO14 /* PD14 */ +#define GPIO_TIM4_RE_CH4 GPIO15 /* PD15 */ + +/* Timer4 BANK */ +#define GPIO_BANK_TIM4_CH1 GPIOB /* PB6 */ +#define GPIO_BANK_TIM4_CH2 GPIOB /* PB7 */ +#define GPIO_BANK_TIM4_CH3 GPIOB /* PB8 */ +#define GPIO_BANK_TIM4_CH4 GPIOB /* PB9 */ +#define GPIO_BANK_TIM4 GPIOB + +#define GPIO_BANK_TIM4_RE_CH1 GPIOD /* PD12 */ +#define GPIO_BANK_TIM4_RE_CH2 GPIOD /* PD13 */ +#define GPIO_BANK_TIM4_RE_CH3 GPIOD /* PD14 */ +#define GPIO_BANK_TIM4_RE_CH4 GPIOD /* PD15 */ +#define GPIO_BANK_TIM4_RE GPIOD + +/* Timer3 GPIO */ +#define GPIO_TIM3_CH1 GPIO6 /* PA6 */ +#define GPIO_TIM3_CH2 GPIO7 /* PA7 */ +#define GPIO_TIM3_CH3 GPIO0 /* PB0 */ +#define GPIO_TIM3_CH4 GPIO1 /* PB1 */ + +#define GPIO_TIM3_PR_CH1 GPIO4 /* PB4 */ +#define GPIO_TIM3_PR_CH2 GPIO5 /* PB5 */ +#define GPIO_TIM3_PR_CH3 GPIO0 /* PB0 */ +#define GPIO_TIM3_PR_CH4 GPIO1 /* PB1 */ + +#define GPIO_TIM3_FR_CH1 GPIO6 /* PC6 */ +#define GPIO_TIM3_FR_CH2 GPIO7 /* PC7 */ +#define GPIO_TIM3_FR_CH3 GPIO8 /* PC8 */ +#define GPIO_TIM3_FR_CH4 GPIO9 /* PC9 */ + +/* Timer3 BANK */ +#define GPIO_BANK_TIM3_CH1 GPIOA /* PA6 */ +#define GPIO_BANK_TIM3_CH2 GPIOA /* PA7 */ +#define GPIO_BANK_TIM3_CH3 GPIOB /* PB0 */ +#define GPIO_BANK_TIM3_CH4 GPIOB /* PB1 */ +#define GPIO_BANK_TIM3_CH12 GPIOA +#define GPIO_BANK_TIM3_CH34 GPIOB + +#define GPIO_BANK_TIM3_PR_CH1 GPIOB /* PB4 */ +#define GPIO_BANK_TIM3_PR_CH2 GPIOB /* PB5 */ +#define GPIO_BANK_TIM3_PR_CH3 GPIOB /* PB0 */ +#define GPIO_BANK_TIM3_PR_CH4 GPIOB /* PB1 */ +#define GPIO_BANK_TIM3_PR GPIOB + +#define GPIO_BANK_TIM3_FR_CH1 GPIOC /* PC6 */ +#define GPIO_BANK_TIM3_FR_CH2 GPIOC /* PC7 */ +#define GPIO_BANK_TIM3_FR_CH3 GPIOC /* PC8 */ +#define GPIO_BANK_TIM3_FR_CH4 GPIOC /* PC9 */ +#define GPIO_BANK_TIM3_FR GPIOC + +/* Timer2 GPIO */ +#define GPIO_TIM2_CH1_ETR GPIO0 /* PA0 */ +#define GPIO_TIM2_CH2 GPIO1 /* PA1 */ +#define GPIO_TIM2_CH3 GPIO2 /* PA2 */ +#define GPIO_TIM2_CH4 GPIO3 /* PA3 */ + +#define GPIO_TIM2_PR1_CH1_ETR GPIO15 /* PA15 */ +#define GPIO_TIM2_PR1_CH2 GPIO3 /* PB3 */ +#define GPIO_TIM2_PR1_CH3 GPIO2 /* PA2 */ +#define GPIO_TIM2_PR1_CH4 GPIO3 /* PA3 */ + +#define GPIO_TIM2_PR2_CH1_ETR GPIO0 /* PA0 */ +#define GPIO_TIM2_PR2_CH2 GPIO1 /* PA1 */ +#define GPIO_TIM2_PR2_CH3 GPIO10 /* PB10 */ +#define GPIO_TIM2_PR2_CH4 GPIO11 /* PB11 */ + +#define GPIO_TIM2_FR_CH1_ETR GPIO15 /* PA15 */ +#define GPIO_TIM2_FR_CH2 GPIO3 /* PB3 */ +#define GPIO_TIM2_FR_CH3 GPIO10 /* PB10 */ +#define GPIO_TIM2_FR_CH4 GPIO11 /* PB11 */ + +/* Timer2 BANK */ +#define GPIO_BANK_TIM2_CH1_ETR GPIOA /* PA0 */ +#define GPIO_BANK_TIM2_CH2 GPIOA /* PA1 */ +#define GPIO_BANK_TIM2_CH3 GPIOA /* PA2 */ +#define GPIO_BANK_TIM2_CH4 GPIOA /* PA3 */ +#define GPIO_BANK_TIM2 GPIOA + +#define GPIO_BANK_TIM2_PR1_CH1_ETR GPIOA /* PA15 */ +#define GPIO_BANK_TIM2_PR1_CH2 GPIOB /* PB3 */ +#define GPIO_BANK_TIM2_PR1_CH3 GPIOA /* PA2 */ +#define GPIO_BANK_TIM2_PR1_CH4 GPIOA /* PA3 */ +#define GPIO_BANK_TIM2_PR1_CH134 GPIOA + +#define GPIO_BANK_TIM2_PR2_CH1_ETR GPIOA /* PA0 */ +#define GPIO_BANK_TIM2_PR2_CH2 GPIOA /* PA1 */ +#define GPIO_BANK_TIM2_PR2_CH3 GPIOB /* PB10 */ +#define GPIO_BANK_TIM2_PR2_CH4 GPIOB /* PB11 */ +#define GPIO_BANK_TIM2_PR2_CH12 GPIOA +#define GPIO_BANK_TIM2_PR2_CH34 GPIOB + +#define GPIO_BANK_TIM2_FR_CH1_ETR GPIOA /* PA15 */ +#define GPIO_BANK_TIM2_FR_CH2 GPIOB /* PB3 */ +#define GPIO_BANK_TIM2_FR_CH3 GPIOB /* PB10 */ +#define GPIO_BANK_TIM2_FR_CH4 GPIOB /* PB11 */ +#define GPIO_BANK_TIM2_FR_CH234 GPIOB + +/* Timer1 GPIO */ +#define GPIO_TIM1_ETR GPIO12 /* PA12 */ +#define GPIO_TIM1_CH1 GPIO8 /* PA8 */ +#define GPIO_TIM1_CH2 GPIO9 /* PA9 */ +#define GPIO_TIM1_CH3 GPIO10 /* PA10 */ +#define GPIO_TIM1_CH4 GPIO11 /* PA11 */ +#define GPIO_TIM1_BKIN GPIO12 /* PB12 */ +#define GPIO_TIM1_CH1N GPIO13 /* PB13 */ +#define GPIO_TIM1_CH2N GPIO14 /* PB14 */ +#define GPIO_TIM1_CH3N GPIO15 /* PB15 */ + +#define GPIO_TIM1_PR_ETR GPIO12 /* PA12 */ +#define GPIO_TIM1_PR_CH1 GPIO8 /* PA8 */ +#define GPIO_TIM1_PR_CH2 GPIO9 /* PA9 */ +#define GPIO_TIM1_PR_CH3 GPIO10 /* PA10 */ +#define GPIO_TIM1_PR_CH4 GPIO11 /* PA11 */ +#define GPIO_TIM1_PR_BKIN GPIO6 /* PA6 */ +#define GPIO_TIM1_PR_CH1N GPIO7 /* PA7 */ +#define GPIO_TIM1_PR_CH2N GPIO0 /* PB0 */ +#define GPIO_TIM1_PR_CH3N GPIO1 /* PB1 */ + +#define GPIO_TIM1_FR_ETR GPIO7 /* PE7 */ +#define GPIO_TIM1_FR_CH1 GPIO9 /* PE9 */ +#define GPIO_TIM1_FR_CH2 GPIO11 /* PE11 */ +#define GPIO_TIM1_FR_CH3 GPIO13 /* PE13 */ +#define GPIO_TIM1_FR_CH4 GPIO14 /* PE14 */ +#define GPIO_TIM1_FR_BKIN GPIO15 /* PE15 */ +#define GPIO_TIM1_FR_CH1N GPIO8 /* PE8 */ +#define GPIO_TIM1_FR_CH2N GPIO10 /* PE10 */ +#define GPIO_TIM1_FR_CH3N GPIO12 /* PE12 */ + +/* Timer1 BANK */ +#define GPIO_BANK_TIM1_ETR GPIOA /* PA12 */ +#define GPIO_BANK_TIM1_CH1 GPIOA /* PA8 */ +#define GPIO_BANK_TIM1_CH2 GPIOA /* PA9 */ +#define GPIO_BANK_TIM1_CH3 GPIOA /* PA10 */ +#define GPIO_BANK_TIM1_CH4 GPIOA /* PA11 */ +#define GPIO_BANK_TIM1_BKIN GPIOB /* PB12 */ +#define GPIO_BANK_TIM1_CH1N GPIOB /* PB13 */ +#define GPIO_BANK_TIM1_CH2N GPIOB /* PB14 */ +#define GPIO_BANK_TIM1_CH3N GPIOB /* PB15 */ +#define GPIO_BANK_TIM1_ETR_CH1234 GPIOA +#define GPIO_BANK_TIM1_BKIN_CH123N GPIOB + +#define GPIO_BANK_TIM1_PR_ETR GPIOA /* PA12 */ +#define GPIO_BANK_TIM1_PR_CH1 GPIOA /* PA8 */ +#define GPIO_BANK_TIM1_PR_CH2 GPIOA /* PA9 */ +#define GPIO_BANK_TIM1_PR_CH3 GPIOA /* PA10 */ +#define GPIO_BANK_TIM1_PR_CH4 GPIOA /* PA11 */ +#define GPIO_BANK_TIM1_PR_BKIN GPIOA /* PA6 */ +#define GPIO_BANK_TIM1_PR_CH1N GPIOA /* PA7 */ +#define GPIO_BANK_TIM1_PR_CH2N GPIOB /* PB0 */ +#define GPIO_BANK_TIM1_PR_CH3N GPIOB /* PB1 */ +#define GPIO_BANK_TIM1_PR_ETR_CH1234_BKIN_CH1N GPIOA +#define GPIO_BANK_TIM1_PR_CH23N GPIOB + +#define GPIO_BANK_TIM1_FR_ETR GPIOE /* PE7 */ +#define GPIO_BANK_TIM1_FR_CH1 GPIOE /* PE9 */ +#define GPIO_BANK_TIM1_FR_CH2 GPIOE /* PE11 */ +#define GPIO_BANK_TIM1_FR_CH3 GPIOE /* PE13 */ +#define GPIO_BANK_TIM1_FR_CH4 GPIOE /* PE14 */ +#define GPIO_BANK_TIM1_FR_BKIN GPIOE /* PE15 */ +#define GPIO_BANK_TIM1_FR_CH1N GPIOE /* PE8 */ +#define GPIO_BANK_TIM1_FR_CH2N GPIOE /* PE10 */ +#define GPIO_BANK_TIM1_FR_CH3N GPIOE /* PE12 */ +#define GPIO_BANK_TIM1_FR GPIOE + +/* UART5 GPIO */ +#define GPIO_UART5_TX GPIO12 /* PC12 */ +#define GPIO_UART5_RX GPIO2 /* PD2 */ + +/* UART5 BANK */ +#define GPIO_BANK_UART5_TX GPIOC /* PC12 */ +#define GPIO_BANK_UART5_RX GPIOD /* PD2 */ + +/* UART4 GPIO */ +#define GPIO_UART4_TX GPIO10 /* PC10 */ +#define GPIO_UART4_RX GPIO11 /* PC11 */ + +/* UART4 BANK */ +#define GPIO_BANK_UART4_TX GPIOC /* PC10 */ +#define GPIO_BANK_UART4_RX GPIOC /* PC11 */ + +/* USART3 GPIO */ +#define GPIO_USART3_TX GPIO10 /* PB10 */ +#define GPIO_USART3_RX GPIO11 /* PB11 */ +#define GPIO_USART3_CK GPIO12 /* PB12 */ +#define GPIO_USART3_CTS GPIO13 /* PB13 */ +#define GPIO_USART3_RTS GPIO14 /* PB14 */ + +#define GPIO_USART3_PR_TX GPIO10 /* PC10 */ +#define GPIO_USART3_PR_RX GPIO11 /* PC11 */ +#define GPIO_USART3_PR_CK GPIO12 /* PC12 */ +#define GPIO_USART3_PR_CTS GPIO13 /* PB13 */ +#define GPIO_USART3_PR_RTS GPIO14 /* PB14 */ + +#define GPIO_USART3_FR_TX GPIO8 /* PD8 */ +#define GPIO_USART3_FR_RX GPIO9 /* PD9 */ +#define GPIO_USART3_FR_CK GPIO10 /* PD10 */ +#define GPIO_USART3_FR_CTS GPIO11 /* PD11 */ +#define GPIO_USART3_FR_RTS GPIO12 /* PD12 */ + +/* USART3 BANK */ +#define GPIO_BANK_USART3_TX GPIOB /* PB10 */ +#define GPIO_BANK_USART3_RX GPIOB /* PB11 */ +#define GPIO_BANK_USART3_CK GPIOB /* PB12 */ +#define GPIO_BANK_USART3_CTS GPIOB /* PB13 */ +#define GPIO_BANK_USART3_RTS GPIOB /* PB14 */ + +#define GPIO_BANK_USART3_PR_TX GPIOC /* PC10 */ +#define GPIO_BANK_USART3_PR_RX GPIOC /* PC11 */ +#define GPIO_BANK_USART3_PR_CK GPIOC /* PC12 */ +#define GPIO_BANK_USART3_PR_CTS GPIOB /* PB13 */ +#define GPIO_BANK_USART3_PR_RTS GPIOB /* PB14 */ + +#define GPIO_BANK_USART3_FR_TX GPIOD /* PD8 */ +#define GPIO_BANK_USART3_FR_RX GPIOD /* PD9 */ +#define GPIO_BANK_USART3_FR_CK GPIOD /* PD10 */ +#define GPIO_BANK_USART3_FR_CTS GPIOD /* PD11 */ +#define GPIO_BANK_USART3_FR_RTS GPIOD /* PD12 */ + +/* USART2 GPIO */ +#define GPIO_USART2_CTS GPIO0 /* PA0 */ +#define GPIO_USART2_RTS GPIO1 /* PA1 */ +#define GPIO_USART2_TX GPIO2 /* PA2 */ +#define GPIO_USART2_RX GPIO3 /* PA3 */ +#define GPIO_USART2_CK GPIO4 /* PA4 */ + +#define GPIO_USART2_RE_CTS GPIO3 /* PD3 */ +#define GPIO_USART2_RE_RTS GPIO4 /* PD4 */ +#define GPIO_USART2_RE_TX GPIO5 /* PD5 */ +#define GPIO_USART2_RE_RX GPIO6 /* PD6 */ +#define GPIO_USART2_RE_CK GPIO7 /* PD7 */ + +/* USART2 BANK */ +#define GPIO_BANK_USART2_CTS GPIOA /* PA0 */ +#define GPIO_BANK_USART2_RTS GPIOA /* PA1 */ +#define GPIO_BANK_USART2_TX GPIOA /* PA2 */ +#define GPIO_BANK_USART2_RX GPIOA /* PA3 */ +#define GPIO_BANK_USART2_CK GPIOA /* PA4 */ + +#define GPIO_BANK_USART2_RE_CTS GPIOD /* PD3 */ +#define GPIO_BANK_USART2_RE_RTS GPIOD /* PD4 */ +#define GPIO_BANK_USART2_RE_TX GPIOD /* PD5 */ +#define GPIO_BANK_USART2_RE_RX GPIOD /* PD6 */ +#define GPIO_BANK_USART2_RE_CK GPIOD /* PD7 */ + +/* USART1 GPIO */ +#define GPIO_USART1_TX GPIO9 /* PA9 */ +#define GPIO_USART1_RX GPIO10 /* PA10 */ + +#define GPIO_USART1_RE_TX GPIO6 /* PB6 */ +#define GPIO_USART1_RE_RX GPIO7 /* PB7 */ + +/* USART1 BANK */ +#define GPIO_BANK_USART1_TX GPIOA /* PA9 */ +#define GPIO_BANK_USART1_RX GPIOA /* PA10 */ + +#define GPIO_BANK_USART1_RE_TX GPIOB /* PB6 */ +#define GPIO_BANK_USART1_RE_RX GPIOB /* PB7 */ + +/* I2C1 GPIO */ +#define GPIO_I2C1_SMBAI GPIO5 /* PB5 */ +#define GPIO_I2C1_SCL GPIO6 /* PB6 */ +#define GPIO_I2C1_SDA GPIO7 /* PB7 */ + +#define GPIO_I2C1_RE_SMBAI GPIO5 /* PB5 */ +#define GPIO_I2C1_RE_SCL GPIO8 /* PB8 */ +#define GPIO_I2C1_RE_SDA GPIO9 /* PB9 */ + +/* I2C1 BANK */ +#define GPIO_BANK_I2C1_SMBAI GPIOB /* PB5 */ +#define GPIO_BANK_I2C1_SCL GPIOB /* PB6 */ +#define GPIO_BANK_I2C1_SDA GPIOB /* PB7 */ + +#define GPIO_BANK_I2C1_RE_SMBAI GPIOB /* PB5 */ +#define GPIO_BANK_I2C1_RE_SCL GPIOB /* PB8 */ +#define GPIO_BANK_I2C1_RE_SDA GPIOB /* PB9 */ + +/* I2C2 GPIO */ +#define GPIO_I2C2_SCL GPIO10 /* PB10 */ +#define GPIO_I2C2_SDA GPIO11 /* PB11 */ +#define GPIO_I2C2_SMBAI GPIO12 /* PB12 */ + +/* I2C2 BANK */ +#define GPIO_BANK_I2C2_SCL GPIOB /* PB10 */ +#define GPIO_BANK_I2C2_SDA GPIOB /* PB11 */ +#define GPIO_BANK_I2C2_SMBAI GPIOB /* PB12 */ + +/* SPI1 GPIO */ +#define GPIO_SPI1_NSS GPIO4 /* PA4 */ +#define GPIO_SPI1_SCK GPIO5 /* PA5 */ +#define GPIO_SPI1_MISO GPIO6 /* PA6 */ +#define GPIO_SPI1_MOSI GPIO7 /* PA7 */ + +#define GPIO_SPI1_RE_NSS GPIO15 /* PA15 */ +#define GPIO_SPI1_RE_SCK GPIO3 /* PB3 */ +#define GPIO_SPI1_RE_MISO GPIO4 /* PB4 */ +#define GPIO_SPI1_RE_MOSI GPIO5 /* PB5 */ + +/* SPI1 BANK */ +#define GPIO_BANK_SPI1_NSS GPIOA /* PA4 */ +#define GPIO_BANK_SPI1_SCK GPIOA /* PA5 */ +#define GPIO_BANK_SPI1_MISO GPIOA /* PA6 */ +#define GPIO_BANK_SPI1_MOSI GPIOA /* PA7 */ + +#define GPIO_BANK_SPI1_RE_NSS GPIOA /* PA15 */ +#define GPIO_BANK_SPI1_RE_SCK GPIOB /* PB3 */ +#define GPIO_BANK_SPI1_RE_MISO GPIOB /* PB4 */ +#define GPIO_BANK_SPI1_RE_MOSI GPIOB /* PB5 */ + +/* SPI2 GPIO */ +#define GPIO_SPI2_NSS GPIO12 /* PB12 */ +#define GPIO_SPI2_SCK GPIO13 /* PB13 */ +#define GPIO_SPI2_MISO GPIO14 /* PB14 */ +#define GPIO_SPI2_MOSI GPIO15 /* PB15 */ + +/* SPI2 BANK */ +#define GPIO_BANK_SPI2_NSS GPIOB /* PB12 */ +#define GPIO_BANK_SPI2_SCK GPIOB /* PB13 */ +#define GPIO_BANK_SPI2_MISO GPIOB /* PB14 */ +#define GPIO_BANK_SPI2_MOSI GPIOB /* PB15 */ + +/* SPI3 GPIO */ +#define GPIO_SPI3_NSS GPIO15 /* PA15 */ +#define GPIO_SPI3_SCK GPIO3 /* PB3 */ +#define GPIO_SPI3_MISO GPIO4 /* PB4 */ +#define GPIO_SPI3_MOSI GPIO5 /* PB5 */ + +#define GPIO_SPI3_RE_NSS GPIO4 /* PA4 */ +#define GPIO_SPI3_RE_SCK GPIO10 /* PC10 */ +#define GPIO_SPI3_RE_MISO GPIO11 /* PC11 */ +#define GPIO_SPI3_RE_MOSI GPIO12 /* PC12 */ + +/* SPI3 BANK */ +#define GPIO_BANK_SPI3_NSS GPIOA /* PA15 */ +#define GPIO_BANK_SPI3_SCK GPIOB /* PB3 */ +#define GPIO_BANK_SPI3_MISO GPIOB /* PB4 */ +#define GPIO_BANK_SPI3_MOSI GPIOB /* PB5 */ + +#define GPIO_BANK_SPI3_RE_NSS GPIOA /* PA4 */ +#define GPIO_BANK_SPI3_RE_SCK GPIOC /* PC10 */ +#define GPIO_BANK_SPI3_RE_MISO GPIOC /* PC11 */ +#define GPIO_BANK_SPI3_RE_MOSI GPIOC /* PC12 */ + +/* ETH GPIO */ +#define GPIO_ETH_RX_DV_CRS_DV GPIO7 /* PA7 */ +#define GPIO_ETH_RXD0 GPIO4 /* PC4 */ +#define GPIO_ETH_RXD1 GPIO5 /* PC5 */ +#define GPIO_ETH_RXD2 GPIO0 /* PB0 */ +#define GPIO_ETH_RXD3 GPIO1 /* PB1 */ + +#define GPIO_ETH_RE_RX_DV_CRS_DV GPIO8 /* PD8 */ +#define GPIO_ETH_RE_RXD0 GPIO9 /* PD9 */ +#define GPIO_ETH_RE_RXD1 GPIO10 /* PD10 */ +#define GPIO_ETH_RE_RXD2 GPIO11 /* PD11 */ +#define GPIO_ETH_RE_RXD3 GPIO12 /* PD12 */ + +/* ETH BANK */ +#define GPIO_BANK_ETH_RX_DV_CRS_DV GPIOA /* PA7 */ +#define GPIO_BANK_ETH_RXD0 GPIOC /* PC4 */ +#define GPIO_BANK_ETH_RXD1 GPIOC /* PC5 */ +#define GPIO_BANK_ETH_RXD2 GPIOB /* PB0 */ +#define GPIO_BANK_ETH_RXD3 GPIOB /* PB1 */ + +#define GPIO_BANK_ETH_RE_RX_DV_CRS_DV GPIOD /* PD8 */ +#define GPIO_BANK_ETH_RE_RXD0 GPIOD /* PD9 */ +#define GPIO_BANK_ETH_RE_RXD1 GPIOD /* PD10 */ +#define GPIO_BANK_ETH_RE_RXD2 GPIOD /* PD11 */ +#define GPIO_BANK_ETH_RE_RXD3 GPIOD /* PD12 */ + +/* --- GPIO registers ------------------------------------------------------ */ + +/* Port configuration register low (GPIOx_CRL) */ +#define GPIO_CRL(port) MMIO32(port + 0x00) +#define GPIOA_CRL GPIO_CRL(GPIOA) +#define GPIOB_CRL GPIO_CRL(GPIOB) +#define GPIOC_CRL GPIO_CRL(GPIOC) +#define GPIOD_CRL GPIO_CRL(GPIOD) +#define GPIOE_CRL GPIO_CRL(GPIOE) +#define GPIOF_CRL GPIO_CRL(GPIOF) +#define GPIOG_CRL GPIO_CRL(GPIOG) + +/* Port configuration register low (GPIOx_CRH) */ +#define GPIO_CRH(port) MMIO32(port + 0x04) +#define GPIOA_CRH GPIO_CRH(GPIOA) +#define GPIOB_CRH GPIO_CRH(GPIOB) +#define GPIOC_CRH GPIO_CRH(GPIOC) +#define GPIOD_CRH GPIO_CRH(GPIOD) +#define GPIOE_CRH GPIO_CRH(GPIOE) +#define GPIOF_CRH GPIO_CRH(GPIOF) +#define GPIOG_CRH GPIO_CRH(GPIOG) + +/* Port input data register (GPIOx_IDR) */ +#define GPIO_IDR(port) MMIO32(port + 0x08) +#define GPIOA_IDR GPIO_IDR(GPIOA) +#define GPIOB_IDR GPIO_IDR(GPIOB) +#define GPIOC_IDR GPIO_IDR(GPIOC) +#define GPIOD_IDR GPIO_IDR(GPIOD) +#define GPIOE_IDR GPIO_IDR(GPIOE) +#define GPIOF_IDR GPIO_IDR(GPIOF) +#define GPIOG_IDR GPIO_IDR(GPIOG) + +/* Port output data register (GPIOx_ODR) */ +#define GPIO_ODR(port) MMIO32(port + 0x0c) +#define GPIOA_ODR GPIO_ODR(GPIOA) +#define GPIOB_ODR GPIO_ODR(GPIOB) +#define GPIOC_ODR GPIO_ODR(GPIOC) +#define GPIOD_ODR GPIO_ODR(GPIOD) +#define GPIOE_ODR GPIO_ODR(GPIOE) +#define GPIOF_ODR GPIO_ODR(GPIOF) +#define GPIOG_ODR GPIO_ODR(GPIOG) + +/* Port bit set/reset register (GPIOx_BSRR) */ +#define GPIO_BSRR(port) MMIO32(port + 0x10) +#define GPIOA_BSRR GPIO_BSRR(GPIOA) +#define GPIOB_BSRR GPIO_BSRR(GPIOB) +#define GPIOC_BSRR GPIO_BSRR(GPIOC) +#define GPIOD_BSRR GPIO_BSRR(GPIOD) +#define GPIOE_BSRR GPIO_BSRR(GPIOE) +#define GPIOF_BSRR GPIO_BSRR(GPIOF) +#define GPIOG_BSRR GPIO_BSRR(GPIOG) + +/* Port bit reset register (GPIOx_BRR) */ +#define GPIO_BRR(port) MMIO16(port + 0x14) +#define GPIOA_BRR GPIO_BRR(GPIOA) +#define GPIOB_BRR GPIO_BRR(GPIOB) +#define GPIOC_BRR GPIO_BRR(GPIOC) +#define GPIOD_BRR GPIO_BRR(GPIOD) +#define GPIOE_BRR GPIO_BRR(GPIOE) +#define GPIOF_BRR GPIO_BRR(GPIOF) +#define GPIOG_BRR GPIO_BRR(GPIOG) + +/* Port configuration lock register (GPIOx_LCKR) */ +#define GPIO_LCKR(port) MMIO32(port + 0x18) +#define GPIOA_LCKR GPIO_LCKR(GPIOA) +#define GPIOB_LCKR GPIO_LCKR(GPIOB) +#define GPIOC_LCKR GPIO_LCKR(GPIOC) +#define GPIOD_LCKR GPIO_LCKR(GPIOD) +#define GPIOE_LCKR GPIO_LCKR(GPIOE) +#define GPIOF_LCKR GPIO_LCKR(GPIOF) +#define GPIOG_LCKR GPIO_LCKR(GPIOG) + +/* --- GPIO_CRL/GPIO_CRH values -------------------------------------------- */ + +/** @defgroup gpio_cnf GPIO Pin Configuration +@ingroup gpio_defines +If mode specifies input, configuration can be +@li Analog input +@li Floating input +@li Pull up/down input + +If mode specifies output, configuration can be +@li Digital push-pull +@li Digital open drain +@li Alternate function push-pull or analog output +@li Alternate function open drain or analog output +@{*/ +/* CNF[1:0] values when MODE[1:0] is 00 (input mode) */ +/** Analog Input */ +#define GPIO_CNF_INPUT_ANALOG 0x00 +/** Digital Input Floating */ +#define GPIO_CNF_INPUT_FLOAT 0x01 /* Default */ +/** Digital Input Pull Up and Down */ +#define GPIO_CNF_INPUT_PULL_UPDOWN 0x02 +/* CNF[1:0] values when MODE[1:0] is != 00 (one of the output modes) */ +/** Digital Output Pushpull */ +#define GPIO_CNF_OUTPUT_PUSHPULL 0x00 +/** Digital Output Open Drain */ +#define GPIO_CNF_OUTPUT_OPENDRAIN 0x01 +/** Alternate Function Output Pushpull */ +#define GPIO_CNF_OUTPUT_ALTFN_PUSHPULL 0x02 +/** Alternate Function Output Open Drain */ +#define GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN 0x03 +/**@}*/ + +/* Pin mode (MODE[1:0]) values */ +/** @defgroup gpio_mode GPIO Pin Mode +@ingroup gpio_defines +@li Input (default after reset) +@li Output mode at 10 MHz maximum speed +@li Output mode at 2 MHz maximum speed +@li Output mode at 50 MHz maximum speed +@{*/ +#define GPIO_MODE_INPUT 0x00 /* Default */ +#define GPIO_MODE_OUTPUT_10_MHZ 0x01 +#define GPIO_MODE_OUTPUT_2_MHZ 0x02 +#define GPIO_MODE_OUTPUT_50_MHZ 0x03 +/**@}*/ + +/* --- GPIO_IDR values ----------------------------------------------------- */ + +/* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */ + +/* --- GPIO_ODR values ----------------------------------------------------- */ + +/* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */ + +/* --- GPIO_BSRR values ---------------------------------------------------- */ + +/* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */ +/* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */ + +/* --- GPIO_BRR values ----------------------------------------------------- */ + +/* GPIO_BRR[15:0]: BRy: Port x reset bit y (y = 0..15) */ + +/* --- AFIO registers ------------------------------------------------------ */ + +/* Event control register (AFIO_EVCR) */ +#define AFIO_EVCR MMIO32(AFIO_BASE + 0x00) + +/* AF remap and debug I/O configuration register (AFIO_MAPR) */ +#define AFIO_MAPR MMIO32(AFIO_BASE + 0x04) + +/* External interrupt configuration register [0..3] (AFIO_EXTICR[1..4])*/ +#define AFIO_EXTICR(i) MMIO32(AFIO_BASE + 0x08 + (i)*4) +#define AFIO_EXTICR1 AFIO_EXTICR(0) +#define AFIO_EXTICR2 AFIO_EXTICR(1) +#define AFIO_EXTICR3 AFIO_EXTICR(2) +#define AFIO_EXTICR4 AFIO_EXTICR(3) + +/* AF remap and debug I/O configuration register (AFIO_MAPR) */ +#define AFIO_MAPR2 MMIO32(AFIO_BASE + 0x1C) + +/* --- AFIO_EVCR values ---------------------------------------------------- */ + +/* EVOE: Event output enable */ +#define AFIO_EVCR_EVOE (1 << 7) + +/* PORT[2:0]: Port selection */ +/** @defgroup afio_evcr_port EVENTOUT Port selection +@ingroup gpio_defines + +@{*/ +#define AFIO_EVCR_PORT_PA (0x0 << 4) +#define AFIO_EVCR_PORT_PB (0x1 << 4) +#define AFIO_EVCR_PORT_PC (0x2 << 4) +#define AFIO_EVCR_PORT_PD (0x3 << 4) +#define AFIO_EVCR_PORT_PE (0x4 << 4) +/**@}*/ + +/* PIN[3:0]: Pin selection */ +/** @defgroup afio_evcr_pin EVENTOUT Pin selection +@ingroup gpio_defines + +@{*/ +#define AFIO_EVCR_PIN_Px0 (0x0 << 0) +#define AFIO_EVCR_PIN_Px1 (0x1 << 0) +#define AFIO_EVCR_PIN_Px2 (0x2 << 0) +#define AFIO_EVCR_PIN_Px3 (0x3 << 0) +#define AFIO_EVCR_PIN_Px4 (0x4 << 0) +#define AFIO_EVCR_PIN_Px5 (0x5 << 0) +#define AFIO_EVCR_PIN_Px6 (0x6 << 0) +#define AFIO_EVCR_PIN_Px7 (0x7 << 0) +#define AFIO_EVCR_PIN_Px8 (0x8 << 0) +#define AFIO_EVCR_PIN_Px9 (0x9 << 0) +#define AFIO_EVCR_PIN_Px10 (0xA << 0) +#define AFIO_EVCR_PIN_Px11 (0xB << 0) +#define AFIO_EVCR_PIN_Px12 (0xC << 0) +#define AFIO_EVCR_PIN_Px13 (0xD << 0) +#define AFIO_EVCR_PIN_Px14 (0xE << 0) +#define AFIO_EVCR_PIN_Px15 (0xF << 0) +/**@}*/ + +/* --- AFIO_MAPR values ---------------------------------------------------- */ + +/* 31 reserved */ + +/** @defgroup afio_remap_cld Alternate Function Remap Controls for Connectivity +Line Devices only +@ingroup gpio_defines + +@{*/ +/* PTP_PPS_REMAP: */ +/** Ethernet PTP PPS remapping (only connectivity line devices) */ +#define AFIO_MAPR_PTP_PPS_REMAP (1 << 30) + +/* TIM2ITR1_IREMAP: */ +/** TIM2 internal trigger 1 remapping (only connectivity line devices) */ +#define AFIO_MAPR_TIM2ITR1_IREMAP (1 << 29) + +/* SPI3_REMAP: */ +/** SPI3/I2S3 remapping (only connectivity line devices) */ +#define AFIO_MAPR_SPI3_REMAP (1 << 28) + +/* MII_REMAP: */ +/** MII or RMII selection (only connectivity line devices) */ +#define AFIO_MAPR_MII_RMII_SEL (1 << 23) + +/* CAN2_REMAP: */ +/** CAN2 I/O remapping (only connectivity line devices) */ +#define AFIO_MAPR_CAN2_REMAP (1 << 22) + +/* ETH_REMAP: */ +/** Ethernet MAC I/O remapping (only connectivity line devices) */ +#define AFIO_MAPR_ETH_REMAP (1 << 21) + +/**@}*/ + +/* 27 reserved */ + +/* SWJ_CFG[2:0]: Serial wire JTAG configuration */ +/** @defgroup afio_swj_disable Serial Wire JTAG disables +@ingroup gpio_defines + +@{*/ +#define AFIO_MAPR_SWJ_MASK (0x7 << 24) +/** Full Serial Wire JTAG capability */ +#define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24) +/** Full Serial Wire JTAG capability without JNTRST */ +#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST (0x1 << 24) +/** JTAG-DP disabled with SW-DP enabled */ +#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (0x2 << 24) +/** JTAG-DP disabled and SW-DP disabled */ +#define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF (0x4 << 24) +/**@}*/ + +/** @defgroup afio_remap Alternate Function Remap Controls +@ingroup gpio_defines + +@{*/ +/* ADC2_ETRGREG_REMAP: */ +/** + * ADC2 external trigger regulator conversion remapping + * (only low-, medium-, high- and XL-density devices) + */ +#define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20) + +/* ADC2_ETRGINJ_REMAP: */ +/** + * ADC2 external trigger injected conversion remapping + * (only low-, medium-, high- and XL-density devices) + */ +#define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19) + +/* ADC1_ETRGREG_REMAP: */ +/** + * ADC1 external trigger regulator conversion remapping + * (only low-, medium-, high- and XL-density devices) + */ +#define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18) + +/* ADC1_ETRGINJ_REMAP: */ +/** + * ADC1 external trigger injected conversion remapping + * (only low-, medium-, high- and XL-density devices) + */ +#define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17) + +/* TIM5CH4_IREMAP: */ +/** TIM5 channel 4 internal remap */ +#define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16) + +/* PD01_REMAP: */ +/** Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_MAPR_PD01_REMAP (1 << 15) + +/* TIM4_REMAP: */ +/** TIM4 remapping */ +#define AFIO_MAPR_TIM4_REMAP (1 << 12) + +/* USART2_REMAP[1:0]: */ +/** USART2 remapping */ +#define AFIO_MAPR_USART2_REMAP (1 << 3) + +/* USART1_REMAP[1:0]: */ +/** USART1 remapping */ +#define AFIO_MAPR_USART1_REMAP (1 << 2) + +/* I2C1_REMAP[1:0]: */ +/** I2C1 remapping */ +#define AFIO_MAPR_I2C1_REMAP (1 << 1) + +/* SPI1_REMAP[1:0]: */ +/** SPI1 remapping */ +#define AFIO_MAPR_SPI1_REMAP (1 << 0) +/**@}*/ + +/* CAN_REMAP[1:0]: CAN1 alternate function remapping */ +/** @defgroup afio_remap_can1 Alternate Function Remap Controls for CAN 1 +@ingroup gpio_defines + +@{*/ +#define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13) +#define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not 36pin pkg */ +#define AFIO_MAPR_CAN1_REMAP_PORTD (0x3 << 13) +/**@}*/ + +/* TIM3_REMAP[1:0]: TIM3 remapping */ +/** @defgroup afio_remap_tim3 Alternate Function Remap Controls for Timer 3 +@ingroup gpio_defines + +@{*/ +#define AFIO_MAPR_TIM3_REMAP_NO_REMAP (0x0 << 10) +#define AFIO_MAPR_TIM3_REMAP_PARTIAL_REMAP (0x2 << 10) +#define AFIO_MAPR_TIM3_REMAP_FULL_REMAP (0x3 << 10) +/**@}*/ + +/* TIM2_REMAP[1:0]: TIM2 remapping */ +/** @defgroup afio_remap_tim2 Alternate Function Remap Controls for Timer 2 +@ingroup gpio_defines + +@{*/ +#define AFIO_MAPR_TIM2_REMAP_NO_REMAP (0x0 << 8) +#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1 (0x1 << 8) +#define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP2 (0x2 << 8) +#define AFIO_MAPR_TIM2_REMAP_FULL_REMAP (0x3 << 8) +/**@}*/ + +/* TIM1_REMAP[1:0]: TIM1 remapping */ +/** @defgroup afio_remap_tim1 Alternate Function Remap Controls for Timer 1 +@ingroup gpio_defines + +@{*/ +#define AFIO_MAPR_TIM1_REMAP_NO_REMAP (0x0 << 6) +#define AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP (0x1 << 6) +#define AFIO_MAPR_TIM1_REMAP_FULL_REMAP (0x3 << 6) +/**@}*/ + +/* USART3_REMAP[1:0]: USART3 remapping */ +/** @defgroup afio_remap_usart3 Alternate Function Remap Controls for USART 3 +@ingroup gpio_defines + +@{*/ +#define AFIO_MAPR_USART3_REMAP_NO_REMAP (0x0 << 4) +#define AFIO_MAPR_USART3_REMAP_PARTIAL_REMAP (0x1 << 4) +#define AFIO_MAPR_USART3_REMAP_FULL_REMAP (0x3 << 4) +/**@}*/ + +/** @defgroup afio_remap2 Alternate Function Remap Controls Secondary Set +@ingroup gpio_defines + +@{*/ +/* FSMC_NADV_DISCONNECT: */ +/** The NADV is disconnected from its allocated pin */ +#define AFIO_MAPR2_FSMC_NADV_DISCONNECT (1 << 10) + +/* TIM14_REMAP: */ +/** TIM14 remapping */ +#define AFIO_MAPR2_TIM14_REMAP (1 << 9) + +/* TIM13_REMAP: */ +/** TIM13 remapping */ +#define AFIO_MAPR2_TIM13_REMAP (1 << 8) + +/* TIM11_REMAP: */ +/** TIM11 remapping */ +#define AFIO_MAPR2_TIM11_REMAP (1 << 7) + +/* TIM10_REMAP: */ +/** TIM10 remapping */ +#define AFIO_MAPR2_TIM10_REMAP (1 << 6) + +/* TIM9_REMAP: */ +/** TIM9 remapping */ +#define AFIO_MAPR2_TIM9_REMAP (1 << 5) + +/**@}*/ + +/* --- AFIO_EXTICR1 values ------------------------------------------------- */ +/* --- AFIO_EXTICR2 values ------------------------------------------------- */ +/* --- AFIO_EXTICR3 values ------------------------------------------------- */ +/* --- AFIO_EXTICR4 values ------------------------------------------------- */ + +/** @defgroup afio_exti Alternate Function EXTI pin number +@ingroup gpio_defines + +@{*/ + +#define AFIO_EXTI0 0 +#define AFIO_EXTI1 1 +#define AFIO_EXTI2 2 +#define AFIO_EXTI3 3 +#define AFIO_EXTI4 4 +#define AFIO_EXTI5 5 +#define AFIO_EXTI6 6 +#define AFIO_EXTI7 7 +#define AFIO_EXTI8 8 +#define AFIO_EXTI9 9 +#define AFIO_EXTI10 10 +#define AFIO_EXTI11 11 +#define AFIO_EXTI12 12 +#define AFIO_EXTI13 13 +#define AFIO_EXTI14 14 +#define AFIO_EXTI15 15 + +/**@}*/ + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void gpio_set_mode(uint32_t gpioport, uint8_t mode, uint8_t cnf, + uint16_t gpios); +void gpio_set_eventout(uint8_t evoutport, uint8_t evoutpin); +void gpio_primary_remap(uint32_t swjenable, uint32_t maps); +void gpio_secondary_remap(uint32_t maps); + +END_DECLS + +#endif +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/f1/i2c.h b/libopencm3/include/libopencm3/stm32/f1/i2c.h new file mode 100644 index 0000000..19c26a3 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f1/i2c.h @@ -0,0 +1,37 @@ +/** @defgroup i2c_defines I2C Defines + +@brief Defined Constants and Types for the STM32F1xx I2C + +@ingroup STM32F1xx_defines + +@version 1.0.0 + +@date 12 October 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_I2C_H +#define LIBOPENCM3_I2C_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f1/irq.json b/libopencm3/include/libopencm3/stm32/f1/irq.json new file mode 100644 index 0000000..20bf00c --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f1/irq.json @@ -0,0 +1,75 @@ +{ + "irqs": [ + "wwdg", + "pvd", + "tamper", + "rtc", + "flash", + "rcc", + "exti0", + "exti1", + "exti2", + "exti3", + "exti4", + "dma1_channel1", + "dma1_channel2", + "dma1_channel3", + "dma1_channel4", + "dma1_channel5", + "dma1_channel6", + "dma1_channel7", + "adc1_2", + "usb_hp_can_tx", + "usb_lp_can_rx0", + "can_rx1", + "can_sce", + "exti9_5", + "tim1_brk", + "tim1_up", + "tim1_trg_com", + "tim1_cc", + "tim2", + "tim3", + "tim4", + "i2c1_ev", + "i2c1_er", + "i2c2_ev", + "i2c2_er", + "spi1", + "spi2", + "usart1", + "usart2", + "usart3", + "exti15_10", + "rtc_alarm", + "usb_wakeup", + "tim8_brk", + "tim8_up", + "tim8_trg_com", + "tim8_cc", + "adc3", + "fsmc", + "sdio", + "tim5", + "spi3", + "uart4", + "uart5", + "tim6", + "tim7", + "dma2_channel1", + "dma2_channel2", + "dma2_channel3", + "dma2_channel4_5", + "dma2_channel5", + "eth", + "eth_wkup", + "can2_tx", + "can2_rx0", + "can2_rx1", + "can2_sce", + "otg_fs" + ], + "partname_humanreadable": "STM32 F1 series", + "partname_doxygen": "STM32F1", + "includeguard": "LIBOPENCM3_STM32_F1_NVIC_H" +} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/stm32/f1/iwdg.h b/libopencm3/include/libopencm3/stm32/f1/iwdg.h new file mode 100644 index 0000000..cdb5115 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f1/iwdg.h @@ -0,0 +1,39 @@ +/** @defgroup iwdg_defines IWDG Defines + +@brief Defined Constants and Types for the STM32F1xx Independent Watchdog +Timer + +@ingroup STM32F1xx_defines + +@version 1.0.0 + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_IWDG_H +#define LIBOPENCM3_IWDG_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f1/memorymap.h b/libopencm3/include/libopencm3/stm32/f1/memorymap.h new file mode 100644 index 0000000..046335e --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f1/memorymap.h @@ -0,0 +1,127 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_MEMORYMAP_H +#define LIBOPENCM3_MEMORYMAP_H + +#include + +/* --- STM32 specific peripheral definitions ------------------------------- */ + +/* Memory map for all buses */ +#define FLASH_BASE (0x08000000U) +#define PERIPH_BASE (0x40000000U) +#define INFO_BASE (0x1ffff000U) +#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) +#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) +#define PERIPH_BASE_AHB (PERIPH_BASE + 0x18000) + +/* Register boundary addresses */ + +/* APB1 */ +#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) +#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) +#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) +#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) +#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) +#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) +#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800) +#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00) +#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) +/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ +#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) +#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) +#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) +/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ +#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) +#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) +/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ +#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) +#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) +#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) +#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) +#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) +#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) +#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00) +#define USB_CAN_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000) +#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) +#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800) +/* PERIPH_BASE_APB1 + 0x6800 (0x4000 6800 - 0x4000 6BFF): Reserved? Typo? */ +#define BACKUP_REGS_BASE (PERIPH_BASE_APB1 + 0x6c00) +#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) +#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) +#define CEC_BASE (PERIPH_BASE_APB1 + 0x7800) +/* PERIPH_BASE_APB1 + 0x7c00 (0x4000 7c00 - 0x4000 FFFF): Reserved */ + +/* APB2 */ +#define AFIO_BASE (PERIPH_BASE_APB2 + 0x0000) +#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) +#define GPIO_PORT_A_BASE (PERIPH_BASE_APB2 + 0x0800) +#define GPIO_PORT_B_BASE (PERIPH_BASE_APB2 + 0x0c00) +#define GPIO_PORT_C_BASE (PERIPH_BASE_APB2 + 0x1000) +#define GPIO_PORT_D_BASE (PERIPH_BASE_APB2 + 0x1400) +#define GPIO_PORT_E_BASE (PERIPH_BASE_APB2 + 0x1800) +#define GPIO_PORT_F_BASE (PERIPH_BASE_APB2 + 0x1c00) +#define GPIO_PORT_G_BASE (PERIPH_BASE_APB2 + 0x2000) +#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2400) +#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2800) +#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2c00) +#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) +#define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400) +#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) +#define ADC3_BASE (PERIPH_BASE_APB2 + 0x3c00) +#define TIM15_BASE (PERIPH_BASE_APB2 + 0x4000) +#define TIM16_BASE (PERIPH_BASE_APB2 + 0x4400) +#define TIM17_BASE (PERIPH_BASE_APB2 + 0x4800) +#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4c00) +#define TIM10_BASE (PERIPH_BASE_APB2 + 0x5000) +#define TIM11_BASE (PERIPH_BASE_APB2 + 0x5400) +/* PERIPH_BASE_APB2 + 0x5800 (0x4001 5800 - 0x4001 7FFF): Reserved */ + +/* AHB */ +#define SDIO_BASE (PERIPH_BASE_AHB + 0x00000) +/* PERIPH_BASE_AHB + 0x0400 (0x4001 8400 - 0x4001 7FFF): Reserved */ +#define DMA1_BASE (PERIPH_BASE_AHB + 0x08000) +#define DMA2_BASE (PERIPH_BASE_AHB + 0x08400) +/* PERIPH_BASE_AHB + 0x8800 (0x4002 0800 - 0x4002 0FFF): Reserved */ +#define RCC_BASE (PERIPH_BASE_AHB + 0x09000) +/* PERIPH_BASE_AHB + 0x9400 (0x4002 1400 - 0x4002 1FFF): Reserved */ +#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x0a000) +#define CRC_BASE (PERIPH_BASE_AHB + 0x0b000) +/* PERIPH_BASE_AHB + 0xb400 (0x4002 3400 - 0x4002 7FFF): Reserved */ +#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000) +/* PERIPH_BASE_AHB + 0x18000 (0x4003 0000 - 0x4FFF FFFF): Reserved */ +#define USB_OTG_FS_BASE (PERIPH_BASE_AHB + 0xffe8000) + +/* PPIB */ +#define DBGMCU_BASE (PPBI_BASE + 0x00042000) + +/* FSMC */ +#define FSMC_BASE (PERIPH_BASE + 0x60000000) + +/* Device Electronic Signature */ +#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x7e0) +#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x7e8) +/* Ignore the "reserved for future use" half of the first word */ +#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) +#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) +#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8) + + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f1/pwr.h b/libopencm3/include/libopencm3/stm32/f1/pwr.h new file mode 100644 index 0000000..51b3977 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f1/pwr.h @@ -0,0 +1,37 @@ +/** @defgroup pwr_defines PWR Defines + +@brief Defined Constants and Types for the STM32F1xx PWR Control + +@ingroup STM32F1xx_defines + +@version 1.0.0 + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_PWR_H +#define LIBOPENCM3_PWR_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f1/rcc.h b/libopencm3/include/libopencm3/stm32/f1/rcc.h new file mode 100644 index 0000000..799b8c2 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f1/rcc.h @@ -0,0 +1,718 @@ +/** @defgroup rcc_defines RCC Defines + * + * @brief Defined Constants and Types for the STM32F1xx Reset and Clock + * Control + * + * @ingroup STM32F1xx_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2009 + * Federico Ruiz-Ugalde \ + * @author @htmlonly © @endhtmlonly 2009 + * Uwe Hermann + * + * @date 18 August 2012 + * + * LGPL License Terms @ref lgpl_license + * */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2009 Federico Ruiz-Ugalde + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ +/**@{*/ + +#ifndef LIBOPENCM3_RCC_H +#define LIBOPENCM3_RCC_H + +/* Note: Regs/bits marked (**) only exist in "connectivity line" STM32s. */ +/* Note: Regs/bits marked (XX) do NOT exist in "connectivity line" STM32s. */ + +/* --- RCC registers ------------------------------------------------------- */ + +#define RCC_CR MMIO32(RCC_BASE + 0x00) +#define RCC_CFGR MMIO32(RCC_BASE + 0x04) +#define RCC_CIR MMIO32(RCC_BASE + 0x08) +#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0c) +#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10) +#define RCC_AHBENR MMIO32(RCC_BASE + 0x14) +#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18) +#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c) +#define RCC_BDCR MMIO32(RCC_BASE + 0x20) +#define RCC_CSR MMIO32(RCC_BASE + 0x24) +#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /*(**)*/ +#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /*(**)*/ + +/* --- RCC_CR values ------------------------------------------------------- */ + +#define RCC_CR_PLL3RDY (1 << 29) /* (**) */ +#define RCC_CR_PLL3ON (1 << 28) /* (**) */ +#define RCC_CR_PLL2RDY (1 << 27) /* (**) */ +#define RCC_CR_PLL2ON (1 << 26) /* (**) */ +#define RCC_CR_PLLRDY (1 << 25) +#define RCC_CR_PLLON (1 << 24) +#define RCC_CR_CSSON (1 << 19) +#define RCC_CR_HSEBYP (1 << 18) +#define RCC_CR_HSERDY (1 << 17) +#define RCC_CR_HSEON (1 << 16) +/* HSICAL: [15:8] */ +/* HSITRIM: [7:3] */ +#define RCC_CR_HSIRDY (1 << 1) +#define RCC_CR_HSION (1 << 0) + +/* --- RCC_CFGR values ----------------------------------------------------- */ + +#define RCC_CFGR_MCO_SHIFT 24 +#define RCC_CFGR_MCO (0xF << RCC_CFGR_MCO_SHIFT) + +#define RCC_CFGR_OTGFSPRE (1 << 22) /* Connectivity line */ +#define RCC_CFGR_USBPRE (1 << 22) /* LD,MD, HD, XL */ + +#define RCC_CFGR_PLLMUL_SHIFT 18 +#define RCC_CFGR_PLLMUL (0xF << RCC_CFGR_PLLMUL_SHIFT) + +#define RCC_CFGR_PLLXTPRE (1 << 17) +#define RCC_CFGR_PLLSRC (1 << 16) + +#define RCC_CFGR_ADCPRE_SHIFT 14 +#define RCC_CFGR_ADCPRE (3 << RCC_CFGR_ADCPRE_SHIFT) + +#define RCC_CFGR_PPRE2_SHIFT 11 +#define RCC_CFGR_PPRE2 (7 << RCC_CFGR_PPRE2_SHIFT) + +#define RCC_CFGR_PPRE1_SHIFT 8 +#define RCC_CFGR_PPRE1 (7 << RCC_CFGR_PPRE1_SHIFT) + +#define RCC_CFGR_HPRE_SHIFT 4 +#define RCC_CFGR_HPRE (0xF << RCC_CFGR_HPRE_SHIFT) + +#define RCC_CFGR_SWS_SHIFT 2 +#define RCC_CFGR_SWS (3 << RCC_CFGR_SWS_SHIFT) + +#define RCC_CFGR_SW_SHIFT 0 +#define RCC_CFGR_SW (3 << RCC_CFGR_SW_SHIFT) + +/* MCO: Microcontroller clock output */ +/** @defgroup rcc_cfgr_co RCC_CFGR Microcontroller Clock Output Source +@ingroup STM32F1xx_rcc_defines + +@{*/ +#define RCC_CFGR_MCO_NOCLK 0x0 +#define RCC_CFGR_MCO_SYSCLK 0x4 +#define RCC_CFGR_MCO_HSICLK 0x5 +#define RCC_CFGR_MCO_HSECLK 0x6 +#define RCC_CFGR_MCO_PLLCLK_DIV2 0x7 +#define RCC_CFGR_MCO_PLL2CLK 0x8 /* (**) */ +#define RCC_CFGR_MCO_PLL3CLK_DIV2 0x9 /* (**) */ +#define RCC_CFGR_MCO_XT1 0xa /* (**) */ +#define RCC_CFGR_MCO_PLL3 0xb /* (**) */ +/**@}*/ + +/* USBPRE: USB prescaler (RCC_CFGR[22]) */ +/** @defgroup rcc_cfgr_usbpre RCC_CFGR USB prescale Factors +@ingroup STM32F1xx_rcc_defines + +@{*/ +#define RCC_CFGR_USBPRE_PLL_CLK_DIV1_5 0x0 +#define RCC_CFGR_USBPRE_PLL_CLK_NODIV 0x1 +/**@}*/ + +/* OTGFSPRE: USB OTG FS prescaler (RCC_CFGR[22]; only in conn. line STM32s) */ +#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3 0x0 +#define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2 0x1 + +/* PLLMUL: PLL multiplication factor */ +/** @defgroup rcc_cfgr_pmf RCC_CFGR PLL Multiplication Factor +@ingroup STM32F1xx_rcc_defines + +@{*/ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL2 0x0 /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL3 0x1 /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL4 0x2 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL5 0x3 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6 0x4 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL7 0x5 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL8 0x6 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL9 0x7 +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL10 0x8 /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL11 0x9 /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL12 0xa /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL13 0xb /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL14 0xc /* (XX) */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL15 0xd /* 0xd: PLL x 15 */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn. + line */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */ +/* #define PLLMUL_PLL_CLK_MUL16 0xf */ /* (XX) */ /* Errata? 17? */ +/**@}*/ + +/* TODO: conn. line differs. */ +/* PLLXTPRE: HSE divider for PLL entry */ +/** @defgroup rcc_cfgr_hsepre RCC_CFGR HSE Divider for PLL +@ingroup STM32F1xx_rcc_defines + +@{*/ +#define RCC_CFGR_PLLXTPRE_HSE_CLK 0x0 +#define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2 0x1 +/**@}*/ + +/* PLLSRC: PLL entry clock source */ +/** @defgroup rcc_cfgr_pcs RCC_CFGR PLL Clock Source +@ingroup STM32F1xx_rcc_defines + +@{*/ +#define RCC_CFGR_PLLSRC_HSI_CLK_DIV2 0x0 +#define RCC_CFGR_PLLSRC_HSE_CLK 0x1 +#define RCC_CFGR_PLLSRC_PREDIV1_CLK 0x1 /* On conn. line */ +/**@}*/ + +/* ADCPRE: ADC prescaler */ +/****************************************************************************/ +/** @defgroup rcc_cfgr_adcpre RCC ADC clock prescaler enable values +@ingroup STM32F1xx_rcc_defines + +@{*/ +#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0 +#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1 +#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2 +#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3 +/**@}*/ + +/* PPRE2: APB high-speed prescaler (APB2) */ +/** @defgroup rcc_cfgr_apb2pre RCC_CFGR APB2 prescale Factors +@ingroup STM32F1xx_rcc_defines + +@{*/ +#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0 +#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4 +#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5 +#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6 +#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7 +/**@}*/ + +/* PPRE1: APB low-speed prescaler (APB1) */ +/** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB1 prescale Factors +@ingroup STM32F1xx_rcc_defines + +@{*/ +#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0 +#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4 +#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5 +#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6 +#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7 +/**@}*/ + +/* HPRE: AHB prescaler */ +/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB prescale Factors +@ingroup STM32F1xx_rcc_defines + +@{*/ +#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0 +#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8 +#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9 +#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa +#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb +#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc +#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd +#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe +#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf +/**@}*/ + +/* SWS: System clock switch status */ +#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x0 +#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x1 +#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x2 + +/* SW: System clock switch */ +/** @defgroup rcc_cfgr_scs RCC_CFGR System Clock Selection +@ingroup STM32F1xx_rcc_defines + +@{*/ +#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x0 +#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x1 +#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2 +/**@}*/ + +/* --- RCC_CIR values ------------------------------------------------------ */ + +/* Clock security system interrupt clear bit */ +#define RCC_CIR_CSSC (1 << 23) + +/* OSC ready interrupt clear bits */ +#define RCC_CIR_PLL3RDYC (1 << 22) /* (**) */ +#define RCC_CIR_PLL2RDYC (1 << 21) /* (**) */ +#define RCC_CIR_PLLRDYC (1 << 20) +#define RCC_CIR_HSERDYC (1 << 19) +#define RCC_CIR_HSIRDYC (1 << 18) +#define RCC_CIR_LSERDYC (1 << 17) +#define RCC_CIR_LSIRDYC (1 << 16) + +/* OSC ready interrupt enable bits */ +#define RCC_CIR_PLL3RDYIE (1 << 14) /* (**) */ +#define RCC_CIR_PLL2RDYIE (1 << 13) /* (**) */ +#define RCC_CIR_PLLRDYIE (1 << 12) +#define RCC_CIR_HSERDYIE (1 << 11) +#define RCC_CIR_HSIRDYIE (1 << 10) +#define RCC_CIR_LSERDYIE (1 << 9) +#define RCC_CIR_LSIRDYIE (1 << 8) + +/* Clock security system interrupt flag bit */ +#define RCC_CIR_CSSF (1 << 7) + +/* OSC ready interrupt flag bits */ +#define RCC_CIR_PLL3RDYF (1 << 6) /* (**) */ +#define RCC_CIR_PLL2RDYF (1 << 5) /* (**) */ +#define RCC_CIR_PLLRDYF (1 << 4) +#define RCC_CIR_HSERDYF (1 << 3) +#define RCC_CIR_HSIRDYF (1 << 2) +#define RCC_CIR_LSERDYF (1 << 1) +#define RCC_CIR_LSIRDYF (1 << 0) + +/* --- RCC_APB2RSTR values ------------------------------------------------- */ + +/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values +@ingroup STM32F1xx_rcc_defines + +@{*/ +#define RCC_APB2RSTR_ADC3RST (1 << 15) /* (XX) */ +#define RCC_APB2RSTR_USART1RST (1 << 14) +#define RCC_APB2RSTR_TIM8RST (1 << 13) /* (XX) */ +#define RCC_APB2RSTR_SPI1RST (1 << 12) +#define RCC_APB2RSTR_TIM1RST (1 << 11) +#define RCC_APB2RSTR_ADC2RST (1 << 10) +#define RCC_APB2RSTR_ADC1RST (1 << 9) +#define RCC_APB2RSTR_IOPGRST (1 << 8) /* (XX) */ +#define RCC_APB2RSTR_IOPFRST (1 << 7) /* (XX) */ +#define RCC_APB2RSTR_IOPERST (1 << 6) +#define RCC_APB2RSTR_IOPDRST (1 << 5) +#define RCC_APB2RSTR_IOPCRST (1 << 4) +#define RCC_APB2RSTR_IOPBRST (1 << 3) +#define RCC_APB2RSTR_IOPARST (1 << 2) +#define RCC_APB2RSTR_AFIORST (1 << 0) +/**@}*/ + +/* --- RCC_APB1RSTR values ------------------------------------------------- */ + +/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values +@ingroup STM32F1xx_rcc_defines + +@{*/ +#define RCC_APB1RSTR_DACRST (1 << 29) +#define RCC_APB1RSTR_PWRRST (1 << 28) +#define RCC_APB1RSTR_BKPRST (1 << 27) +#define RCC_APB1RSTR_CAN2RST (1 << 26) /* (**) */ +#define RCC_APB1RSTR_CAN1RST (1 << 25) /* (**) */ +#define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for + CAN1RST */ +#define RCC_APB1RSTR_USBRST (1 << 23) /* (XX) */ +#define RCC_APB1RSTR_I2C2RST (1 << 22) +#define RCC_APB1RSTR_I2C1RST (1 << 21) +#define RCC_APB1RSTR_UART5RST (1 << 20) +#define RCC_APB1RSTR_UART4RST (1 << 19) +#define RCC_APB1RSTR_USART3RST (1 << 18) +#define RCC_APB1RSTR_USART2RST (1 << 17) +#define RCC_APB1RSTR_SPI3RST (1 << 15) +#define RCC_APB1RSTR_SPI2RST (1 << 14) +#define RCC_APB1RSTR_WWDGRST (1 << 11) +#define RCC_APB1RSTR_TIM7RST (1 << 5) +#define RCC_APB1RSTR_TIM6RST (1 << 4) +#define RCC_APB1RSTR_TIM5RST (1 << 3) +#define RCC_APB1RSTR_TIM4RST (1 << 2) +#define RCC_APB1RSTR_TIM3RST (1 << 1) +#define RCC_APB1RSTR_TIM2RST (1 << 0) +/**@}*/ + +/* --- RCC_AHBENR values --------------------------------------------------- */ + +/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values +@ingroup STM32F1xx_rcc_defines + +@{*/ +#define RCC_AHBENR_ETHMACENRX (1 << 16) +#define RCC_AHBENR_ETHMACENTX (1 << 15) +#define RCC_AHBENR_ETHMACEN (1 << 14) +#define RCC_AHBENR_OTGFSEN (1 << 12) +#define RCC_AHBENR_SDIOEN (1 << 10) +#define RCC_AHBENR_FSMCEN (1 << 8) +#define RCC_AHBENR_CRCEN (1 << 6) +#define RCC_AHBENR_FLITFEN (1 << 4) +#define RCC_AHBENR_SRAMEN (1 << 2) +#define RCC_AHBENR_DMA2EN (1 << 1) +#define RCC_AHBENR_DMA1EN (1 << 0) +/**@}*/ + +/* --- RCC_APB2ENR values -------------------------------------------------- */ + +/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values +@ingroup STM32F1xx_rcc_defines + +@{*/ +#define RCC_APB2ENR_ADC3EN (1 << 15) /* (XX) */ +#define RCC_APB2ENR_USART1EN (1 << 14) +#define RCC_APB2ENR_TIM8EN (1 << 13) /* (XX) */ +#define RCC_APB2ENR_SPI1EN (1 << 12) +#define RCC_APB2ENR_TIM1EN (1 << 11) +#define RCC_APB2ENR_ADC2EN (1 << 10) +#define RCC_APB2ENR_ADC1EN (1 << 9) +#define RCC_APB2ENR_IOPGEN (1 << 8) /* (XX) */ +#define RCC_APB2ENR_IOPFEN (1 << 7) /* (XX) */ +#define RCC_APB2ENR_IOPEEN (1 << 6) +#define RCC_APB2ENR_IOPDEN (1 << 5) +#define RCC_APB2ENR_IOPCEN (1 << 4) +#define RCC_APB2ENR_IOPBEN (1 << 3) +#define RCC_APB2ENR_IOPAEN (1 << 2) +#define RCC_APB2ENR_AFIOEN (1 << 0) +/**@}*/ + +/* --- RCC_APB1ENR values -------------------------------------------------- */ + +/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values +@ingroup STM32F1xx_rcc_defines + +@{*/ +#define RCC_APB1ENR_DACEN (1 << 29) +#define RCC_APB1ENR_PWREN (1 << 28) +#define RCC_APB1ENR_BKPEN (1 << 27) +#define RCC_APB1ENR_CAN2EN (1 << 26) /* (**) */ +#define RCC_APB1ENR_CAN1EN (1 << 25) /* (**) */ +#define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for + CAN1EN */ +#define RCC_APB1ENR_USBEN (1 << 23) /* (XX) */ +#define RCC_APB1ENR_I2C2EN (1 << 22) +#define RCC_APB1ENR_I2C1EN (1 << 21) +#define RCC_APB1ENR_UART5EN (1 << 20) +#define RCC_APB1ENR_UART4EN (1 << 19) +#define RCC_APB1ENR_USART3EN (1 << 18) +#define RCC_APB1ENR_USART2EN (1 << 17) +#define RCC_APB1ENR_SPI3EN (1 << 15) +#define RCC_APB1ENR_SPI2EN (1 << 14) +#define RCC_APB1ENR_WWDGEN (1 << 11) +#define RCC_APB1ENR_TIM7EN (1 << 5) +#define RCC_APB1ENR_TIM6EN (1 << 4) +#define RCC_APB1ENR_TIM5EN (1 << 3) +#define RCC_APB1ENR_TIM4EN (1 << 2) +#define RCC_APB1ENR_TIM3EN (1 << 1) +#define RCC_APB1ENR_TIM2EN (1 << 0) +/**@}*/ + +/* --- RCC_BDCR values ----------------------------------------------------- */ + +#define RCC_BDCR_BDRST (1 << 16) +#define RCC_BDCR_RTCEN (1 << 15) +/* RCC_BDCR[9:8]: RTCSEL */ +#define RCC_BDCR_LSEBYP (1 << 2) +#define RCC_BDCR_LSERDY (1 << 1) +#define RCC_BDCR_LSEON (1 << 0) + +/* --- RCC_CSR values ------------------------------------------------------ */ + +#define RCC_CSR_LPWRRSTF (1 << 31) +#define RCC_CSR_WWDGRSTF (1 << 30) +#define RCC_CSR_IWDGRSTF (1 << 29) +#define RCC_CSR_SFTRSTF (1 << 28) +#define RCC_CSR_PORRSTF (1 << 27) +#define RCC_CSR_PINRSTF (1 << 26) +#define RCC_CSR_RMVF (1 << 24) +#define RCC_CSR_LSIRDY (1 << 1) +#define RCC_CSR_LSION (1 << 0) + +/* --- RCC_AHBRSTR values -------------------------------------------------- */ + +/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values +@ingroup STM32F1xx_rcc_defines + +@{*/ +#define RCC_AHBRSTR_ETHMACRST (1 << 14) +#define RCC_AHBRSTR_OTGFSRST (1 << 12) +/**@}*/ + +/* --- RCC_CFGR2 values ---------------------------------------------------- */ + +/* I2S3SRC: I2S3 clock source */ +#define RCC_CFGR2_I2S3SRC_SYSCLK 0x0 +#define RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK 0x1 + +/* I2S2SRC: I2S2 clock source */ +#define RCC_CFGR2_I2S2SRC_SYSCLK 0x0 +#define RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK 0x1 +#define RCC_CFGR2_I2S2SRC (1 << 17) + +/* PREDIV1SRC: PREDIV1 entry clock source */ +#define RCC_CFGR2_PREDIV1SRC_HSE_CLK 0x0 +#define RCC_CFGR2_PREDIV1SRC_PLL2_CLK 0x1 +#define RCC_CFGR2_PREDIV1SRC (1 << 16) + +#define RCC_CFGR2_PLL3MUL_SHIFT 12 +#define RCC_CFGR2_PLL3MUL (0xF << RCC_CFGR2_PLL3MUL_SHIFT) + +#define RCC_CFGR2_PLL2MUL_SHIFT 8 +#define RCC_CFGR2_PLL2MUL (0xF << RCC_CFGR2_PLL2MUL_SHIFT) + +#define RCC_CFGR2_PREDIV2_SHIFT 4 +#define RCC_CFGR2_PREDIV2 (0xF << RCC_CFGR2_PREDIV2_SHIFT) + +#define RCC_CFGR2_PREDIV1_SHIFT 0 +#define RCC_CFGR2_PREDIV1 (0xF << RCC_CFGR2_PREDIV1_SHIFT) + +/* PLL3MUL: PLL3 multiplication factor */ +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8 0x6 +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9 0x7 +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10 0x8 +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11 0x9 +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12 0xa +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13 0xb +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14 0xc +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16 0xe +#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20 0xf + +/* PLL2MUL: PLL2 multiplication factor */ +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8 0x6 +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9 0x7 +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10 0x8 +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11 0x9 +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12 0xa +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13 0xb +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14 0xc +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 0xe +#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 0xf + +/* PREDIV: PREDIV division factor */ +#define RCC_CFGR2_PREDIV_NODIV 0x0 +#define RCC_CFGR2_PREDIV_DIV2 0x1 +#define RCC_CFGR2_PREDIV_DIV3 0x2 +#define RCC_CFGR2_PREDIV_DIV4 0x3 +#define RCC_CFGR2_PREDIV_DIV5 0x4 +#define RCC_CFGR2_PREDIV_DIV6 0x5 +#define RCC_CFGR2_PREDIV_DIV7 0x6 +#define RCC_CFGR2_PREDIV_DIV8 0x7 +#define RCC_CFGR2_PREDIV_DIV9 0x8 +#define RCC_CFGR2_PREDIV_DIV10 0x9 +#define RCC_CFGR2_PREDIV_DIV11 0xa +#define RCC_CFGR2_PREDIV_DIV12 0xb +#define RCC_CFGR2_PREDIV_DIV13 0xc +#define RCC_CFGR2_PREDIV_DIV14 0xd +#define RCC_CFGR2_PREDIV_DIV15 0xe +#define RCC_CFGR2_PREDIV_DIV16 0xf + +/* PREDIV2: PREDIV2 division factor */ +#define RCC_CFGR2_PREDIV2_NODIV 0x0 +#define RCC_CFGR2_PREDIV2_DIV2 0x1 +#define RCC_CFGR2_PREDIV2_DIV3 0x2 +#define RCC_CFGR2_PREDIV2_DIV4 0x3 +#define RCC_CFGR2_PREDIV2_DIV5 0x4 +#define RCC_CFGR2_PREDIV2_DIV6 0x5 +#define RCC_CFGR2_PREDIV2_DIV7 0x6 +#define RCC_CFGR2_PREDIV2_DIV8 0x7 +#define RCC_CFGR2_PREDIV2_DIV9 0x8 +#define RCC_CFGR2_PREDIV2_DIV10 0x9 +#define RCC_CFGR2_PREDIV2_DIV11 0xa +#define RCC_CFGR2_PREDIV2_DIV12 0xb +#define RCC_CFGR2_PREDIV2_DIV13 0xc +#define RCC_CFGR2_PREDIV2_DIV14 0xd +#define RCC_CFGR2_PREDIV2_DIV15 0xe +#define RCC_CFGR2_PREDIV2_DIV16 0xf + +/* --- Variable definitions ------------------------------------------------ */ +extern uint32_t rcc_ppre1_frequency; +extern uint32_t rcc_ppre2_frequency; + +/* --- Function prototypes ------------------------------------------------- */ + +enum rcc_osc { + PLL, PLL2, PLL3, HSE, HSI, LSE, LSI +}; + +#define _REG_BIT(base, bit) (((base) << 5) + (bit)) + +/* V = value line F100 + * N = standard line F101, F102, F103 + * C = communication line F105, F107 + */ +enum rcc_periph_clken { + + /* AHB peripherals */ + RCC_DMA1 = _REG_BIT(0x14, 0),/*VNC*/ + RCC_DMA2 = _REG_BIT(0x14, 1),/*VNC*/ + RCC_SRAM = _REG_BIT(0x14, 2),/*VNC*/ + RCC_FLTF = _REG_BIT(0x14, 4),/*VNC*/ + RCC_CRC = _REG_BIT(0x14, 6),/*VNC*/ + RCC_FSMC = _REG_BIT(0x14, 8),/*VN-*/ + RCC_SDIO = _REG_BIT(0x14, 10),/*-N-*/ + RCC_OTGFS = _REG_BIT(0x14, 12),/*--C*/ + RCC_ETHMAC = _REG_BIT(0x14, 14),/*--C*/ + RCC_ETHMACTX = _REG_BIT(0x14, 15),/*--C*/ + RCC_ETHMACRX = _REG_BIT(0x14, 16),/*--C*/ + + /* APB2 peripherals */ + RCC_AFIO = _REG_BIT(0x18, 0),/*VNC*/ + RCC_GPIOA = _REG_BIT(0x18, 2),/*VNC*/ + RCC_GPIOB = _REG_BIT(0x18, 3),/*VNC*/ + RCC_GPIOC = _REG_BIT(0x18, 4),/*VNC*/ + RCC_GPIOD = _REG_BIT(0x18, 5),/*VNC*/ + RCC_GPIOE = _REG_BIT(0x18, 6),/*VNC*/ + RCC_GPIOF = _REG_BIT(0x18, 7),/*VN-*/ + RCC_GPIOG = _REG_BIT(0x18, 8),/*VN-*/ + RCC_ADC1 = _REG_BIT(0x18, 9),/*VNC*/ + RCC_ADC2 = _REG_BIT(0x18, 10),/*-NC*/ + RCC_TIM1 = _REG_BIT(0x18, 11),/*VNC*/ + RCC_SPI1 = _REG_BIT(0x18, 12),/*VNC*/ + RCC_TIM8 = _REG_BIT(0x18, 13),/*-N-*/ + RCC_USART1 = _REG_BIT(0x18, 14),/*VNC*/ + RCC_ADC3 = _REG_BIT(0x18, 15),/*-N-*/ + RCC_TIM15 = _REG_BIT(0x18, 16),/*V--*/ + RCC_TIM16 = _REG_BIT(0x18, 17),/*V--*/ + RCC_TIM17 = _REG_BIT(0x18, 18),/*V--*/ + RCC_TIM9 = _REG_BIT(0x18, 19),/*-N-*/ + RCC_TIM10 = _REG_BIT(0x18, 20),/*-N-*/ + RCC_TIM11 = _REG_BIT(0x18, 21),/*-N-*/ + + /* APB1 peripherals */ + RCC_TIM2 = _REG_BIT(0x1C, 0),/*VNC*/ + RCC_TIM3 = _REG_BIT(0x1C, 1),/*VNC*/ + RCC_TIM4 = _REG_BIT(0x1C, 2),/*VNC*/ + RCC_TIM5 = _REG_BIT(0x1C, 3),/*VNC*/ + RCC_TIM6 = _REG_BIT(0x1C, 4),/*VNC*/ + RCC_TIM7 = _REG_BIT(0x1C, 5),/*VNC*/ + RCC_TIM12 = _REG_BIT(0x1C, 6),/*VN-*/ + RCC_TIM13 = _REG_BIT(0x1C, 7),/*VN-*/ + RCC_TIM14 = _REG_BIT(0x1C, 8),/*VN-*/ + RCC_WWDG = _REG_BIT(0x1C, 11),/*VNC*/ + RCC_SPI2 = _REG_BIT(0x1C, 14),/*VNC*/ + RCC_SPI3 = _REG_BIT(0x1C, 15),/*VNC*/ + RCC_USART2 = _REG_BIT(0x1C, 17),/*VNC*/ + RCC_USART3 = _REG_BIT(0x1C, 18),/*VNC*/ + RCC_UART4 = _REG_BIT(0x1C, 19),/*VNC*/ + RCC_UART5 = _REG_BIT(0x1C, 20),/*VNC*/ + RCC_I2C1 = _REG_BIT(0x1C, 21),/*VNC*/ + RCC_I2C2 = _REG_BIT(0x1C, 22),/*VNC*/ + RCC_USB = _REG_BIT(0x1C, 23),/*-N-*/ + RCC_CAN = _REG_BIT(0x1C, 25),/*-N-*/ + RCC_CAN1 = _REG_BIT(0x1C, 25),/*--C*/ + RCC_CAN2 = _REG_BIT(0x1C, 26),/*--C*/ + RCC_BKP = _REG_BIT(0x1C, 27),/*VNC*/ + RCC_PWR = _REG_BIT(0x1C, 28),/*VNC*/ + RCC_DAC = _REG_BIT(0x1C, 29),/*VNC*/ + RCC_CEC = _REG_BIT(0x1C, 30),/*V--*/ +}; + +enum rcc_periph_rst { + + /* AHB peripherals */ + RST_OTGFS = _REG_BIT(0x28, 12),/*--C*/ + RST_ETHMAC = _REG_BIT(0x28, 14),/*--C*/ + + /* APB2 peripherals */ + RST_AFIO = _REG_BIT(0x0c, 0),/*VNC*/ + RST_GPIOA = _REG_BIT(0x0c, 2),/*VNC*/ + RST_GPIOB = _REG_BIT(0x0c, 3),/*VNC*/ + RST_GPIOC = _REG_BIT(0x0c, 4),/*VNC*/ + RST_GPIOD = _REG_BIT(0x0c, 5),/*VNC*/ + RST_GPIOE = _REG_BIT(0x0c, 6),/*VNC*/ + RST_GPIOF = _REG_BIT(0x0c, 7),/*VN-*/ + RST_GPIOG = _REG_BIT(0x0c, 8),/*VN-*/ + RST_ADC1 = _REG_BIT(0x0c, 9),/*VNC*/ + RST_ADC2 = _REG_BIT(0x0c, 10),/*-NC*/ + RST_TIM1 = _REG_BIT(0x0c, 11),/*VNC*/ + RST_SPI1 = _REG_BIT(0x0c, 12),/*VNC*/ + RST_TIM8 = _REG_BIT(0x0c, 13),/*-N-*/ + RST_USART1 = _REG_BIT(0x0c, 14),/*VNC*/ + RST_ADC3 = _REG_BIT(0x0c, 15),/*-N-*/ + RST_TIM15 = _REG_BIT(0x0c, 16),/*V--*/ + RST_TIM16 = _REG_BIT(0x0c, 17),/*V--*/ + RST_TIM17 = _REG_BIT(0x0c, 18),/*V--*/ + RST_TIM9 = _REG_BIT(0x0c, 19),/*-N-*/ + RST_TIM10 = _REG_BIT(0x0c, 20),/*-N-*/ + RST_TIM11 = _REG_BIT(0x0c, 21),/*-N-*/ + + /* APB1 peripherals */ + RST_TIM2 = _REG_BIT(0x10, 0),/*VNC*/ + RST_TIM3 = _REG_BIT(0x10, 1),/*VNC*/ + RST_TIM4 = _REG_BIT(0x10, 2),/*VNC*/ + RST_TIM5 = _REG_BIT(0x10, 3),/*VNC*/ + RST_TIM6 = _REG_BIT(0x10, 4),/*VNC*/ + RST_TIM7 = _REG_BIT(0x10, 5),/*VNC*/ + RST_TIM12 = _REG_BIT(0x10, 6),/*VN-*/ + RST_TIM13 = _REG_BIT(0x10, 7),/*VN-*/ + RST_TIM14 = _REG_BIT(0x10, 8),/*VN-*/ + RST_WWDG = _REG_BIT(0x10, 11),/*VNC*/ + RST_SPI2 = _REG_BIT(0x10, 14),/*VNC*/ + RST_SPI3 = _REG_BIT(0x10, 15),/*VNC*/ + RST_USART2 = _REG_BIT(0x10, 17),/*VNC*/ + RST_USART3 = _REG_BIT(0x10, 18),/*VNC*/ + RST_UART4 = _REG_BIT(0x10, 19),/*VNC*/ + RST_UART5 = _REG_BIT(0x10, 20),/*VNC*/ + RST_I2C1 = _REG_BIT(0x10, 21),/*VNC*/ + RST_I2C2 = _REG_BIT(0x10, 22),/*VNC*/ + RST_USB = _REG_BIT(0x10, 23),/*-N-*/ + RST_CAN = _REG_BIT(0x10, 24),/*-N-*/ + RST_CAN1 = _REG_BIT(0x10, 24),/*--C*/ + RST_CAN2 = _REG_BIT(0x10, 25),/*--C*/ + RST_BKP = _REG_BIT(0x10, 27),/*VNC*/ + RST_PWR = _REG_BIT(0x10, 28),/*VNC*/ + RST_DAC = _REG_BIT(0x10, 29),/*VNC*/ + RST_CEC = _REG_BIT(0x10, 30),/*V--*/ +}; + +#include + +BEGIN_DECLS + +void rcc_osc_ready_int_clear(enum rcc_osc osc); +void rcc_osc_ready_int_enable(enum rcc_osc osc); +void rcc_osc_ready_int_disable(enum rcc_osc osc); +int rcc_osc_ready_int_flag(enum rcc_osc osc); +void rcc_css_int_clear(void); +int rcc_css_int_flag(void); +void rcc_wait_for_osc_ready(enum rcc_osc osc); +void rcc_osc_on(enum rcc_osc osc); +void rcc_osc_off(enum rcc_osc osc); +void rcc_css_enable(void); +void rcc_css_disable(void); +void rcc_set_mco(uint32_t mcosrc); +void rcc_osc_bypass_enable(enum rcc_osc osc); +void rcc_osc_bypass_disable(enum rcc_osc osc); +void rcc_set_sysclk_source(uint32_t clk); +void rcc_set_pll_multiplication_factor(uint32_t mul); +void rcc_set_pll2_multiplication_factor(uint32_t mul); +void rcc_set_pll3_multiplication_factor(uint32_t mul); +void rcc_set_pll_source(uint32_t pllsrc); +void rcc_set_pllxtpre(uint32_t pllxtpre); +void rcc_set_adcpre(uint32_t adcpre); +void rcc_set_ppre2(uint32_t ppre2); +void rcc_set_ppre1(uint32_t ppre1); +void rcc_set_hpre(uint32_t hpre); +void rcc_set_usbpre(uint32_t usbpre); +void rcc_set_prediv1(uint32_t prediv); +void rcc_set_prediv2(uint32_t prediv); +void rcc_set_prediv1_source(uint32_t rccsrc); +uint32_t rcc_system_clock_source(void); +void rcc_clock_setup_in_hsi_out_64mhz(void); +void rcc_clock_setup_in_hsi_out_48mhz(void); +void rcc_clock_setup_in_hsi_out_24mhz(void); +void rcc_clock_setup_in_hse_8mhz_out_24mhz(void); +void rcc_clock_setup_in_hse_8mhz_out_72mhz(void); +void rcc_clock_setup_in_hse_12mhz_out_72mhz(void); +void rcc_clock_setup_in_hse_16mhz_out_72mhz(void); +void rcc_clock_setup_in_hse_25mhz_out_72mhz(void); +void rcc_backupdomain_reset(void); + +END_DECLS + +#endif +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/f1/rtc.h b/libopencm3/include/libopencm3/stm32/f1/rtc.h new file mode 100644 index 0000000..3a60fca --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f1/rtc.h @@ -0,0 +1,170 @@ +/** @defgroup rtc_defines RTC Defines + * + * @brief Defined Constants and Types for the STM32F1xx Real Time Clock + * + * @ingroup STM32F1xx_defines + * + * @author @htmlonly © @endhtmlonly 2010 Uwe Hermann + * + * @version 1.0.0 + * + * @date 4 March 2013 + * + * LGPL License Terms @ref lgpl_license + * */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* + * The F1 RTC is a straight time stamp, a completely different peripheral to + * that found in the F2, F3, F4, L1 and F0. + */ + +#ifndef LIBOPENCM3_RTC_H +#define LIBOPENCM3_RTC_H +/**@{*/ + +#include +#include + +/* --- RTC registers ------------------------------------------------------- */ + +/* RTC control register high (RTC_CRH) */ +#define RTC_CRH MMIO32(RTC_BASE + 0x00) + +/* RTC control register low (RTC_CRL) */ +#define RTC_CRL MMIO32(RTC_BASE + 0x04) + +/* RTC prescaler load register (RTC_PRLH / RTC_PRLL) */ +#define RTC_PRLH MMIO32(RTC_BASE + 0x08) +#define RTC_PRLL MMIO32(RTC_BASE + 0x0c) + +/* RTC prescaler divider register (RTC_DIVH / RTC_DIVL) */ +#define RTC_DIVH MMIO32(RTC_BASE + 0x10) +#define RTC_DIVL MMIO32(RTC_BASE + 0x14) + +/* RTC counter register (RTC_CNTH / RTC_CNTL) */ +#define RTC_CNTH MMIO32(RTC_BASE + 0x18) +#define RTC_CNTL MMIO32(RTC_BASE + 0x1c) + +/* RTC alarm register high (RTC_ALRH / RTC_ALRL) */ +#define RTC_ALRH MMIO32(RTC_BASE + 0x20) +#define RTC_ALRL MMIO32(RTC_BASE + 0x24) + +/* --- RTC_CRH values -------------------------------------------------------*/ + +/* Note: Bits [15:3] are reserved, and forced to 0 by hardware. */ + +/* OWIE: Overflow interrupt enable */ +#define RTC_CRH_OWIE (1 << 2) + +/* ALRIE: Alarm interrupt enable */ +#define RTC_CRH_ALRIE (1 << 1) + +/* SECIE: Second interrupt enable */ +#define RTC_CRH_SECIE (1 << 0) + +/* --- RTC_CRL values -------------------------------------------------------*/ + +/* Note: Bits [15:6] are reserved, and forced to 0 by hardware. */ + +/* RTOFF: RTC operation OFF */ +#define RTC_CRL_RTOFF (1 << 5) + +/* CNF: Configuration flag */ +#define RTC_CRL_CNF (1 << 4) + +/* RSF: Registers synchronized flag */ +#define RTC_CRL_RSF (1 << 3) + +/* OWF: Overflow flag */ +#define RTC_CRL_OWF (1 << 2) + +/* ALRF: Alarm flag */ +#define RTC_CRL_ALRF (1 << 1) + +/* SECF: Second flag */ +#define RTC_CRL_SECF (1 << 0) + +/* --- RTC_PRLH values ------------------------------------------------------*/ + +/* Note: Bits [15:4] are reserved, and forced to 0 by hardware. */ + +/* TODO */ + +/* --- RTC_PRLL values ------------------------------------------------------*/ + +/* TODO */ + +/* --- RTC_DIVH values ------------------------------------------------------*/ + +/* Bits [15:4] are reserved. */ + +/* TODO */ + +/* --- RTC_DIVL values ------------------------------------------------------*/ + +/* TODO */ + +/* --- RTC_CNTH values ------------------------------------------------------*/ + +/* TODO */ + +/* --- RTC_CNTL values ------------------------------------------------------*/ + +/* TODO */ + +/* --- RTC_ALRH values ------------------------------------------------------*/ + +/* TODO */ + +/* --- RTC_ALRL values ------------------------------------------------------*/ + +/* TODO */ + +/* --- Function prototypes --------------------------------------------------*/ + +typedef enum { + RTC_SEC, RTC_ALR, RTC_OW, +} rtcflag_t; + +BEGIN_DECLS + +void rtc_awake_from_off(enum rcc_osc clock_source); +void rtc_enter_config_mode(void); +void rtc_exit_config_mode(void); +void rtc_set_alarm_time(uint32_t alarm_time); +void rtc_enable_alarm(void); +void rtc_disable_alarm(void); +void rtc_set_prescale_val(uint32_t prescale_val); +uint32_t rtc_get_counter_val(void); +uint32_t rtc_get_prescale_div_val(void); +uint32_t rtc_get_alarm_val(void); +void rtc_set_counter_val(uint32_t counter_val); +void rtc_interrupt_enable(rtcflag_t flag_val); +void rtc_interrupt_disable(rtcflag_t flag_val); +void rtc_clear_flag(rtcflag_t flag_val); +uint32_t rtc_check_flag(rtcflag_t flag_val); +void rtc_awake_from_standby(void); +void rtc_auto_awake(enum rcc_osc clock_source, uint32_t prescale_val); + +END_DECLS +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f1/spi.h b/libopencm3/include/libopencm3/stm32/f1/spi.h new file mode 100644 index 0000000..8513454 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f1/spi.h @@ -0,0 +1,37 @@ +/** @defgroup spi_defines SPI Defines + +@brief Defined Constants and Types for the STM32F1xx SPI + +@ingroup STM32F1xx_defines + +@version 1.0.0 + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_SPI_H +#define LIBOPENCM3_SPI_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f1/timer.h b/libopencm3/include/libopencm3/stm32/f1/timer.h new file mode 100644 index 0000000..6046d79 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f1/timer.h @@ -0,0 +1,56 @@ +/** @defgroup timer_defines Timer Defines + +@brief libopencm3 Defined Constants and Types for the STM32F1xx Timers + +@ingroup STM32F1xx_defines + +@version 1.0.0 + +@date 8 March 2013 + +@author @htmlonly © @endhtmlonly 2011 Fergus Noble + +LGPL License Terms @ref lgpl_license +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_TIMER_H +#define LIBOPENCM3_TIMER_H + +#include + +/** Input Capture input polarity */ +enum tim_ic_pol { + TIM_IC_RISING, + TIM_IC_FALLING, +}; + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void timer_ic_set_polarity(uint32_t timer, + enum tim_ic_id ic, + enum tim_ic_pol pol); + +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f1/usart.h b/libopencm3/include/libopencm3/stm32/f1/usart.h new file mode 100644 index 0000000..324d78e --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f1/usart.h @@ -0,0 +1,37 @@ +/** @defgroup usart_defines USART Defines + +@brief Defined Constants and Types for the STM32F1xx USART + +@ingroup STM32F1xx_defines + +@version 1.0.0 + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_USART_H +#define LIBOPENCM3_USART_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f2/crc.h b/libopencm3/include/libopencm3/stm32/f2/crc.h new file mode 100644 index 0000000..45c16ba --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f2/crc.h @@ -0,0 +1,38 @@ +/** @defgroup crc_defines CRC Defines + +@brief libopencm3 Defined Constants and Types for the STM32F2xx CRC +Generator + +@ingroup STM32F2xx_defines + +@version 1.0.0 + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CRC_H +#define LIBOPENCM3_CRC_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f2/crypto.h b/libopencm3/include/libopencm3/stm32/f2/crypto.h new file mode 100644 index 0000000..02ea8b5 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f2/crypto.h @@ -0,0 +1,36 @@ +/** @defgroup crypto_defines CRYPTO Defines + * + * @brief Defined Constants and Types for the STM32F2xx CRYP Controller + * + * @ingroup STM32F2xx_defines + * + * @version 1.0.0 + * + * @date 17 Jun 2013 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CRYPTO_H +#define LIBOPENCM3_CRYPTO_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f2/dac.h b/libopencm3/include/libopencm3/stm32/f2/dac.h new file mode 100644 index 0000000..5d148a6 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f2/dac.h @@ -0,0 +1,37 @@ +/** @defgroup dac_defines DAC Defines + +@brief Defined Constants and Types for the STM32F2xx DAC + +@ingroup STM32F2xx_defines + +@version 1.0.0 + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DAC_H +#define LIBOPENCM3_DAC_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f2/dma.h b/libopencm3/include/libopencm3/stm32/f2/dma.h new file mode 100644 index 0000000..8fe846d --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f2/dma.h @@ -0,0 +1,37 @@ +/** @defgroup dma_defines DMA Defines + +@ingroup STM32F2xx_defines + +@brief Defined Constants and Types for the STM32F2xx DMA Controller + +@version 1.0.0 + +@date 18 October 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DMA_H +#define LIBOPENCM3_DMA_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f2/doc-stm32f2.h b/libopencm3/include/libopencm3/stm32/f2/doc-stm32f2.h new file mode 100644 index 0000000..faa7f29 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f2/doc-stm32f2.h @@ -0,0 +1,33 @@ +/** @mainpage libopencm3 STM32F2 + +@version 1.0.0 + +@date 14 September 2012 + +API documentation for ST Microelectronics STM32F2 Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + + +/** @defgroup STM32F2xx STM32F2xx +Libraries for ST Microelectronics STM32F2xx series. + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup STM32F2xx_defines STM32F2xx Defines + +@brief Defined Constants and Types for the STM32F2xx series + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/libopencm3/include/libopencm3/stm32/f2/exti.h b/libopencm3/include/libopencm3/stm32/f2/exti.h new file mode 100644 index 0000000..5caadf8 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f2/exti.h @@ -0,0 +1,41 @@ +/** @defgroup exti_defines EXTI Defines + * + * @brief Defined Constants and Types for the STM32F2xx External Interrupts + * + * + * @ingroup STM32F2xx_defines + * + * @author @htmlonly © @endhtmlonly 2013 + * Piotr Esden-Tempski + * + * @version 1.0.0 + * + * @date 14 January 2014 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Piotr Esden-Tempski + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EXTI_H +#define LIBOPENCM3_EXTI_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f2/flash.h b/libopencm3/include/libopencm3/stm32/f2/flash.h new file mode 100644 index 0000000..7066802 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f2/flash.h @@ -0,0 +1,37 @@ +/** @defgroup flash_defines FLASH Defines + * + * @ingroup STM32F2xx_defines + * + * @brief Defined Constants and Types for the STM32F2xx FLASH Memory + * + * @version 1.0.0 + * + * @date 14 January 2014 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_FLASH_H +#define LIBOPENCM3_FLASH_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f2/gpio.h b/libopencm3/include/libopencm3/stm32/f2/gpio.h new file mode 100644 index 0000000..fed9353 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f2/gpio.h @@ -0,0 +1,37 @@ +/** @defgroup gpio_defines GPIO Defines + +@brief Defined Constants and Types for the STM32F2xx General Purpose I/O + +@ingroup STM32F2xx_defines + +@version 1.0.0 + +@date 1 July 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_GPIO_H +#define LIBOPENCM3_GPIO_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f2/hash.h b/libopencm3/include/libopencm3/stm32/f2/hash.h new file mode 100644 index 0000000..9f9cea9 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f2/hash.h @@ -0,0 +1,36 @@ +/** @defgroup hash_defines HASH Defines + +@ingroup STM32F2xx_defines + +@brief Defined Constants and Types for the STM32F2xx HASH Controller + +@version 1.0.0 + +@date 31 May 2013 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_HASH_H +#define LIBOPENCM3_HASH_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f2/i2c.h b/libopencm3/include/libopencm3/stm32/f2/i2c.h new file mode 100644 index 0000000..c1be84c --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f2/i2c.h @@ -0,0 +1,37 @@ +/** @defgroup i2c_defines I2C Defines + +@brief Defined Constants and Types for the STM32F2xx I2C + +@ingroup STM32F2xx_defines + +@version 1.0.0 + +@date 12 October 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_I2C_H +#define LIBOPENCM3_I2C_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f2/irq.json b/libopencm3/include/libopencm3/stm32/f2/irq.json new file mode 100644 index 0000000..ec59674 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f2/irq.json @@ -0,0 +1,88 @@ +{ + "irqs": [ + "nvic_wwdg", + "pvd", + "tamp_stamp", + "rtc_wkup", + "flash", + "rcc", + "exti0", + "exti1", + "exti2", + "exti3", + "exti4", + "dma1_stream0", + "dma1_stream1", + "dma1_stream2", + "dma1_stream3", + "dma1_stream4", + "dma1_stream5", + "dma1_stream6", + "adc", + "can1_tx", + "can1_rx0", + "can1_rx1", + "can1_sce", + "exti9_5", + "tim1_brk_tim9", + "tim1_up_tim10", + "tim1_trg_com_tim11", + "tim1_cc", + "tim2", + "tim3", + "tim4", + "i2c1_ev", + "i2c1_er", + "i2c2_ev", + "i2c2_er", + "spi1", + "spi2", + "usart1", + "usart2", + "usart3", + "exti15_10", + "rtc_alarm", + "usb_fs_wkup", + "tim8_brk_tim12", + "tim8_up_tim13", + "tim8_trg_com_tim14", + "tim8_cc", + "dma1_stream7", + "fsmc", + "sdio", + "tim5", + "spi3", + "uart4", + "uart5", + "tim6_dac", + "tim7", + "dma2_stream0", + "dma2_stream1", + "dma2_stream2", + "dma2_stream3", + "dma2_stream4", + "eth", + "eth_wkup", + "can2_tx", + "can2_rx0", + "can2_rx1", + "can2_sce", + "otg_fs", + "dma2_stream5", + "dma2_stream6", + "dma2_stream7", + "usart6", + "i2c3_ev", + "i2c3_er", + "otg_hs_ep1_out", + "otg_hs_ep1_in", + "otg_hs_wkup", + "otg_hs", + "dcmi", + "cryp", + "hash_rng" + ], + "partname_humanreadable": "STM32 F2 series", + "partname_doxygen": "STM32F2", + "includeguard": "LIBOPENCM3_STM32_F2_NVIC_H" +} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/stm32/f2/iwdg.h b/libopencm3/include/libopencm3/stm32/f2/iwdg.h new file mode 100644 index 0000000..23ccb10 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f2/iwdg.h @@ -0,0 +1,39 @@ +/** @defgroup iwdg_defines IWDG Defines + +@brief Defined Constants and Types for the STM32F2xx Independent Watchdog +Timer + +@ingroup STM32F2xx_defines + +@version 1.0.0 + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_IWDG_H +#define LIBOPENCM3_IWDG_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f2/memorymap.h b/libopencm3/include/libopencm3/stm32/f2/memorymap.h new file mode 100644 index 0000000..afd4ae3 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f2/memorymap.h @@ -0,0 +1,141 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_MEMORYMAP_H +#define LIBOPENCM3_MEMORYMAP_H + +#include + +/* --- STM32F20x specific peripheral definitions --------------------------- */ + +/* Memory map for all busses */ +#define PERIPH_BASE (0x40000000U) +#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) +#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) +#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000) +#define PERIPH_BASE_AHB2 (0x50000000U) +#define PERIPH_BASE_AHB3 (0x60000000U) + +/* Register boundary addresses */ + +/* APB1 */ +#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) +#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) +#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) +#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) +#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) +#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) +#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800) +#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00) +#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) +/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ +#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) +#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) +#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) +/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ +#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) +#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) +/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ +#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) +#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) +#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) +#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) +#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) +#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) +#define I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00) +/* PERIPH_BASE_APB1 + 0x6000 (0x4000 6000 - 0x4000 63FF): Reserved */ +#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) +#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800) +/* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */ +#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) +#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) +/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 FFFF): Reserved */ + +/* APB2 */ +#define TIM1_BASE (PERIPH_BASE_APB2 + 0x0000) +#define TIM8_BASE (PERIPH_BASE_APB2 + 0x0400) +/* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 0FFF): Reserved */ +#define USART1_BASE (PERIPH_BASE_APB2 + 0x1000) +#define USART6_BASE (PERIPH_BASE_APB2 + 0x1400) +/* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */ +#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000) +#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2000) +#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2000) +/* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */ +#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2C00) +/* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */ +#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) +/* PERIPH_BASE_APB2 + 0x3400 (0x4001 3400 - 0x4001 37FF): Reserved */ +#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800) +#define EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00) +#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4000) +#define TIM10_BASE (PERIPH_BASE_APB2 + 0x4400) +#define TIM11_BASE (PERIPH_BASE_APB2 + 0x4800) +/* PERIPH_BASE_APB2 + 0x4C00 (0x4001 4C00 - 0x4001 FFFF): Reserved */ + +/* AHB1 */ +#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000) +#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400) +#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800) +#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00) +#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000) +#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400) +#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800) +#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00) +#define GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000) +/* PERIPH_BASE_AHB1 + 0x2400 (0x4002 2400 - 0x4002 2FFF): Reserved */ +#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) +/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */ +#define RCC_BASE (PERIPH_BASE_AHB1 + 0x3800) +#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00) +#define BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000) +/* PERIPH_BASE_AHB1 + 0x5000 (0x4002 5000 - 0x4002 5FFF): Reserved */ +#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000) +#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400) +/* PERIPH_BASE_AHB1 + 0x6800 (0x4002 6800 - 0x4002 7FFF): Reserved */ +#define ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000) +/* PERIPH_BASE_AHB1 + 0x9400 (0x4002 9400 - 0x4003 FFFF): Reserved */ +#define USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000) +/* PERIPH_BASE_AHB1 + 0x60000 (0x4008 0000 - 0x4FFF FFFF): Reserved */ + +/* AHB2 */ +#define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x0000) +/* PERIPH_BASE_AHB2 + 0x40000 (0x5004 0000 - 0x5004 FFFF): Reserved */ +#define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000) +/* PERIPH_BASE_AHB2 + 0x50400 (0x5005 0400 - 0x5005 FFFF): Reserved */ +#define CRYP_BASE (PERIPH_BASE_AHB2 + 0x60000) +#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400) +#define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800) +/* PERIPH_BASE_AHB2 + 0x61000 (0x5006 1000 - 0x5FFF FFFF): Reserved */ + +/* AHB3 */ +#define FSMC_BASE (PERIPH_BASE_AHB3 + 0x40000000) + +/* PPIB */ +#define DBGMCU_BASE (PPBI_BASE + 0x00042000) + +/* Device Electronic Signature */ +#define DESIG_FLASH_SIZE_BASE (0x1FFF7A22U) +#define DESIG_UNIQUE_ID_BASE (0x1FFF7A10U) +#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) +#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) +#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8) + + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f2/pwr.h b/libopencm3/include/libopencm3/stm32/f2/pwr.h new file mode 100644 index 0000000..f946f88 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f2/pwr.h @@ -0,0 +1,59 @@ +/** @defgroup pwr_defines PWR Defines + +@brief Defined Constants and Types for the STM32F2xx PWR Control + +@ingroup STM32F2xx_defines + +@version 1.0.0 + +@date 4 March 2013 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_PWR_F2_H +#define LIBOPENCM3_PWR_F2_H + +#include + +/* + * This file extends the common STM32 version with definitions only + * applicable to the STM32F2 series of devices. + */ + +/* --- PWR_CR values ------------------------------------------------------- */ + +/* Bits [31:10]: Reserved, always read as 0. */ + +/* FPDS: Flash power down in stop mode */ +#define PWR_CR_FPDS (1 << 9) + +/* --- PWR_CSR values ------------------------------------------------------ */ + +/* Bits [31:10]: Reserved, always read as 0. */ + +/* BRE: Backup regulator enable */ +#define PWR_CSR_BRE (1 << 9) + +/* Bits [7:4]: Reserved, always read as 0. */ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f2/rcc.h b/libopencm3/include/libopencm3/stm32/f2/rcc.h new file mode 100644 index 0000000..17b05f9 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f2/rcc.h @@ -0,0 +1,756 @@ +/** @defgroup rcc_defines RCC Defines + * + * @brief Defined Constants and Types for the STM32F2xx Reset and Clock + * Control + * + * @ingroup STM32F2xx_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2009 + * Federico Ruiz-Ugalde \ + * @author @htmlonly © @endhtmlonly 2009 + * Uwe Hermann + * @author @htmlonly © @endhtmlonly 2011 + * Fergus Noble + * + * @date 18 August 2012 + * + * LGPL License Terms @ref lgpl_license + * */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2009 Federico Ruiz-Ugalde + * Copyright (C) 2011 Fergus Noble + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ +/**@{*/ + +#ifndef LIBOPENCM3_RCC_H +#define LIBOPENCM3_RCC_H + +/* --- RCC registers ------------------------------------------------------- */ + +#define RCC_CR MMIO32(RCC_BASE + 0x00) +#define RCC_PLLCFGR MMIO32(RCC_BASE + 0x04) +#define RCC_CFGR MMIO32(RCC_BASE + 0x08) +#define RCC_CIR MMIO32(RCC_BASE + 0x0c) +#define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x10) +#define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x14) +#define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x18) +/* RCC_BASE + 0x1c Reserved */ +#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x20) +#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x24) +/* RCC_BASE + 0x28 Reserved */ +/* RCC_BASE + 0x2c Reserved */ +#define RCC_AHB1ENR MMIO32(RCC_BASE + 0x30) +#define RCC_AHB2ENR MMIO32(RCC_BASE + 0x34) +#define RCC_AHB3ENR MMIO32(RCC_BASE + 0x38) +/* RCC_BASE + 0x3c Reserved */ +#define RCC_APB1ENR MMIO32(RCC_BASE + 0x40) +#define RCC_APB2ENR MMIO32(RCC_BASE + 0x44) +/* RCC_BASE + 0x48 Reserved */ +/* RCC_BASE + 0x4c Reserved */ +#define RCC_AHB1LPENR MMIO32(RCC_BASE + 0x50) +#define RCC_AHB2LPENR MMIO32(RCC_BASE + 0x54) +#define RCC_AHB3LPENR MMIO32(RCC_BASE + 0x58) +/* RCC_BASE + 0x5c Reserved */ +#define RCC_APB1LPENR MMIO32(RCC_BASE + 0x60) +#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x64) +/* RCC_BASE + 0x68 Reserved */ +/* RCC_BASE + 0x6c Reserved */ +#define RCC_BDCR MMIO32(RCC_BASE + 0x70) +#define RCC_CSR MMIO32(RCC_BASE + 0x74) +/* RCC_BASE + 0x78 Reserved */ +/* RCC_BASE + 0x7c Reserved */ +#define RCC_SSCGR MMIO32(RCC_BASE + 0x80) +#define RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84) + +/* --- RCC_CR values ------------------------------------------------------- */ + +#define RCC_CR_PLLI2SRDY (1 << 27) +#define RCC_CR_PLLI2SON (1 << 26) +#define RCC_CR_PLLRDY (1 << 25) +#define RCC_CR_PLLON (1 << 24) +#define RCC_CR_CSSON (1 << 19) +#define RCC_CR_HSEBYP (1 << 18) +#define RCC_CR_HSERDY (1 << 17) +#define RCC_CR_HSEON (1 << 16) +/* HSICAL: [15:8] */ +/* HSITRIM: [7:3] */ +#define RCC_CR_HSIRDY (1 << 1) +#define RCC_CR_HSION (1 << 0) + +/* --- RCC_PLLCFGR values -------------------------------------------------- */ + +/* PLLQ: [27:24] */ +#define RCC_PLLCFGR_PLLQ_SHIFT 24 +#define RCC_PLLCFGR_PLLSRC (1 << 22) +/* PLLP: [17:16] */ +#define RCC_PLLCFGR_PLLP_SHIFT 16 +/* PLLN: [14:6] */ +#define RCC_PLLCFGR_PLLN_SHIFT 6 +/* PLLM: [5:0] */ +#define RCC_PLLCFGR_PLLM_SHIFT 0 + +/* --- RCC_CFGR values ----------------------------------------------------- */ + +/* MCO2: Microcontroller clock output 2 */ +#define RCC_CFGR_MCO2_SHIFT 30 +#define RCC_CFGR_MCO2_SYSCLK 0x0 +#define RCC_CFGR_MCO2_PLLI2S 0x1 +#define RCC_CFGR_MCO2_HSE 0x2 +#define RCC_CFGR_MCO2_PLL 0x3 + +/* MCO1/2PRE: MCO Prescalers */ +#define RCC_CFGR_MCO2PRE_SHIFT 27 +#define RCC_CFGR_MCO1PRE_SHIFT 24 +#define RCC_CFGR_MCOPRE_DIV_NONE 0x0 +#define RCC_CFGR_MCOPRE_DIV_2 0x4 +#define RCC_CFGR_MCOPRE_DIV_3 0x5 +#define RCC_CFGR_MCOPRE_DIV_4 0x6 +#define RCC_CFGR_MCOPRE_DIV_5 0x7 + +/* I2SSRC: I2S clock selection */ +#define RCC_CFGR_I2SSRC (1 << 23) + +/* MCO1: Microcontroller clock output 1 */ +#define RCC_CFGR_MCO1_SHIFT 21 +#define RCC_CFGR_MCO1_HSI 0x0 +#define RCC_CFGR_MCO1_LSE 0x1 +#define RCC_CFGR_MCO1_HSE 0x2 +#define RCC_CFGR_MCO1_PLL 0x3 + +/* RTCPRE: HSE division factor for RTC clock */ +#define RCC_CFGR_RTCPRE_SHIFT 21 + +/* PPRE1/2: APB high-speed prescalers */ +#define RCC_CFGR_PPRE2_SHIFT 13 +#define RCC_CFGR_PPRE1_SHIFT 10 +#define RCC_CFGR_PPRE_DIV_NONE 0x0 +#define RCC_CFGR_PPRE_DIV_2 0x4 +#define RCC_CFGR_PPRE_DIV_4 0x5 +#define RCC_CFGR_PPRE_DIV_8 0x6 +#define RCC_CFGR_PPRE_DIV_16 0x7 + +/* HPRE: AHB high-speed prescaler */ +#define RCC_CFGR_HPRE_SHIFT 4 +#define RCC_CFGR_HPRE_DIV_NONE 0x0 +#define RCC_CFGR_HPRE_DIV_2 (0x8 + 0) +#define RCC_CFGR_HPRE_DIV_4 (0x8 + 1) +#define RCC_CFGR_HPRE_DIV_8 (0x8 + 2) +#define RCC_CFGR_HPRE_DIV_16 (0x8 + 3) +#define RCC_CFGR_HPRE_DIV_64 (0x8 + 4) +#define RCC_CFGR_HPRE_DIV_128 (0x8 + 5) +#define RCC_CFGR_HPRE_DIV_256 (0x8 + 6) +#define RCC_CFGR_HPRE_DIV_512 (0x8 + 7) + +/* SWS: System clock switch status */ +#define RCC_CFGR_SWS_SHIFT 2 +#define RCC_CFGR_SWS_HSI 0x0 +#define RCC_CFGR_SWS_HSE 0x1 +#define RCC_CFGR_SWS_PLL 0x2 + +/* SW: System clock switch */ +#define RCC_CFGR_SW_SHIFT 0 +#define RCC_CFGR_SW_HSI 0x0 +#define RCC_CFGR_SW_HSE 0x1 +#define RCC_CFGR_SW_PLL 0x2 + +/* --- RCC_CIR values ------------------------------------------------------ */ + +/* Clock security system interrupt clear bit */ +#define RCC_CIR_CSSC (1 << 23) + +/* OSC ready interrupt clear bits */ +#define RCC_CIR_PLLI2SRDYC (1 << 21) +#define RCC_CIR_PLLRDYC (1 << 20) +#define RCC_CIR_HSERDYC (1 << 19) +#define RCC_CIR_HSIRDYC (1 << 18) +#define RCC_CIR_LSERDYC (1 << 17) +#define RCC_CIR_LSIRDYC (1 << 16) + +/* OSC ready interrupt enable bits */ +#define RCC_CIR_PLLI2SRDYIE (1 << 13) +#define RCC_CIR_PLLRDYIE (1 << 12) +#define RCC_CIR_HSERDYIE (1 << 11) +#define RCC_CIR_HSIRDYIE (1 << 10) +#define RCC_CIR_LSERDYIE (1 << 9) +#define RCC_CIR_LSIRDYIE (1 << 8) + +/* Clock security system interrupt flag bit */ +#define RCC_CIR_CSSF (1 << 7) + +/* OSC ready interrupt flag bits */ +#define RCC_CIR_PLLI2SRDYF (1 << 5) +#define RCC_CIR_PLLRDYF (1 << 4) +#define RCC_CIR_HSERDYF (1 << 3) +#define RCC_CIR_HSIRDYF (1 << 2) +#define RCC_CIR_LSERDYF (1 << 1) +#define RCC_CIR_LSIRDYF (1 << 0) + +/* --- RCC_AHB1RSTR values ------------------------------------------------- */ + +#define RCC_AHB1RSTR_OTGHSRST (1 << 29) +#define RCC_AHB1RSTR_ETHMACRST (1 << 25) +#define RCC_AHB1RSTR_DMA2RST (1 << 22) +#define RCC_AHB1RSTR_DMA1RST (1 << 21) +#define RCC_AHB1RSTR_CRCRST (1 << 12) +#define RCC_AHB1RSTR_IOPIRST (1 << 8) +#define RCC_AHB1RSTR_IOPHRST (1 << 7) +#define RCC_AHB1RSTR_IOPGRST (1 << 6) +#define RCC_AHB1RSTR_IOPFRST (1 << 5) +#define RCC_AHB1RSTR_IOPERST (1 << 4) +#define RCC_AHB1RSTR_IOPDRST (1 << 3) +#define RCC_AHB1RSTR_IOPCRST (1 << 2) +#define RCC_AHB1RSTR_IOPBRST (1 << 1) +#define RCC_AHB1RSTR_IOPARST (1 << 0) + +/* --- RCC_AHB2RSTR values ------------------------------------------------- */ + +#define RCC_AHB2RSTR_OTGFSRST (1 << 7) +#define RCC_AHB2RSTR_RNGRST (1 << 6) +#define RCC_AHB2RSTR_HASHRST (1 << 5) +#define RCC_AHB2RSTR_CRYPRST (1 << 4) +#define RCC_AHB2RSTR_DCMIRST (1 << 0) + +/* --- RCC_AHB3RSTR values ------------------------------------------------- */ + +#define RCC_AHB3RSTR_FSMCRST (1 << 0) + +/* --- RCC_APB1RSTR values ------------------------------------------------- */ + +#define RCC_APB1RSTR_DACRST (1 << 29) +#define RCC_APB1RSTR_PWRRST (1 << 28) +#define RCC_APB1RSTR_CAN2RST (1 << 26) +#define RCC_APB1RSTR_CAN1RST (1 << 25) +#define RCC_APB1RSTR_I2C3RST (1 << 23) +#define RCC_APB1RSTR_I2C2RST (1 << 22) +#define RCC_APB1RSTR_I2C1RST (1 << 21) +#define RCC_APB1RSTR_UART5RST (1 << 20) +#define RCC_APB1RSTR_UART4RST (1 << 19) +#define RCC_APB1RSTR_USART3RST (1 << 18) +#define RCC_APB1RSTR_USART2RST (1 << 17) +#define RCC_APB1RSTR_SPI3RST (1 << 15) +#define RCC_APB1RSTR_SPI2RST (1 << 14) +#define RCC_APB1RSTR_WWDGRST (1 << 11) +#define RCC_APB1RSTR_TIM14RST (1 << 8) +#define RCC_APB1RSTR_TIM13RST (1 << 7) +#define RCC_APB1RSTR_TIM12RST (1 << 6) +#define RCC_APB1RSTR_TIM7RST (1 << 5) +#define RCC_APB1RSTR_TIM6RST (1 << 4) +#define RCC_APB1RSTR_TIM5RST (1 << 3) +#define RCC_APB1RSTR_TIM4RST (1 << 2) +#define RCC_APB1RSTR_TIM3RST (1 << 1) +#define RCC_APB1RSTR_TIM2RST (1 << 0) + +/* --- RCC_APB2RSTR values ------------------------------------------------- */ + +#define RCC_APB2RSTR_TIM11RST (1 << 18) +#define RCC_APB2RSTR_TIM10RST (1 << 17) +#define RCC_APB2RSTR_TIM9RST (1 << 16) +#define RCC_APB2RSTR_SYSCFGRST (1 << 14) +#define RCC_APB2RSTR_SPI1RST (1 << 12) +#define RCC_APB2RSTR_SDIORST (1 << 11) +#define RCC_APB2RSTR_ADCRST (1 << 8) +#define RCC_APB2RSTR_USART6RST (1 << 5) +#define RCC_APB2RSTR_USART1RST (1 << 4) +#define RCC_APB2RSTR_TIM8RST (1 << 1) +#define RCC_APB2RSTR_TIM1RST (1 << 0) + +/* --- RCC_AHB1ENR values ------------------------------------------------- */ + +#define RCC_AHB1ENR_OTGHSULPIEN (1 << 30) +#define RCC_AHB1ENR_OTGHSEN (1 << 29) +#define RCC_AHB1ENR_ETHMACPTPEN (1 << 28) +#define RCC_AHB1ENR_ETHMACRXEN (1 << 27) +#define RCC_AHB1ENR_ETHMACTXEN (1 << 26) +#define RCC_AHB1ENR_ETHMACEN (1 << 25) +#define RCC_AHB1ENR_DMA2EN (1 << 22) +#define RCC_AHB1ENR_DMA1EN (1 << 21) +#define RCC_AHB1ENR_BKPSRAMEN (1 << 18) +#define RCC_AHB1ENR_CRCEN (1 << 12) +#define RCC_AHB1ENR_IOPIEN (1 << 8) +#define RCC_AHB1ENR_IOPHEN (1 << 7) +#define RCC_AHB1ENR_IOPGEN (1 << 6) +#define RCC_AHB1ENR_IOPFEN (1 << 5) +#define RCC_AHB1ENR_IOPEEN (1 << 4) +#define RCC_AHB1ENR_IOPDEN (1 << 3) +#define RCC_AHB1ENR_IOPCEN (1 << 2) +#define RCC_AHB1ENR_IOPBEN (1 << 1) +#define RCC_AHB1ENR_IOPAEN (1 << 0) + +/* --- RCC_AHB2ENR values ------------------------------------------------- */ + +#define RCC_AHB2ENR_OTGFSEN (1 << 7) +#define RCC_AHB2ENR_RNGEN (1 << 6) +#define RCC_AHB2ENR_HASHEN (1 << 5) +#define RCC_AHB2ENR_CRYPEN (1 << 4) +#define RCC_AHB2ENR_DCMIEN (1 << 0) + +/* --- RCC_AHB3ENR values ------------------------------------------------- */ + +#define RCC_AHB3ENR_FSMCEN (1 << 0) + +/* --- RCC_APB1ENR values ------------------------------------------------- */ + +#define RCC_APB1ENR_DACEN (1 << 29) +#define RCC_APB1ENR_PWREN (1 << 28) +#define RCC_APB1ENR_CAN2EN (1 << 26) +#define RCC_APB1ENR_CAN1EN (1 << 25) +#define RCC_APB1ENR_I2C3EN (1 << 23) +#define RCC_APB1ENR_I2C2EN (1 << 22) +#define RCC_APB1ENR_I2C1EN (1 << 21) +#define RCC_APB1ENR_UART5EN (1 << 20) +#define RCC_APB1ENR_UART4EN (1 << 19) +#define RCC_APB1ENR_USART3EN (1 << 18) +#define RCC_APB1ENR_USART2EN (1 << 17) +#define RCC_APB1ENR_SPI3EN (1 << 15) +#define RCC_APB1ENR_SPI2EN (1 << 14) +#define RCC_APB1ENR_WWDGEN (1 << 11) +#define RCC_APB1ENR_TIM14EN (1 << 8) +#define RCC_APB1ENR_TIM13EN (1 << 7) +#define RCC_APB1ENR_TIM12EN (1 << 6) +#define RCC_APB1ENR_TIM7EN (1 << 5) +#define RCC_APB1ENR_TIM6EN (1 << 4) +#define RCC_APB1ENR_TIM5EN (1 << 3) +#define RCC_APB1ENR_TIM4EN (1 << 2) +#define RCC_APB1ENR_TIM3EN (1 << 1) +#define RCC_APB1ENR_TIM2EN (1 << 0) + +/* --- RCC_APB2ENR values ------------------------------------------------- */ + +#define RCC_APB2ENR_TIM11EN (1 << 18) +#define RCC_APB2ENR_TIM10EN (1 << 17) +#define RCC_APB2ENR_TIM9EN (1 << 16) +#define RCC_APB2ENR_SYSCFGEN (1 << 14) +#define RCC_APB2ENR_SPI1EN (1 << 12) +#define RCC_APB2ENR_SDIOEN (1 << 11) +#define RCC_APB2ENR_ADC3EN (1 << 10) +#define RCC_APB2ENR_ADC2EN (1 << 9) +#define RCC_APB2ENR_ADC1EN (1 << 8) +#define RCC_APB2ENR_USART6EN (1 << 5) +#define RCC_APB2ENR_USART1EN (1 << 4) +#define RCC_APB2ENR_TIM8EN (1 << 1) +#define RCC_APB2ENR_TIM1EN (1 << 0) + +/* --- RCC_AHB1LPENR values ------------------------------------------------- */ + +#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30) +#define RCC_AHB1LPENR_OTGHSLPEN (1 << 29) +#define RCC_AHB1LPENR_ETHMACPTPLPEN (1 << 28) +#define RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27) +#define RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26) +#define RCC_AHB1LPENR_ETHMACLPEN (1 << 25) +#define RCC_AHB1LPENR_DMA2LPEN (1 << 22) +#define RCC_AHB1LPENR_DMA1LPEN (1 << 21) +#define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18) +#define RCC_AHB1LPENR_SRAM2LPEN (1 << 17) +#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) +#define RCC_AHB1LPENR_FLITFLPEN (1 << 15) +#define RCC_AHB1LPENR_CRCLPEN (1 << 12) +#define RCC_AHB1LPENR_IOPILPEN (1 << 8) +#define RCC_AHB1LPENR_IOPHLPEN (1 << 7) +#define RCC_AHB1LPENR_IOPGLPEN (1 << 6) +#define RCC_AHB1LPENR_IOPFLPEN (1 << 5) +#define RCC_AHB1LPENR_IOPELPEN (1 << 4) +#define RCC_AHB1LPENR_IOPDLPEN (1 << 3) +#define RCC_AHB1LPENR_IOPCLPEN (1 << 2) +#define RCC_AHB1LPENR_IOPBLPEN (1 << 1) +#define RCC_AHB1LPENR_IOPALPEN (1 << 0) + +/* --- RCC_AHB2LPENR values ------------------------------------------------- */ + +#define RCC_AHB2LPENR_OTGFSLPEN (1 << 7) +#define RCC_AHB2LPENR_RNGLPEN (1 << 6) +#define RCC_AHB2LPENR_HASHLPEN (1 << 5) +#define RCC_AHB2LPENR_CRYPLPEN (1 << 4) +#define RCC_AHB2LPENR_DCMILPEN (1 << 0) + +/* --- RCC_AHB3LPENR values ------------------------------------------------- */ + +#define RCC_AHB3LPENR_FSMCLPEN (1 << 0) + +/* --- RCC_APB1LPENR values ------------------------------------------------- */ + +#define RCC_APB1LPENR_DACLPEN (1 << 29) +#define RCC_APB1LPENR_PWRLPEN (1 << 28) +#define RCC_APB1LPENR_CAN2LPEN (1 << 26) +#define RCC_APB1LPENR_CAN1LPEN (1 << 25) +#define RCC_APB1LPENR_I2C3LPEN (1 << 23) +#define RCC_APB1LPENR_I2C2LPEN (1 << 22) +#define RCC_APB1LPENR_I2C1LPEN (1 << 21) +#define RCC_APB1LPENR_UART5LPEN (1 << 20) +#define RCC_APB1LPENR_UART4LPEN (1 << 19) +#define RCC_APB1LPENR_USART3LPEN (1 << 18) +#define RCC_APB1LPENR_USART2LPEN (1 << 17) +#define RCC_APB1LPENR_SPI3LPEN (1 << 15) +#define RCC_APB1LPENR_SPI2LPEN (1 << 14) +#define RCC_APB1LPENR_WWDGLPEN (1 << 11) +#define RCC_APB1LPENR_TIM14LPEN (1 << 8) +#define RCC_APB1LPENR_TIM13LPEN (1 << 7) +#define RCC_APB1LPENR_TIM12LPEN (1 << 6) +#define RCC_APB1LPENR_TIM7LPEN (1 << 5) +#define RCC_APB1LPENR_TIM6LPEN (1 << 4) +#define RCC_APB1LPENR_TIM5LPEN (1 << 3) +#define RCC_APB1LPENR_TIM4LPEN (1 << 2) +#define RCC_APB1LPENR_TIM3LPEN (1 << 1) +#define RCC_APB1LPENR_TIM2LPEN (1 << 0) + +/* --- RCC_APB2LPENR values ------------------------------------------------- */ + +#define RCC_APB2LPENR_TIM11LPEN (1 << 18) +#define RCC_APB2LPENR_TIM10LPEN (1 << 17) +#define RCC_APB2LPENR_TIM9LPEN (1 << 16) +#define RCC_APB2LPENR_SYSCFGLPEN (1 << 14) +#define RCC_APB2LPENR_SPI1LPEN (1 << 12) +#define RCC_APB2LPENR_SDIOLPEN (1 << 11) +#define RCC_APB2LPENR_ADC3LPEN (1 << 10) +#define RCC_APB2LPENR_ADC2LPEN (1 << 9) +#define RCC_APB2LPENR_ADC1LPEN (1 << 8) +#define RCC_APB2LPENR_USART6LPEN (1 << 5) +#define RCC_APB2LPENR_USART1LPEN (1 << 4) +#define RCC_APB2LPENR_TIM8LPEN (1 << 1) +#define RCC_APB2LPENR_TIM1LPEN (1 << 0) + +/* --- RCC_BDCR values ----------------------------------------------------- */ + +#define RCC_BDCR_BDRST (1 << 16) +#define RCC_BDCR_RTCEN (1 << 15) +/* RCC_BDCR[9:8]: RTCSEL */ +#define RCC_BDCR_LSEBYP (1 << 2) +#define RCC_BDCR_LSERDY (1 << 1) +#define RCC_BDCR_LSEON (1 << 0) + +/* --- RCC_CSR values ------------------------------------------------------ */ + +#define RCC_CSR_LPWRRSTF (1 << 31) +#define RCC_CSR_WWDGRSTF (1 << 30) +#define RCC_CSR_IWDGRSTF (1 << 29) +#define RCC_CSR_SFTRSTF (1 << 28) +#define RCC_CSR_PORRSTF (1 << 27) +#define RCC_CSR_PINRSTF (1 << 26) +#define RCC_CSR_BORRSTF (1 << 25) +#define RCC_CSR_RMVF (1 << 24) +#define RCC_CSR_LSIRDY (1 << 1) +#define RCC_CSR_LSION (1 << 0) + +/* --- RCC_SSCGR values ---------------------------------------------------- */ + +/* PLL spread spectrum clock generation documented in Datasheet. */ + +#define RCC_SSCGR_SSCGEN (1 << 31) +#define RCC_SSCGR_SPREADSEL (1 << 30) +/* RCC_SSCGR[27:16]: INCSTEP */ +#define RCC_SSCGR_INCSTEP_SHIFT 16 +/* RCC_SSCGR[15:0]: MODPER */ +#define RCC_SSCGR_MODPER_SHIFT 15 + +/* --- RCC_PLLI2SCFGR values ----------------------------------------------- */ + +/* RCC_PLLI2SCFGR[30:28]: PLLI2SR */ +#define RCC_PLLI2SCFGR_PLLI2SR_SHIFT 28 +/* RCC_PLLI2SCFGR[14:6]: PLLI2SN */ +#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6 + +/* --- Variable definitions ------------------------------------------------ */ +extern uint32_t rcc_ppre1_frequency; +extern uint32_t rcc_ppre2_frequency; + +/* --- Function prototypes ------------------------------------------------- */ + +typedef enum { + CLOCK_3V3_120MHZ, + CLOCK_3V3_END +} clock_3v3_t; + +typedef struct { + uint8_t pllm; + uint16_t plln; + uint8_t pllp; + uint8_t pllq; + uint32_t flash_config; + uint8_t hpre; + uint8_t ppre1; + uint8_t ppre2; + uint32_t apb1_frequency; + uint32_t apb2_frequency; +} clock_scale_t; + +extern const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END]; + +typedef enum { + PLL, HSE, HSI, LSE, LSI +} osc_t; + +#define _REG_BIT(base, bit) (((base) << 5) + (bit)) + +enum rcc_periph_clken { + /* AHB1 peripherals */ + RCC_GPIOA = _REG_BIT(0x30, 0), + RCC_GPIOB = _REG_BIT(0x30, 1), + RCC_GPIOC = _REG_BIT(0x30, 2), + RCC_GPIOD = _REG_BIT(0x30, 3), + RCC_GPIOE = _REG_BIT(0x30, 4), + RCC_GPIOF = _REG_BIT(0x30, 5), + RCC_GPIOG = _REG_BIT(0x30, 6), + RCC_GPIOH = _REG_BIT(0x30, 7), + RCC_GPIOI = _REG_BIT(0x30, 8), + RCC_CRC = _REG_BIT(0x30, 12), + RCC_BKPSRAM = _REG_BIT(0x30, 18), + RCC_DMA1 = _REG_BIT(0x30, 21), + RCC_DMA2 = _REG_BIT(0x30, 22), + RCC_ETHMAC = _REG_BIT(0x30, 25), + RCC_ETHMACTX = _REG_BIT(0x30, 26), + RCC_ETHMACRX = _REG_BIT(0x30, 27), + RCC_ETHMACPTP = _REG_BIT(0x30, 28), + RCC_OTGHS = _REG_BIT(0x30, 29), + RCC_OTGHSULPI = _REG_BIT(0x30, 30), + + /* AHB2 peripherals */ + RCC_DCMI = _REG_BIT(0x34, 0), + RCC_CRYP = _REG_BIT(0x34, 4), + RCC_HASH = _REG_BIT(0x34, 5), + RCC_RNG = _REG_BIT(0x34, 6), + RCC_OTGFS = _REG_BIT(0x34, 7), + + /* AHB3 peripherals */ + RCC_FSMC = _REG_BIT(0x38, 0), + + /* APB1 peripherals */ + RCC_TIM2 = _REG_BIT(0x40, 0), + RCC_TIM3 = _REG_BIT(0x40, 1), + RCC_TIM4 = _REG_BIT(0x40, 2), + RCC_TIM5 = _REG_BIT(0x40, 3), + RCC_TIM6 = _REG_BIT(0x40, 4), + RCC_TIM7 = _REG_BIT(0x40, 5), + RCC_TIM12 = _REG_BIT(0x40, 6), + RCC_TIM13 = _REG_BIT(0x40, 7), + RCC_TIM14 = _REG_BIT(0x40, 8), + RCC_WWDG = _REG_BIT(0x40, 11), + RCC_SPI2 = _REG_BIT(0x40, 14), + RCC_SPI3 = _REG_BIT(0x40, 15), + RCC_USART2 = _REG_BIT(0x40, 17), + RCC_USART3 = _REG_BIT(0x40, 18), + RCC_UART4 = _REG_BIT(0x40, 19), + RCC_UART5 = _REG_BIT(0x40, 20), + RCC_I2C1 = _REG_BIT(0x40, 21), + RCC_I2C2 = _REG_BIT(0x40, 22), + RCC_I2C3 = _REG_BIT(0x40, 23), + RCC_CAN1 = _REG_BIT(0x40, 25), + RCC_CAN2 = _REG_BIT(0x40, 26), + RCC_PWR = _REG_BIT(0x40, 28), + RCC_DAC = _REG_BIT(0x40, 29), + + /* APB2 peripherals */ + RCC_TIM1 = _REG_BIT(0x44, 0), + RCC_TIM8 = _REG_BIT(0x44, 1), + RCC_USART1 = _REG_BIT(0x44, 4), + RCC_USART6 = _REG_BIT(0x44, 5), + RCC_ADC1 = _REG_BIT(0x44, 8), + RCC_ADC2 = _REG_BIT(0x44, 9), + RCC_ADC3 = _REG_BIT(0x44, 10), + RCC_SDIO = _REG_BIT(0x44, 11), + RCC_SPI1 = _REG_BIT(0x44, 12), + RCC_SYSCFG = _REG_BIT(0x44, 14), + RCC_TIM9 = _REG_BIT(0x44, 16), + RCC_TIM10 = _REG_BIT(0x44, 17), + RCC_TIM11 = _REG_BIT(0x44, 18), + + /* Extended peripherals */ + RCC_RTC = _REG_BIT(0x70, 15),/* BDCR[15] */ + + /* AHB1 peripherals */ + SCC_GPIOA = _REG_BIT(0x50, 0), + SCC_GPIOB = _REG_BIT(0x50, 1), + SCC_GPIOC = _REG_BIT(0x50, 2), + SCC_GPIOD = _REG_BIT(0x50, 3), + SCC_GPIOE = _REG_BIT(0x50, 4), + SCC_GPIOF = _REG_BIT(0x50, 5), + SCC_GPIOG = _REG_BIT(0x50, 6), + SCC_GPIOH = _REG_BIT(0x50, 7), + SCC_GPIOI = _REG_BIT(0x50, 8), + SCC_CRC = _REG_BIT(0x50, 12), + SCC_FLTIF = _REG_BIT(0x50, 15), + SCC_SRAM1 = _REG_BIT(0x50, 16), + SCC_SRAM2 = _REG_BIT(0x50, 17), + SCC_BKPSRAM = _REG_BIT(0x50, 18), + SCC_DMA1 = _REG_BIT(0x50, 21), + SCC_DMA2 = _REG_BIT(0x50, 22), + SCC_ETHMAC = _REG_BIT(0x50, 25), + SCC_ETHMACTX = _REG_BIT(0x50, 26), + SCC_ETHMACRX = _REG_BIT(0x50, 27), + SCC_ETHMACPTP = _REG_BIT(0x50, 28), + SCC_OTGHS = _REG_BIT(0x50, 29), + SCC_OTGHSULPI = _REG_BIT(0x50, 30), + + /* AHB2 peripherals */ + SCC_DCMI = _REG_BIT(0x54, 0), + SCC_CRYP = _REG_BIT(0x54, 4), + SCC_HASH = _REG_BIT(0x54, 5), + SCC_RNG = _REG_BIT(0x54, 6), + SCC_OTGFS = _REG_BIT(0x54, 7), + + /* AHB3 peripherals */ + SCC_FSMC = _REG_BIT(0x58, 0), + + /* APB1 peripherals */ + SCC_TIM2 = _REG_BIT(0x60, 0), + SCC_TIM3 = _REG_BIT(0x60, 1), + SCC_TIM4 = _REG_BIT(0x60, 2), + SCC_TIM5 = _REG_BIT(0x60, 3), + SCC_TIM6 = _REG_BIT(0x60, 4), + SCC_TIM7 = _REG_BIT(0x60, 5), + SCC_TIM12 = _REG_BIT(0x60, 6), + SCC_TIM13 = _REG_BIT(0x60, 7), + SCC_TIM14 = _REG_BIT(0x60, 8), + SCC_WWDG = _REG_BIT(0x60, 11), + SCC_SPI2 = _REG_BIT(0x60, 14), + SCC_SPI3 = _REG_BIT(0x60, 15), + SCC_USART2 = _REG_BIT(0x60, 17), + SCC_USART3 = _REG_BIT(0x60, 18), + SCC_UART4 = _REG_BIT(0x60, 19), + SCC_UART5 = _REG_BIT(0x60, 20), + SCC_I2C1 = _REG_BIT(0x60, 21), + SCC_I2C2 = _REG_BIT(0x60, 22), + SCC_I2C3 = _REG_BIT(0x60, 23), + SCC_CAN1 = _REG_BIT(0x60, 25), + SCC_CAN2 = _REG_BIT(0x60, 26), + SCC_PWR = _REG_BIT(0x60, 28), + SCC_DAC = _REG_BIT(0x60, 29), + + /* APB2 peripherals */ + SCC_TIM1 = _REG_BIT(0x64, 0), + SCC_TIM8 = _REG_BIT(0x64, 1), + SCC_USART1 = _REG_BIT(0x64, 4), + SCC_USART6 = _REG_BIT(0x64, 5), + SCC_ADC1 = _REG_BIT(0x64, 8), + SCC_ADC2 = _REG_BIT(0x64, 9), + SCC_ADC3 = _REG_BIT(0x64, 10), + SCC_SDIO = _REG_BIT(0x64, 11), + SCC_SPI1 = _REG_BIT(0x64, 12), + SCC_SYSCFG = _REG_BIT(0x64, 14), + SCC_TIM9 = _REG_BIT(0x64, 16), + SCC_TIM10 = _REG_BIT(0x64, 17), + SCC_TIM11 = _REG_BIT(0x64, 18), +}; + +enum rcc_periph_rst { + /* AHB1 peripherals */ + RST_GPIOA = _REG_BIT(0x10, 0), + RST_GPIOB = _REG_BIT(0x10, 1), + RST_GPIOC = _REG_BIT(0x10, 2), + RST_GPIOD = _REG_BIT(0x10, 3), + RST_GPIOE = _REG_BIT(0x10, 4), + RST_GPIOF = _REG_BIT(0x10, 5), + RST_GPIOG = _REG_BIT(0x10, 6), + RST_GPIOH = _REG_BIT(0x10, 7), + RST_GPIOI = _REG_BIT(0x10, 8), + RST_CRC = _REG_BIT(0x10, 12), + RST_DMA1 = _REG_BIT(0x10, 21), + RST_DMA2 = _REG_BIT(0x10, 22), + RST_ETHMAC = _REG_BIT(0x10, 25), + RST_OTGHS = _REG_BIT(0x10, 29), + + /* AHB2 peripherals */ + RST_DCMI = _REG_BIT(0x14, 0), + RST_CRYP = _REG_BIT(0x14, 4), + RST_HASH = _REG_BIT(0x14, 5), + RST_RNG = _REG_BIT(0x14, 6), + RST_OTGFS = _REG_BIT(0x14, 7), + + /* AHB3 peripherals */ + RST_FSMC = _REG_BIT(0x18, 0), + + /* APB1 peripherals */ + RST_TIM2 = _REG_BIT(0x20, 0), + RST_TIM3 = _REG_BIT(0x20, 1), + RST_TIM4 = _REG_BIT(0x20, 2), + RST_TIM5 = _REG_BIT(0x20, 3), + RST_TIM6 = _REG_BIT(0x20, 4), + RST_TIM7 = _REG_BIT(0x20, 5), + RST_TIM12 = _REG_BIT(0x20, 6), + RST_TIM13 = _REG_BIT(0x20, 7), + RST_TIM14 = _REG_BIT(0x20, 8), + RST_WWDG = _REG_BIT(0x20, 11), + RST_SPI2 = _REG_BIT(0x20, 14), + RST_SPI3 = _REG_BIT(0x20, 15), + RST_USART2 = _REG_BIT(0x20, 17), + RST_USART3 = _REG_BIT(0x20, 18), + RST_UART4 = _REG_BIT(0x20, 19), + RST_UART5 = _REG_BIT(0x20, 20), + RST_I2C1 = _REG_BIT(0x20, 21), + RST_I2C2 = _REG_BIT(0x20, 22), + RST_I2C3 = _REG_BIT(0x20, 23), + RST_CAN1 = _REG_BIT(0x20, 25), + RST_CAN2 = _REG_BIT(0x20, 26), + RST_PWR = _REG_BIT(0x20, 28), + RST_DAC = _REG_BIT(0x20, 29), + + /* APB2 peripherals */ + RST_TIM1 = _REG_BIT(0x24, 0), + RST_TIM8 = _REG_BIT(0x24, 1), + RST_USART1 = _REG_BIT(0x24, 4), + RST_USART6 = _REG_BIT(0x24, 5), + RST_ADC = _REG_BIT(0x24, 8), + RST_SDIO = _REG_BIT(0x24, 11), + RST_SPI1 = _REG_BIT(0x24, 12), + RST_SYSCFG = _REG_BIT(0x24, 14), + RST_TIM9 = _REG_BIT(0x24, 16), + RST_TIM10 = _REG_BIT(0x24, 17), + RST_TIM11 = _REG_BIT(0x24, 18), +}; + +#undef _REG_BIT + +#include + +BEGIN_DECLS + +void rcc_osc_ready_int_clear(osc_t osc); +void rcc_osc_ready_int_enable(osc_t osc); +void rcc_osc_ready_int_disable(osc_t osc); +int rcc_osc_ready_int_flag(osc_t osc); +void rcc_css_int_clear(void); +int rcc_css_int_flag(void); +void rcc_wait_for_osc_ready(osc_t osc); +void rcc_wait_for_sysclk_status(osc_t osc); +void rcc_osc_on(osc_t osc); +void rcc_osc_off(osc_t osc); +void rcc_css_enable(void); +void rcc_css_disable(void); +void rcc_osc_bypass_enable(osc_t osc); +void rcc_osc_bypass_disable(osc_t osc); +void rcc_set_sysclk_source(uint32_t clk); +void rcc_set_pll_source(uint32_t pllsrc); +void rcc_set_ppre2(uint32_t ppre2); +void rcc_set_ppre1(uint32_t ppre1); +void rcc_set_hpre(uint32_t hpre); +void rcc_set_rtcpre(uint32_t rtcpre); +void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, + uint32_t pllq); +void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, + uint32_t pllq); +uint32_t rcc_system_clock_source(void); +void rcc_clock_setup_hse_3v3(const clock_scale_t *clock); +void rcc_backupdomain_reset(void); + +END_DECLS + +#endif +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/f2/rng.h b/libopencm3/include/libopencm3/stm32/f2/rng.h new file mode 100644 index 0000000..6c3def6 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f2/rng.h @@ -0,0 +1,23 @@ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_RNG_H +#define LIBOPENCM3_RNG_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f2/rtc.h b/libopencm3/include/libopencm3/stm32/f2/rtc.h new file mode 100644 index 0000000..bae06ac --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f2/rtc.h @@ -0,0 +1,36 @@ +/** @defgroup rtc_defines RTC Defines + +@brief Defined Constants and Types for the STM32F2xx RTC + +@ingroup STM32F2xx_defines + +@version 1.0.0 + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_RTC_H +#define LIBOPENCM3_RTC_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f2/spi.h b/libopencm3/include/libopencm3/stm32/f2/spi.h new file mode 100644 index 0000000..c503eab --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f2/spi.h @@ -0,0 +1,37 @@ +/** @defgroup spi_defines SPI Defines + +@brief Defined Constants and Types for the STM32F2xx SPI + +@ingroup STM32F2xx_defines + +@version 1.0.0 + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_SPI_H +#define LIBOPENCM3_SPI_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f2/syscfg.h b/libopencm3/include/libopencm3/stm32/f2/syscfg.h new file mode 100644 index 0000000..579e6d6 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f2/syscfg.h @@ -0,0 +1,44 @@ +/** @defgroup syscfg_defines SYSCFG Defines + * + * @ingroup STM32F2xx_defines + * + * @brief Defined Constants and Types for the STM32F2xx Sysconfig + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2013 + * Frantisek Burian + * + * @date 13 January 2014 + * + * LGPL License Terms @ref lgpl_license + * */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ +/**@{*/ + +#ifndef LIBOPENCM3_SYSCFG_H +#define LIBOPENCM3_SYSCFG_H + +#include + +#endif +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/f2/timer.h b/libopencm3/include/libopencm3/stm32/f2/timer.h new file mode 100644 index 0000000..7dc6d32 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f2/timer.h @@ -0,0 +1,39 @@ +/** @defgroup timer_defines Timer Defines + +@brief libopencm3 Defined Constants and Types for the STM32F2xx Timers + +@ingroup STM32F2xx_defines + +@version 1.0.0 + +@date 8 March 2013 + +@author @htmlonly © @endhtmlonly 2011 Fergus Noble + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_TIMER_H +#define LIBOPENCM3_TIMER_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f2/usart.h b/libopencm3/include/libopencm3/stm32/f2/usart.h new file mode 100644 index 0000000..8d4485b --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f2/usart.h @@ -0,0 +1,37 @@ +/** @defgroup usart_defines USART Defines + +@brief Defined Constants and Types for the STM32F2xx USART + +@ingroup STM32F2xx_defines + +@version 1.0.0 + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_USART_H +#define LIBOPENCM3_USART_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f3/adc.h b/libopencm3/include/libopencm3/stm32/f3/adc.h new file mode 100644 index 0000000..89d5939 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/adc.h @@ -0,0 +1,939 @@ +/** @defgroup adc_defines ADC Defines + * + * @brief Defined Constants and Types for the STM32F37x Analog to Digital + * converter + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 ARCOS-Lab UCR + * Copyright (C) 2013 Fernando Cortes + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_ADC_H +#define LIBOPENCM3_ADC_H + +#define ADC1 ADC1_BASE +#define ADC2 ADC2_BASE +#define ADC3 ADC3_BASE +#define ADC4 ADC4_BASE + +/* Master and slave ADCs common registers (ADC12 or ADC34) */ + + +/*----------- ADC registers -------------------------------------- */ + +/* ADC interrupt and status register (ADCx_ISR, x=1..4) */ +#define ADC_ISR(adc_base) MMIO32(adc_base + 0x00) +#define ADC1_ISR ADC_ISR(ADC1_BASE) +#define ADC2_ISR ADC_ISR(ADC2_BASE) +#define ADC3_ISR ADC_ISR(ADC3_BASE) +#define ADC4_ISR ADC_ISR(ADC4_BASE) + + +/* Interrupt Enable Register (ADCx_IER, x=1..4) IER */ +#define ADC_IER(adc_base) MMIO32(adc_base + 0x04) +#define ADC1_IER ADC_IER(ADC1_BASE) +#define ADC2_IER ADC_IER(ADC2_BASE) +#define ADC3_IER ADC_IER(ADC3_BASE) +#define ADC4_IER ADC_IER(ADC4_BASE) + + +/* Control Register (ADCx_CR, x=1..4) CR */ +#define ADC_CR(adc_base) MMIO32(adc_base + 0x08) +#define ADC1_CR ADC_CR(ADC1_BASE) +#define ADC2_CR ADC_CR(ADC2_BASE) +#define ADC3_CR ADC_CR(ADC3_BASE) +#define ADC4_CR ADC_CR(ADC4_BASE) + + +/* Configuration Register (ADCx_CFGR, x=1..4) CFGR */ +#define ADC_CFGR(adc_base) MMIO32(adc_base + 0x0C) +#define ADC1_CFGR ADC_CFGR(ADC1_BASE) +#define ADC2_CFGR ADC_CFGR(ADC2_BASE) +#define ADC3_CFGR ADC_CFGR(ADC3_BASE) +#define ADC4_CFGR ADC_CFGR(ADC4_BASE) + + +/* Sample Time Register 1 (ADCx_SMPR1, x=1..4) SMPR1 */ +#define ADC_SMPR1(adc_base) MMIO32(adc_base + 0x14) +#define ADC1_SMPR1 ADC_SMPR1(ADC1_BASE) +#define ADC2_SMPR1 ADC_SMPR1(ADC2_BASE) +#define ADC3_SMPR1 ADC_SMPR1(ADC3_BASE) +#define ADC4_SMPR1 ADC_SMPR1(ADC4_BASE) + + +/* Sample Time Register 2 (ADCx_SMPR2, x=1..4) SMPR2 */ +#define ADC_SMPR2(adc_base) MMIO32(adc_base + 0x18) +#define ADC1_SMPR2 ADC_SMPR2(ADC1_BASE) +#define ADC2_SMPR2 ADC_SMPR2(ADC2_BASE) +#define ADC3_SMPR2 ADC_SMPR2(ADC3_BASE) +#define ADC4_SMPR2 ADC_SMPR2(ADC4_BASE) + + +/* Watchdog Threshold Register 1 (ADCx_TR1, x=1..4) TR1 */ +#define ADC_TR1(adc_base) MMIO32(adc_base + 0x20) +#define ADC1_TR1 ADC_TR1(ADC1_BASE) +#define ADC2_TR1 ADC_TR1(ADC2_BASE) +#define ADC3_TR1 ADC_TR1(ADC3_BASE) +#define ADC4_TR1 ADC_TR1(ADC4_BASE) + + +/* Watchdog Threshold Register 2 (ADCx_TR2, x=1..4) TR2 */ +#define ADC_TR2(adc_base) MMIO32(adc_base + 0x24) +#define ADC1_TR2 ADC_TR2(ADC1_BASE) +#define ADC2_TR2 ADC_TR2(ADC2_BASE) +#define ADC3_TR2 ADC_TR2(ADC3_BASE) +#define ADC4_TR2 ADC_TR2(ADC4_BASE) + + +/* Watchdog Threshold Register 3 (ADCx_TR3, x=1..4) TR3 */ +#define ADC_TR3(adc_base) MMIO32(adc_base + 0x28) +#define ADC1_TR3 ADC_TR3(ADC1_BASE) +#define ADC2_TR3 ADC_TR3(ADC2_BASE) +#define ADC3_TR3 ADC_TR3(ADC3_BASE) +#define ADC4_TR3 ADC_TR3(ADC4_BASE) + + +/* Regular Sequence Register 1 (ADCx_SQR1, x=1..4) SQR1 */ +#define ADC_SQR1(adc_base) MMIO32(adc_base + 0x30) +#define ADC1_SQR1 ADC_SQR1(ADC1_BASE) +#define ADC2_SQR1 ADC_SQR1(ADC2_BASE) +#define ADC3_SQR1 ADC_SQR1(ADC3_BASE) +#define ADC4_SQR1 ADC_SQR1(ADC4_BASE) + + +/* Regular Sequence Register 2 (ADCx_SQR2, x=1..4) SQR2 */ +#define ADC_SQR2(adc_base) MMIO32(adc_base + 0x34) +#define ADC1_SQR2 ADC_SQR2(ADC1_BASE) +#define ADC2_SQR2 ADC_SQR2(ADC2_BASE) +#define ADC3_SQR2 ADC_SQR2(ADC3_BASE) +#define ADC4_SQR2 ADC_SQR2(ADC4_BASE) + + +/* Regular Sequence Register 3 (ADCx_SQR3, x=1..4) SQR3 */ +#define ADC_SQR3(adc_base) MMIO32(adc_base + 0x38) +#define ADC1_SQR3 ADC_SQR3(ADC1_BASE) +#define ADC2_SQR3 ADC_SQR3(ADC2_BASE) +#define ADC3_SQR3 ADC_SQR3(ADC3_BASE) +#define ADC4_SQR3 ADC_SQR3(ADC4_BASE) + + +/* Regular Sequence Register 4 (ADCx_SQR3, x=1..4) SQR4 */ +#define ADC_SQR4(adc_base) MMIO32(adc_base + 0x3C) +#define ADC1_SQR4 ADC_SQR4(ADC1_BASE) +#define ADC2_SQR4 ADC_SQR4(ADC2_BASE) +#define ADC3_SQR4 ADC_SQR4(ADC3_BASE) +#define ADC4_SQR4 ADC_SQR4(ADC4_BASE) + + +/* regular Data Register (ADCx_DR, x=1..4) DR */ +#define ADC_DR(adc_base) MMIO32(adc_base + 0x40) +#define ADC1_DR ADC_DR(ADC1_BASE) +#define ADC2_DR ADC_DR(ADC2_BASE) +#define ADC3_DR ADC_DR(ADC3_BASE) +#define ADC4_DR ADC_DR(ADC4_BASE) + + +/* Injected Sequence Register (ADCx_JSQR, x=1..4) JSQR */ +#define ADC_JSQR(adc_base) MMIO32(adc_base + 0x30) +#define ADC1_JSQR ADC_JSQR(ADC1_BASE) +#define ADC2_JSQR ADC_JSQR(ADC2_BASE) +#define ADC3_JSQR ADC_JSQR(ADC3_BASE) +#define ADC4_JSQR ADC_JSQR(ADC4_BASE) + + +/* Offset Register x (ADCx_OFRy, x=1..4) (y=1..4) OFRy */ +#define ADC_OFR1(adc_base) MMIO32(adc_base + 0x60) +#define ADC1_OFR1 ADC_OFR1(ADC1_BASE) +#define ADC2_OFR1 ADC_OFR1(ADC2_BASE) +#define ADC3_OFR1 ADC_OFR1(ADC3_BASE) +#define ADC4_OFR1 ADC_OFR1(ADC4_BASE) + +#define ADC_OFR2(adc_base) MMIO32(adc_base + 0x64) +#define ADC1_OFR2 ADC_OFR2(ADC1_BASE) +#define ADC2_OFR2 ADC_OFR2(ADC2_BASE) +#define ADC3_OFR2 ADC_OFR2(ADC3_BASE) +#define ADC4_OFR2 ADC_OFR2(ADC4_BASE) + +#define ADC_OFR3(adc_base) MMIO32(adc_base + 0x68) +#define ADC1_OFR3 ADC_OFR3(ADC1_BASE) +#define ADC2_OFR3 ADC_OFR3(ADC2_BASE) +#define ADC3_OFR3 ADC_OFR3(ADC3_BASE) +#define ADC4_OFR3 ADC_OFR3(ADC4_BASE) + +#define ADC_OFR4(adc_base) MMIO32(adc_base + 0x6C) +#define ADC1_OFR4 ADC_OFR4(ADC1_BASE) +#define ADC2_OFR4 ADC_OFR4(ADC2_BASE) +#define ADC3_OFR4 ADC_OFR4(ADC3_BASE) +#define ADC4_OFR4 ADC_OFR4(ADC4_BASE) + + +/* Injected Data Register y (ADCx_JDRy, x=1..4, y= 1..4) JDRy */ +#define ADC_JDR1(adc_base) MMIO32(adc_base + 0x80) +#define ADC1_JDR1 ADC_JDR1(ADC1_BASE) +#define ADC2_JDR1 ADC_JDR1(ADC2_BASE) +#define ADC3_JDR1 ADC_JDR1(ADC3_BASE) +#define ADC4_JDR1 ADC_JDR1(ADC4_BASE) + +#define ADC_JDR2(adc_base) MMIO32(adc_base + 0x84) +#define ADC1_JDR2 ADC_JDR2(ADC1_BASE) +#define ADC2_JDR2 ADC_JDR2(ADC2_BASE) +#define ADC3_JDR2 ADC_JDR2(ADC3_BASE) +#define ADC4_JDR2 ADC_JDR2(ADC4_BASE) + +#define ADC_JDR3(adc_base) MMIO32(adc_base + 0x88) +#define ADC1_JDR3 ADC_JDR3(ADC1_BASE) +#define ADC2_JDR3 ADC_JDR3(ADC2_BASE) +#define ADC3_JDR3 ADC_JDR3(ADC3_BASE) +#define ADC4_JDR3 ADC_JDR3(ADC4_BASE) + +#define ADC_JDR4(adc_base) MMIO32(adc_base + 0x8C) +#define ADC1_JDR4 ADC_JDR4(ADC1_BASE) +#define ADC2_JDR4 ADC_JDR4(ADC2_BASE) +#define ADC3_JDR4 ADC_JDR4(ADC3_BASE) +#define ADC4_JDR4 ADC_JDR4(ADC4_BASE) + + +/* Analog Watchdog 2 Configuration Register (ADCx_AWD2CR, x=1..4) AWD2CR */ +#define ADC_AWD2CR(adc_base) MMIO32(adc_base + 0xA0) +#define ADC1_AWD2CR ADC_AWD2CR(ADC1_BASE) +#define ADC2_AWD2CR ADC_AWD2CR(ADC2_BASE) +#define ADC3_AWD2CR ADC_AWD2CR(ADC3_BASE) +#define ADC4_AWD2CR ADC_AWD2CR(ADC4_BASE) + + +/* Analog Watchdog 3 Configuration Register (ADCx_AWD3CR, x=1..4) AWD3CR */ +#define ADC_AWD3CR(adc_base) MMIO32(adc_base + 0xA4) +#define ADC1_AWD3CR ADC_AWD3CR(ADC1_BASE) +#define ADC2_AWD3CR ADC_AWD3CR(ADC2_BASE) +#define ADC3_AWD3CR ADC_AWD3CR(ADC3_BASE) +#define ADC4_AWD3CR ADC_AWD3CR(ADC4_BASE) + + +/* Differential Mode Selection Register 2 (ADCx_DIFSEL, x=1..4) DIFSEL */ +#define ADC_DIFSEL(adc_base) MMIO32(adc_base + 0xB0) +#define ADC1_DIFSEL ADC_DIFSEL(ADC1_BASE) +#define ADC2_DIFSEL ADC_DIFSEL(ADC2_BASE) +#define ADC3_DIFSEL ADC_DIFSEL(ADC3_BASE) +#define ADC4_DIFSEL ADC_DIFSEL(ADC4_BASE) + + +/* Calibration Factors (ADCx_CALFACT, x=1..4) CALFACT */ +#define ADC_CALFACT(adc_base) MMIO32(adc_base + 0xB4) +#define ADC1_CALFACT ADC_CALFACT(ADC1_BASE) +#define ADC2_CALFACT ADC_CALFACT(ADC2_BASE) +#define ADC3_CALFACT ADC_CALFACT(ADC3_BASE) +#define ADC4_CALFACT ADC_CALFACT(ADC4_BASE) + +/* ADC common (shared) registers */ +#define ADC_COMMON_REGISTERS_BASE (ADC1_BASE+0x300) +#define ADC_CSR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x0) +#define ADC_CCR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x8) +#define ADC_CDR MMIO32(ADC_COMMON_REGISTERS_BASE + 0xA) + + +/*------- ADC_ISR values ---------*/ + +/* QOVF: Injected context queue overflow */ +#define ADC_ISR_JQOVF (1 << 10) + +/* AWD3: Analog watchdog 3 flag */ +#define ADC_ISR_AWD3 (1 << 9) + +/* AWD2: Analog watchdog 2 flag */ +#define ADC_ISR_AWD2 (1 << 8) + +/* AWD1: Analog watchdog 1 flag */ +#define ADC_ISR_AWD1 (1 << 7) + +/* JEOS: Injected channel end of sequence flag */ +#define ADC_ISR_JEOS (1 << 6) + +/* JEOC: Injected channel end of conversion flag */ +#define ADC_ISR_JEOC (1 << 5) + +/* OVR: ADC overrun */ +#define ADC_ISR_OVR (1 << 4) + +/* EOS: End of regular sequence flag */ +#define ADC_ISR_EOS (1 << 3) + +/* EOC: End of conversion flag */ +#define ADC_ISR_EOC (1 << 2) + +/* EOSMP: End of sampling flag */ +#define ADC_ISR_EOSMP (1 << 1) + +/* ADRDY: ADC ready */ +#define ADC_ISR_ADRDY (1 << 0) + + +/*------- ADC_IER values ---------*/ + +/* JQOVFIE: Injected context queue overflow interrupt enable */ +#define ADC_IER_JQOVFIE (1 << 10) + +/* AWD3IE: Analog watchdog 3 interrupt enable */ +#define ADC_IER_AWD3IE (1 << 9) + +/* AWD2IE: Analog watchdog 2 interrupt enable */ +#define ADC_IER_AWD2IE (1 << 8) + +/* AWD1IE: Analog watchdog 1 interrupt enable */ +#define ADC_IER_AWD1IE (1 << 7) + +/* JEOSIE: End of injected sequence of conversions interrupt enable */ +#define ADC_IER_JEOSIE (1 << 6) + +/* JEOCIE: End of injected conversion interrupt enable */ +#define ADC_IER_JEOCIE (1 << 5) + +/* OVRIE: Overrun interrupt enable */ +#define ADC_IER_OVRIE (1 << 4) + +/* EOSIE: End of regular sequence of conversions interrupt enable */ +#define ADC_IER_EOSIE (1 << 3) + +/* EOCIE: End of regular conversion interrupt enable */ +#define ADC_IER_EOCIE (1 << 2) + +/* EOSMPIE: End of sampling flag interrupt enable for regular conversions */ +#define ADC_IER_EOSMPIE (1 << 1) + +/* ADRDYIE : ADC ready interrupt enable */ +#define ADC_IER_ADRDYIE (1 << 0) + + +/*------- ADC_CR values ---------*/ + +/* ADCAL: ADC calibration */ +#define ADC_CR_ADCAL (1 << 31) + +/* ADCALDIF: Differential mode for calibration */ +#define ADC_CR_ADCALDIF (1 << 30) + +/* ADVREGEN: ADC voltage regulador enable */ +#define ADC_CR_ADVREGEN_INTERMEDIATE (0x0 << 28) +#define ADC_CR_ADVREGEN_ENABLE (0x1 << 28) +#define ADC_CR_ADVREGEN_DISABLE (0x2 << 28) +/* --- Bit 0x3 reserved --- */ + +/* JADSTP: ADC stop of injected conversion command */ +#define ADC_CR_JADSTP (1 << 5) + +/* ADSTP: ADC stop of regular conversion command */ +#define ADC_CR_ADSTP (1 << 4) + +/* JADSTART: ADC start of injected conversion */ +#define ADC_CR_JADSTART (1 << 3) + +/* ADSTART: ADC start of regular conversion */ +#define ADC_CR_ADSTART (1 << 2) + +/* ADDIS: ADC disable command */ +#define ADC_CR_ADDIS (1 << 1) + +/* ADEN: ADC enable control */ +#define ADC_CR_ADEN (1 << 0) + + +/*------- ADC_CFGR values ---------*/ + +/* AWD1CH[4:0]: Analog watchdog 1 channel selection */ +/* Bit 0x0 reserved */ +#define ADC_CFGR_AWD1CH_ADC_IN_CH_1 (0x01 << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_2 (0x02 << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_3 (0x03 << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_4 (0x04 << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_5 (0x05 << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_6 (0x06 << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_7 (0x07 << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_8 (0x08 << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_9 (0x09 << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_10 (0x0A << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_11 (0x0B << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_12 (0x0C << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_13 (0x0D << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_14 (0x0E << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_15 (0x0F << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_16 (0x10 << 26) +#define ADC_CFGR_AWD1CH_ADC_IN_CH_17 (0x11 << 26) + +#define ADC_CFGR_AWD1CH_MASK (0x1F << 26) + +/* Ohters bits reserved, must not be used */ + +/* JAUTO: Autoamtic injected group conversion */ +#define ADC_CFGR_JAUTO (1 << 25) + +/* JAWD1EN: Analog watchdog 1 enable on injected channels */ +#define ADC_CFGR_JAWD1EN (1 << 24) + +/* AWD1EN: Analog watchdog 1 enable on regular channels */ +#define ADC_CFGR_AWD1EN (1 << 23) + +/* AWD1SGL: Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR_AWD1SGL (1 << 22) + +/* JQM: JSQR queue mode */ +#define ADC_CFGR_JQM (1 << 21) + +/* JDISCEN: Discontinuous mode on injected channels */ +#define ADC_CFGR_JDISCEN (1 << 20) + +/* DISCNUM[2:0]: Discontinuous mode channel count */ +#define ADC_CFGR_DISCNUM_1_CH (0x0 << 17) +#define ADC_CFGR_DISCNUM_2_CH (0x1 << 17) +#define ADC_CFGR_DISCNUM_3_CH (0x2 << 17) +#define ADC_CFGR_DISCNUM_4_CH (0x3 << 17) +#define ADC_CFGR_DISCNUM_5_CH (0x4 << 17) +#define ADC_CFGR_DISCNUM_6_CH (0x5 << 17) +#define ADC_CFGR_DISCNUM_7_CH (0x6 << 17) +#define ADC_CFGR_DISCNUM_8_CH (0x7 << 17) +#define ADC_CFGR_DISCNUM_SHIFT 17 + +/* DISCEN: Discontinuous mode for regular channels */ +#define ADC_CFGR_DISCEN (1 << 16) + +/* AUTDLY: Delayed conversion mode */ +#define ADC_CFGR_AUTDLY (1 << 14) + +/* CONT: Single / continuous conversion mode for regular conversions */ +#define ADC_CFGR_CONT (1 << 13) + +/* OVRMOD: Overrun Mode */ +#define ADC_CFGR_OVRMOD (1 << 12) + +/* + * EXTEN[1:0]: External trigger enable and polarity selection for regular + * channels + */ +#define ADC_CFGR_EXTEN_DISABLED (0x0 << 10) +#define ADC_CFGR_EXTEN_RISING_EDGE (0x1 << 10) +#define ADC_CFGR_EXTEN_FALLING_EDGE (0x2 << 10) +#define ADC_CFGR_EXTEN_BOTH_EDGES (0x3 << 10) + +#define ADC_CFGR_EXTEN_MASK (0x3 << 10) + +/* EXTSEL[3:0]: External trigger selection for regular group */ +#define ADC_CFGR_EXTSEL_EVENT_0 (0x0 << 6) +#define ADC_CFGR_EXTSEL_EVENT_1 (0x1 << 6) +#define ADC_CFGR_EXTSEL_EVENT_2 (0x2 << 6) +#define ADC_CFGR_EXTSEL_EVENT_3 (0x3 << 6) +#define ADC_CFGR_EXTSEL_EVENT_4 (0x4 << 6) +#define ADC_CFGR_EXTSEL_EVENT_5 (0x5 << 6) +#define ADC_CFGR_EXTSEL_EVENT_6 (0x6 << 6) +#define ADC_CFGR_EXTSEL_EVENT_7 (0x7 << 6) +#define ADC_CFGR_EXTSEL_EVENT_8 (0x8 << 6) +#define ADC_CFGR_EXTSEL_EVENT_9 (0x9 << 6) +#define ADC_CFGR_EXTSEL_EVENT_10 (0xA << 6) +#define ADC_CFGR_EXTSEL_EVENT_11 (0xB << 6) +#define ADC_CFGR_EXTSEL_EVENT_12 (0xC << 6) +#define ADC_CFGR_EXTSEL_EVENT_13 (0xD << 6) +#define ADC_CFGR_EXTSEL_EVENT_14 (0xE << 6) +#define ADC_CFGR_EXTSEL_EVENT_15 (0xF << 6) + +#define ADC_CFGR_EXTSEL_MASK (0xF << 6) + +/* ALIGN: Data alignment */ +#define ADC_CFGR_ALIGN (1 << 5) + +/* RES[1:0]: Data resolution */ +#define ADC_CFGR_RES_12_BIT (0x0 << 3) +#define ADC_CFGR_RES_10_BIT (0x1 << 3) +#define ADC_CFGR_RES_8_BIT (0x2 << 3) +#define ADC_CFGR_RES_6_BIT (0x3 << 3) + +#define ADC_CFGR_RES_MASK (0x3 << 3) + +/* DMACFG: Direct memory access configuration */ +#define ADC_CFGR_DMACFG (1 << 1) + +/* DMAEN: Direct memory access enable */ +#define ADC_CFGR_DMAEN (1 << 0) + + +/*------- ADC_SMPR1 values ---------*/ +#define ADC_SMPR1_SMP8_LSB 24 +#define ADC_SMPR1_SMP7_LSB 21 +#define ADC_SMPR1_SMP6_LSB 18 +#define ADC_SMPR1_SMP5_LSB 15 +#define ADC_SMPR1_SMP4_LSB 12 +#define ADC_SMPR1_SMP3_LSB 9 +#define ADC_SMPR1_SMP2_LSB 6 +#define ADC_SMPR1_SMP1_LSB 3 +#define ADC_SMPR1_SMP8_MSK (0x7 << ADC_SMP8_LSB) +#define ADC_SMPR1_SMP7_MSK (0x7 << ADC_SMP7_LSB) +#define ADC_SMPR1_SMP6_MSK (0x7 << ADC_SMP6_LSB) +#define ADC_SMPR1_SMP5_MSK (0x7 << ADC_SMP5_LSB) +#define ADC_SMPR1_SMP4_MSK (0x7 << ADC_SMP4_LSB) +#define ADC_SMPR1_SMP3_MSK (0x7 << ADC_SMP3_LSB) +#define ADC_SMPR1_SMP2_MSK (0x7 << ADC_SMP2_LSB) +#define ADC_SMPR1_SMP1_MSK (0x7 << ADC_SMP1_LSB) +/****************************************************************************/ +/* ADC_SMPR1 ADC Sample Time Selection for Channels */ +/** @defgroup adc_sample_r1 ADC Sample Time Selection for ADC1 +@ingroup adc_defines + +@{*/ +#define ADC_SMPR1_SMP_1DOT5CYC 0x0 +#define ADC_SMPR1_SMP_2DOT5CYC 0x1 +#define ADC_SMPR1_SMP_4DOT5CYC 0x2 +#define ADC_SMPR1_SMP_7DOT5CYC 0x3 +#define ADC_SMPR1_SMP_19DOT5CYC 0x4 +#define ADC_SMPR1_SMP_61DOT5CYC 0x5 +#define ADC_SMPR1_SMP_181DOT5CYC 0x6 +#define ADC_SMPR1_SMP_601DOT5CYC 0x7 +/**@}*/ + +/* SMPx[2:0]: Channel x sampling time selection */ + + +/*------- ADC_SMPR2 values ---------*/ + +/* SMPx[2:0]: Channel x sampling time selection */ + + + +/*------- ADC_TR1 values ---------*/ + +/* Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold */ + +/* Bit 11:0 LT1[11:0]: Analog watchdog 1 lower threshold */ + + +/*------- ADC_T2 values ---------*/ + +/* Bits 23:16 HT2[7:0]: Analog watchdog 2 higher threshold */ + +/* Bit 7:0 LT2[7:0]: Analog watchdog 2 lower threshold */ + + +/*------- ADC_T3 values ---------*/ + +/* Bits 23:16 HT3[7:0]: Analog watchdog 3 higher threshold */ + +/* Bit 7:0 LT3[7:0]: Analog watchdog 3 lower threshold */ + + +/*------- ADC_SQR1 values ---------*/ + +#define ADC_SQR1_L_LSB 0 +#define ADC_SQR1_SQ1_LSB 6 +#define ADC_SQR1_SQ2_LSB 12 +#define ADC_SQR1_SQ3_LSB 18 +#define ADC_SQR1_SQ4_LSB 24 +#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB) +#define ADC_SQR1_SQ1_MSK (0x1f << ADC_SQR1_SQ1_LSB) +#define ADC_SQR1_SQ2_MSK (0x1f << ADC_SQR1_SQ2_LSB) +#define ADC_SQR1_SQ3_MSK (0x1f << ADC_SQR1_SQ3_LSB) +#define ADC_SQR1_SQ4_MSK (0x1f << ADC_SQR1_SQ4_LSB) + +/* Bits 28:24 SQ4[4:0]: 4th conversion in regular sequence */ + +/* Bits 22:18 SQ3[4:0]: 3rd conversion in regular sequence */ + +/* Bits 16:12 SQ2[4:0]: 2nd conversion in regular sequence */ + +/* Bits 10:6 SQ1[4:0]: 1st conversion in regular sequence */ + +/* L[3:0]: Regular channel sequence length */ +#define ADC_SQR1_L_1_CONVERSION (0x0 << 0) +#define ADC_SQR1_L_2_CONVERSION (0x1 << 0) +#define ADC_SQR1_L_3_CONVERSION (0x2 << 0) +#define ADC_SQR1_L_4_CONVERSION (0x3 << 0) +#define ADC_SQR1_L_5_CONVERSION (0x4 << 0) +#define ADC_SQR1_L_6_CONVERSION (0x5 << 0) +#define ADC_SQR1_L_7_CONVERSION (0x6 << 0) +#define ADC_SQR1_L_8_CONVERSION (0x7 << 0) +#define ADC_SQR1_L_9_CONVERSION (0x8 << 0) +#define ADC_SQR1_L_10_CONVERSION (0x9 << 0) +#define ADC_SQR1_L_11_CONVERSION (0xA << 0) +#define ADC_SQR1_L_12_CONVERSION (0xB << 0) +#define ADC_SQR1_L_13_CONVERSION (0xC << 0) +#define ADC_SQR1_L_14_CONVERSION (0xD << 0) +#define ADC_SQR1_L_15_CONVERSION (0xE << 0) +#define ADC_SQR1_L_16_CONVERSION (0xF << 0) + + +/*------- ADC_SQR2 values ---------*/ + +/* Bits 28:24 SQ9[4:0]: 9th conversion in regular sequence */ + +/* Bits 22:18 SQ8[4:0]: 8th conversion in regular sequence */ + +/* Bits 16:12 SQ7[4:0]: 7th conversion in regular sequence */ + +/* Bits 10:6 SQ6[4:0]: 6th conversion in regular sequence */ + +/* Bits 4:0 SQ5[4:0]: 5th conversion in regular sequence */ + + +/*------- ADC_SQR3 values ---------*/ + +/* Bits 28:24 SQ14[4:0]: 14th conversion in regular sequence */ + +/* Bits 22:18 SQ13[4:0]: 13th conversion in regular sequence */ + +/* Bits 16:12 SQ12[4:0]: 12th conversion in regular sequence */ + +/* Bits 10:6 SQ11[4:0]: 11th conversion in regular sequence */ + +/* Bits 4:0 SQ10[4:0]: 10th conversion in regular sequence */ + + +/*------- ADC_SQR4 values ---------*/ + +/* Bits 10:6 SQ16[4:0]: 16th conversion in regular sequence */ + +/* Bits 4:0 SQ15[4:0]: 15th conversion in regular sequence */ + + +/*------- ADC_DR values ---------*/ + +/* Bits 15:0 RDATA[15:0]: Regular Data converted */ + + +/*------- ADC_JSQR values ---------*/ + +#define ADC_JSQR_JL_LSB 0 +#define ADC_JSQR_JL_SHIFT 0 +#define ADC_JSQR_JSQ4_LSB 26 +#define ADC_JSQR_JSQ3_LSB 20 +#define ADC_JSQR_JSQ2_LSB 14 +#define ADC_JSQR_JSQ1_LSB 8 + +#define ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 6 + 8)) +#define ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_SHIFT) + +/* Bits 30:26 JSQ4[4:0]: 4th conversion in the injected sequence */ + +/* Bits 24:20 JSQ3[4:0]: 3rd conversion in the injected sequence */ + +/* Bits 18:14 JSQ2[4:0]: 2nd conversion in the injected sequence */ + +/* Bits 12:8 JSQ1[4:0]: 1st conversion in the injected sequence */ + +/* + * JEXTEN[1:0]: External Trigger Enable and Polarity Selection for injected + * channels + */ +#define ADC_JSQR_JEXTEN_DISABLED (0x0 << 6) +#define ADC_JSQR_JEXTEN_RISING_EDGE (0x1 << 6) +#define ADC_JSQR_JEXTEN_FALLING_EDGE (0x2 << 6) +#define ADC_JSQR_JEXTEN_BOTH_EDGES (0x3 << 6) + +#define ADC_JSQR_JEXTEN_MASK (0x3 << 6) + +/* JEXTSEL[3:0]: External Trigger Selection for injected group */ +#define ADC_JSQR_JEXTSEL_EVENT_0 (0x0 << 2) +#define ADC_JSQR_JEXTSEL_EVENT_1 (0x1 << 2) +#define ADC_JSQR_JEXTSEL_EVENT_2 (0x2 << 2) +#define ADC_JSQR_JEXTSEL_EVENT_3 (0x3 << 2) +#define ADC_JSQR_JEXTSEL_EVENT_4 (0x4 << 2) +#define ADC_JSQR_JEXTSEL_EVENT_5 (0x5 << 2) +#define ADC_JSQR_JEXTSEL_EVENT_6 (0x6 << 2) +#define ADC_JSQR_JEXTSEL_EVENT_7 (0x7 << 2) +#define ADC_JSQR_JEXTSEL_EVENT_8 (0x8 << 2) +#define ADC_JSQR_JEXTSEL_EVENT_9 (0x9 << 2) +#define ADC_JSQR_JEXTSEL_EVENT_10 (0xA << 2) +#define ADC_JSQR_JEXTSEL_EVENT_11 (0xB << 2) +#define ADC_JSQR_JEXTSEL_EVENT_12 (0xC << 2) +#define ADC_JSQR_JEXTSEL_EVENT_13 (0xD << 2) +#define ADC_JSQR_JEXTSEL_EVENT_14 (0xE << 2) +#define ADC_JSQR_JEXTSEL_EVENT_15 (0xF << 2) + +#define ADC_JSQR_JEXTSEL_MASK (0xF << 2) + +/* JL[1:0]: Injected channel sequence length */ +#define ADC_JSQR_JL_1_CONVERSION (0x0 << 0) +#define ADC_JSQR_JL_2_CONVERSIONS (0x1 << 0) +#define ADC_JSQR_JL_3_CONVERSIONS (0x2 << 0) +#define ADC_JSQR_JL_4_CONVERSIONS (0x3 << 0) + + +/*------- ADC_OFR1 values ---------*/ + +/* OFFSET1_EN: Offset 1 Enable */ +#define ADC_OFR1_OFFSET1_EN (1 << 31) + +/* Bits 30:26 OFFSET1_CH[4:0]: Channel selection for the Data offset 1 */ + +/* + * Bits 11:0 OFFSET1[11:0]: Data offset y for the channel programmed into bits + * OFFSET1_CH[4:0] + */ + + +/*------- ADC_OFR2 values ---------*/ + +/* OFFSET2_EN: Offset 2 Enable */ +#define ADC_OFR2_OFFSET2_EN (1 << 31) + +/* Bits 30:26 OFFSET2_CH[4:0]: Channel selection for the Data offset 2 */ + +/* + * Bits 11:0 OFFSET2[11:0]: Data offset y for the channel programmed into bits + * OFFSET2_CH[4:0] + */ + + +/*------- ADC_OFR3 values ---------*/ + +/* OFFSET3_EN: Offset 3 Enable */ +#define ADC_OFR3_OFFSET3_EN (1 << 31) + +/* Bits 30:26 OFFSET3_CH[4:0]: Channel selection for the Data offset 3 */ + +/* + * Bits 11:0 OFFSET3[11:0]: Data offset y for the channel programmed into bits + * OFFSET3_CH[4:0] + */ + + +/*------- ADC_OFR4 values ---------*/ + +/* OFFSET4_EN: Offset 4 Enable */ +#define ADC_OFR4_OFFSET4_EN (1 << 31) + +/* Bits 30:26 OFFSET4_CH[4:0]: Channel selection for the Data offset 4 */ + +/* + * Bits 11:0 OFFSET4[11:0]: Data offset y for the channel programmed into bits + * OFFSET4_CH[4:0] + */ + + +/*------- ADC_JDRy, y= 1..4 values -------*/ + +/* Bits 15:0 JDATA[15:0]: Injected data */ + + +/*------- ADC_AWD2CR values ---------*/ + +/* Bits 18:1 AWD2CH[18:1]: Analog watchdog 2 channel selection */ + + +/*------- ADC_AWD3CR values ---------*/ + +/* Bits 18:1 AWD3CH[18:1]: Analog watchdog 3 channel selection */ + + +/*------- ADC_DIFSEL values ---------*/ + +/* DIFSEL[18:16]: Differential mode for channels 18 to 16. */ + +/* Bits 15:1 DIFSEL[15:1]: Differential mode for channels 15 to 1 */ + + +/*------- ADC_CALFACT values ---------*/ + +/* Bits 22:16 CALFACT_D[6:0]: Calibration Factors in differential mode */ + +/* Bits 6:0 CALFACT_S[6:0]: Calibration Factors In Single-Ended mode */ + + +/*--------------- ADC_CSR values ------------------------*/ + +/* Bit 26 JQOVF_SLV: Injected Context Queue Overflow flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV (1 << 26) + +/* Bit 25 AWD3_SLV: Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV (1 << 25) + +/* Bit 24 AWD2_SLV: Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV (1 << 24) + +/* Bit 23 AWD1_SLV: Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV (1 << 23) + +/* Bit 22 JEOS_SLV: End of injected sequence flag of the slave ADC */ +#define ADC_CSR_JEOS_SLV (1 << 22) + +/* Bit 21 JEOC_SLV: End of injected conversion flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV (1 << 21) + +/* Bit 20 OVR_SLV: Overrun flag of the slave ADC */ +#define ADC_CSR_OVR_SLV (1 << 20) + +/* Bit 19 EOS_SLV: End of regular sequence flag of the slave ADC */ +#define ADC_CSR_EOS_SLV (1 << 19) + +/* Bit 18 EOC_SLV: End of regular conversion of the slave ADC */ +#define ADC_CSR_EOC_SLV (1 << 18) + +/* Bit 17 EOSMP_SLV: End of Sampling phase flag of the slave ADC */ +#define ADC_CSR_EOSMP_SLV (1 << 17) + +/* Bit 16 ADRDY_SLV: Slave ADC ready */ +#define ADC_CSR_ADRDY_SLV (1 << 16) + +/* Bit 10 JQOVF_MST: Injected Context Queue Overflow flag of the master ADC */ +#define ADC_CSR_JQOVF_MST (1 << 10) + +/* Bit 9 AWD3_MST: Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_AWD3_MST (1 << 9) + +/* Bit 8 AWD2_MST: Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD2_MST (1 << 8) + +/* Bit 7 AWD1_MST: Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD1_MST (1 << 7) + +/* Bit 6 JEOS_MST: End of injected sequence flag of the master ADC */ +#define ADC_CSR_JEOS_MST (1 << 6) + +/* Bit 5 JEOC_MST: End of injected conversion flag of the master ADC */ +#define ADC_CSR_JEOC_MST (1 << 5) + +/* Bit 4 OVR_MST: Overrun flag of the master ADC */ +#define ADC_CSR_OVR_MST (1 << 4) + +/* Bit 3 EOS_MST: End of regular sequence flag of the master ADC */ +#define ADC_CSR_EOS_MST (1 << 3) + +/* Bit 2 EOC_MST: End of regular conversion of the master ADC */ +#define ADC_CSR_EOC_MST (1 << 2) + +/* Bit 1 EOSMP_MST: End of Sampling phase flag of the master ADC */ +#define ADC_CSR_EOSMP_MST (1 << 1) + +/* Bit 0 ADRDY_MST: Master ADC ready */ +#define ADC_CSR_ADRDY_MST (1 << 0) + + +/*-------- ADC_CCR values ------------*/ + +/* VBATEN: VBAT enable */ +#define ADC_CCR_VBATEN (1 << 24) + +/* TSEN: Temperature sensor enable */ +#define ADC_CCR_TSEN (1 << 23) + +/* VREFEN: VREFINT enable */ +#define ADC_CCR_VREFEN (1 << 22) + +/* CKMODE[1:0]: ADC clock mode */ +#define ADC_CCR_CKMODE_CKX (0x0 << 16) +#define ADC_CCR_CKMODE_DIV1 (0x1 << 16) +#define ADC_CCR_CKMODE_DIV2 (0x2 << 16) +#define ADC_CCR_CKMODE_DIV4 (0x3 << 16) + +#define ADC_CCR_CKMODE_MASK (0x3 << 16) + +/* MDMA[1:0]: Direct memory access mode for dual ADC mode */ +#define ADC_CCR_MDMA_DISABLE (0x0 << 14) +/*#define ADC_CCR_MDMA_RESERVED (0x1 << 14)*/ +#define ADC_CCR_MDMA_12_10_BIT (0x2 << 14) +#define ADC_CCR_MDMA_8_6_BIT (0x3 << 14) + +/* DMACFG: DMA configuration (for dual ADC mode) */ +#define ADC_CCR_DMACFG (1 << 13) + +/* DELAY: Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_SHIFT 8 + +/* DUAL[4:0]: Dual ADC mode selection */ +#define ADC_CCR_DUAL_SHIFT 0 + + +/*---------------- ADC_CDR values -----------------*/ + +/* Bits 31:16 RDATA_SLV[15:0]: Regular data of the slave ADC */ + +/* Bits 15:0 RDATA_MST[15:0]: Regular data of the master ADC. */ + + + +BEGIN_DECLS + +void adc_power_on(uint32_t adc); +void adc_off(uint32_t adc); +void adc_enable_analog_watchdog_regular(uint32_t adc); +void adc_disable_analog_watchdog_regular(uint32_t adc); +void adc_enable_analog_watchdog_injected(uint32_t adc); +void adc_disable_analog_watchdog_injected(uint32_t adc); +void adc_enable_discontinuous_mode_regular(uint32_t adc, uint8_t length); +void adc_disable_discontinuous_mode_regular(uint32_t adc); +void adc_enable_discontinuous_mode_injected(uint32_t adc); +void adc_disable_discontinuous_mode_injected(uint32_t adc); +void adc_enable_automatic_injected_group_conversion(uint32_t adc); +void adc_disable_automatic_injected_group_conversion(uint32_t adc); +void adc_enable_analog_watchdog_on_all_channels(uint32_t adc); +void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, + uint8_t channel); +/*void adc_enable_scan_mode(uint32_t adc);*/ +/*void adc_disable_scan_mode(uint32_t adc);*/ +void adc_enable_eoc_interrupt_injected(uint32_t adc); +void adc_disable_eoc_interrupt_injected(uint32_t adc); +void adc_enable_all_awd_interrupt(uint32_t adc); +void adc_disable_all_awd_interrupt(uint32_t adc); +void adc_enable_eoc_interrupt(uint32_t adc); +void adc_disable_eoc_interrupt(uint32_t adc); +void adc_start_conversion_regular(uint32_t adc); +void adc_start_conversion_injected(uint32_t adc); +void adc_disable_external_trigger_regular(uint32_t adc); +void adc_disable_external_trigger_injected(uint32_t adc); +void adc_set_left_aligned(uint32_t adc); +void adc_set_right_aligned(uint32_t adc); +void adc_enable_dma(uint32_t adc); +void adc_disable_dma(uint32_t adc); +void adc_set_continuous_conversion_mode(uint32_t adc); +void adc_set_single_conversion_mode(uint32_t adc); +void adc_set_sample_time(uint32_t adc, uint8_t channel, uint8_t time); +void adc_set_sample_time_on_all_channels(uint32_t adc, uint8_t time); +void adc_set_watchdog_high_threshold(uint32_t adc, uint8_t threshold); +void adc_set_watchdog_low_threshold(uint32_t adc, uint8_t threshold); +void adc_set_regular_sequence(uint32_t adc, uint8_t length, uint8_t channel[]); +void adc_set_injected_sequence(uint32_t adc, uint8_t length, uint8_t channel[]); +bool adc_eoc(uint32_t adc); +bool adc_eoc_injected(uint32_t adc); +uint32_t adc_read_regular(uint32_t adc); +uint32_t adc_read_injected(uint32_t adc, uint8_t reg); +void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset); + +void adc_set_clk_prescale(uint32_t prescaler); +void adc_set_multi_mode(uint32_t mode); +void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, + uint32_t polarity); +void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, + uint32_t polarity); +void adc_set_resolution(uint32_t adc, uint16_t resolution); +void adc_enable_overrun_interrupt(uint32_t adc); +void adc_disable_overrun_interrupt(uint32_t adc); +bool adc_get_overrun_flag(uint32_t adc); +void adc_clear_overrun_flag(uint32_t adc); +bool adc_awd(uint32_t adc); +void adc_eoc_after_each(uint32_t adc); +void adc_eoc_after_group(uint32_t adc); +/*void adc_set_dma_continue(uint32_t adc);*/ +/*void adc_set_dma_terminate(uint32_t adc);*/ +void adc_enable_temperature_sensor(void); +void adc_disable_temperature_sensor(void); + +END_DECLS + + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/crc.h b/libopencm3/include/libopencm3/stm32/f3/crc.h new file mode 100644 index 0000000..828832b --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/crc.h @@ -0,0 +1,70 @@ +/** @defgroup crc_defines CRC Defines + * + * @brief Defined Constants and Types for the STM32F3xx CRC Generator + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 18 August 2012 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CRC_H +#define LIBOPENCM3_CRC_H + +#include + +/* --- CRC registers ------------------------------------------------------- */ + +/* Initial CRC value (CRC_INIT) */ +#define CRC_INIT MMIO32(CRC_BASE + 0x10) + +/* CRC polynomial (CRC_POL) */ +#define CRC_POL MMIO32(CRC_BASE + 0x14) + +/* --- CRC_CR values ------------------------------------------------------- */ + +/* REV_OUT: Reverse output data */ +#define CRC_CR_REV_OUT (1 << 7) + +/* REV_IN[1:0]: Reverse input data */ +#define CRC_CR_REV_IN_NOT_AFFECTED (0x0 << 5) +#define CRC_CR_REV_IN_BYTE (0x1 << 5) +#define CRC_CR_REV_IN_HALF_WORD (0x2 << 5) +#define CRC_CR_REV_IN_WORD (0x3 << 5) + +/* POLYSIZE[1:0]: Polynomial size */ +#define CRC_CR_POLYSIZE_32 (0x0 << 3) +#define CRC_CR_POLYSIZE_16 (0x1 << 3) +#define CRC_CR_POLYSIZE_8 (0x2 << 3) +#define CRC_CR_POLYSIZE_7 (0x3 << 3) + +/* --- CRC_INIT values ----------------------------------------------------- */ + +/* Bits 31:0 CRC_INIT: Programmable initial CRC value */ + +/* --- CRC_POL values ------------------------------------------------------ */ + +/* Bits 31:0 POL[31:0]: Programmable polynomial */ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/dac.h b/libopencm3/include/libopencm3/stm32/f3/dac.h new file mode 100644 index 0000000..aceea8c --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/dac.h @@ -0,0 +1,37 @@ +/** @defgroup dac_defines DAC Defines + * + * @brief Defined Constants and Types for the STM32F3xx DAC + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 5 December 2012 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DAC_H +#define LIBOPENCM3_DAC_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f3/dma.h b/libopencm3/include/libopencm3/stm32/f3/dma.h new file mode 100644 index 0000000..ae738cc --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/dma.h @@ -0,0 +1,37 @@ +/** @defgroup dma_defines DMA Defines + * + * @ingroup STM32F3xx_defines + * + * @brief Defined Constants and Types for the STM32F3xx DMA Controller + * + * @version 1.0.0 + * + * @date 30 November 2012 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DMA_H +#define LIBOPENCM3_DMA_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f3/doc-stm32f3.h b/libopencm3/include/libopencm3/stm32/f3/doc-stm32f3.h new file mode 100644 index 0000000..5adc4ed --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/doc-stm32f3.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 STM32F3 + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * API documentation for ST Microelectronics STM32F3 Cortex M3 series. + * + * LGPL License Terms @ref lgpl_license + */ + +/** @defgroup STM32F3xx STM32F3xx + * Libraries for ST Microelectronics STM32F3xx series. + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ + +/** @defgroup STM32F3xx_defines STM32F3xx Defines + * + * @brief Defined Constants and Types for the STM32F3xx series + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ + diff --git a/libopencm3/include/libopencm3/stm32/f3/exti.h b/libopencm3/include/libopencm3/stm32/f3/exti.h new file mode 100644 index 0000000..d94916d --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/exti.h @@ -0,0 +1,51 @@ +/** @defgroup exti_defines EXTI Defines + * + * @brief Defined Constants and Types for the STM32F3xx External Interrupts + * + * + * @ingroup STM32F3xx_defines + * + * @author @htmlonly © @endhtmlonly 2013 + * Piotr Esden-Tempski + * + * @version 1.0.0 + * + * @date 14 January 2014 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Piotr Esden-Tempski + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EXTI_H +#define LIBOPENCM3_EXTI_H +/**@{*/ + +#include + +/* --- EXTI registers ------------------------------------------------------ */ +#define EXTI_IMR2 MMIO32(EXTI_BASE + 0x18) +#define EXTI_EMR2 MMIO32(EXTI_BASE + 0x1C) +#define EXTI_RTSR2 MMIO32(EXTI_BASE + 0x20) +#define EXTI_FTSR2 MMIO32(EXTI_BASE + 0x24) +#define EXTI_SWIER2 MMIO32(EXTI_BASE + 0x28) +#define EXTI_PR2 MMIO32(EXTI_BASE + 0x2C) +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/flash.h b/libopencm3/include/libopencm3/stm32/f3/flash.h new file mode 100644 index 0000000..58a8c9f --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/flash.h @@ -0,0 +1,73 @@ +/** @defgroup flash_defines FLASH Defines + * + * @brief Defined Constants and Types for the STM32F3xx Flash + * controller + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_FLASH_H +#define LIBOPENCM3_FLASH_H +/**@{*/ + +#include + +/* --- FLASH registers ----------------------------------------------------- */ + +#define FLASH_AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) +#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1C) +#define FLASH_WRPR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) + +/* --- FLASH_ACR values ---------------------------------------------------- */ + +#define FLASH_ACR_PRFTBS (1 << 5) +#define FLASH_ACR_PRFTBE (1 << 4) +#define FLASH_ACR_HLFCYA (1 << 3) + +/* --- FLASH_SR values ----------------------------------------------------- */ + +#define FLASH_SR_BSY (1 << 0) +#define FLASH_SR_ERLYBSY (1 << 1) +#define FLASH_SR_PGPERR (1 << 2) +#define FLASH_SR_WRPRTERR (1 << 4) +#define FLASH_SR_EOP (1 << 5) + +/* --- FLASH_CR values ----------------------------------------------------- */ + +#define FLASH_CR_OBL_LAUNCH (1 << 13) +#define FLASH_CR_EOPIE (1 << 12) +#define FLASH_CR_ERRIE (1 << 10) +#define FLASH_CR_OPTWRE (1 << 9) +#define FLASH_CR_LOCK (1 << 7) +#define FLASH_CR_STRT (1 << 6) +#define FLASH_CR_OPTER (1 << 5) +#define FLASH_CR_OPTPG (1 << 4) +#define FLASH_CR_MER (1 << 2) +#define FLASH_CR_PER (1 << 1) +#define FLASH_CR_PG (1 << 0) +/**@}*/ + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f3/gpio.h b/libopencm3/include/libopencm3/stm32/f3/gpio.h new file mode 100644 index 0000000..82aad6b --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/gpio.h @@ -0,0 +1,38 @@ +/** @defgroup gpio_defines GPIO Defines + * + * @brief Defined Constants and Types for the STM32F3xx General Purpose + * I/O + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 1 July 2012 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_GPIO_H +#define LIBOPENCM3_GPIO_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f3/i2c.h b/libopencm3/include/libopencm3/stm32/f3/i2c.h new file mode 100644 index 0000000..a16ff95 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/i2c.h @@ -0,0 +1,443 @@ +/** @defgroup i2c_defines I2C Defines + * + * @brief Defined Constants and Types for the STM32F3xx I2C + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 12 October 2012 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_I2C_H +#define LIBOPENCM3_I2C_H + +/**@{*/ + +/* --- Convenience macros -------------------------------------------------- */ + +/* I2C register base addresses (for convenience) */ +/*****************************************************************************/ +/** @defgroup i2c_reg_base I2C register base address + * @ingroup i2c_defines + * @{*/ +#define I2C1 I2C1_BASE +#define I2C2 I2C2_BASE +/**@}*/ + +/* --- I2C registers ------------------------------------------------------- */ + +/* Control register 1 (I2Cx_CR1) */ +#define I2C_CR1(i2c_base) MMIO32(i2c_base + 0x00) +#define I2C1_CR1 I2C_CR1(I2C1) +#define I2C2_CR1 I2C_CR1(I2C2) + +/* Control register 2 (I2Cx_CR2) */ +#define I2C_CR2(i2c_base) MMIO32(i2c_base + 0x04) +#define I2C1_CR2 I2C_CR2(I2C1) +#define I2C2_CR2 I2C_CR2(I2C2) + +/* Own address register 1 (I2Cx_OAR1) */ +#define I2C_OAR1(i2c_base) MMIO32(i2c_base + 0x08) +#define I2C1_OAR1 I2C_OAR1(I2C1) +#define I2C2_OAR1 I2C_OAR1(I2C2) + +/* Own address register 2 (I2Cx_OAR2) */ +#define I2C_OAR2(i2c_base) MMIO32(i2c_base + 0x0c) +#define I2C1_OAR2 I2C_OAR2(I2C1) +#define I2C2_OAR2 I2C_OAR2(I2C2) + +/* Timing register (I2Cx_TIMINGR) */ +#define I2C_TIMINGR(i2c_base) MMIO32(i2c_base + 0x10) +#define I2C1_TIMINGR I2C_TIMINGR(I2C1) +#define I2C2_TIMINGR I2C_TIMINGR(I2C2) + +/* Timeout register (I2Cx_TIMEOUTR) */ +#define I2C_TIMEOUTR(i2c_base) MMIO32(i2c_base + 0x14) +#define I2C1_TIMEOUTR I2C_TIMEOUTR(I2C1) +#define I2C2_TIMEOUTR I2C_TIMEOUTR(I2C2) + +/* Interrupt and Status register (I2Cx_ISR) */ +#define I2C_ISR(i2c_base) MMIO32(i2c_base + 0x18) +#define I2C1_ISR I2C_ISR(I2C1) +#define I2C2_ISR I2C_ISR(I2C2) + +/* Interrupt clear register (I2Cx_ICR) */ +#define I2C_ICR(i2c_base) MMIO32(i2c_base + 0x1C) +#define I2C1_ICR I2C_ICR(I2C1) +#define I2C2_ICR I2C_ICR(I2C2) + +/* PEC register (I2Cx_PECR) */ +#define I2C_PECR(i2c_base) MMIO32(i2c_base + 0x20) +#define I2C1_PECR I2C_PECR(I2C1) +#define I2C2_PECR I2C_PECR(I2C2) + +/* Receive data register (I2Cx_RXDR) */ +#define I2C_RXDR(i2c_base) MMIO32(i2c_base + 0x24) +#define I2C1_RXDR I2C_RXDR(I2C1) +#define I2C2_RXDR I2C_RXDR(I2C2) + +/* Transmit data register (I2Cx_TXDR) */ +#define I2C_TXDR(i2c_base) MMIO32(i2c_base + 0x28) +#define I2C1_TXDR I2C_TXDR(I2C1) +#define I2C2_TXDR I2C_TXDR(I2C2) + +/* --- I2Cx_CR1 values ----------------------------------------------------- */ + +/* PECEN: PEC enable */ +#define I2C_CR1_PECEN (1 << 23) + +/* ALERTEN: SMBus alert enable */ +#define I2C_CR1_ALERTEN (1 << 22) + +/* SMBDEN: SMBus Device Default address enable */ +#define I2C_CR1_SMBDEN (1 << 21) + +/* SMBHEN: SMBus Host address enable */ +#define I2C_CR1_SMBHEN (1 << 20) + +/* GCEN: General call enable */ +#define I2C_CR1_GCEN (1 << 19) + +/* WUPEN: Wakeup from STOP enable */ +#define I2C_CR1_WUPEN (1 << 18) + +/* NOSTRETCH: Clock stretching disable */ +#define I2C_CR1_NOSTRETCH (1 << 17) + +/* SBC: Slave byte control */ +#define I2C_CR1_SBC (1 << 16) + +/* RXDMAEN: DMA reception requests enable */ +#define I2C_CR1_RXDMAEN (1 << 15) + +/* TXDMAEN: DMA transmission requests enable */ +#define I2C_CR1_TXDMAEN (1 << 14) + +/* ANFOFF: Analog noise filter OFF */ +#define I2C_CR1_ANFOFF (1 << 12) + +/* DNF[3:0]: Digital noise filter */ +#define I2C_CR1_DNF_DISABLED (0x0 << 8) +#define I2C_CR1_DNF_UP_1_TI2CCLK (0x1 << 8) +#define I2C_CR1_DNF_UP_2_TI2CCLK (0x2 << 8) +#define I2C_CR1_DNF_UP_3_TI2CCLK (0x3 << 8) +#define I2C_CR1_DNF_UP_4_TI2CCLK (0x4 << 8) +#define I2C_CR1_DNF_UP_5_TI2CCLK (0x5 << 8) +#define I2C_CR1_DNF_UP_6_TI2CCLK (0x6 << 8) +#define I2C_CR1_DNF_UP_7_TI2CCLK (0x7 << 8) +#define I2C_CR1_DNF_UP_8_TI2CCLK (0x8 << 8) +#define I2C_CR1_DNF_UP_9_TI2CCLK (0x9 << 8) +#define I2C_CR1_DNF_UP_10_TI2CCLK (0xA << 8) +#define I2C_CR1_DNF_UP_11_TI2CCLK (0xB << 8) +#define I2C_CR1_DNF_UP_12_TI2CCLK (0xC << 8) +#define I2C_CR1_DNF_UP_13_TI2CCLK (0xD << 8) +#define I2C_CR1_DNF_UP_14_TI2CCLK (0xE << 8) +#define I2C_CR1_DNF_UP_15_TI2CCLK (0xF << 8) +#define I2C_CR1_DNF_MASK (0xF << 8) + +/* ERRIE: Error interrupts enable */ +#define I2C_CR1_ERRIE (1 << 7) + +/* TCIE: Transfer Complete interrupt enable */ +#define I2C_CR1_TCIE (1 << 6) + +/* STOPIE: STOP detection Interrupt enable */ +#define I2C_CR1_STOPIE (1 << 5) + +/* NACKIE: Not acknowledge received Interrupt enable */ +#define I2C_CR1_NACKIE (1 << 4) + +/* ADDRIE: Address match Interrupt enable (slave only) */ +#define I2C_CR1_DDRIE (1 << 3) + +/* RXIE: RX Interrupt enable */ +#define I2C_CR1_RXIE (1 << 2) + +/* TXIE: TX Interrupt enable */ +#define I2C_CR1_TXIE (1 << 1) + +/* PE: Peripheral enable */ +#define I2C_CR1_PE (1 << 0) + +/* --- I2Cx_CR2 values ----------------------------------------------------- */ + +/* PECBYTE: Packet error checking byte */ +#define I2C_CR2_PECBYTE (1 << 26) + +/* AUTOEND: Automatic end mode (master mode) */ +#define I2C_CR2_AUTOEND (1 << 25) + +/* RELOAD: NBYTES reload mode */ +#define I2C_CR2_RELOAD (1 << 24) + +/* NBYTES[7:0]: Number of bytes (23,16) */ +#define I2C_CR2_NBYTES_SHIFT 16 +#define I2C_CR2_NBYTES_MASK (0xFF << I2C_CR2_NBYTES_SHIFT) + +/* NACK: NACK generation (slave mode) */ +#define I2C_CR2_NACK (1 << 15) + +/* STOP: Stop generation (master mode) */ +#define I2C_CR2_STOP (1 << 14) + +/* START: Start generation */ +#define I2C_CR2_START (1 << 13) + +/* HEAD10R: 10-bit address header only read direction (master receiver mode) */ +#define I2C_CR2_HEAD10R (1 << 12) + +/* ADD10: 10-bit addressing mode (master mode) */ +#define I2C_CR2_ADD10 (1 << 11) + +/* RD_WRN: Transfer direction (master mode) */ +#define I2C_CR2_RD_WRN (1 << 10) + +#define I2C_CR2_SADD_7BIT_SHIFT 1 +#define I2C_CR2_SADD_10BIT_SHIFT 0 +#define I2C_CR2_SADD_7BIT_MASK (0x7F << I2C_CR2_SADD_7BIT_SHIFT) +#define I2C_CR2_SADD_10BIT_MASK 0x3FF + +/* --- I2Cx_OAR1 values ---------------------------------------------------- */ + +/* OA1EN: Own Address 1 enable */ +#define I2C_OAR1_OA1EN_DISABLE (0x0 << 15) +#define I2C_OAR1_OA1EN_ENABLE (0x1 << 15) + +/* OA1MODE Own Address 1 10-bit mode */ +#define I2C_OAR1_OA1MODE (1 << 10) +#define I2C_OAR1_OA1MODE_7BIT 0 +#define I2C_OAR1_OA1MODE_10BIT 1 + +/* OA1[9:8]: Interface address */ + +/* OA1[7:1]: Interface address */ + +/* OA1[0]: Interface address */ +#define I2C_OAR1_OA1 (1 << 10) +#define I2C_OAR1_OA1_7BIT 0 +#define I2C_OAR1_OA1_10BIT 1 + +/* --- I2Cx_OAR2 values ---------------------------------------------------- */ + +/* OA2EN: Own Address 2 enable */ +#define I2C_OAR2_OA2EN (1 << 15) + +/* OA2MSK[2:0]: Own Address 2 masks */ +#define I2C_OAR2_OA2MSK_NO_MASK (0x0 << 8) +#define I2C_OAR2_OA2MSK_OA2_7_OA2_2 (0x1 << 8) +#define I2C_OAR2_OA2MSK_OA2_7_OA2_3 (0x2 << 8) +#define I2C_OAR2_OA2MSK_OA2_7_OA2_4 (0x3 << 8) +#define I2C_OAR2_OA2MSK_OA2_7_OA2_5 (0x4 << 8) +#define I2C_OAR2_OA2MSK_OA2_7_OA2_6 (0x5 << 8) +#define I2C_OAR2_OA2MSK_OA2_7 (0x6 << 8) +#define I2C_OAR2_OA2MSK_NO_CMP (0x7 << 8) + +/* OA2[7:1]: Interface address */ + +/* --- I2Cx_TIMINGR values ------------------------------------------------- */ + +/* PRESC[3:0]: Timing prescaler (31,28) */ +#define I2C_TIMINGR_PRESC_SHIFT 28 +#define I2C_TIMINGR_PRESC_MASK (0xF << 28) + +/* SCLDEL[3:0]: Data setup time (23,20) */ +#define I2C_TIMINGR_SCLDEL_SHIFT 20 +#define I2C_TIMINGR_SCLDEL_MASK (0xF << I2C_TIMINGR_SCLDEL_SHIFT) + +/* SDADEL[3:0]: Data hold time (19,16) */ +#define I2C_TIMINGR_SDADEL_SHIFT 16 +#define I2C_TIMINGR_SDADEL_MASK (0xF << I2C_TIMINGR_SDADEL_SHIFT) + +/* SCLH[7:0]: SCL high period (master mode) (15,8) */ +#define I2C_TIMINGR_SCLH_SHIFT 8 +#define I2C_TIMINGR_SCLH_MASK (0xFF << I2C_TIMINGR_SCLH_SHIFT) + +/* SCLL[7:0]: SCL low period (master mode) (7,0) */ +#define I2C_TIMINGR_SCLL_SHIFT 0 +#define I2C_TIMINGR_SCLL_MASK (0xFF << I2C_TIMINGR_SCLL_SHIFT) + +/* --- I2Cx_TIEMOUTR values ------------------------------------------------ */ + +/* TEXTEN: Extended clock timeout enable */ +#define I2C_TIEMOUTR_TEXTEN (1 << 31) + +/* XXX: Not clear yet. */ +/* TIMEOUTB[11:0]: Bus timeout B */ + +/* TIMOUTEN: Clock timeout enable */ +#define I2C_TIEMOUTR_TIMOUTEN (1 << 15) + +/* TIDLE: Idle clock timeout detection */ +#define I2C_TIEMOUTR_TIDLE_SCL_LOW (0x0 << 12) +#define I2C_TIEMOUTR_TIDLE_SCL_SDA_HIGH (0x1 << 12) + +/* XXX: Not clear yet. */ +/* TIMEOUTA[11:0]: Bus Timeout A */ + +/* --- I2Cx_ISR values ----------------------------------------------------- */ + +/* Bits 31:24 Reserved, must be kept at reset value */ + +/* XXX: Not clear yet. */ +/* ADDCODE[6:0]: Address match code (Slave mode) */ + +/* DIR: Transfer direction (Slave mode) */ +#define I2C_ISR_DIR_READ (0x1 << 16) +#define I2C_ISR_DIR_WRITE (0x0 << 16) + +/* BUSY: Bus busy */ +#define I2C_ISR_BUSY (1 << 15) + +/* ALERT: SMBus alert */ +#define I2C_ISR_ALERT (1 << 13) + +/* TIMEOUT: Timeout or tLOW detection flag */ +#define I2C_ISR_TIMEOUT (1 << 12) + +/* PECERR: PEC Error in reception */ +#define I2C_ISR_PECERR (1 << 11) + +/* OVR: Overrun/Underrun (slave mode) */ +#define I2C_ISR_OVR (1 << 10) + +/* ARLO: Arbitration lost */ +#define I2C_ISR_ARLO (1 << 9) + +/* BERR: Bus error */ +#define I2C_ISR_BERR (1 << 8) + +/* TCR: Transfer Complete Reload */ +#define I2C_ISR_TCR (1 << 7) + +/* TC: Transfer Complete (master mode) */ +#define I2C_ISR_TC (1 << 6) + +/* STOPF: Stop detection flag */ +#define I2C_ISR_STOPF (1 << 5) + +/* NACKF: Not Acknowledge received flag */ +#define I2C_ISR_NACKF (1 << 4) + +/* ADDR: Address matched (slave mode) */ +#define I2C_ISR_ADDR (1 << 3) + +/* RXNE: Receive data register not empty (receivers) */ +#define I2C_ISR_RXNE (1 << 2) + +/* TXIS: Transmit interrupt status (transmitters) */ +#define I2C_ISR_TXIS (1 << 1) + +/* TXE: Transmit data register empty (transmitters) */ +#define I2C_ISR_TXE (1 << 0) + +/* --- I2Cx_ICR values ----------------------------------------------------- */ + +/* ALERTCF: Alert flag clear */ +#define I2C_ICR_ALERTCF (1 << 13) + +/* TIMOUTCF: Timeout detection flag clear */ +#define I2C_ICR_TIMOUTCF (1 << 12) + +/* PECCF: PEC Error flag clear */ +#define I2C_ICR_PECCF (1 << 11) + +/* OVRCF: Overrun/Underrun flag clear */ +#define I2C_ICR_OVRCF (1 << 10) + +/* ARLOCF: Arbitration Lost flag clear */ +#define I2C_ICR_ARLOCF (1 << 9) + +/* BERRCF: Bus error flag clear */ +#define I2C_ICR_BERRCF (1 << 8) + +/* STOPCF: Stop detection flag clear */ +#define I2C_ICR_STOPCF (1 << 5) + +/* NACKCF: Not Acknowledge flag clear */ +#define I2C_ICR_NACKCF (1 << 4) + +/* ADDRCF: Address Matched flag clear */ +#define I2C_ICR_ADDRCF (1 << 3) + +/* --- I2Cx_PECR values ---------------------------------------------------- */ + +/* PEC[7:0] Packet error checking register */ + +/* --- I2C function prototypes---------------------------------------------- */ + +BEGIN_DECLS + +void i2c_reset(uint32_t i2c); +void i2c_peripheral_enable(uint32_t i2c); +void i2c_peripheral_disable(uint32_t i2c); +void i2c_send_start(uint32_t i2c); +void i2c_send_stop(uint32_t i2c); +void i2c_clear_stop(uint32_t i2c); +void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave); +void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave); +void i2c_set_clock_frequency(uint32_t i2c, uint8_t freq); +void i2c_send_data(uint32_t i2c, uint8_t data); +uint8_t i2c_get_data(uint32_t i2c); + +void i2c_enable_analog_filter(uint32_t i2c); +void i2c_disable_analog_filter(uint32_t i2c); +void i2c_set_digital_filter(uint32_t i2c, uint8_t dnf_setting); +void i2c_set_prescaler(uint32_t i2c, uint8_t presc); +void i2c_set_data_setup_time(uint32_t i2c, uint8_t s_time); +void i2c_set_data_hold_time(uint32_t i2c, uint8_t h_time); +void i2c_set_scl_high_period(uint32_t i2c, uint8_t period); +void i2c_set_scl_low_period(uint32_t i2c, uint8_t period); +void i2c_enable_stretching(uint32_t i2c); +void i2c_disable_stretching(uint32_t i2c); +void i2c_100khz_i2cclk8mhz(uint32_t i2c); +void i2c_set_7bit_addr_mode(uint32_t i2c); +void i2c_set_10bit_addr_mode(uint32_t i2c); +void i2c_set_7bit_address(uint32_t i2c, uint8_t addr); +void i2c_set_10bit_address(uint32_t i2c, uint16_t addr); +void i2c_set_write_transfer_dir(uint32_t i2c); +void i2c_set_read_transfer_dir(uint32_t i2c); +void i2c_set_bytes_to_transfer(uint32_t i2c, uint32_t n_bytes); +uint8_t i2c_is_start(uint32_t i2c); +void i2c_enable_autoend(uint32_t i2c); +void i2c_disable_autoend(uint32_t i2c); +uint8_t i2c_nack(uint32_t i2c); +uint8_t i2c_busy(uint32_t i2c); +uint8_t i2c_transmit_int_status(uint32_t i2c); +uint8_t i2c_transfer_complete(uint32_t i2c); +uint8_t i2c_received_data(uint32_t i2c); +void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt); +void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt); +void i2c_enable_rxdma(uint32_t i2c); +void i2c_disable_rxdma(uint32_t i2c); +void i2c_enable_txdma(uint32_t i2c); +void i2c_disable_txdma(uint32_t i2c); +void write_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, + uint8_t size, uint8_t *data); +void read_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, + uint8_t size, uint8_t *data); + +END_DECLS + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/irq.json b/libopencm3/include/libopencm3/stm32/f3/irq.json new file mode 100644 index 0000000..ee8042e --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/irq.json @@ -0,0 +1,88 @@ +{ + "irqs": [ + "nvic_wwdg", + "pvd", + "tamp_stamp", + "rtc_wkup", + "flash", + "rcc", + "exti0", + "exti1", + "exti2_tsc", + "exti3", + "exti4", + "dma1_channel1", + "dma1_channel2", + "dma1_channel3", + "dma1_channel4", + "dma1_channel5", + "dma1_channel6", + "dma1_channel7", + "adc1_2", + "usb_hp_can1_tx", + "usb_lp_can1_rx0", + "can1_rx1", + "can1_sce", + "exti9_5", + "tim1_brk_tim15", + "tim1_up_tim16", + "tim1_trg_com_tim17", + "tim1_cc", + "tim2", + "tim3", + "tim4", + "i2c1_ev_exti23", + "i2c1_er", + "i2c2_ev_exti24", + "i2c2_er", + "spi1", + "spi2", + "usart1_exti25", + "usart2_exti26", + "usart3_exti28", + "exti15_10", + "rtc_alarm", + "usb_wkup_a", + "tim8_brk", + "tim8_up", + "tim8_trg_com", + "tim8_cc", + "adc3", + "reserved_1", + "reserved_2", + "reserved_3", + "spi3", + "uart4_exti34", + "uart5_exti35", + "tim6_dac", + "tim7", + "dma2_channel1", + "dma2_channel2", + "dma2_channel3", + "dma2_channel4", + "dma2_channel5", + "eth", + "reserved_4", + "reserved_5", + "comp123", + "comp456", + "comp7", + "reserved_6", + "reserved_7", + "reserved_8", + "reserved_9", + "reserved_10", + "reserved_11", + "reserved_12", + "usb_hp", + "usb_lp", + "usb_wkup", + "reserved_13", + "reserved_14", + "reserved_15", + "reserved_16" + ], + "partname_humanreadable": "STM32 F3 series", + "partname_doxygen": "STM32F3", + "includeguard": "LIBOPENCM3_STM32_F3_NVIC_H" +} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/stm32/f3/iwdg.h b/libopencm3/include/libopencm3/stm32/f3/iwdg.h new file mode 100644 index 0000000..c7413a4 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/iwdg.h @@ -0,0 +1,53 @@ +/** @defgroup iwdg_defines IWDG Defines + * + * @brief Defined Constants and Types for the STM32F3xx Independent Watchdog + * Timer + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 18 August 2012 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_IWDG_H +#define LIBOPENCM3_IWDG_H + +#include + +/* --- IWDG registers ------------------------------------------------------ */ + +/* Window register (IWDG_WINR) */ +#define IWDG_WINR MMIO32(IWDG_BASE + 0x10) + +/* --- IWDG_SR values ------------------------------------------------------ */ + +/* WVU: Watchdog counter window value update */ +#define IWGD_SR_WVU (1 << 2) + +/* --- IWDG_WIN values ----------------------------------------------------- */ + +/* Bits 11:0 WIN[11:0]: Watchdog counter window value */ + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f3/memorymap.h b/libopencm3/include/libopencm3/stm32/f3/memorymap.h new file mode 100644 index 0000000..efaded7 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/memorymap.h @@ -0,0 +1,129 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * Modified by 2013 Fernando Cortes (stm32f3) + * Modified by 2013 Guillermo Rivera (stm32f3) + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_MEMORYMAP_H +#define LIBOPENCM3_MEMORYMAP_H + +#include + +/* --- STM32F3 specific peripheral definitions ----------------------------- */ + +/* Memory map for all busses */ +#define PERIPH_BASE (0x40000000U) +#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) +#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) +#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000) +#define PERIPH_BASE_AHB2 (0x48000000U) +#define PERIPH_BASE_AHB3 (0x50000000U) + +/* Register boundary addresses */ + +/* APB1 */ +#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) +#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) +#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) +/* PERIPH_BASE_APB1 + 0x0C00 (0x4000 0C00 - 0x4000 0FFF): Reserved */ +#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) +#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) +/* PERIPH_BASE_APB1 + 0x1800 (0x4000 1800 - 0x4000 27FF): Reserved */ +#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) +#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) +#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) +#define I2S2_EXT_BASE (PERIPH_BASE_APB1 + 0x3400) +#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) +#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) +#define I2S3_EXT_BASE (PERIPH_BASE_APB1 + 0x4000) +#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) +#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) +#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) +#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) +#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) +#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) +#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5C00) +#define USB_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000) +#define BX_CAN_BASE (PERIPH_BASE_APB1 + 0x6400) +/* PERIPH_BASE_APB1 + 0x6800 (0x4000 6800 - 0x4000 6BFF): Reserved */ +/* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */ +#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) +#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) +/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 7FFF): Reserved */ + + +/* APB2 */ +#define TIM17_BASE (PERIPH_BASE_APB2 + 0x4800) +#define TIM16_BASE (PERIPH_BASE_APB2 + 0x4400) +#define TIM15_BASE (PERIPH_BASE_APB2 + 0x4000) +/* PERIPH_BASE_APB2 + 0x3C00 (0x4001 3C00 - 0x4001 3FFF): Reserved */ +#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) +#define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400) +#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) +#define TIM1_BASE (PERIPH_BASE_APB2 + 0x2C00) +/* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 2BFF): Reserved */ +#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) +#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000) +#define COMP_BASE (PERIPH_BASE_APB2 + 0x0000) +#define OPAMP_BASE (PERIPH_BASE_APB2 + 0x0000) + + +/* AHB2 */ +#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB2 + 0x0000) +#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB2 + 0x0400) +#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB2 + 0x0800) +#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB2 + 0x0C00) +#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB2 + 0x1000) +#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB2 + 0x1400) + + +/* AHB1 */ +#define TSC_BASE (PERIPH_BASE_AHB1 + 0x4000) +/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */ +#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) +/* PERIPH_BASE_AHB1 + 0x2400 (0x4002 2400 - 0x4002 2FFF): Reserved */ +#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x2000) +/* PERIPH_BASE_AHB1 + 0x1400 (0x4002 1400 - 0x4002 1FFF): Reserved */ +#define RCC_BASE (PERIPH_BASE_AHB1 + 0x1000) +/* PERIPH_BASE_AHB1 + 0x0800 (0x4002 0800 - 0x4002 0FFF): Reserved */ +#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x0000) +#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x0400) + + +/* AHB3 */ +#define ADC3_BASE (PERIPH_BASE_AHB3 + 0x0400) +#define ADC4_BASE (PERIPH_BASE_AHB3 + 0x0400) +#define ADC1_BASE (PERIPH_BASE_AHB3 + 0x0000) +#define ADC2_BASE (PERIPH_BASE_AHB3 + 0x0000) + +/* PPIB */ +#define DBGMCU_BASE (PPBI_BASE + 0x00042000) + +/* Device Electronic Signature */ +#define DESIG_FLASH_SIZE_BASE (0x1FFFF7CCU) +#define DESIG_UNIQUE_ID_BASE (0x1FFFF7ACU) +#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) +#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) +#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8) + +/* ST provided factory calibration values @ 3.3V */ +#define ST_VREFINT_CAL MMIO16(0x1FFFF7BA) +#define ST_TSENSE_CAL1_30C MMIO16(0x1FFFF7B8) +#define ST_TSENSE_CAL2_110 MMIO16(0x1FFFF7C2) + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/pwr.h b/libopencm3/include/libopencm3/stm32/f3/pwr.h new file mode 100644 index 0000000..e30acb9 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/pwr.h @@ -0,0 +1,69 @@ +/** @defgroup pwr_defines PWR Defines + * + * @brief Defined Constants and Types for the STM32F3xx Power control + * + * @ingroup STM32F3xx_defines + * + * @author @htmlonly © @endhtmlonly 2011 + * Stephen Caudle + * @author @htmlonly © @endhtmlonly 2013 + * Fernando Cortes + * @author @htmlonly © @endhtmlonly 2013 + * Guillermo Rivera + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Stephen Caudle + * Modified by 2013 Fernando Cortes (stm32f3) + * Modified by 2013 Guillermo Rivera (stm32f3) + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_PWR_F3_H +#define LIBOPENCM3_PWR_F3_H + +#include + +/* --- PWR_CR values ------------------------------------------------------- */ + +/* Bits [31:10]: Reserved */ +#define PWR_CR_DBP (1 << 8) +/* Bits [7:5]: Reserved PLS: PVD level selection. (Power Voltage Detector) */ +#define PWR_CR_PVDE (1 << 4) +#define PWR_CR_CSBF (1 << 3) +#define PWR_CR_CWUF (1 << 2) +#define PWR_CR_PDDS (1 << 1) +#define PWR_CR_LPDS (1 << 0) + + +/* --- PWR_CSR values ------------------------------------------------------ */ + +/* Bits [31:10]: Reserved */ +#define PWR_CSR_EWUP2 (1 << 9) +#define PWR_CSR_EWUP1 (1 << 8) +/* Bits [7:3]: Reserved */ +#define PWR_CSR_PVDO (1 << 2) +#define PWR_CSR_SBF (1 << 1) +#define PWR_CSR_WUF (1 << 0) + + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/rcc.h b/libopencm3/include/libopencm3/stm32/f3/rcc.h new file mode 100644 index 0000000..41caaa3 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/rcc.h @@ -0,0 +1,602 @@ +/** @defgroup rcc_defines RCC Defines + * + * @brief Defined Constants and Types for the STM32F3xx Reset and Clock + * Control + * + * @ingroup STM32F3xx_defines + * + * @author @htmlonly © @endhtmlonly 2009 + * Federico Ruiz-Ugalde \ + * @author @htmlonly © @endhtmlonly 2009 + * Uwe Hermann + * @author @htmlonly © @endhtmlonly 2011 + * Fergus Noble + * @author @htmlonly © @endhtmlonly 2011 + * Stephen Caudle + * @author @htmlonly © @endhtmlonly 2013 + * Fernando Cortes + * @author @htmlonly © @endhtmlonly 2013 + * Guillermo Rivera + * + * @version 1.0.0 + * + * @date 11 July 2013 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2009 Federico Ruiz-Ugalde + * Copyright (C) 2011 Fergus Noble + * Copyright (C) 2011 Stephen Caudle + * Modified by 2013 Fernando Cortes (stm32f3) + * Modified by 2013 Guillermo Rivera (stm32f3) + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_RCC_H +#define LIBOPENCM3_RCC_H + +/* --- RCC registers ------------------------------------------------------- */ + +#define RCC_CR MMIO32(RCC_BASE + 0x00) +#define RCC_CFGR MMIO32(RCC_BASE + 0x04) +#define RCC_CIR MMIO32(RCC_BASE + 0x08) +#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x0C) +#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x10) +#define RCC_AHBENR MMIO32(RCC_BASE + 0x14) +#define RCC_APB2ENR MMIO32(RCC_BASE + 0x18) +#define RCC_APB1ENR MMIO32(RCC_BASE + 0x1C) +#define RCC_BDCR MMIO32(RCC_BASE + 0x20) +#define RCC_CSR MMIO32(RCC_BASE + 0x24) +#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) +#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2C) +#define RCC_CFGR3 MMIO32(RCC_BASE + 0x30) + +/* --- RCC_CR values ------------------------------------------------------- */ + +#define RCC_CR_PLLRDY (1 << 25) +#define RCC_CR_PLLON (1 << 24) +#define RCC_CR_CSSON (1 << 19) +#define RCC_CR_HSEBYP (1 << 18) +#define RCC_CR_HSERDY (1 << 17) +#define RCC_CR_HSEON (1 << 16) +/* HSICAL: [15:8] */ +/* HSITRIM: [7:3] */ +#define RCC_CR_HSIRDY (1 << 1) +#define RCC_CR_HSION (1 << 0) + +/* --- RCC_CFGR values ----------------------------------------------------- */ +#define RCC_CFGR_MCOF (1 << 28) +#define RCC_CFGR_I2SSRC (1 << 23) +#define RCC_CFGR_USBPRES (1 << 22) +#define RCC_CFGR_PLLXTPRE (1 << 17) +#define RCC_CFGR_PLLSRC (1 << 16) + +/* MCO: Microcontroller clock output */ +#define RCC_CFGR_MCO_SHIFT 24 +#define RCC_CFGR_MCO_DISABLED 0x0 +/*Reserve RCC_CFGR_MCO 0x1*/ +#define RCC_CFGR_MCO_LSI 0x2 +#define RCC_CFGR_MCO_LSE 0x3 +#define RCC_CFGR_MCO_SYSCLK 0x4 +#define RCC_CFGR_MCO_HSI 0x5 +#define RCC_CFGR_MCO_HSE 0x6 +#define RCC_CFGR_MCO_PLL 0x7 + +/* PLLSRC: PLL source values */ +#define RCC_CFGR_PLLSRC_HSI_DIV2 0 +#define RCC_CFGR_PLLSRC_HSE_PREDIV 1 + +/* PLLMUL: PLL multiplication factor */ +#define RCC_CFGR_PLLMUL_SHIFT 18 +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X2 0x0 +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X3 0x1 +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X4 0x2 +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X5 0x3 +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X6 0x4 +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X7 0x5 +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X8 0x6 +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X9 0x7 +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X10 0x8 +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X11 0x9 +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X12 0xA +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X13 0xB +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X14 0xC +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X15 0xD +#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X16 0xE +#define RCC_CFGR_PLLMUL_MASK (0xF << RCC_CFGR_PLLMUL_SHIFT) + +/* PPRE2: APB high-speed prescaler (APB2) */ +#define RCC_CFGR_PPRE2_SHIFT 11 +/* 0XX: HCLK not divided */ +#define RCC_CFGR_PPRE2_DIV_NONE 0x0 + +#define RCC_CFGR_PPRE2_DIV_2 0x4 +#define RCC_CFGR_PPRE2_DIV_4 0x5 +#define RCC_CFGR_PPRE2_DIV_8 0x6 +#define RCC_CFGR_PPRE2_DIV_16 0x7 + +/* PPRE1:APB Low-speed prescaler (APB1) */ +#define RCC_CFGR_PPRE1_SHIFT 8 +/* 0XX: HCLK not divided */ +#define RCC_CFGR_PPRE1_DIV_NONE 0x0 +#define RCC_CFGR_PPRE1_DIV_2 0x4 +#define RCC_CFGR_PPRE1_DIV_4 0x5 +#define RCC_CFGR_PPRE1_DIV_8 0x6 +#define RCC_CFGR_PPRE1_DIV_16 0x7 + +/* HPRE: HLCK prescaler */ +#define RCC_CFGR_HPRE_SHIFT 4 +/* 0XXX: SYSCLK not divided */ +#define RCC_CFGR_HPRE_DIV_NONE 0x0 +#define RCC_CFGR_HPRE_DIV_2 0x8 +#define RCC_CFGR_HPRE_DIV_4 0x9 +#define RCC_CFGR_HPRE_DIV_8 0xA +#define RCC_CFGR_HPRE_DIV_16 0xB +#define RCC_CFGR_HPRE_DIV_64 0xC +#define RCC_CFGR_HPRE_DIV_128 0xD +#define RCC_CFGR_HPRE_DIV_256 0xE +#define RCC_CFGR_HPRE_DIV_512 0xF + +/* SWS: System clock switch status */ +#define RCC_CFGR_SWS_SHIFT 2 +#define RCC_CFGR_SWS_HSI 0x0 +#define RCC_CFGR_SWS_HSE 0x1 +#define RCC_CFGR_SWS_PLL 0x2 + +/* SW: System clock switch */ +#define RCC_CFGR_SW_SHIFT 0 +#define RCC_CFGR_SW_HSI 0x0 +#define RCC_CFGR_SW_HSE 0x1 +#define RCC_CFGR_SW_PLL 0x2 + +/* --- RCC_CIR values ------------------------------------------------------ */ + +/* Clock security system interrupt clear bit */ +#define RCC_CIR_CSSC (1 << 23) + +/* OSC ready interrupt clear bits */ +#define RCC_CIR_PLLRDYC (1 << 20) +#define RCC_CIR_HSERDYC (1 << 19) +#define RCC_CIR_HSIRDYC (1 << 18) +#define RCC_CIR_LSERDYC (1 << 17) +#define RCC_CIR_LSIRDYC (1 << 16) + +/* OSC ready interrupt enable bits */ +#define RCC_CIR_PLLRDYIE (1 << 12) +#define RCC_CIR_HSERDYIE (1 << 11) +#define RCC_CIR_HSIRDYIE (1 << 10) +#define RCC_CIR_LSERDYIE (1 << 9) +#define RCC_CIR_LSIRDYIE (1 << 8) + +/* Clock security system interrupt flag bit */ +#define RCC_CIR_CSSF (1 << 7) + +/* OSC ready interrupt flag bits */ +#define RCC_CIR_PLLRDYF (1 << 4) +#define RCC_CIR_HSERDYF (1 << 3) +#define RCC_CIR_HSIRDYF (1 << 2) +#define RCC_CIR_LSERDYF (1 << 1) +#define RCC_CIR_LSIRDYF (1 << 0) + +/* --- RCC_APB2RSTR values ------------------------------------------------- */ + +#define RCC_APB2RSTR_TIM17RST (1 << 18) +#define RCC_APB2RSTR_TIM16RST (1 << 17) +#define RCC_APB2RSTR_TIM15RST (1 << 16) +#define RCC_APB2RSTR_USART1RST (1 << 14) +#define RCC_APB2RSTR_TIM8RST (1 << 13) +#define RCC_APB2RSTR_SPI1RST (1 << 12) +#define RCC_APB2RSTR_TIM1RST (1 << 11) +#define RCC_APB2RSTR_SYSCFGRST (1 << 0) + +/* --- RCC_APB1RSTR values ------------------------------------------------- */ + +#define RCC_APB1RSTR_DACRST (1 << 29) +#define RCC_APB1RSTR_PWRRST (1 << 28) +#define RCC_APB1RSTR_CANRST (1 << 25) +#define RCC_APB1RSTR_USBRST (1 << 23) +#define RCC_APB1RSTR_I2C2RST (1 << 22) +#define RCC_APB1RSTR_I2C1RST (1 << 21) +#define RCC_APB1RSTR_UART5RST (1 << 20) +#define RCC_APB1RSTR_UART4RST (1 << 19) +#define RCC_APB1RSTR_USART3RST (1 << 18) +#define RCC_APB1RSTR_USART2RST (1 << 17) +#define RCC_APB1RSTR_SPI3RST (1 << 15) +#define RCC_APB1RSTR_SPI2RST (1 << 14) +#define RCC_APB1RSTR_WWDGRST (1 << 11) +#define RCC_APB1RSTR_TIM7RST (1 << 5) +#define RCC_APB1RSTR_TIM6RST (1 << 4) +#define RCC_APB1RSTR_TIM4RST (1 << 2) +#define RCC_APB1RSTR_TIM3RST (1 << 1) +#define RCC_APB1RSTR_TIM2RST (1 << 0) + +/* --- RCC_AHBENR values --------------------------------------------------- */ +#define RCC_AHBENR_ADC34EN (1 << 29) +#define RCC_AHBENR_ADC12EN (1 << 28) +#define RCC_AHBENR_TSCEN (1 << 24) +#define RCC_AHBENR_IOPFEN (1 << 22) +#define RCC_AHBENR_IOPEEN (1 << 21) +#define RCC_AHBENR_IOPDEN (1 << 20) +#define RCC_AHBENR_IOPCEN (1 << 19) +#define RCC_AHBENR_IOPBEN (1 << 18) +#define RCC_AHBENR_IOPAEN (1 << 17) +#define RCC_AHBENR_CRCEN (1 << 6) +#define RCC_AHBENR_FLITFEN (1 << 4) +#define RCC_AHBENR_SRAMEN (1 << 2) +#define RCC_AHBENR_DMA2EN (1 << 1) +#define RCC_AHBENR_DMA1EN (1 << 0) + +/* --- RCC_APB2ENR values -------------------------------------------------- */ + +#define RCC_APB2ENR_TIM17EN (1 << 18) +#define RCC_APB2ENR_TIM16EN (1 << 17) +#define RCC_APB2ENR_TIM15EN (1 << 16) +#define RCC_APB2ENR_USART1EN (1 << 14) +#define RCC_APB2ENR_TIM8EN (1 << 13) +#define RCC_APB2ENR_SPI1EN (1 << 12) +#define RCC_APB2ENR_TIM1EN (1 << 11) +#define RCC_APB2ENR_SYSCFGEN (1 << 0) + +/* --- RCC_APB1ENR values -------------------------------------------------- */ + +#define RCC_APB1ENR_DACEN (1 << 29) +#define RCC_APB1ENR_PWREN (1 << 28) +#define RCC_APB1ENR_CANEN (1 << 25) +#define RCC_APB1ENR_USBEN (1 << 23) +#define RCC_APB1ENR_I2C2EN (1 << 22) +#define RCC_APB1ENR_I2C1EN (1 << 21) +#define RCC_APB1ENR_USART5EN (1 << 20) +#define RCC_APB1ENR_USART4EN (1 << 19) +#define RCC_APB1ENR_USART3EN (1 << 18) +#define RCC_APB1ENR_USART2EN (1 << 17) +#define RCC_APB1ENR_SPI3EN (1 << 15) +#define RCC_APB1ENR_SPI2EN (1 << 14) +#define RCC_APB1ENR_WWDGEN (1 << 11) +#define RCC_APB1ENR_TIM7EN (1 << 5) +#define RCC_APB1ENR_TIM6EN (1 << 4) +#define RCC_APB1ENR_TIM4EN (1 << 2) +#define RCC_APB1ENR_TIM3EN (1 << 1) +#define RCC_APB1ENR_TIM2EN (1 << 0) + +/* --- RCC_BDCR values ----------------------------------------------------- */ + +#define RCC_BDCR_BDRST (1 << 16) +#define RCC_BDCR_RTCEN (1 << 15) +/* RCC_BDCR[9:8]: RTCSEL */ +/* RCC_BDCR[4:3]: LSEDRV */ +#define RCC_BDCR_LSEBYP (1 << 2) +#define RCC_BDCR_LSERDY (1 << 1) +#define RCC_BDCR_LSEON (1 << 0) + +/* --- RCC_CSR values ------------------------------------------------------ */ + +#define RCC_CSR_LPWRRSTF (1 << 31) +#define RCC_CSR_WWDGRSTF (1 << 30) +#define RCC_CSR_IWDGRSTF (1 << 29) +#define RCC_CSR_SFTRSTF (1 << 28) +#define RCC_CSR_PORRSTF (1 << 27) +#define RCC_CSR_PINRSTF (1 << 26) +#define RCC_CSR_OBLRSTF (1 << 25) +#define RCC_CSR_RMVF (1 << 24) +#define RCC_CSR_LSIRDY (1 << 1) +#define RCC_CSR_LSION (1 << 0) + +/* --- RCC_AHBRSTR values -------------------------------------------------- */ +#define RCC_AHBRSTR_ADC34RST (1 << 29) +#define RCC_AHBRSTR_ADC12RST (1 << 28) +#define RCC_AHBRSTR_TSCRST (1 << 24) +#define RCC_AHBRSTR_IOPFRST (1 << 22) +#define RCC_AHBRSTR_IOPERST (1 << 21) +#define RCC_AHBRSTR_IOPDRST (1 << 20) +#define RCC_AHBRSTR_IOPCRST (1 << 19) +#define RCC_AHBRSTR_IOPBRST (1 << 18) +#define RCC_AHBRSTR_IOPARST (1 << 17) + +/* --- RCC_CFGR2 values ---------------------------------------------------- */ +/* ADC34PRES: ADC34 prescaler */ +#define RCC_CFGR2_ADC34PRES_SHIFT 9 +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_1 0x10 +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_2 0x11 +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_4 0x12 +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_6 0x13 +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_8 0x14 +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_10 0x15 +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_12 0x16 +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_16 0x17 +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_32 0x18 +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_64 0x19 +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_128 0x1A +#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_256 0x1B +/* OTHERS */ +/* #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV256 0x */ + +/* ADC12PRES ADC prescaler */ +/* REVISAR DIRECCIONES */ +#define RCC_CFGR2_ADC12PRES_SHIFT 4 +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_1 0x10 +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_2 0x11 +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_4 0x12 +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_6 0x13 +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_8 0x14 +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_10 0x15 +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_12 0x16 +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_16 0x17 +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_32 0x18 +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_64 0x19 +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_128 0x1A +#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_256 0x1B +/* OTHERS */ +/* #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV256 0x */ + +/* PREDIV[3:0] PREDIV division factor */ +/* REVISAR DIRECCIONES */ +#define RCC_CFGR2_PREDIV_SHIFT 0 +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_NONE 0x0 +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_2 0x1 +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_3 0x2 +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_4 0x3 +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_5 0x4 +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_6 0x5 +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_7 0x6 +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_8 0x7 +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_9 0x8 +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_10 0x9 +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_11 0xA +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_12 0xB +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_13 0xC +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_14 0xD +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_15 0xE +#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_16 0xF + +/* --- RCC_CFGR3 values ---------------------------------------------------- */ +#define RCC_CFGR3_TIM8SW (1 << 9) +#define RCC_CFGR3_TIM1SW (1 << 8) +#define RCC_CFGR3_I2C2SW (1 << 5) +#define RCC_CFGR3_I2C1SW (1 << 4) +/* UART5SW: UART5 clock source selection */ +#define RCC_CFGR3_UART5SW_SHIFT 22 +#define RCC_CFGR3_UART5SW_PCLK 0x0 +#define RCC_CFGR3_UART5SW_SYSCLK 0x1 +#define RCC_CFGR3_UART5SW_LSE 0x2 +#define RCC_CFGR3_UART5SW_HSI 0x3 +/* UART4SW: UART4 clock source selection */ +#define RCC_CFGR3_UART4SW_SHIFT 20 +#define RCC_CFGR3_UART4SW_PCLK 0x0 +#define RCC_CFGR3_UART4SW_SYSCLK 0x1 +#define RCC_CFGR3_UART4SW_LSE 0x2 +#define RCC_CFGR3_UART4SW_HSI 0x3 +/* UART3SW: UART3 clock source selection */ +#define RCC_CFGR3_UART3SW_SHIFT 18 +#define RCC_CFGR3_UART3SW_PCLK 0x0 +#define RCC_CFGR3_UART3SW_SYSCLK 0x1 +#define RCC_CFGR3_UART3SW_LSE 0x2 +#define RCC_CFGR3_UART3SW_HSI 0x3 +/* UART2SW: UART2 clock source selection */ +#define RCC_CFGR3_UART2SW_SHIFT 16 +#define RCC_CFGR3_UART2SW_PCLK 0x0 +#define RCC_CFGR3_UART2SW_SYSCLK 0x1 +#define RCC_CFGR3_UART2SW_LSE 0x2 +#define RCC_CFGR3_UART2SW_HSI 0x3 +/* UART1SW: UART1 clock source selection */ +#define RCC_CFGR3_UART1SW_SHIFT 0 +#define RCC_CFGR3_UART1SW_PCLK 0x0 +#define RCC_CFGR3_UART1SW_SYSCLK 0x1 +#define RCC_CFGR3_UART1SW_LSE 0x2 +#define RCC_CFGR3_UART1SW_HSI 0x3 + + +/* --- Variable definitions ------------------------------------------------ */ +extern uint32_t rcc_ppre1_frequency; +extern uint32_t rcc_ppre2_frequency; + +/* --- Function prototypes ------------------------------------------------- */ + +enum rcc_clock { + CLOCK_44MHZ, + CLOCK_48MHZ, + CLOCK_64MHZ, + CLOCK_END +}; + +typedef struct { + uint8_t pll; + uint8_t pllsrc; + uint32_t flash_config; + uint8_t hpre; + uint8_t ppre1; + uint8_t ppre2; + uint8_t power_save; + uint32_t apb1_frequency; + uint32_t apb2_frequency; +} clock_scale_t; + +extern const clock_scale_t hsi_8mhz[CLOCK_END]; + +enum osc { + PLL, HSE, HSI, LSE, LSI +}; + +#define _REG_BIT(base, bit) (((base) << 5) + (bit)) + +/* Availability in comment: + * 0: F30x + * 1: F31x + * 7: F37x + * 8: F38x + */ +enum rcc_periph_clken { + /* AHB peripherals*/ + RCC_DMA1 = _REG_BIT(0x14, 0),/*0178*/ + RCC_DMA2 = _REG_BIT(0x14, 1),/*0178*/ + RCC_SRAM = _REG_BIT(0x14, 2),/*0178*/ + RCC_FLTIF = _REG_BIT(0x14, 4),/*0178*/ + RCC_CRC = _REG_BIT(0x14, 6),/*0178*/ + RCC_GPIOA = _REG_BIT(0x14, 17),/*0178*/ + RCC_GPIOB = _REG_BIT(0x14, 18),/*0178*/ + RCC_GPIOC = _REG_BIT(0x14, 19),/*0178*/ + RCC_GPIOD = _REG_BIT(0x14, 20),/*0178*/ + RCC_GPIOE = _REG_BIT(0x14, 21),/*0178*/ + RCC_GPIOF = _REG_BIT(0x14, 22),/*0178*/ + RCC_TSC = _REG_BIT(0x14, 24),/*0178*/ + RCC_ADC12 = _REG_BIT(0x14, 28),/*01--*/ + RCC_ADC34 = _REG_BIT(0x14, 29),/*01--*/ + + /* APB2 peripherals */ + RCC_SYSCFG = _REG_BIT(0x18, 0),/*0178*/ + RCC_ADC = _REG_BIT(0x18, 9),/*--78*/ + RCC_TIM1 = _REG_BIT(0x18, 11),/*01--*/ + RCC_SPI1 = _REG_BIT(0x18, 12),/*0178*/ + RCC_TIM8 = _REG_BIT(0x18, 13),/*01--*/ + RCC_USART1 = _REG_BIT(0x18, 14),/*0178*/ + RCC_TIM15 = _REG_BIT(0x18, 16),/*0178*/ + RCC_TIM16 = _REG_BIT(0x18, 17),/*0178*/ + RCC_TIM17 = _REG_BIT(0x18, 18),/*0178*/ + RCC_TIM19 = _REG_BIT(0x18, 19),/*--78*/ + RCC_DBGMCU = _REG_BIT(0x18, 22),/*--78*/ + RCC_SDADC1 = _REG_BIT(0x18, 24),/*--78*/ + RCC_SDADC2 = _REG_BIT(0x18, 25),/*--78*/ + RCC_SDADC3 = _REG_BIT(0x18, 26),/*--78*/ + + /* APB1 peripherals */ + RCC_TIM2 = _REG_BIT(0x1C, 0),/*0178*/ + RCC_TIM3 = _REG_BIT(0x1C, 1),/*0178*/ + RCC_TIM4 = _REG_BIT(0x1C, 2),/*0178*/ + RCC_TIM5 = _REG_BIT(0x1C, 3),/*--78*/ + RCC_TIM6 = _REG_BIT(0x1C, 4),/*0178*/ + RCC_TIM7 = _REG_BIT(0x1C, 5),/*0178*/ + RCC_TIM12 = _REG_BIT(0x1C, 6),/*--78*/ + RCC_TIM13 = _REG_BIT(0x1C, 7),/*--78*/ + RCC_TIM14 = _REG_BIT(0x1C, 8),/*--78*/ + RCC_TIM18 = _REG_BIT(0x1C, 9),/*--78*/ + RCC_WWDG = _REG_BIT(0x1C, 11),/*0178*/ + RCC_SPI2 = _REG_BIT(0x1C, 14),/*0178*/ + RCC_SPI3 = _REG_BIT(0x1C, 15),/*0178*/ + RCC_USART2 = _REG_BIT(0x1C, 17),/*0178*/ + RCC_USART3 = _REG_BIT(0x1C, 18),/*0178*/ + RCC_UART4 = _REG_BIT(0x1C, 19),/*01--*/ + RCC_UART5 = _REG_BIT(0x1C, 20),/*01--*/ + RCC_I2C1 = _REG_BIT(0x1C, 21),/*0178*/ + RCC_I2C2 = _REG_BIT(0x1C, 22),/*0178*/ + RCC_USB = _REG_BIT(0x1C, 23),/*0178*/ + RCC_CAN = _REG_BIT(0x1C, 25),/*0178*/ + RCC_DAC2 = _REG_BIT(0x1C, 26),/*--78*/ + RCC_PWR = _REG_BIT(0x1C, 28),/*0178*/ + RCC_DAC = _REG_BIT(0x1C, 29),/*12--*/ + RCC_DAC1 = _REG_BIT(0x1C, 29),/*--78*/ + RCC_CEC = _REG_BIT(0x1C, 29),/*--78*/ +}; + +enum rcc_periph_rst { + /* APB2 peripherals*/ + RST_SYSCFG = _REG_BIT(0x0C, 0),/*0178*/ + RST_ADC = _REG_BIT(0x0C, 9),/*--78*/ + RST_TIM1 = _REG_BIT(0x0C, 11),/*01--*/ + RST_SPI1 = _REG_BIT(0x0C, 12),/*0178*/ + RST_TIM8 = _REG_BIT(0x0C, 13),/*01--*/ + RST_USART1 = _REG_BIT(0x0C, 14),/*0178*/ + RST_TIM15 = _REG_BIT(0x0C, 16),/*0178*/ + RST_TIM16 = _REG_BIT(0x0C, 17),/*0178*/ + RST_TIM17 = _REG_BIT(0x0C, 18),/*0178*/ + RST_TIM19 = _REG_BIT(0x0C, 19),/*--78*/ + RST_SDADC1 = _REG_BIT(0x0C, 24),/*--78*/ + RST_SDADC2 = _REG_BIT(0x0C, 25),/*--78*/ + RST_SDADC3 = _REG_BIT(0x0C, 26),/*--78*/ + + /* APB1 peripherals */ + RST_TIM2 = _REG_BIT(0x10, 0),/*0178*/ + RST_TIM3 = _REG_BIT(0x10, 1),/*0178*/ + RST_TIM4 = _REG_BIT(0x10, 2),/*0178*/ + RST_TIM5 = _REG_BIT(0x10, 3),/*--78*/ + RST_TIM6 = _REG_BIT(0x10, 4),/*0178*/ + RST_TIM7 = _REG_BIT(0x10, 5),/*0178*/ + RST_TIM12 = _REG_BIT(0x10, 6),/*--78*/ + RST_TIM13 = _REG_BIT(0x10, 7),/*--78*/ + RST_TIM14 = _REG_BIT(0x10, 8),/*--78*/ + RST_TIM18 = _REG_BIT(0x10, 9),/*--78*/ + RST_WWDG = _REG_BIT(0x10, 11),/*0178*/ + RST_SPI2 = _REG_BIT(0x10, 14),/*0178*/ + RST_SPI3 = _REG_BIT(0x10, 15),/*0178*/ + RST_USART2 = _REG_BIT(0x10, 17),/*0178*/ + RST_USART3 = _REG_BIT(0x10, 18),/*0178*/ + RST_UART4 = _REG_BIT(0x10, 19),/*01--*/ + RST_UART5 = _REG_BIT(0x10, 20),/*01--*/ + RST_I2C1 = _REG_BIT(0x10, 21),/*0178*/ + RST_I2C2 = _REG_BIT(0x10, 22),/*0178*/ + RST_USB = _REG_BIT(0x10, 23),/*0178*/ + RST_CAN = _REG_BIT(0x10, 25),/*0178*/ + RST_DAC2 = _REG_BIT(0x10, 26),/*--78*/ + RST_PWR = _REG_BIT(0x10, 28),/*0178*/ + RST_DAC = _REG_BIT(0x10, 29),/*01--*/ + RST_DAC1 = _REG_BIT(0x10, 29),/*--78*/ + RST_CEC = _REG_BIT(0x10, 30),/*--78*/ + + /* AHB peripherals */ + RST_GPIOA = _REG_BIT(0x28, 17),/*0178*/ + RST_GPIOB = _REG_BIT(0x28, 18),/*0178*/ + RST_GPIOC = _REG_BIT(0x28, 19),/*0178*/ + RST_GPIOD = _REG_BIT(0x28, 20),/*0178*/ + RST_GPIOE = _REG_BIT(0x28, 21),/*0178*/ + RST_GPIOF = _REG_BIT(0x28, 22),/*0178*/ + RST_TSC = _REG_BIT(0x28, 24),/*0178*/ + RST_ADC12 = _REG_BIT(0x28, 28),/*01--*/ + RST_ADC34 = _REG_BIT(0x28, 29),/*01--*/ + + /* BDCR[16] */ + RST_BD = _REG_BIT(0x20, 16), +}; + +#undef _REG_BIT + +#include + +BEGIN_DECLS + +void rcc_osc_ready_int_clear(enum osc osc); +void rcc_osc_ready_int_enable(enum osc osc); +void rcc_osc_ready_int_disable(enum osc osc); +int rcc_osc_ready_int_flag(enum osc osc); +void rcc_css_int_clear(void); +int rcc_css_int_flag(void); +void rcc_wait_for_osc_ready(enum osc osc); +void rcc_wait_for_osc_not_ready(enum osc osc); +void rcc_wait_for_sysclk_status(enum osc osc); +void rcc_osc_on(enum osc osc); +void rcc_osc_off(enum osc osc); +void rcc_css_enable(void); +void rcc_css_disable(void); +void rcc_osc_bypass_enable(enum osc osc); +void rcc_osc_bypass_disable(enum osc osc); +void rcc_set_sysclk_source(uint32_t clk); +void rcc_set_pll_source(uint32_t pllsrc); +void rcc_set_ppre2(uint32_t ppre2); +void rcc_set_ppre1(uint32_t ppre1); +void rcc_set_hpre(uint32_t hpre); +void rcc_set_main_pll_hsi(uint32_t pll); +uint32_t rcc_get_system_clock_source(void); +void rcc_backupdomain_reset(void); +void rcc_clock_setup_hsi(const clock_scale_t *clock); +void rcc_set_i2c_clock_hsi(uint32_t i2c); +void rcc_set_i2c_clock_sysclk(uint32_t i2c); +uint32_t rcc_get_i2c_clocks(void); +void rcc_usb_prescale_1_5(void); +void rcc_usb_prescale_1(void); + +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/rtc.h b/libopencm3/include/libopencm3/stm32/f3/rtc.h new file mode 100644 index 0000000..b982496 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/rtc.h @@ -0,0 +1,42 @@ +/** @defgroup rtc_defines RTC Defines + * + * @brief Defined Constants and Types for the STM32F3xx Real Time Clock + * + * @ingroup STM32F3xx_defines + * + * @author @htmlonly © @endhtmlonly 2014 + * Ken Sarkies + * + * @version 1.0.0 + * + * @date 13 January 2014 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2014 Ken Sarkies + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_RTC_F3_H +#define LIBOPENCM3_RTC_F3_H +/**@{*/ + +#include +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/spi.h b/libopencm3/include/libopencm3/stm32/f3/spi.h new file mode 100644 index 0000000..ad48fda --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/spi.h @@ -0,0 +1,36 @@ +/** @defgroup spi_defines SPI Defines + * + * @brief Defined Constants and Types for the STM32F3xx SPI + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 5 December 2012 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_SPI_H +#define LIBOPENCM3_SPI_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/syscfg.h b/libopencm3/include/libopencm3/stm32/f3/syscfg.h new file mode 100644 index 0000000..39733da --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/syscfg.h @@ -0,0 +1,41 @@ +/** @defgroup syscfg_defines SYSCFG Defines + * + * @ingroup STM32F3xx_defines + * + * @brief Defined Constants and Types for the STM32F3xx Sysconfig + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2013 + * Frantisek Burian + * + * @date 13 January 2014 + * + * LGPL License Terms @ref lgpl_license + * */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_SYSCFG_H +#define LIBOPENCM3_SYSCFG_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/timer.h b/libopencm3/include/libopencm3/stm32/f3/timer.h new file mode 100644 index 0000000..f9284c7 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/timer.h @@ -0,0 +1,39 @@ +/** @defgroup timer_defines Timer Defines + * + * @brief Defined Constants and Types for the STM32F3xx Timers + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 8 March 2013 + * + * @author @htmlonly © @endhtmlonly 2011 Fergus Noble + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_TIMER_H +#define LIBOPENCM3_TIMER_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f3/usart.h b/libopencm3/include/libopencm3/stm32/f3/usart.h new file mode 100644 index 0000000..8619563 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f3/usart.h @@ -0,0 +1,527 @@ +/** @defgroup usart_defines USART Defines + * + * @brief Defined Constants and Types for the STM32F3xx USART + * + * @ingroup STM32F3xx_defines + * + * @version 1.0.0 + * + * @date 5 December 2012 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_USART_H +#define LIBOPENCM3_USART_H + +#include + +/* --- USART registers ----------------------------------------------------- */ + +/* Control register 1 (USARTx_CR1) */ +#define USART_CR1(usart_base) MMIO32(usart_base + 0x00) +#define USART1_CR1 USART_CR1(USART1_BASE) +#define USART2_CR1 USART_CR1(USART2_BASE) +#define USART3_CR1 USART_CR1(USART3_BASE) +#define UART4_CR1 USART_CR1(UART4_BASE) +#define UART5_CR1 USART_CR1(UART5_BASE) + +/* Control register 2 (USARTx_CR2) */ +#define USART_CR2(usart_base) MMIO32(usart_base + 0x04) +#define USART1_CR2 USART_CR2(USART1_BASE) +#define USART2_CR2 USART_CR2(USART2_BASE) +#define USART3_CR2 USART_CR2(USART3_BASE) +#define UART4_CR2 USART_CR2(UART4_BASE) +#define UART5_CR2 USART_CR2(UART5_BASE) + +/* Control register 3 (USARTx_CR3) */ +#define USART_CR3(usart_base) MMIO32(usart_base + 0x08) +#define USART1_CR3 USART_CR3(USART1_BASE) +#define USART2_CR3 USART_CR3(USART2_BASE) +#define USART3_CR3 USART_CR3(USART3_BASE) +#define UART4_CR3 USART_CR3(UART4_BASE) +#define UART5_CR3 USART_CR3(UART5_BASE) + +/* Baud rate register (USARTx_BRR) */ +#define USART_BRR(usart_base) MMIO32(usart_base + 0x0C) +#define USART1_BRR USART_BRR(USART1_BASE) +#define USART2_BRR USART_BRR(USART2_BASE) +#define USART3_BRR USART_BRR(USART3_BASE) +#define UART4_BRR USART_BRR(UART4_BASE) +#define UART5_BRR USART_BRR(UART5_BASE) + +/* Guard time and prescaler register (USARTx_GTPR) */ +#define USART_GTPR(usart_base) MMIO32(usart_base + 0x10) +#define USART1_GTPR USART_GTPR(USART1_BASE) +#define USART2_GTPR USART_GTPR(USART2_BASE) +#define USART3_GTPR USART_GTPR(USART3_BASE) +#define UART4_GTPR USART_GTPR(UART4_BASE) +#define UART5_GTPR USART_GTPR(UART5_BASE) + +/* Receiver timeout register (USART_RTOR) */ +#define USART_RTOR(usart_base) MMIO32(usart_base + 0x14) +#define USART1_RTOR USART_RTOR(USART1_BASE) +#define USART2_RTOR USART_RTOR(USART2_BASE) +#define USART3_RTOR USART_RTOR(USART3_BASE) +#define UART4_RTOR USART_RTOR(UART4_BASE) +#define UART5_RTOR USART_RTOR(UART5_BASE) + +/* Request register (USART_RQR) */ +#define USART_RQR(usart_base) MMIO32(usart_base + 0x18) +#define USART1_RQR USART_RQR(USART1_BASE) +#define USART2_RQR USART_RQR(USART2_BASE) +#define USART3_RQR USART_RQR(USART3_BASE) +#define UART4_RQR USART_RQR(UART4_BASE) +#define UART5_RQR USART_RQR(UART5_BASE) + +/* Interrupt & status register (USART_ISR) */ +#define USART_ISR(usart_base) MMIO32(usart_base + 0x1C) +#define USART1_ISR USART_ISR(USART1_BASE) +#define USART2_ISR USART_ISR(USART2_BASE) +#define USART3_ISR USART_ISR(USART3_BASE) +#define UART4_ISR USART_ISR(UART4_BASE) +#define UART5_ISR USART_ISR(UART5_BASE) + +/* Interrupt flag clear register (USART_ICR) */ +#define USART_ICR(usart_base) MMIO32(usart_base + 0x20) +#define USART1_ICR USART_ICR(USART1_BASE) +#define USART2_ICR USART_ICR(USART2_BASE) +#define USART3_ICR USART_ICR(USART3_BASE) +#define UART4_ICR USART_ICR(UART4_BASE) +#define UART5_ICR USART_ICR(UART5_BASE) + +/* Receive data register (USART_RDR) */ +#define USART_RDR(usart_base) MMIO32(usart_base + 0x24) +#define USART1_RDR USART_RDR(USART1_BASE) +#define USART2_RDR USART_RDR(USART2_BASE) +#define USART3_RDR USART_RDR(USART3_BASE) +#define UART4_RDR USART_RDR(UART4_BASE) +#define UART5_RDR USART_RDR(UART5_BASE) + +/* Transmit data register (USART_TDR) */ +#define USART_TDR(usart_base) MMIO32(usart_base + 0x28) +#define USART1_TDR USART_TDR(USART1_BASE) +#define USART2_TDR USART_TDR(USART2_BASE) +#define USART3_TDR USART_TDR(USART3_BASE) +#define UART4_TDR USART_TDR(UART4_BASE) +#define UART5_TDR USART_TDR(UART5_BASE) + + +/* --- USART_CR1 values ---------------------------------------------------- */ + +/* EOBIE: End of Block interrupt enable */ +#define USART_CR1_EOBIE (1 << 27) + +/* RTOIE: Receiver timeout interrupt enable */ +#define USART_CR1_RTOIE (1 << 26) + +/* DEAT[4:0]: Driver Enable assertion time */ + +/* DEDT[4:0]: Driver Enable deassertion time */ + +/* OVER8: Oversampling mode */ +#define USART_CR1_OVER8 (1 << 15) + +/* CMIE: Character match interrupt enable */ +#define USART_CR1_CMIE (1 << 14) + +/* MME: Mute mode enable */ +#define USART_CR1_MME (1 << 13) + +/* M: Word length */ +#define USART_CR1_M (1 << 12) + +/* WAKE: Receiver wakeup method */ +#define USART_CR1_WAKE (1 << 11) + +/* PCE: Parity control enable */ +#define USART_CR1_PCE (1 << 10) + +/* PS: Parity selection */ +#define USART_CR1_PS (1 << 9) + +/* PEIE: PE interrupt enable */ +#define USART_CR1_PEIE (1 << 8) + +/* TXEIE: Interrupt enable */ +#define USART_CR1_TXEIE (1 << 7) + +/* TCIE: Transmission complete interrupt enable */ +#define USART_CR1_TCIE (1 << 6) + +/* RXNEIE: RXNE interrupt enable */ +#define USART_CR1_RXNEIE (1 << 5) + +/* IDLEIE: IDLE interrupt enable */ +#define USART_CR1_IDLEIE (1 << 4) + +/* TE: Transmitter enable */ +#define USART_CR1_TE (1 << 3) + +/* RE: Receiver enable */ +#define USART_CR1_RE (1 << 2) + +/* UESM: USART enable in Stop mode */ +#define USART_CR1_UESM (1 << 1) + +/* UE: USART enable */ +#define USART_CR1_UE (1 << 0) + + +/* --- USART_CR2 values ---------------------------------------------------- */ + +/* ADD[7:4]: Address of the USART node (31,28) */ +#define USART_CR2_ADD1_MASK (0xF << 28) + +/* ADD[3:0]: Address of the USART node (27,24) */ +#define USART_CR2_ADD2_MASK (0xF << 24) + +/* RTOEN: Receiver timeout enable */ +#define USART_CR2_RTOEN (1 << 23) + +/* ABRMOD[1:0]: Auto baud rate mode */ +#define USART_CR2_ABRMOD_BAUD (0x0 << 21) +#define USART_CR2_ABRMOD_FALL_EDGE (0x1 << 21) +#define USART_CR2_ABRMOD_FRAME_0x7F (0x2 << 21) +#define USART_CR2_ABRMOD_FRAME_0x55 (0x3 << 21) + +/* ABREN: Auto baud rate enable */ +#define USART_CR2_ABREN (1 << 20) + +/* MSBFIRST: Most significant bit first */ +#define USART_CR2_MSBFIRST (1 << 19) + +/* DATAINV: Binary data inversion */ +#define USART_CR2_DATAINV (1 << 18) + +/* TXINV: TX pin active level inversion */ +#define USART_CR2_TXINV (1 << 17) + +/* RXINV: RX pin active level inversion */ +#define USART_CR2_RXINV (1 << 16) + +/* SWAP: Swap TX/RX pins */ +#define USART_CR2_SWAP (1 << 15) + +/* LINEN: LIN mode enable */ +#define USART_CR2_LINEN (1 << 14) + +/* STOP[13:12]: STOP bits */ +#define USART_CR2_STOPBITS_1 (0x00 << 12) /* 1 stop bit */ +#define USART_CR2_STOPBITS_0_5 (0x01 << 12) /* 0.5 stop bits */ +#define USART_CR2_STOPBITS_2 (0x02 << 12) /* 2 stop bits */ +#define USART_CR2_STOPBITS_1_5 (0x03 << 12) /* 1.5 stop bits */ +#define USART_CR2_STOPBITS_MASK (0x03 << 12) +#define USART_CR2_STOPBITS_SHIFT 12 + +/* CLKEN: Clock enable */ +#define USART_CR2_CLKEN (1 << 11) + +/* CPOL: Clock polarity */ +#define USART_CR2_CPOL (1 << 10) + +/* CPHA: Clock phase */ +#define USART_CR2_CPHA (1 << 9) + +/* LBCL: Last bit clock pulse */ +#define USART_CR2_LBCL (1 << 8) + +/* LBDIE: LIN break detection interrupt enable */ +#define USART_CR2_LBDIE (1 << 6) + +/* LBDL: LIN break detection length */ +#define USART_CR2_LBDL (1 << 5) + +/* ADDM7:7-bit Address Detection/4-bit Address Detection */ +#define USART_CR2_ADDM7 (1 << 4) + +/* ADD[3:0]: Addres of the usart node +#define USART_CR2_ADD_MASK 0xF */ + +/* --- USART_CR3 values ---------------------------------------------------- */ + +/* WUFIE: Wakeup from Stop mode interrupt enable */ +#define USART_CR3_WUFIE (1 << 22) + +/* WUS[1:0]: Wakeup from Stop mode interrupt flag selectio */ +#define USART_CR3_WUS_ON (0x0 << 20) +/* RESERVE #define USART_CR3_WUS (0x1 << 20) */ +#define USART_CR3_WUS_START_BIT (0x2 << 20) +#define USART_CR3_WUS_RXNE (0x3 << 20) + +/* SCARCNT[2:0]: Smartcard auto-retry count */ +#define USART_CR3_SCARCNT_OFF (0x0 << 17) +/* 0x1 to 0x7: number of automatic retransmission attempts */ + +/* DEP: Driver enable polarity selection */ +#define USART_CR3_DEP (1 << 15) + +/* DEM: Driver enable mode */ +#define USART_CR3_DEM (1 << 14) + +/* DDRE: DMA Disable on Reception Error */ +#define USART_CR3_DDRE (1 << 13) + +/* OVRDIS: Overrun Disable */ +#define USART_CR3_OVRDIS (1 << 12) + +/* ONEBIT: One sample bit method enable */ +#define USART_CR3_ONEBIT (1 << 11) + +/* CTSIE: CTS interrupt enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_CTSIE (1 << 10) + +/* CTSE: CTS enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_CTSE (1 << 9) + +/* RTSE: RTS enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_RTSE (1 << 8) + +/* DMAT: DMA enable transmitter */ +/* Note: N/A on UART5 */ +#define USART_CR3_DMAT (1 << 7) + +/* DMAR: DMA enable receiver */ +/* Note: N/A on UART5 */ +#define USART_CR3_DMAR (1 << 6) + +/* SCEN: Smartcard mode enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_SCEN (1 << 5) + +/* NACK: Smartcard NACK enable */ +/* Note: N/A on UART4 & UART5 */ +#define USART_CR3_NACK (1 << 4) + +/* HDSEL: Half-duplex selection */ +#define USART_CR3_HDSEL (1 << 3) + +/* IRLP: IrDA low-power */ +#define USART_CR3_IRLP (1 << 2) + +/* IREN: IrDA mode enable */ +#define USART_CR3_IREN (1 << 1) + +/* EIE: Error interrupt enable */ +#define USART_CR3_EIE (1 << 0) + +/* --- USART_BRR values ---------------------------------------------------- */ + +/* DIV_Mantissa[11:0]: mantissa of USARTDIV */ +#define USART_BRR_DIV_MANTISSA_MASK (0xFFF << 4) +/* DIV_Fraction[3:0]: fraction of USARTDIV */ +#define USART_BRR_DIV_FRACTION_MASK 0xF + +/* --- USART_GTPR values --------------------------------------------------- */ + +/* GT[7:0]: Guard time value */ +/* Note: N/A on UART4 & UART5 */ +#define USART_GTPR_GT_MASK (0xFF << 8) + +/* PSC[7:0]: Prescaler value */ +/* Note: N/A on UART4/5 */ +#define USART_GTPR_PSC_MASK 0xFF + +/* --- USART_RTOR values --------------------------------------------------- */ + +/* XXX: Preguntar */ +/* BLEN[7:0]: Block Length */ +#define USART_RTOR_BLEN1_MASK (0xFF << 24) + +/* RTO[23:0]: Receiver timeout value */ +#define USART_RTOR_BLEN2_MASK (0xFFFF << 0) + +/* --- USART_RQR values --------------------------------------------------- */ + +/* TXFRQ: Transmit data flush request */ +#define USART_RQR_TXFRQ (1 << 4) + +/* RXFRQ: Receive data flush request */ +#define USART_RQR_RXFRQ (1 << 3) + +/* MMRQ: Mute mode request */ +#define USART_RQR_MMRQ (1 << 2) + +/* SBKRQ: Send break request */ +#define USART_RQR_SBKRQ (1 << 1) + +/* ABRRQ: Auto baud rate request */ +#define USART_RQR_ABKRQ (1 << 0) + +/* --- USART_ISR values --------------------------------------------------- */ + +/* REACK: Receive enable acknowledge flag */ +#define USART_ISR_REACK (1 << 22) + +/* TEACK: Transmit enable acknowledge flag */ +#define USART_ISR_TEACK (1 << 21) + +/* WUF: Wakeup from Stop mode flag */ +#define USART_ISR_WUF (1 << 20) + +/* RWU: Receiver wakeup from Mute mode */ +#define USART_ISR_RWU (1 << 19) + +/* SBKF: Send break flag */ +#define USART_ISR_SBKF (1 << 18) + +/* CMF: Character match flag */ +#define USART_ISR_CMF (1 << 17) + +/* BUSY: Busy flag */ +#define USART_ISR_BUSY (1 << 16) + +/* ABRF: Auto baud rate flag */ +#define USART_ISR_ABRF (1 << 15) + +/* ABRE: Auto baud rate error */ +#define USART_ISR_ABRE (1 << 14) + +/* EOBF: End of block flag */ +#define USART_ISR_EOBF (1 << 12) + +/* RTOF: Receiver timeout */ +#define USART_ISR_RTOF (1 << 11) + +/* CTS: CTS flag */ +#define USART_ISR_CTS (1 << 10) + +/* CTSIF: CTS interrupt flag */ +#define USART_ISR_CTSIF (1 << 9) + +/* LBDF: LIN break detection flag */ +#define USART_ISR_LBDF (1 << 8) + +/* TXE: Transmit data register empty */ +#define USART_ISR_TXE (1 << 7) + +/* TC: Transmission complete */ +#define USART_ISR_TC (1 << 6) + +/* RXNE: Read data register not empty */ +#define USART_ISR_RXNE (1 << 5) + +/* IDLE: Idle line detected */ +#define USART_ISR_IDLE (1 << 4) + +/* ORE: Overrun error */ +#define USART_ISR_ORE (1 << 3) + +/* NF: Noise detected flag */ +#define USART_ISR_NF (1 << 2) + +/* FE: Framing error */ +#define USART_ISR_FE (1 << 1) + +/* PE: Parity error */ +#define USART_ISR_PE (1 << 0) + +/* --- USART_SR values ----------------------------------------------------- */ +/****************************************************************************/ +/** @defgroup usart_sr_flags USART Status register Flags +@ingroup STM32F_usart_defines + +@{*/ + +/** CTS: CTS flag */ +/** @note: undefined on UART4 and UART5 */ +#define USART_SR_CTS USART_ISR_CTS + +/** LBD: LIN break detection flag */ +#define USART_SR_LBD USART_ISR_LBDF + +/** TXE: Transmit data buffer empty */ +#define USART_SR_TXE USART_ISR_TXE + +/** TC: Transmission complete */ +#define USART_SR_TC USART_ISR_TC + +/** RXNE: Read data register not empty */ +#define USART_SR_RXNE USART_ISR_RXNE + +/** IDLE: Idle line detected */ +#define USART_SR_IDLE USART_ISR_IDLE + +/** ORE: Overrun error */ +#define USART_SR_ORE USART_ISR_ORE + +/** NE: Noise error flag */ +#define USART_SR_NE USART_ISR_NF + +/** FE: Framing error */ +#define USART_SR_FE USART_ISR_FE + +/** PE: Parity error */ +#define USART_SR_PE USART_ISR_PE +/**@}*/ + +/* --- USART_ICR values --------------------------------------------------- */ + +/* WUCF: Wakeup from Stop mode clear flag */ +#define USART_ICR_WUCF (1 << 20) + +/* CMCF: Character match clear flag */ +#define USART_ICR_CMCF (1 << 17) + +/* EOBCF: End of timeout clear flag */ +#define USART_ICR_EOBCF (1 << 12) + +/* RTOCF: Receiver timeout clear flag */ +#define USART_ICR_RTOCF (1 << 11) + +/* CTSCF: CTS clear flag */ +#define USART_ICR_CTSCF (1 << 9) + +/* LBDCF: LIN break detection clear flag */ +#define USART_ICR_LBDCF (1 << 8) + +/* TCCF: Transmission complete clear flag */ +#define USART_ICR_TCCF (1 << 6) + +/* IDLECF: Idle line detected clear flag */ +#define USART_ICR_IDLECF (1 << 4) + +/* ORECF: Overrun error clear flag */ +#define USART_ICR_ORECF (1 << 3) + +/* NCF: Noise detected clear flag */ +#define USART_ICR_NCF (1 << 2) + +/* FECF: Framing error clear flag */ +#define USART_ICR_FECF (1 << 1) + +/* PECF: Parity error clear flag */ +#define USART_ICR_PECF (1 << 0) + +/* --- USART_RDR values --------------------------------------------------- */ + +/* RDR[8:0]: Receive data value */ +#define USART_RDR_MASK (0x1FF << 0) + +/* --- USART_TDR values --------------------------------------------------- */ + +/* TDR[8:0]: Transmit data value */ +#define USART_TDR_MASK (0x1FF << 0) + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f4/adc.h b/libopencm3/include/libopencm3/stm32/f4/adc.h new file mode 100644 index 0000000..56188f4 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/adc.h @@ -0,0 +1,586 @@ +/** @defgroup adc_defines ADC Defines + +@brief Defined Constants and Types for the STM32F4xx Analog to Digital +Converters + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2012 +Matthew Lai +@author @htmlonly © @endhtmlonly 2009 +Edward Cheeseman + +@date 31 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Matthew Lai + * Copyright (C) 2009 Edward Cheeseman + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_ADC_H +#define LIBOPENCM3_ADC_H + +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ +#define ADC_JOFR1(block) MMIO32(block + 0x14) +#define ADC_JOFR2(block) MMIO32(block + 0x18) +#define ADC_JOFR3(block) MMIO32(block + 0x1c) +#define ADC_JOFR4(block) MMIO32(block + 0x20) + +/* ADC watchdog high threshold register (ADC_HTR) */ +#define ADC_HTR(block) MMIO32(block + 0x24) + +/* ADC watchdog low threshold register (ADC_LTR) */ +#define ADC_LTR(block) MMIO32(block + 0x28) + +/* ADC regular sequence register 1 (ADC_SQR1) */ +#define ADC_SQR1(block) MMIO32(block + 0x2c) + +/* ADC regular sequence register 2 (ADC_SQR2) */ +#define ADC_SQR2(block) MMIO32(block + 0x30) + +/* ADC regular sequence register 3 (ADC_SQR3) */ +#define ADC_SQR3(block) MMIO32(block + 0x34) + +/* ADC injected sequence register (ADC_JSQR) */ +#define ADC_JSQR(block) MMIO32(block + 0x38) + +/* ADC injected data register x (ADC_JDRx) (x=1..4) */ +#define ADC_JDR1(block) MMIO32(block + 0x3c) +#define ADC_JDR2(block) MMIO32(block + 0x40) +#define ADC_JDR3(block) MMIO32(block + 0x44) +#define ADC_JDR4(block) MMIO32(block + 0x48) + +/* ADC regular data register (ADC_DR) */ +#define ADC_DR(block) MMIO32(block + 0x4c) + +/* ADC common (shared) registers */ +#define ADC_COMMON_REGISTERS_BASE (ADC1_BASE+0x300) +#define ADC_CSR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x0) +#define ADC_CCR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x4) +#define ADC_CDR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x8) + +/* --- ADC Channels ------------------------------------------------------- */ + +/* Thanks ST! F40x and F41x are on 16, F42x and F43x are on 18! */ +#define ADC_CHANNEL_TEMP_F40 ADC_CHANNEL16 +#define ADC_CHANNEL_TEMP_F42 ADC_CHANNEL18 +#define ADC_CHANNEL_VREFINT ADC_CHANNEL17 +#define ADC_CHANNEL_VBAT ADC_CHANNEL18 + +/* --- ADC_SR values ------------------------------------------------------- */ + +#define ADC_SR_OVR (1 << 5) + +/* --- ADC_CR1 values specific to STM32F2,4--------------------------------- */ + +/* OVRIE: Overrun interrupt enable */ +#define ADC_CR1_OVRIE (1 << 26) + +/* RES[1:0]: Resolution */ +/****************************************************************************/ +/** @defgroup adc_cr1_res ADC Resolution. +@ingroup adc_defines + +@{*/ +#define ADC_CR1_RES_12BIT (0x0 << 24) +#define ADC_CR1_RES_10BIT (0x1 << 24) +#define ADC_CR1_RES_8BIT (0x2 << 24) +#define ADC_CR1_RES_6BIT (0x3 << 24) +/**@}*/ +#define ADC_CR1_RES_MASK (0x3 << 24) +#define ADC_CR1_RES_SHIFT 24 + +/* Note: Bits [21:16] are reserved, and must be kept at reset value. */ + +/* --- ADC_CR1 values (note some of these are defined elsewhere) ----------- */ +#define ADC_CR1_AWDCH_MAX 18 + + +/* --- ADC_CR2 values ------------------------------------------------------ */ + +/* SWSTART: Start conversion of regular channels. */ +#define ADC_CR2_SWSTART (1 << 30) + +/* EXTEN[1:0]: External trigger enable for regular channels. */ +/****************************************************************************/ +/** @defgroup adc_trigger_polarity_regular ADC Trigger Polarity +@ingroup adc_defines + +@{*/ +#define ADC_CR2_EXTEN_DISABLED (0x0 << 28) +#define ADC_CR2_EXTEN_RISING_EDGE (0x1 << 28) +#define ADC_CR2_EXTEN_FALLING_EDGE (0x2 << 28) +#define ADC_CR2_EXTEN_BOTH_EDGES (0x3 << 28) +/**@}*/ +#define ADC_CR2_EXTEN_MASK (0x3 << 28) +#define ADC_CR2_EXTEN_SHIFT 28 + +/* EXTSEL[3:0]: External event selection for regular group. */ +/****************************************************************************/ +/** @defgroup adc_trigger_regular ADC Trigger Identifier for Regular group +@ingroup adc_defines + +@{*/ +/** Timer 1 Compare Output 1 */ +#define ADC_CR2_EXTSEL_TIM1_CC1 (0x0 << 24) +/** Timer 1 Compare Output 2 */ +#define ADC_CR2_EXTSEL_TIM1_CC2 (0x1 << 24) +/** Timer 1 Compare Output 3 */ +#define ADC_CR2_EXTSEL_TIM1_CC3 (0x2 << 24) +/** Timer 2 Compare Output 2 */ +#define ADC_CR2_EXTSEL_TIM2_CC2 (0x3 << 24) +/** Timer 2 Compare Output 3 */ +#define ADC_CR2_EXTSEL_TIM2_CC3 (0x4 << 24) +/** Timer 2 Compare Output 4 */ +#define ADC_CR2_EXTSEL_TIM2_CC4 (0x5 << 24) +/** Timer 2 TRGO Event */ +#define ADC_CR2_EXTSEL_TIM2_TRGO (0x6 << 24) +/** Timer 3 Compare Output 1 */ +#define ADC_CR2_EXTSEL_TIM3_CC1 (0x7 << 24) +/** Timer 3 TRGO Event */ +#define ADC_CR2_EXTSEL_TIM3_TRGO (0x8 << 24) +/** Timer 4 Compare Output 4 */ +#define ADC_CR2_EXTSEL_TIM4_CC4 (0x9 << 24) +/** Timer 5 Compare Output 1 */ +#define ADC_CR2_EXTSEL_TIM5_CC1 (0xA << 24) +/** Timer 5 Compare Output 2 */ +#define ADC_CR2_EXTSEL_TIM5_CC2 (0xB << 24) +/** Timer 5 Compare Output 3 */ +#define ADC_CR2_EXTSEL_TIM5_CC3 (0xC << 24) +/** Timer 8 Compare Output 1 */ +#define ADC_CR2_EXTSEL_TIM8_CC1 (0xD << 24) +/** Timer 8 TRGO Event */ +#define ADC_CR2_EXTSEL_TIM8_TRGO (0xE << 24) +/** EXTI Line 11 Event */ +#define ADC_CR2_EXTSEL_EXTI_LINE_11 (0xF << 24) +/**@}*/ +#define ADC_CR2_EXTSEL_MASK (0xF << 24) +#define ADC_CR2_EXTSEL_SHIFT 24 + +/* Bit 23 is reserved */ + +/* JSWSTART: Start conversion of injected channels. */ +#define ADC_CR2_JSWSTART (1 << 22) + +/* JEXTEN[1:0]: External trigger enable for injected channels. */ +/****************************************************************************/ +/** @defgroup adc_trigger_polarity_injected ADC Injected Trigger Polarity +@ingroup adc_defines + +@{*/ +#define ADC_CR2_JEXTEN_DISABLED (0x0 << 20) +#define ADC_CR2_JEXTEN_RISING_EDGE (0x1 << 20) +#define ADC_CR2_JEXTEN_FALLING_EDGE (0x2 << 20) +#define ADC_CR2_JEXTEN_BOTH_EDGES (0x3 << 20) +/**@}*/ +#define ADC_CR2_JEXTEN_MASK (0x3 << 20) +#define ADC_CR2_JEXTEN_SHIFT 20 + +/* JEXTSEL[3:0]: External event selection for injected group. */ +/****************************************************************************/ +/** @defgroup adc_trigger_injected ADC Trigger Identifier for Injected group +@ingroup adc_defines + +@{*/ +#define ADC_CR2_JEXTSEL_TIM1_CC4 (0x0 << 16) +#define ADC_CR2_JEXTSEL_TIM1_TRGO (0x1 << 16) +#define ADC_CR2_JEXTSEL_TIM2_CC1 (0x2 << 16) +#define ADC_CR2_JEXTSEL_TIM2_TRGO (0x3 << 16) +#define ADC_CR2_JEXTSEL_TIM3_CC2 (0x4 << 16) +#define ADC_CR2_JEXTSEL_TIM3_CC4 (0x5 << 16) +#define ADC_CR2_JEXTSEL_TIM4_CC1 (0x6 << 16) +#define ADC_CR2_JEXTSEL_TIM4_CC2 (0x7 << 16) +#define ADC_CR2_JEXTSEL_TIM4_CC3 (0x8 << 16) +#define ADC_CR2_JEXTSEL_TIM4_TRGO (0x9 << 16) +#define ADC_CR2_JEXTSEL_TIM5_CC4 (0xA << 16) +#define ADC_CR2_JEXTSEL_TIM5_TRGO (0xB << 16) +#define ADC_CR2_JEXTSEL_TIM8_CC2 (0xC << 16) +#define ADC_CR2_JEXTSEL_TIM8_CC3 (0xD << 16) +#define ADC_CR2_JEXTSEL_TIM8_CC4 (0xE << 16) +#define ADC_CR2_JEXTSEL_EXTI_LINE_15 (0xF << 16) +/**@}*/ +#define ADC_CR2_JEXTSEL_MASK (0xF << 16) +#define ADC_CR2_JEXTSEL_SHIFT 16 + +/* ALIGN: Data alignement. */ +#define ADC_CR2_ALIGN_RIGHT (0 << 11) +#define ADC_CR2_ALIGN_LEFT (1 << 11) +#define ADC_CR2_ALIGN (1 << 11) + +/* EOCS: End of conversion selection. */ +#define ADC_CR2_EOCS (1 << 10) + +/* DDS: DMA disable selection */ +#define ADC_CR2_DDS (1 << 9) + +/* DMA: Direct memory access mode. (ADC1 and ADC3 only!) */ +#define ADC_CR2_DMA (1 << 8) + +/* Note: Bits [7:2] are reserved and must be kept at reset value. */ + +/* CONT: Continous conversion. */ +#define ADC_CR2_CONT (1 << 1) + +/* ADON: A/D converter On/Off. */ +/* Note: If any other bit in this register apart from ADON is changed at the + * same time, then conversion is not triggered. This is to prevent triggering + * an erroneous conversion. + * Conclusion: Must be separately written. + */ +#define ADC_CR2_ADON (1 << 0) + +/* --- ADC_SMPR1 values ---------------------------------------------------- */ + +#define ADC_SMPR1_SMP17_LSB 21 +#define ADC_SMPR1_SMP16_LSB 18 +#define ADC_SMPR1_SMP15_LSB 15 +#define ADC_SMPR1_SMP14_LSB 12 +#define ADC_SMPR1_SMP13_LSB 9 +#define ADC_SMPR1_SMP12_LSB 6 +#define ADC_SMPR1_SMP11_LSB 3 +#define ADC_SMPR1_SMP10_LSB 0 +#define ADC_SMPR1_SMP17_MSK (0x7 << ADC_SMP17_LSB) +#define ADC_SMPR1_SMP16_MSK (0x7 << ADC_SMP16_LSB) +#define ADC_SMPR1_SMP15_MSK (0x7 << ADC_SMP15_LSB) +#define ADC_SMPR1_SMP14_MSK (0x7 << ADC_SMP14_LSB) +#define ADC_SMPR1_SMP13_MSK (0x7 << ADC_SMP13_LSB) +#define ADC_SMPR1_SMP12_MSK (0x7 << ADC_SMP12_LSB) +#define ADC_SMPR1_SMP11_MSK (0x7 << ADC_SMP11_LSB) +#define ADC_SMPR1_SMP10_MSK (0x7 << ADC_SMP10_LSB) + +/* --- ADC_SMPR2 values ---------------------------------------------------- */ + +#define ADC_SMPR2_SMP9_LSB 27 +#define ADC_SMPR2_SMP8_LSB 24 +#define ADC_SMPR2_SMP7_LSB 21 +#define ADC_SMPR2_SMP6_LSB 18 +#define ADC_SMPR2_SMP5_LSB 15 +#define ADC_SMPR2_SMP4_LSB 12 +#define ADC_SMPR2_SMP3_LSB 9 +#define ADC_SMPR2_SMP2_LSB 6 +#define ADC_SMPR2_SMP1_LSB 3 +#define ADC_SMPR2_SMP0_LSB 0 +#define ADC_SMPR2_SMP9_MSK (0x7 << ADC_SMP9_LSB) +#define ADC_SMPR2_SMP8_MSK (0x7 << ADC_SMP8_LSB) +#define ADC_SMPR2_SMP7_MSK (0x7 << ADC_SMP7_LSB) +#define ADC_SMPR2_SMP6_MSK (0x7 << ADC_SMP6_LSB) +#define ADC_SMPR2_SMP5_MSK (0x7 << ADC_SMP5_LSB) +#define ADC_SMPR2_SMP4_MSK (0x7 << ADC_SMP4_LSB) +#define ADC_SMPR2_SMP3_MSK (0x7 << ADC_SMP3_LSB) +#define ADC_SMPR2_SMP2_MSK (0x7 << ADC_SMP2_LSB) +#define ADC_SMPR2_SMP1_MSK (0x7 << ADC_SMP1_LSB) +#define ADC_SMPR2_SMP0_MSK (0x7 << ADC_SMP0_LSB) + +/* --- ADC_SMPRx values --------------------------------------------------- */ +/****************************************************************************/ +/* ADC_SMPRG ADC Sample Time Selection for Channels */ +/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels +@ingroup adc_defines + +@{*/ +#define ADC_SMPR_SMP_3CYC 0x0 +#define ADC_SMPR_SMP_15CYC 0x1 +#define ADC_SMPR_SMP_28CYC 0x2 +#define ADC_SMPR_SMP_56CYC 0x3 +#define ADC_SMPR_SMP_84CYC 0x4 +#define ADC_SMPR_SMP_112CYC 0x5 +#define ADC_SMPR_SMP_144CYC 0x6 +#define ADC_SMPR_SMP_480CYC 0x7 +/**@}*/ + +/* --- ADC_SQR1 values ----------------------------------------------------- */ + +#define ADC_SQR_MAX_CHANNELS_REGULAR 16 + +#define ADC_SQR1_SQ16_LSB 15 +#define ADC_SQR1_SQ15_LSB 10 +#define ADC_SQR1_SQ14_LSB 5 +#define ADC_SQR1_SQ13_LSB 0 +#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB) +#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB) +#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB) +#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB) +#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB) + +/* --- ADC_SQR2 values ----------------------------------------------------- */ + +#define ADC_SQR2_SQ12_LSB 25 +#define ADC_SQR2_SQ11_LSB 20 +#define ADC_SQR2_SQ10_LSB 15 +#define ADC_SQR2_SQ9_LSB 10 +#define ADC_SQR2_SQ8_LSB 5 +#define ADC_SQR2_SQ7_LSB 0 +#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB) +#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB) +#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB) +#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB) +#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB) +#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB) + +/* --- ADC_SQR3 values ----------------------------------------------------- */ + +#define ADC_SQR3_SQ6_LSB 25 +#define ADC_SQR3_SQ5_LSB 20 +#define ADC_SQR3_SQ4_LSB 15 +#define ADC_SQR3_SQ3_LSB 10 +#define ADC_SQR3_SQ2_LSB 5 +#define ADC_SQR3_SQ1_LSB 0 +#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB) +#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB) +#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB) +#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB) +#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB) +#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB) + +/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */ + +#define ADC_JDATA_LSB 0 +#define ADC_DATA_LSB 0 +#define ADC_JDATA_MSK (0xffff << ADC_JDATA_LSB) +#define ADC_DATA_MSK (0xffff << ADC_DA) + +/* --- Common Registers ---------------------------------------------------- */ + +/* --- ADC_CSR values (read only images) ------------------------------------ */ + +/* OVR3: Overrun ADC3. */ +#define ADC_CSR_OVR3 (1 << 21) + +/* STRT3: Regular channel start ADC3. */ +#define ADC_CSR_STRT3 (1 << 20) + +/* JSTRT3: Injected channel start ADC3. */ +#define ADC_CSR_JSTRT3 (1 << 19) + +/* JEOC3: Injected channel end of conversion ADC3. */ +#define ADC_CSR_JEOC3 (1 << 18) + +/* EOC3: Regular channel end of conversion ADC3. */ +#define ADC_CSR_EOC3 (1 << 17) + +/* EOC3: Regular channel end of conversion ADC3. */ +#define ADC_CSR_AWD3 (1 << 16) + +/* Bits 15:14 Reserved, must be kept at reset value */ + +/* OVR2: Overrun ADC2. */ +#define ADC_CSR_OVR2 (1 << 13) + +/* STRT2: Regular channel start ADC2. */ +#define ADC_CSR_STRT2 (1 << 12) + +/* JSTRT2: Injected channel start ADC2. */ +#define ADC_CSR_JSTRT2 (1 << 11) + +/* JEOC2: Injected channel end of conversion ADC2. */ +#define ADC_CSR_JEOC2 (1 << 10) + +/* EOC2: Regular channel end of conversion ADC2. */ +#define ADC_CSR_EOC2 (1 << 9) + +/* EOC2: Regular channel end of conversion ADC2. */ +#define ADC_CSR_AWD2 (1 << 8) + +/* Bits 7:6 Reserved, must be kept at reset value */ + +/* OVR1: Overrun ADC1. */ +#define ADC_CSR_OVR1 (1 << 5) + +/* STRT1: Regular channel start ADC1. */ +#define ADC_CSR_STRT1 (1 << 4) + +/* JSTRT1: Injected channel start ADC1. */ +#define ADC_CSR_JSTRT1 (1 << 3) + +/* JEOC1: Injected channel end of conversion ADC1. */ +#define ADC_CSR_JEOC1 (1 << 2) + +/* EOC1: Regular channel end of conversion ADC1. */ +#define ADC_CSR_EOC1 (1 << 1) + +/* EOC1: Regular channel end of conversion ADC1. */ +#define ADC_CSR_AWD1 (1 << 0) + +/* --- ADC_CCR values ------------------------------------------------------ */ + +/* TSVREFE: Temperature sensor and Vrefint enable. */ +#define ADC_CCR_TSVREFE (1 << 23) + +/* VBATE: VBat enable. */ +#define ADC_CCR_VBATE (1 << 22) + +/* Bit 18:21 reserved, must be kept at reset value. */ + +/* ADCPRE: ADC prescaler. */ +/****************************************************************************/ +/** @defgroup adc_ccr_adcpre ADC Prescale +@ingroup adc_defines + +@{*/ +#define ADC_CCR_ADCPRE_BY2 (0x0 << 16) +#define ADC_CCR_ADCPRE_BY4 (0x1 << 16) +#define ADC_CCR_ADCPRE_BY6 (0x2 << 16) +#define ADC_CCR_ADCPRE_BY8 (0x3 << 16) +/**@}*/ +#define ADC_CCR_ADCPRE_MASK (0x3 << 16) +#define ADC_CCR_ADCPRE_SHIFT 16 + +/* DMA: Direct memory access mode for multi ADC mode. */ +/****************************************************************************/ +/** @defgroup adc_dma_mode ADC DMA mode for multi ADC mode +@ingroup adc_defines + +@{*/ +#define ADC_CCR_DMA_DISABLE (0x0 << 14) +#define ADC_CCR_DMA_MODE_1 (0x1 << 14) +#define ADC_CCR_DMA_MODE_2 (0x2 << 14) +#define ADC_CCR_DMA_MODE_3 (0x3 << 14) +/**@}*/ +#define ADC_CCR_DMA_MASK (0x3 << 14) +#define ADC_CCR_DMA_SHIFT 14 + +/* DDS: DMA disable selection (for multi-ADC mode). */ +#define ADC_CCR_DDS (1 << 13) + +/* Bit 12 reserved, must be kept at reset value */ + +/* DELAY: Delay between 2 sampling phases. */ +/****************************************************************************/ +/** @defgroup adc_delay ADC Delay between 2 sampling phases +@ingroup adc_defines + +@{*/ +#define ADC_CCR_DELAY_5ADCCLK (0x0 << 8) +#define ADC_CCR_DELAY_6ADCCLK (0x1 << 8) +#define ADC_CCR_DELAY_7ADCCLK (0x2 << 8) +#define ADC_CCR_DELAY_8ADCCLK (0x3 << 8) +#define ADC_CCR_DELAY_9ADCCLK (0x4 << 8) +#define ADC_CCR_DELAY_10ADCCLK (0x5 << 8) +#define ADC_CCR_DELAY_11ADCCLK (0x6 << 8) +#define ADC_CCR_DELAY_12ADCCLK (0x7 << 8) +#define ADC_CCR_DELAY_13ADCCLK (0x8 << 8) +#define ADC_CCR_DELAY_14ADCCLK (0x9 << 8) +#define ADC_CCR_DELAY_15ADCCLK (0xa << 8) +#define ADC_CCR_DELAY_16ADCCLK (0xb << 8) +#define ADC_CCR_DELAY_17ADCCLK (0xc << 8) +#define ADC_CCR_DELAY_18ADCCLK (0xd << 8) +#define ADC_CCR_DELAY_19ADCCLK (0xe << 8) +#define ADC_CCR_DELAY_20ADCCLK (0xf << 8) +/**@}*/ +#define ADC_CCR_DELAY_MASK (0xf << 8) +#define ADC_CCR_DELAY_SHIFT 8 + +/* Bit 7:5 reserved, must be kept at reset value */ + +/* MULTI: Multi ADC mode selection. */ +/****************************************************************************/ +/** @defgroup adc_multi_mode ADC Multi mode selection +@ingroup adc_defines + +@{*/ + +/** All ADCs independent */ +#define ADC_CCR_MULTI_INDEPENDENT (0x00 << 0) + +/* Dual modes (ADC1 + ADC2) */ +/** + * Dual modes (ADC1 + ADC2) Combined regular simultaneous + + * injected simultaneous mode. + */ +#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_INJECTED_SIMUL (0x01 << 0) +/** + * Dual modes (ADC1 + ADC2) Combined regular simultaneous + + * alternate trigger mode. + */ +#define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_ALTERNATE_TRIG (0x02 << 0) +/** Dual modes (ADC1 + ADC2) Injected simultaneous mode only. */ +#define ADC_CCR_MULTI_DUAL_INJECTED_SIMUL (0x05 << 0) +/** Dual modes (ADC1 + ADC2) Regular simultaneous mode only. */ +#define ADC_CCR_MULTI_DUAL_REGULAR_SIMUL (0x06 << 0) +/** Dual modes (ADC1 + ADC2) Interleaved mode only. */ +#define ADC_CCR_MULTI_DUAL_INTERLEAVED (0x07 << 0) +/** Dual modes (ADC1 + ADC2) Alternate trigger mode only. */ +#define ADC_CCR_MULTI_DUAL_ALTERNATE_TRIG (0x09 << 0) + +/* Triple modes (ADC1 + ADC2 + ADC3) */ +/** + * Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + + * injected simultaneous mode. + */ +#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_INJECTED_SIMUL (0x11 << 0) +/** + * Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + + * alternate trigger mode. + */ +#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_ALTERNATE_TRIG (0x12 << 0) +/** Triple modes (ADC1 + ADC2 + ADC3) Injected simultaneous mode only. */ +#define ADC_CCR_MULTI_TRIPLE_INJECTED_SIMUL (0x15 << 0) +/** Triple modes (ADC1 + ADC2 + ADC3) Regular simultaneous mode only. */ +#define ADC_CCR_MULTI_TRIPLE_REGULAR_SIMUL (0x16 << 0) +/** Triple modes (ADC1 + ADC2 + ADC3) Interleaved mode only. */ +#define ADC_CCR_MULTI_TRIPLE_INTERLEAVED (0x17 << 0) +/** Triple modes (ADC1 + ADC2 + ADC3) Alternate trigger mode only. */ +#define ADC_CCR_MULTI_TRIPLE_ALTERNATE_TRIG (0x19 << 0) +/**@}*/ + +#define ADC_CCR_MULTI_MASK (0x1f << 0) +#define ADC_CCR_MULTI_SHIFT 0 + +/* --- ADC_CDR values ------------------------------------------------------ */ + +#define ADC_CDR_DATA2_MASK (0xffff << 16) +#define ADC_CDR_DATA2_SHIFT 16 + +#define ADC_CDR_DATA1_MASK (0xffff << 0) +#define ADC_CDR_DATA1_SHIFT 0 + +BEGIN_DECLS + +void adc_set_clk_prescale(uint32_t prescaler); +void adc_set_multi_mode(uint32_t mode); +void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, + uint32_t polarity); +void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, + uint32_t polarity); +void adc_set_resolution(uint32_t adc, uint32_t resolution); +void adc_enable_overrun_interrupt(uint32_t adc); +void adc_disable_overrun_interrupt(uint32_t adc); +bool adc_get_overrun_flag(uint32_t adc); +void adc_clear_overrun_flag(uint32_t adc); +bool adc_awd(uint32_t adc); +void adc_eoc_after_each(uint32_t adc); +void adc_eoc_after_group(uint32_t adc); +void adc_set_dma_continue(uint32_t adc); +void adc_set_dma_terminate(uint32_t adc); + +void adc_enable_temperature_sensor(void); +void adc_disable_temperature_sensor(void); + +END_DECLS + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/crc.h b/libopencm3/include/libopencm3/stm32/f4/crc.h new file mode 100644 index 0000000..ccda3a4 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/crc.h @@ -0,0 +1,38 @@ +/** @defgroup crc_defines CRC Defines + +@brief libopencm3 Defined Constants and Types for the STM32F4xx CRC +Generator + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CRC_H +#define LIBOPENCM3_CRC_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/crypto.h b/libopencm3/include/libopencm3/stm32/f4/crypto.h new file mode 100644 index 0000000..3dd433f --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/crypto.h @@ -0,0 +1,97 @@ +/** @defgroup crypto_defines CRYPTO Defines + * + * @brief Defined constants and Types for the STM32F4xx Crypto Coprocessor + * + * @ingroup STM32F4xx_defines + * + * @version 1.0.0 + * + * @date 22 Jun 2013 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CRYPTO_H +#define LIBOPENCM3_CRYPTO_H + +#include + +/**@{*/ + +/* --- CRYP registers ------------------------------------------------------ */ +/** @defgroup crypto_defines_registers Registers (for F42xx or F43xx only) + * + * @brief Register access to the CRYP controller. Registers for F42xx and 43xx + * + * @ingroup crypto_defines + */ +/**@{*/ + +/* CRYP_CSGCMCCMxR: Crypto context registers CCM mode, i=0-7*/ +#define CRYP_CSGCMCCMR(i) MMIO32(CRYP_BASE + 0x50 + (i) * 4) + +/* CRYP_CSGCMxR: Crypto context registers all modes, i=0-7*/ +#define CRYP_CSGCMR(i) MMIO32(CRYP_BASE + 0x70 + (i) * 4) + +/* --- CRYP_CR values ------------------------------------------------------ */ + +/* Only for part STM32F42xx and STM32F43xx: */ + +/* GCM_CMPH: GCM or CCM phase state */ +#define CRYP_CR_GCM_CMPH_SHIFT 16 +#define CRYP_CR_GCM_CMPH (3 << CRYP_CR_GCM_CMPH_SHIFT) +#define CRYP_CR_GCM_CMPH_INIT (0 << CRYP_CR_GCM_CMPH_SHIFT) +#define CRYP_CR_GCM_CMPH_HEADER (1 << CRYP_CR_GCM_CMPH_SHIFT) +#define CRYP_CR_GCM_CMPH_PAYLOAD (2 << CRYP_CR_GCM_CMPH_SHIFT) +#define CRYP_CR_GCM_CMPH_FINAL (3 << CRYP_CR_GCM_CMPH_SHIFT) + +/* ALGOMODE3: Algorithm mode, fourth bit */ +#define CRYP_CR_ALGOMODE3 (1 << 19) + +/**@}*/ + +/** @defgroup crypto_api API (for F42xx or F43xx only) + * + * @brief API for the CRYP controller. + * + * @warning Only for F42xx and 43xx + * + * @ingroup crypto_defines + */ +/**@{*/ + +enum crypto_mode_mac { + ENCRYPT_GCM = CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE3, + ENCRYPT_CCM = CRYP_CR_ALGOMODE_TDES_CBC | CRYP_CR_ALGOMODE3, + DECRYPT_GCM = CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE3 | + CRYP_CR_ALGODIR, + DECRYPT_CCM = CRYP_CR_ALGOMODE_TDES_CBC | CRYP_CR_ALGOMODE3 | + CRYP_CR_ALGODIR, +}; + +BEGIN_DECLS + +void crypto_context_swap(uint32_t *buf); +void crypto_set_mac_algorithm(enum crypto_mode_mac mode); + +END_DECLS +/**@}*/ +/**@}*/ +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/dac.h b/libopencm3/include/libopencm3/stm32/f4/dac.h new file mode 100644 index 0000000..f7714f3 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/dac.h @@ -0,0 +1,37 @@ +/** @defgroup dac_defines DAC Defines + +@brief Defined Constants and Types for the STM32F4xx DAC + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DAC_H +#define LIBOPENCM3_DAC_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f4/dma.h b/libopencm3/include/libopencm3/stm32/f4/dma.h new file mode 100644 index 0000000..229c64c --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/dma.h @@ -0,0 +1,37 @@ +/** @defgroup dma_defines DMA Defines + +@ingroup STM32F4xx_defines + +@brief Defined Constants and Types for the STM32F4xx DMA Controller + +@version 1.0.0 + +@date 30 November 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DMA_H +#define LIBOPENCM3_DMA_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f4/doc-stm32f4.h b/libopencm3/include/libopencm3/stm32/f4/doc-stm32f4.h new file mode 100644 index 0000000..39d7091 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/doc-stm32f4.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 STM32F4 + +@version 1.0.0 + +@date 7 September 2012 + +API documentation for ST Microelectronics STM32F4 Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup STM32F4xx STM32F4xx +Libraries for ST Microelectronics STM32F4xx series. + +@version 1.0.0 + +@date 7 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup STM32F4xx_defines STM32F4xx Defines + +@brief Defined Constants and Types for the STM32F4xx series + +@version 1.0.0 + +@date 7 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/libopencm3/include/libopencm3/stm32/f4/exti.h b/libopencm3/include/libopencm3/stm32/f4/exti.h new file mode 100644 index 0000000..727b577 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/exti.h @@ -0,0 +1,41 @@ +/** @defgroup exti_defines EXTI Defines + * + * @brief Defined Constants and Types for the STM32F4xx External Interrupts + * + * + * @ingroup STM32F4xx_defines + * + * @author @htmlonly © @endhtmlonly 2013 + * Piotr Esden-Tempski + * + * @version 1.0.0 + * + * @date 14 January 2014 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Piotr Esden-Tempski + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EXTI_H +#define LIBOPENCM3_EXTI_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/flash.h b/libopencm3/include/libopencm3/stm32/f4/flash.h new file mode 100644 index 0000000..55f8972 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/flash.h @@ -0,0 +1,37 @@ +/** @defgroup flash_defines FLASH Defines + * + * @ingroup STM32F4xx_defines + * + * @brief Defined Constants and Types for the STM32F4xx FLASH Memory + * + * @version 1.0.0 + * + * @date 14 January 2014 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_FLASH_H +#define LIBOPENCM3_FLASH_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f4/fmc.h b/libopencm3/include/libopencm3/stm32/f4/fmc.h new file mode 100644 index 0000000..4741dd3 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/fmc.h @@ -0,0 +1,247 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Chuck McManis + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_FMC_H +#define LIBOPENCM3_FMC_H + +#ifndef LIBOPENCM3_FSMC_H +error "This file should not be included directly, it is included with fsmc.h" +#endif + +/* --- Convenience macros -------------------------------------------------- */ + +#define FMC_BANK5_BASE 0xa0000000U +#define FMC_BANK6_BASE 0xb0000000U +#define FMC_BANK7_BASE 0xc0000000U +#define FMC_BANK8_BASE 0xd0000000U + +/* --- FMC registers ------------------------------------------------------ */ + +/* SDRAM Control Registers 1 .. 2 */ +#define FMC_SDCR(x) MMIO32(FSMC_BASE + 0x140 + 4 * x) +#define FMC_SDCR1 FMC_SDCR(0) +#define FMC_SDCR2 FMC_SDCR(1) + + +/* SDRAM Timing Registers 1 .. 2 */ +#define FMC_SDTR(x) MMIO32(FSMC_BASE + 0x148 + 4 * x) +#define FMC_SDTR1 FMC_SDTR(0) +#define FMC_SDTR2 FMC_SDTR(1) + +/* SDRAM Command Mode Register */ +#define FMC_SDCMR MMIO32(FSMC_BASE + (uint32_t) 0x150) + +/* SDRAM Refresh Timer Register */ +#define FMC_SDRTR MMIO32(FSMC_BASE + 0x154) + +/* SDRAM Status Register */ +#define FMC_SDSR MMIO32(FSMC_BASE + (uint32_t) 0x158) + +/* --- FMC_SDCRx values ---------------------------------------------------- */ + +/* Bits [31:15]: Reserved. */ + +/* RPIPE: Read Pipe */ +#define FMC_SDCR_RPIPE_SHIFT (1 << 13) +#define FMC_SDCR_RPIPE_MASK (3 << 13) +#define FMC_SDCR_RPIPE_NONE (0x0) /* No Delay */ +#define FMC_SDCR_RPIPE_1CLK (1 << 13) /* one clock */ +#define FMC_SDCR_RPIPE_2CLK (2 << 13) /* two clocks */ + +/* RBURST: Burst Read */ +#define FMC_SDCR_RBURST (1 << 12) + +/* SDCLK: SDRAM Clock Configuration */ +#define FMC_SDCR_SDCLK_SHIFT (1 << 10) +#define FMC_SDCR_SDCLK_MASK (3 << 10) +#define FMC_SDCR_SDCLK_DISABLE (0) +#define FMC_SDCR_SDCLK_2HCLK (2 << 10) +#define FMC_SDCR_SDCLK_3HCLK (3 << 10) + +/* WP: Write Protect */ +#define FMC_SDCR_WP_ENABLE (1 << 9) + +/* CAS: CAS Latency */ +#define FMC_SDCR_CAS_SHIFT (1 << 7) +#define FMC_SDCR_CAS_1CYC (1 << 7) +#define FMC_SDCR_CAS_2CYC (2 << 7) +#define FMC_SDCR_CAS_3CYC (3 << 7) + +/* NB: Number of Internal banks */ +#define FMC_SDCR_NB2 0 +#define FMC_SDCR_NB4 (1 << 6) + +/* MWID: Memory width */ +#define FMC_SDCR_MWID_SHIFT (1 << 4) +#define FMC_SDCR_MWID_8b (0 << 4) +#define FMC_SDCR_MWID_16b (1 << 4) +#define FMC_SDCR_MWID_32b (2 << 4) + +/* NR: Number of rows */ +#define FMC_SDCR_NR_SHIFT (1 << 2) +#define FMC_SDCR_NR_11 (0 << 2) +#define FMC_SDCR_NR_12 (1 << 2) +#define FMC_SDCR_NR_13 (2 << 2) + +/* NC: Number of Columns */ +#define FMC_SDCR_NC_SHIFT (1 << 0) +#define FMC_SDCR_NC_8 (0 << 0) +#define FMC_SDCR_NC_9 (1 << 0) +#define FMC_SDCR_NC_10 (2 << 0) +#define FMC_SDCR_NC_11 (3 << 0) + +/* --- FMC_SDTRx values --------------------------------------------------- */ + +/* Bits [31:28]: Reserved. */ + +/* TRCD: Row to Column Delay */ +#define FMC_SDTR_TRCD_SHIFT (1 << 24) +#define FMC_SDTR_TRCD_MASK (15 << 24) + +/* TRP: Row Precharge Delay */ +#define FMC_SDTR_TRP_SHIFT (1 << 20) +#define FMC_SDTR_TRP_MASK (15 << 20) + +/* TWR: Recovery Delay */ +#define FMC_SDTR_TWR_SHIFT (1 << 16) +#define FMC_SDTR_TWR_MASK (15 << 16) + +/* TRC: Row Cycle Delay */ +#define FMC_SDTR_TRC_SHIFT (1 << 12) +#define FMC_SDTR_TRC_MASK (15 << 12) + +/* TRAS: Self Refresh Time */ +#define FMC_SDTR_TRAS_SHIFT (1 << 8) +#define FMC_SDTR_TRAS_MASK (15 << 8) + +/* TXSR: Exit Self-refresh Delay */ +#define FMC_SDTR_TXSR_SHIFT (1 << 4) +#define FMC_SDTR_TXSR_MASK (15 << 4) + +/* TRMD: Load Mode Register to Active */ +#define FMC_SDTR_TMRD_SHIFT (1 << 0) +#define FMC_SDTR_TMRD_MASK (15 << 0) + +/* + * Some config bits only count in CR1 or TR1, even if you + * are just configuring bank 2, so these masks let you copy + * out those bits after you have computed values for CR2 and + * TR2 and put them into CR1 and TR1 + */ +#define FMC_SDTR_DNC_MASK ( FMC_SDTR_TRP_MASK| FMC_SDTR_TRC_MASK ) +#define FMC_SDCR_DNC_MASK ( FMC_SDCR_SDCLK_MASK |\ + FMC_SDCR_RPIPE_MASK |\ + FMC_SDCR_RBURST ) + +/* --- FMC_SDCMR values --------------------------------------------------- */ + +/* Bits [31:22]: Reserved. */ + +/* MRD: Mode Register Definition */ +#define FMC_SDCMR_MRD_SHIFT (1 << 9) +#define FMC_SDCMR_MRD_MASK (0x1fff << 9) + +/* NRFS: Number of Auto-refresh */ +#define FMC_SDCMR_NRFS_SHIFT (1 << 5) +#define FMC_SDCMR_NRFS_MASK (15 << 5) + +/* CTB1: Command Target Bank 1 */ +#define FMC_SDCMR_CTB1 (1 << 4) + +/* CTB2: Command Target Bank 2 */ +#define FMC_SDCMR_CTB2 (1 << 3) + +/* MODE: Command Mode */ +#define FMC_SDCMR_MODE_SHIFT (1 << 0) +#define FMC_SDCMR_MODE_MASK (7 << 0) +#define FMC_SDCMR_MODE_NORMAL 0 +#define FMC_SDCMR_MODE_CLOCK_CONFIG_ENA 1 +#define FMC_SDCMR_MODE_PALL 2 +#define FMC_SDCMR_MODE_AUTO_REFRESH 3 +#define FMC_SDCMR_MODE_LOAD_MODE_REGISTER 4 +#define FMC_SDCMR_MODE_SELF_REFRESH 5 +#define FMC_SDCMR_MODE_POWER_DOWN 6 + +/* --- FMC_SDRTR values ---------------------------------------------------- */ + +/* Bits [31:15]: Reserved. */ + +/* REIE: Refresh Error Interrupt Enable */ +#define FMC_SDRTR_REIE (1 << 14) + +/* COUNT: Refresh Timer Count */ +#define FMC_SDRTR_COUNT_SHIFT (1 << 1) +#define FMC_SDRTR_COUNT_MASK (0x1fff << 1) + +/* CRE: Clear Refresh Error Flag */ +#define FMC_SDRTR_CRE (1 << 0) + +/* --- FMC_SDSR values ---------------------------------------------------- */ + +/* Bits [31:6]: Reserved. */ + +/* BUSY: Set if the SDRAM is working on the command */ +#define FMC_SDSR_BUSY (1 << 5) + +/* MODES: Status modes */ +#define FMC_SDSR_MODE_NORMAL 0 +#define FMC_SDSR_MODE_SELF_REFRESH 1 +#define FMC_SDSR_MODE_POWER_DOWN 2 + +/* Mode shift */ +#define FMC_SDSR_MODE2_SHIFT ( 1 << 3) +#define FMC_SDSR_MODE1_SHIFT ( 1 << 1) + +/* RE: Refresh Error */ +#define FMC_SDSR_RE (1 << 0) + +/* Helper function for setting the timing parameters */ +struct sdram_timing { + int trcd; /* RCD Delay */ + int trp; /* RP Delay */ + int twr; /* Write Recovery Time */ + int trc; /* Row Cycle Delay */ + int tras; /* Self Refresh TIme */ + int txsr; /* Exit Self Refresh Time */ + int tmrd; /* Load to Active delay */ +}; + +/* Mode register parameters */ +#define SDRAM_MODE_BURST_LENGTH_1 ((uint16_t)0x0000) +#define SDRAM_MODE_BURST_LENGTH_2 ((uint16_t)0x0001) +#define SDRAM_MODE_BURST_LENGTH_4 ((uint16_t)0x0002) +#define SDRAM_MODE_BURST_LENGTH_8 ((uint16_t)0x0004) +#define SDRAM_MODE_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define SDRAM_MODE_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define SDRAM_MODE_CAS_LATENCY_2 ((uint16_t)0x0020) +#define SDRAM_MODE_CAS_LATENCY_3 ((uint16_t)0x0030) +#define SDRAM_MODE_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define SDRAM_MODE_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define SDRAM_MODE_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) + +enum fmc_sdram_bank { SDRAM_BANK1, SDRAM_BANK2, SDRAM_BOTH_BANKS }; +enum fmc_sdram_command { SDRAM_CLK_CONF, SDRAM_NORMAL, SDRAM_PALL, + SDRAM_AUTO_REFRESH, SDRAM_LOAD_MODE, + SDRAM_SELF_REFRESH, SDRAM_POWER_DOWN }; + +/* Send an array of timing parameters (indices above) to create SDTR register value */ +uint32_t sdram_timing(struct sdram_timing *t); +void sdram_command(enum fmc_sdram_bank bank, enum fmc_sdram_command cmd, + int autorefresh, int modereg); +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/gpio.h b/libopencm3/include/libopencm3/stm32/f4/gpio.h new file mode 100644 index 0000000..696b88b --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/gpio.h @@ -0,0 +1,37 @@ +/** @defgroup gpio_defines GPIO Defines + +@brief Defined Constants and Types for the STM32F4xx General Purpose I/O + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@date 1 July 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_GPIO_H +#define LIBOPENCM3_GPIO_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f4/hash.h b/libopencm3/include/libopencm3/stm32/f4/hash.h new file mode 100644 index 0000000..a44b374 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/hash.h @@ -0,0 +1,36 @@ +/** @defgroup hash_defines HASH Defines + +@ingroup STM32F4xx_defines + +@brief Defined Constants and Types for the STM32F4xx HASH Controller + +@version 1.0.0 + +@date 31 May 2013 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_HASH_H +#define LIBOPENCM3_HASH_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/i2c.h b/libopencm3/include/libopencm3/stm32/f4/i2c.h new file mode 100644 index 0000000..02b6a99 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/i2c.h @@ -0,0 +1,37 @@ +/** @defgroup i2c_defines I2C Defines + +@brief Defined Constants and Types for the STM32F4xx I2C + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@date 12 October 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_I2C_H +#define LIBOPENCM3_I2C_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f4/irq.json b/libopencm3/include/libopencm3/stm32/f4/irq.json new file mode 100644 index 0000000..9acf1dd --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/irq.json @@ -0,0 +1,98 @@ +{ + "irqs": [ + "nvic_wwdg", + "pvd", + "tamp_stamp", + "rtc_wkup", + "flash", + "rcc", + "exti0", + "exti1", + "exti2", + "exti3", + "exti4", + "dma1_stream0", + "dma1_stream1", + "dma1_stream2", + "dma1_stream3", + "dma1_stream4", + "dma1_stream5", + "dma1_stream6", + "adc", + "can1_tx", + "can1_rx0", + "can1_rx1", + "can1_sce", + "exti9_5", + "tim1_brk_tim9", + "tim1_up_tim10", + "tim1_trg_com_tim11", + "tim1_cc", + "tim2", + "tim3", + "tim4", + "i2c1_ev", + "i2c1_er", + "i2c2_ev", + "i2c2_er", + "spi1", + "spi2", + "usart1", + "usart2", + "usart3", + "exti15_10", + "rtc_alarm", + "usb_fs_wkup", + "tim8_brk_tim12", + "tim8_up_tim13", + "tim8_trg_com_tim14", + "tim8_cc", + "dma1_stream7", + "fsmc", + "sdio", + "tim5", + "spi3", + "uart4", + "uart5", + "tim6_dac", + "tim7", + "dma2_stream0", + "dma2_stream1", + "dma2_stream2", + "dma2_stream3", + "dma2_stream4", + "eth", + "eth_wkup", + "can2_tx", + "can2_rx0", + "can2_rx1", + "can2_sce", + "otg_fs", + "dma2_stream5", + "dma2_stream6", + "dma2_stream7", + "usart6", + "i2c3_ev", + "i2c3_er", + "otg_hs_ep1_out", + "otg_hs_ep1_in", + "otg_hs_wkup", + "otg_hs", + "dcmi", + "cryp", + "hash_rng", + "fpu", + "uart7", + "uart8", + "spi4", + "spi5", + "spi6", + "sai1", + "lcd_tft", + "lcd_tft_err", + "dma2d" + ], + "partname_humanreadable": "STM32 F4 series", + "partname_doxygen": "STM32F4", + "includeguard": "LIBOPENCM3_STM32_F4_NVIC_H" +} diff --git a/libopencm3/include/libopencm3/stm32/f4/iwdg.h b/libopencm3/include/libopencm3/stm32/f4/iwdg.h new file mode 100644 index 0000000..12f3612 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/iwdg.h @@ -0,0 +1,39 @@ +/** @defgroup iwdg_defines IWDG Defines + +@brief Defined Constants and Types for the STM32F4xx Independent Watchdog +Timer + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_IWDG_H +#define LIBOPENCM3_IWDG_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f4/memorymap.h b/libopencm3/include/libopencm3/stm32/f4/memorymap.h new file mode 100644 index 0000000..2d637eb --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/memorymap.h @@ -0,0 +1,155 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_MEMORYMAP_H +#define LIBOPENCM3_MEMORYMAP_H + +#include + +/* --- STM32F4 specific peripheral definitions ----------------------------- */ + +/* Memory map for all busses */ +#define PERIPH_BASE (0x40000000U) +#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) +#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) +#define PERIPH_BASE_AHB1 (PERIPH_BASE + 0x20000) +#define PERIPH_BASE_AHB2 0x50000000U +#define PERIPH_BASE_AHB3 0x60000000U + +/* Register boundary addresses */ + +/* APB1 */ +#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) +#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) +#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) +#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) +#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) +#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) +#define TIM12_BASE (PERIPH_BASE_APB1 + 0x1800) +#define TIM13_BASE (PERIPH_BASE_APB1 + 0x1c00) +#define TIM14_BASE (PERIPH_BASE_APB1 + 0x2000) +/* PERIPH_BASE_APB1 + 0x2400 (0x4000 2400 - 0x4000 27FF): Reserved */ +#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) +#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) +#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) +#define I2S3_EXT_BASE (PERIPH_BASE_APB1 + 0x3400) +#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) +#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) +#define I2S2_EXT_BASE (PERIPH_BASE_APB1 + 0x4000) +#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) +#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) +#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) +#define UART5_BASE (PERIPH_BASE_APB1 + 0x5000) +#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) +#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) +#define I2C3_BASE (PERIPH_BASE_APB1 + 0x5C00) +/* PERIPH_BASE_APB1 + 0x6000 (0x4000 6000 - 0x4000 63FF): Reserved */ +#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) +#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800) +/* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */ +#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) +#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) +#define UART7_BASE (PERIPH_BASE_APB1 + 0x7800) +#define UART8_BASE (PERIPH_BASE_APB1 + 0x7c00) +/* PERIPH_BASE_APB1 + 0x7800 (0x4000 8000 - 0x4000 FFFF): Reserved */ + +/* APB2 */ +#define TIM1_BASE (PERIPH_BASE_APB2 + 0x0000) +#define TIM8_BASE (PERIPH_BASE_APB2 + 0x0400) +/* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 0FFF): Reserved */ +#define USART1_BASE (PERIPH_BASE_APB2 + 0x1000) +#define USART6_BASE (PERIPH_BASE_APB2 + 0x1400) +/* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */ +#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000) +#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2100) +#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2200) +#define ADC_COMMON_BASE (PERIPH_BASE_APB2 + 0x2300) +/* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */ +#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2C00) +/* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */ +#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) +#define SPI4_BASE (PERIPH_BASE_APB2 + 0x3400) +/* PERIPH_BASE_APB2 + 0x3500 (0x4001 3500 - 0x4001 37FF): Reserved */ +#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x3800) +#define EXTI_BASE (PERIPH_BASE_APB2 + 0x3C00) +#define TIM9_BASE (PERIPH_BASE_APB2 + 0x4000) +#define TIM10_BASE (PERIPH_BASE_APB2 + 0x4400) +#define TIM11_BASE (PERIPH_BASE_APB2 + 0x4800) +/* PERIPH_BASE_APB2 + 0x4C00 (0x4001 4C00 - 0x4001 4FFF): Reserved */ +#define SPI5_BASE (PERIPH_BASE_APB2 + 0x5000) +#define SPI6_BASE (PERIPH_BASE_APB2 + 0x5400) +#define SAI1_BASE (PERIPH_BASE_APB2 + 0x5800) +#define LCD_TFT_BASE (PERIPH_BASE_APB2 + 0x6800) +/* PERIPH_BASE_APB2 + 0x6C00 (0x4001 6C00 - 0x4001 FFFF): Reserved */ + +/* AHB1 */ +#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB1 + 0x0000) +#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB1 + 0x0400) +#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB1 + 0x0800) +#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB1 + 0x0C00) +#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB1 + 0x1000) +#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB1 + 0x1400) +#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800) +#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00) +#define GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000) +/* PERIPH_BASE_AHB1 + 0x2400 (0x4002 2400 - 0x4002 2FFF): Reserved */ +#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) +/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */ +#define RCC_BASE (PERIPH_BASE_AHB1 + 0x3800) +#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB1 + 0x3C00) +#define BKPSRAM_BASE (PERIPH_BASE_AHB1 + 0x4000) +/* PERIPH_BASE_AHB1 + 0x5000 (0x4002 5000 - 0x4002 5FFF): Reserved */ +#define DMA1_BASE (PERIPH_BASE_AHB1 + 0x6000) +#define DMA2_BASE (PERIPH_BASE_AHB1 + 0x6400) +/* PERIPH_BASE_AHB1 + 0x6800 (0x4002 6800 - 0x4002 7FFF): Reserved */ +#define ETHERNET_BASE (PERIPH_BASE_AHB1 + 0x8000) +/* PERIPH_BASE_AHB1 + 0x9400 (0x4002 9400 - 0x4003 FFFF): Reserved */ +#define USB_OTG_HS_BASE (PERIPH_BASE_AHB1 + 0x20000) +/* PERIPH_BASE_AHB1 + 0x60000 (0x4008 0000 - 0x4FFF FFFF): Reserved */ + +/* AHB2 */ +#define USB_OTG_FS_BASE (PERIPH_BASE_AHB2 + 0x00000) +/* PERIPH_BASE_AHB2 + 0x40000 (0x5004 0000 - 0x5004 FFFF): Reserved */ +#define DCMI_BASE (PERIPH_BASE_AHB2 + 0x50000) +/* PERIPH_BASE_AHB2 + 0x50400 (0x5005 0400 - 0x5005 FFFF): Reserved */ +#define CRYP_BASE (PERIPH_BASE_AHB2 + 0x60000) +#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400) +/* PERIPH_BASE_AHB2 + 0x60C00 (0x5006 0C00 - 0x5006 07FF): Reserved */ +#define RNG_BASE (PERIPH_BASE_AHB2 + 0x60800) +/* PERIPH_BASE_AHB2 + 0x61000 (0x5006 1000 - 0x5FFF FFFF): Reserved */ + +/* AHB3 */ +#define FSMC_BASE (PERIPH_BASE_AHB3 + 0x40000000U) + +/* PPIB */ +#define DBGMCU_BASE (PPBI_BASE + 0x00042000) + +/* Device Electronic Signature */ +#define DESIG_FLASH_SIZE_BASE (0x1FFF7A22U) +#define DESIG_UNIQUE_ID_BASE (0x1FFF7A10U) +#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) +#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) +#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 8) + +/* ST provided factory calibration values @ 3.3V */ +#define ST_VREFINT_CAL MMIO16(0x1FFF7A2A) +#define ST_TSENSE_CAL1_30C MMIO16(0x1FFF7A2C) +#define ST_TSENSE_CAL2_110 MMIO16(0x1FFF7A2E) + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/pwr.h b/libopencm3/include/libopencm3/stm32/f4/pwr.h new file mode 100644 index 0000000..b2ff76f --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/pwr.h @@ -0,0 +1,86 @@ +/** @defgroup pwr_defines PWR Defines + +@brief Defined Constants and Types for the STM32F4xx Power Control + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2011 Stephen Caudle + +@date 4 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Stephen Caudle + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_PWR_H +#define LIBOPENCM3_PWR_H + +#include + +/* + * This file extends the common STM32 version with definitions only + * applicable to the STM32F4 series of devices. + */ + +/* --- PWR_CR values ------------------------------------------------------- */ + +/* Bits [31:15]: Reserved */ + +/* VOS: Regulator voltage scaling output selection */ +#define PWR_CR_VOS (1 << 14) + +/* Bits [13:10]: Reserved */ + +/* FPDS: Flash power down in stop mode */ +#define PWR_CR_FPDS (1 << 9) + +/* --- PWR_CSR values ------------------------------------------------------ */ + +/* Bits [31:15]: Reserved */ + +/* VOSRDY: Regulator voltage scaling output selection ready bit */ +#define PWR_CSR_VOSRDY (1 << 14) + +/* Bits [13:10]: Reserved */ + +/* BRE: Backup regulator enable */ +#define PWR_CSR_BRE (1 << 9) + +/* Bits [7:4]: Reserved */ + +/* BRR: Backup regulator ready */ +#define PWR_CSR_BRR (1 << 3) + +/* --- Function prototypes ------------------------------------------------- */ + +typedef enum { + SCALE1, + SCALE2, +} vos_scale_t; + +BEGIN_DECLS + +void pwr_set_vos_scale(vos_scale_t scale); + +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/rcc.h b/libopencm3/include/libopencm3/stm32/f4/rcc.h new file mode 100644 index 0000000..0d094f7 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/rcc.h @@ -0,0 +1,784 @@ +/** @defgroup rcc_defines RCC Defines + * + * @brief Defined Constants and Types for the STM32F4xx Reset and Clock + * Control + * + * @ingroup STM32F4xx_defines + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2009 + * Federico Ruiz-Ugalde \ + * @author @htmlonly © @endhtmlonly 2009 + * Uwe Hermann + * @author @htmlonly © @endhtmlonly 2011 + * Fergus Noble + * @author @htmlonly © @endhtmlonly 2011 + * Stephen Caudle + * + * @date 18 August 2012 + * + * LGPL License Terms @ref lgpl_license + * */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2009 Federico Ruiz-Ugalde + * Copyright (C) 2011 Fergus Noble + * Copyright (C) 2011 Stephen Caudle + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_RCC_H +#define LIBOPENCM3_RCC_H + +/* --- RCC registers ------------------------------------------------------- */ + +#define RCC_CR MMIO32(RCC_BASE + 0x00) +#define RCC_PLLCFGR MMIO32(RCC_BASE + 0x04) +#define RCC_CFGR MMIO32(RCC_BASE + 0x08) +#define RCC_CIR MMIO32(RCC_BASE + 0x0c) +#define RCC_AHB1RSTR MMIO32(RCC_BASE + 0x10) +#define RCC_AHB2RSTR MMIO32(RCC_BASE + 0x14) +#define RCC_AHB3RSTR MMIO32(RCC_BASE + 0x18) +/* RCC_BASE + 0x1c Reserved */ +#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x20) +#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x24) +/* RCC_BASE + 0x28 Reserved */ +/* RCC_BASE + 0x2c Reserved */ +#define RCC_AHB1ENR MMIO32(RCC_BASE + 0x30) +#define RCC_AHB2ENR MMIO32(RCC_BASE + 0x34) +#define RCC_AHB3ENR MMIO32(RCC_BASE + 0x38) +/* RCC_BASE + 0x3c Reserved */ +#define RCC_APB1ENR MMIO32(RCC_BASE + 0x40) +#define RCC_APB2ENR MMIO32(RCC_BASE + 0x44) +/* RCC_BASE + 0x48 Reserved */ +/* RCC_BASE + 0x4c Reserved */ +#define RCC_AHB1LPENR MMIO32(RCC_BASE + 0x50) +#define RCC_AHB2LPENR MMIO32(RCC_BASE + 0x54) +#define RCC_AHB3LPENR MMIO32(RCC_BASE + 0x58) +/* RCC_BASE + 0x5c Reserved */ +#define RCC_APB1LPENR MMIO32(RCC_BASE + 0x60) +#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x64) +/* RCC_BASE + 0x68 Reserved */ +/* RCC_BASE + 0x6c Reserved */ +#define RCC_BDCR MMIO32(RCC_BASE + 0x70) +#define RCC_CSR MMIO32(RCC_BASE + 0x74) +/* RCC_BASE + 0x78 Reserved */ +/* RCC_BASE + 0x7c Reserved */ +#define RCC_SSCGR MMIO32(RCC_BASE + 0x80) +#define RCC_PLLI2SCFGR MMIO32(RCC_BASE + 0x84) + +/* --- RCC_CR values ------------------------------------------------------- */ + +#define RCC_CR_PLLI2SRDY (1 << 27) +#define RCC_CR_PLLI2SON (1 << 26) +#define RCC_CR_PLLRDY (1 << 25) +#define RCC_CR_PLLON (1 << 24) +#define RCC_CR_CSSON (1 << 19) +#define RCC_CR_HSEBYP (1 << 18) +#define RCC_CR_HSERDY (1 << 17) +#define RCC_CR_HSEON (1 << 16) +/* HSICAL: [15:8] */ +/* HSITRIM: [7:3] */ +#define RCC_CR_HSIRDY (1 << 1) +#define RCC_CR_HSION (1 << 0) + +/* --- RCC_PLLCFGR values -------------------------------------------------- */ + +/* PLLQ: [27:24] */ +#define RCC_PLLCFGR_PLLQ_SHIFT 24 +#define RCC_PLLCFGR_PLLSRC (1 << 22) +/* PLLP: [17:16] */ +#define RCC_PLLCFGR_PLLP_SHIFT 16 +/* PLLN: [14:6] */ +#define RCC_PLLCFGR_PLLN_SHIFT 6 +/* PLLM: [5:0] */ +#define RCC_PLLCFGR_PLLM_SHIFT 0 + +/* --- RCC_CFGR values ----------------------------------------------------- */ + +/* MCO2: Microcontroller clock output 2 */ +#define RCC_CFGR_MCO2_SHIFT 30 +#define RCC_CFGR_MCO2_SYSCLK 0x0 +#define RCC_CFGR_MCO2_PLLI2S 0x1 +#define RCC_CFGR_MCO2_HSE 0x2 +#define RCC_CFGR_MCO2_PLL 0x3 + +/* MCO1/2PRE: MCO Prescalers */ +#define RCC_CFGR_MCO2PRE_SHIFT 27 +#define RCC_CFGR_MCO1PRE_SHIFT 24 +#define RCC_CFGR_MCOPRE_DIV_NONE 0x0 +#define RCC_CFGR_MCOPRE_DIV_2 0x4 +#define RCC_CFGR_MCOPRE_DIV_3 0x5 +#define RCC_CFGR_MCOPRE_DIV_4 0x6 +#define RCC_CFGR_MCOPRE_DIV_5 0x7 + +/* I2SSRC: I2S clock selection */ +#define RCC_CFGR_I2SSRC (1 << 23) + +/* MCO1: Microcontroller clock output 1 */ +#define RCC_CFGR_MCO1_SHIFT 21 +#define RCC_CFGR_MCO1_HSI 0x0 +#define RCC_CFGR_MCO1_LSE 0x1 +#define RCC_CFGR_MCO1_HSE 0x2 +#define RCC_CFGR_MCO1_PLL 0x3 + +/* RTCPRE: HSE division factor for RTC clock */ +#define RCC_CFGR_RTCPRE_SHIFT 21 + +/* PPRE1/2: APB high-speed prescalers */ +#define RCC_CFGR_PPRE2_SHIFT 13 +#define RCC_CFGR_PPRE1_SHIFT 10 +#define RCC_CFGR_PPRE_DIV_NONE 0x0 +#define RCC_CFGR_PPRE_DIV_2 0x4 +#define RCC_CFGR_PPRE_DIV_4 0x5 +#define RCC_CFGR_PPRE_DIV_8 0x6 +#define RCC_CFGR_PPRE_DIV_16 0x7 + +/* HPRE: AHB high-speed prescaler */ +#define RCC_CFGR_HPRE_SHIFT 4 +#define RCC_CFGR_HPRE_DIV_NONE 0x0 +#define RCC_CFGR_HPRE_DIV_2 (0x8 + 0) +#define RCC_CFGR_HPRE_DIV_4 (0x8 + 1) +#define RCC_CFGR_HPRE_DIV_8 (0x8 + 2) +#define RCC_CFGR_HPRE_DIV_16 (0x8 + 3) +#define RCC_CFGR_HPRE_DIV_64 (0x8 + 4) +#define RCC_CFGR_HPRE_DIV_128 (0x8 + 5) +#define RCC_CFGR_HPRE_DIV_256 (0x8 + 6) +#define RCC_CFGR_HPRE_DIV_512 (0x8 + 7) + +/* SWS: System clock switch status */ +#define RCC_CFGR_SWS_SHIFT 2 +#define RCC_CFGR_SWS_HSI 0x0 +#define RCC_CFGR_SWS_HSE 0x1 +#define RCC_CFGR_SWS_PLL 0x2 + +/* SW: System clock switch */ +#define RCC_CFGR_SW_SHIFT 0 +#define RCC_CFGR_SW_HSI 0x0 +#define RCC_CFGR_SW_HSE 0x1 +#define RCC_CFGR_SW_PLL 0x2 + +/* --- RCC_CIR values ------------------------------------------------------ */ + +/* Clock security system interrupt clear bit */ +#define RCC_CIR_CSSC (1 << 23) + +/* OSC ready interrupt clear bits */ +#define RCC_CIR_PLLI2SRDYC (1 << 21) +#define RCC_CIR_PLLRDYC (1 << 20) +#define RCC_CIR_HSERDYC (1 << 19) +#define RCC_CIR_HSIRDYC (1 << 18) +#define RCC_CIR_LSERDYC (1 << 17) +#define RCC_CIR_LSIRDYC (1 << 16) + +/* OSC ready interrupt enable bits */ +#define RCC_CIR_PLLI2SRDYIE (1 << 13) +#define RCC_CIR_PLLRDYIE (1 << 12) +#define RCC_CIR_HSERDYIE (1 << 11) +#define RCC_CIR_HSIRDYIE (1 << 10) +#define RCC_CIR_LSERDYIE (1 << 9) +#define RCC_CIR_LSIRDYIE (1 << 8) + +/* Clock security system interrupt flag bit */ +#define RCC_CIR_CSSF (1 << 7) + +/* OSC ready interrupt flag bits */ +#define RCC_CIR_PLLI2SRDYF (1 << 5) +#define RCC_CIR_PLLRDYF (1 << 4) +#define RCC_CIR_HSERDYF (1 << 3) +#define RCC_CIR_HSIRDYF (1 << 2) +#define RCC_CIR_LSERDYF (1 << 1) +#define RCC_CIR_LSIRDYF (1 << 0) + +/* --- RCC_AHB1RSTR values ------------------------------------------------- */ + +#define RCC_AHB1RSTR_OTGHSRST (1 << 29) +#define RCC_AHB1RSTR_ETHMACRST (1 << 25) +#define RCC_AHB1RSTR_DMA2RST (1 << 22) +#define RCC_AHB1RSTR_DMA1RST (1 << 21) +#define RCC_AHB1RSTR_CRCRST (1 << 12) +#define RCC_AHB1RSTR_IOPIRST (1 << 8) +#define RCC_AHB1RSTR_IOPHRST (1 << 7) +#define RCC_AHB1RSTR_IOPGRST (1 << 6) +#define RCC_AHB1RSTR_IOPFRST (1 << 5) +#define RCC_AHB1RSTR_IOPERST (1 << 4) +#define RCC_AHB1RSTR_IOPDRST (1 << 3) +#define RCC_AHB1RSTR_IOPCRST (1 << 2) +#define RCC_AHB1RSTR_IOPBRST (1 << 1) +#define RCC_AHB1RSTR_IOPARST (1 << 0) + +/* --- RCC_AHB2RSTR values ------------------------------------------------- */ + +#define RCC_AHB2RSTR_OTGFSRST (1 << 7) +#define RCC_AHB2RSTR_RNGRST (1 << 6) +#define RCC_AHB2RSTR_HASHRST (1 << 5) +#define RCC_AHB2RSTR_CRYPRST (1 << 4) +#define RCC_AHB2RSTR_DCMIRST (1 << 0) + +/* --- RCC_AHB3RSTR values ------------------------------------------------- */ + +#define RCC_AHB3RSTR_FSMCRST (1 << 0) + +/* --- RCC_APB1RSTR values ------------------------------------------------- */ + +#define RCC_APB1RSTR_DACRST (1 << 29) +#define RCC_APB1RSTR_PWRRST (1 << 28) +#define RCC_APB1RSTR_CAN2RST (1 << 26) +#define RCC_APB1RSTR_CAN1RST (1 << 25) +#define RCC_APB1RSTR_I2C3RST (1 << 23) +#define RCC_APB1RSTR_I2C2RST (1 << 22) +#define RCC_APB1RSTR_I2C1RST (1 << 21) +#define RCC_APB1RSTR_UART5RST (1 << 20) +#define RCC_APB1RSTR_UART4RST (1 << 19) +#define RCC_APB1RSTR_USART3RST (1 << 18) +#define RCC_APB1RSTR_USART2RST (1 << 17) +#define RCC_APB1RSTR_SPI3RST (1 << 15) +#define RCC_APB1RSTR_SPI2RST (1 << 14) +#define RCC_APB1RSTR_WWDGRST (1 << 11) +#define RCC_APB1RSTR_TIM14RST (1 << 8) +#define RCC_APB1RSTR_TIM13RST (1 << 7) +#define RCC_APB1RSTR_TIM12RST (1 << 6) +#define RCC_APB1RSTR_TIM7RST (1 << 5) +#define RCC_APB1RSTR_TIM6RST (1 << 4) +#define RCC_APB1RSTR_TIM5RST (1 << 3) +#define RCC_APB1RSTR_TIM4RST (1 << 2) +#define RCC_APB1RSTR_TIM3RST (1 << 1) +#define RCC_APB1RSTR_TIM2RST (1 << 0) + +/* --- RCC_APB2RSTR values ------------------------------------------------- */ + +#define RCC_APB2RSTR_TIM11RST (1 << 18) +#define RCC_APB2RSTR_TIM10RST (1 << 17) +#define RCC_APB2RSTR_TIM9RST (1 << 16) +#define RCC_APB2RSTR_SYSCFGRST (1 << 14) +#define RCC_APB2RSTR_SPI1RST (1 << 12) +#define RCC_APB2RSTR_SDIORST (1 << 11) +#define RCC_APB2RSTR_ADCRST (1 << 8) +#define RCC_APB2RSTR_USART6RST (1 << 5) +#define RCC_APB2RSTR_USART1RST (1 << 4) +#define RCC_APB2RSTR_TIM8RST (1 << 1) +#define RCC_APB2RSTR_TIM1RST (1 << 0) + +/* --- RCC_AHB1ENR values ------------------------------------------------- */ + +#define RCC_AHB1ENR_OTGHSULPIEN (1 << 30) +#define RCC_AHB1ENR_OTGHSEN (1 << 29) +#define RCC_AHB1ENR_ETHMACPTPEN (1 << 28) +#define RCC_AHB1ENR_ETHMACRXEN (1 << 27) +#define RCC_AHB1ENR_ETHMACTXEN (1 << 26) +#define RCC_AHB1ENR_ETHMACEN (1 << 25) +#define RCC_AHB1ENR_DMA2EN (1 << 22) +#define RCC_AHB1ENR_DMA1EN (1 << 21) +#define RCC_AHB1ENR_BKPSRAMEN (1 << 18) +#define RCC_AHB1ENR_CRCEN (1 << 12) +#define RCC_AHB1ENR_IOPIEN (1 << 8) +#define RCC_AHB1ENR_IOPHEN (1 << 7) +#define RCC_AHB1ENR_IOPGEN (1 << 6) +#define RCC_AHB1ENR_IOPFEN (1 << 5) +#define RCC_AHB1ENR_IOPEEN (1 << 4) +#define RCC_AHB1ENR_IOPDEN (1 << 3) +#define RCC_AHB1ENR_IOPCEN (1 << 2) +#define RCC_AHB1ENR_IOPBEN (1 << 1) +#define RCC_AHB1ENR_IOPAEN (1 << 0) + +/* --- RCC_AHB2ENR values ------------------------------------------------- */ + +#define RCC_AHB2ENR_OTGFSEN (1 << 7) +#define RCC_AHB2ENR_RNGEN (1 << 6) +#define RCC_AHB2ENR_HASHEN (1 << 5) +#define RCC_AHB2ENR_CRYPEN (1 << 4) +#define RCC_AHB2ENR_DCMIEN (1 << 0) + +/* --- RCC_AHB3ENR values ------------------------------------------------- */ + +#define RCC_AHB3ENR_FSMCEN (1 << 0) +/* Alternate now that F429 has DRAM controller as well */ +#define RCC_AHB3ENR_FMCEN (1 << 0) + +/* --- RCC_APB1ENR values ------------------------------------------------- */ + +#define RCC_APB1ENR_UART8EN (1 << 31) +#define RCC_APB1ENR_UART7EN (1 << 30) +#define RCC_APB1ENR_DACEN (1 << 29) +#define RCC_APB1ENR_PWREN (1 << 28) +#define RCC_APB1ENR_CAN2EN (1 << 26) +#define RCC_APB1ENR_CAN1EN (1 << 25) +#define RCC_APB1ENR_I2C3EN (1 << 23) +#define RCC_APB1ENR_I2C2EN (1 << 22) +#define RCC_APB1ENR_I2C1EN (1 << 21) +#define RCC_APB1ENR_UART5EN (1 << 20) +#define RCC_APB1ENR_UART4EN (1 << 19) +#define RCC_APB1ENR_USART3EN (1 << 18) +#define RCC_APB1ENR_USART2EN (1 << 17) +#define RCC_APB1ENR_SPI3EN (1 << 15) +#define RCC_APB1ENR_SPI2EN (1 << 14) +#define RCC_APB1ENR_WWDGEN (1 << 11) +#define RCC_APB1ENR_TIM14EN (1 << 8) +#define RCC_APB1ENR_TIM13EN (1 << 7) +#define RCC_APB1ENR_TIM12EN (1 << 6) +#define RCC_APB1ENR_TIM7EN (1 << 5) +#define RCC_APB1ENR_TIM6EN (1 << 4) +#define RCC_APB1ENR_TIM5EN (1 << 3) +#define RCC_APB1ENR_TIM4EN (1 << 2) +#define RCC_APB1ENR_TIM3EN (1 << 1) +#define RCC_APB1ENR_TIM2EN (1 << 0) + +/* --- RCC_APB2ENR values ------------------------------------------------- */ + +#define RCC_APB2ENR_SPI6EN (1 << 21) +#define RCC_APB2ENR_SPI5EN (1 << 20) +#define RCC_APB2ENR_TIM11EN (1 << 18) +#define RCC_APB2ENR_TIM10EN (1 << 17) +#define RCC_APB2ENR_TIM9EN (1 << 16) +#define RCC_APB2ENR_SYSCFGEN (1 << 14) +#define RCC_APB2ENR_SPI4EN (1 << 13) +#define RCC_APB2ENR_SPI1EN (1 << 12) +#define RCC_APB2ENR_SDIOEN (1 << 11) +#define RCC_APB2ENR_ADC3EN (1 << 10) +#define RCC_APB2ENR_ADC2EN (1 << 9) +#define RCC_APB2ENR_ADC1EN (1 << 8) +#define RCC_APB2ENR_USART6EN (1 << 5) +#define RCC_APB2ENR_USART1EN (1 << 4) +#define RCC_APB2ENR_TIM8EN (1 << 1) +#define RCC_APB2ENR_TIM1EN (1 << 0) + +/* --- RCC_AHB1LPENR values ------------------------------------------------- */ + +#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30) +#define RCC_AHB1LPENR_OTGHSLPEN (1 << 29) +#define RCC_AHB1LPENR_ETHMACPTPLPEN (1 << 28) +#define RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27) +#define RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26) +#define RCC_AHB1LPENR_ETHMACLPEN (1 << 25) +#define RCC_AHB1LPENR_DMA2LPEN (1 << 22) +#define RCC_AHB1LPENR_DMA1LPEN (1 << 21) +#define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18) +#define RCC_AHB1LPENR_SRAM2LPEN (1 << 17) +#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) +#define RCC_AHB1LPENR_FLITFLPEN (1 << 15) +#define RCC_AHB1LPENR_CRCLPEN (1 << 12) +#define RCC_AHB1LPENR_IOPILPEN (1 << 8) +#define RCC_AHB1LPENR_IOPHLPEN (1 << 7) +#define RCC_AHB1LPENR_IOPGLPEN (1 << 6) +#define RCC_AHB1LPENR_IOPFLPEN (1 << 5) +#define RCC_AHB1LPENR_IOPELPEN (1 << 4) +#define RCC_AHB1LPENR_IOPDLPEN (1 << 3) +#define RCC_AHB1LPENR_IOPCLPEN (1 << 2) +#define RCC_AHB1LPENR_IOPBLPEN (1 << 1) +#define RCC_AHB1LPENR_IOPALPEN (1 << 0) + +/* --- RCC_AHB2LPENR values ------------------------------------------------- */ + +#define RCC_AHB2LPENR_OTGFSLPEN (1 << 7) +#define RCC_AHB2LPENR_RNGLPEN (1 << 6) +#define RCC_AHB2LPENR_HASHLPEN (1 << 5) +#define RCC_AHB2LPENR_CRYPLPEN (1 << 4) +#define RCC_AHB2LPENR_DCMILPEN (1 << 0) + +/* --- RCC_AHB3LPENR values ------------------------------------------------- */ + +#define RCC_AHB3LPENR_FSMCLPEN (1 << 0) + +/* --- RCC_APB1LPENR values ------------------------------------------------- */ + +#define RCC_APB1LPENR_DACLPEN (1 << 29) +#define RCC_APB1LPENR_PWRLPEN (1 << 28) +#define RCC_APB1LPENR_CAN2LPEN (1 << 26) +#define RCC_APB1LPENR_CAN1LPEN (1 << 25) +#define RCC_APB1LPENR_I2C3LPEN (1 << 23) +#define RCC_APB1LPENR_I2C2LPEN (1 << 22) +#define RCC_APB1LPENR_I2C1LPEN (1 << 21) +#define RCC_APB1LPENR_UART5LPEN (1 << 20) +#define RCC_APB1LPENR_UART4LPEN (1 << 19) +#define RCC_APB1LPENR_USART3LPEN (1 << 18) +#define RCC_APB1LPENR_USART2LPEN (1 << 17) +#define RCC_APB1LPENR_SPI3LPEN (1 << 15) +#define RCC_APB1LPENR_SPI2LPEN (1 << 14) +#define RCC_APB1LPENR_WWDGLPEN (1 << 11) +#define RCC_APB1LPENR_TIM14LPEN (1 << 8) +#define RCC_APB1LPENR_TIM13LPEN (1 << 7) +#define RCC_APB1LPENR_TIM12LPEN (1 << 6) +#define RCC_APB1LPENR_TIM7LPEN (1 << 5) +#define RCC_APB1LPENR_TIM6LPEN (1 << 4) +#define RCC_APB1LPENR_TIM5LPEN (1 << 3) +#define RCC_APB1LPENR_TIM4LPEN (1 << 2) +#define RCC_APB1LPENR_TIM3LPEN (1 << 1) +#define RCC_APB1LPENR_TIM2LPEN (1 << 0) + +/* --- RCC_APB2LPENR values ------------------------------------------------- */ + +#define RCC_APB2LPENR_TIM11LPEN (1 << 18) +#define RCC_APB2LPENR_TIM10LPEN (1 << 17) +#define RCC_APB2LPENR_TIM9LPEN (1 << 16) +#define RCC_APB2LPENR_SYSCFGLPEN (1 << 14) +#define RCC_APB2LPENR_SPI1LPEN (1 << 12) +#define RCC_APB2LPENR_SDIOLPEN (1 << 11) +#define RCC_APB2LPENR_ADC3LPEN (1 << 10) +#define RCC_APB2LPENR_ADC2LPEN (1 << 9) +#define RCC_APB2LPENR_ADC1LPEN (1 << 8) +#define RCC_APB2LPENR_USART6LPEN (1 << 5) +#define RCC_APB2LPENR_USART1LPEN (1 << 4) +#define RCC_APB2LPENR_TIM8LPEN (1 << 1) +#define RCC_APB2LPENR_TIM1LPEN (1 << 0) + +/* --- RCC_BDCR values ----------------------------------------------------- */ + +#define RCC_BDCR_BDRST (1 << 16) +#define RCC_BDCR_RTCEN (1 << 15) +/* RCC_BDCR[9:8]: RTCSEL */ +#define RCC_BDCR_LSEBYP (1 << 2) +#define RCC_BDCR_LSERDY (1 << 1) +#define RCC_BDCR_LSEON (1 << 0) + +/* --- RCC_CSR values ------------------------------------------------------ */ + +#define RCC_CSR_LPWRRSTF (1 << 31) +#define RCC_CSR_WWDGRSTF (1 << 30) +#define RCC_CSR_IWDGRSTF (1 << 29) +#define RCC_CSR_SFTRSTF (1 << 28) +#define RCC_CSR_PORRSTF (1 << 27) +#define RCC_CSR_PINRSTF (1 << 26) +#define RCC_CSR_BORRSTF (1 << 25) +#define RCC_CSR_RMVF (1 << 24) +#define RCC_CSR_LSIRDY (1 << 1) +#define RCC_CSR_LSION (1 << 0) + +/* --- RCC_SSCGR values ---------------------------------------------------- */ + +/* PLL spread spectrum clock generation documented in Datasheet. */ + +#define RCC_SSCGR_SSCGEN (1 << 31) +#define RCC_SSCGR_SPREADSEL (1 << 30) +/* RCC_SSCGR[27:16]: INCSTEP */ +#define RCC_SSCGR_INCSTEP_SHIFT 16 +/* RCC_SSCGR[15:0]: MODPER */ +#define RCC_SSCGR_MODPER_SHIFT 15 + +/* --- RCC_PLLI2SCFGR values ----------------------------------------------- */ + +/* RCC_PLLI2SCFGR[30:28]: PLLI2SR */ +#define RCC_PLLI2SCFGR_PLLI2SR_SHIFT 28 +/* RCC_PLLI2SCFGR[14:6]: PLLI2SN */ +#define RCC_PLLI2SCFGR_PLLI2SN_SHIFT 6 + +/* --- Variable definitions ------------------------------------------------ */ +extern uint32_t rcc_ppre1_frequency; +extern uint32_t rcc_ppre2_frequency; + +/* --- Function prototypes ------------------------------------------------- */ + +typedef enum { + CLOCK_3V3_48MHZ, + CLOCK_3V3_120MHZ, + CLOCK_3V3_168MHZ, + CLOCK_3V3_END +} clock_3v3_t; + +typedef struct { + uint8_t pllm; + uint16_t plln; + uint8_t pllp; + uint8_t pllq; + uint32_t flash_config; + uint8_t hpre; + uint8_t ppre1; + uint8_t ppre2; + uint8_t power_save; + uint32_t apb1_frequency; + uint32_t apb2_frequency; +} clock_scale_t; + +extern const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END]; +extern const clock_scale_t hse_12mhz_3v3[CLOCK_3V3_END]; +extern const clock_scale_t hse_16mhz_3v3[CLOCK_3V3_END]; + +enum rcc_osc { + PLL, HSE, HSI, LSE, LSI +}; + +#define _REG_BIT(base, bit) (((base) << 5) + (bit)) + +enum rcc_periph_clken { + /* AHB1 peripherals*/ + RCC_GPIOA = _REG_BIT(0x30, 0), + RCC_GPIOB = _REG_BIT(0x30, 1), + RCC_GPIOC = _REG_BIT(0x30, 2), + RCC_GPIOD = _REG_BIT(0x30, 3), + RCC_GPIOE = _REG_BIT(0x30, 4), + RCC_GPIOF = _REG_BIT(0x30, 5), + RCC_GPIOG = _REG_BIT(0x30, 6), + RCC_GPIOH = _REG_BIT(0x30, 7), + RCC_GPIOI = _REG_BIT(0x30, 8), + RCC_CRC = _REG_BIT(0x30, 12), + RCC_BKPSRAM = _REG_BIT(0x30, 18), + RCC_CCMDATARAM = _REG_BIT(0x30, 20), + RCC_DMA1 = _REG_BIT(0x30, 21), + RCC_DMA2 = _REG_BIT(0x30, 22), + RCC_ETHMAC = _REG_BIT(0x30, 25), + RCC_ETHMACTX = _REG_BIT(0x30, 26), + RCC_ETHMACRX = _REG_BIT(0x30, 27), + RCC_ETHMACPTP = _REG_BIT(0x30, 28), + RCC_OTGHS = _REG_BIT(0x30, 29), + RCC_OTGHSULPI = _REG_BIT(0x30, 30), + + /* AHB2 peripherals */ + RCC_DCMI = _REG_BIT(0x34, 0), + RCC_CRYP = _REG_BIT(0x34, 4), + RCC_HASH = _REG_BIT(0x34, 5), + RCC_RNG = _REG_BIT(0x34, 6), + RCC_OTGFS = _REG_BIT(0x34, 7), + + /* AHB3 peripherals */ + RCC_FSMC = _REG_BIT(0x38, 0), + + /* APB1 peripherals*/ + RCC_TIM2 = _REG_BIT(0x40, 0), + RCC_TIM3 = _REG_BIT(0x40, 1), + RCC_TIM4 = _REG_BIT(0x40, 2), + RCC_TIM5 = _REG_BIT(0x40, 3), + RCC_TIM6 = _REG_BIT(0x40, 4), + RCC_TIM7 = _REG_BIT(0x40, 5), + RCC_TIM12 = _REG_BIT(0x40, 6), + RCC_TIM13 = _REG_BIT(0x40, 7), + RCC_TIM14 = _REG_BIT(0x40, 8), + RCC_WWDG = _REG_BIT(0x40, 11), + RCC_SPI2 = _REG_BIT(0x40, 14), + RCC_SPI3 = _REG_BIT(0x40, 15), + RCC_USART2 = _REG_BIT(0x40, 17), + RCC_USART3 = _REG_BIT(0x40, 18), + RCC_UART4 = _REG_BIT(0x40, 19), + RCC_UART5 = _REG_BIT(0x40, 20), + RCC_I2C1 = _REG_BIT(0x40, 21), + RCC_I2C2 = _REG_BIT(0x40, 22), + RCC_I2C3 = _REG_BIT(0x40, 23), + RCC_CAN1 = _REG_BIT(0x40, 25), + RCC_CAN2 = _REG_BIT(0x40, 26), + RCC_PWR = _REG_BIT(0x40, 28), + RCC_DAC = _REG_BIT(0x40, 29), + RCC_UART7 = _REG_BIT(0x40, 30),/* F2xx, F3xx */ + RCC_UART8 = _REG_BIT(0x40, 31),/* F2xx, F3xx */ + + /* APB2 peripherals */ + RCC_TIM1 = _REG_BIT(0x44, 0), + RCC_TIM8 = _REG_BIT(0x44, 1), + RCC_USART1 = _REG_BIT(0x44, 4), + RCC_USART6 = _REG_BIT(0x44, 5), + RCC_ADC1 = _REG_BIT(0x44, 8), + RCC_ADC2 = _REG_BIT(0x44, 9), + RCC_ADC3 = _REG_BIT(0x44, 10), + RCC_SDIO = _REG_BIT(0x44, 11), + RCC_SPI1 = _REG_BIT(0x44, 12), + RCC_SPI4 = _REG_BIT(0x44, 13),/* F2xx, F3xx */ + RCC_SYSCFG = _REG_BIT(0x44, 14), + RCC_TIM9 = _REG_BIT(0x44, 16), + RCC_TIM10 = _REG_BIT(0x44, 17), + RCC_TIM11 = _REG_BIT(0x44, 18), + RCC_SPI5 = _REG_BIT(0x44, 20),/* F2xx, F3xx */ + RCC_SPI6 = _REG_BIT(0x44, 21),/* F2xx, F3xx */ + + /* BDCR */ + RCC_RTC = _REG_BIT(0x70, 15), + + /* AHB1 peripherals*/ + SCC_GPIOA = _REG_BIT(0x50, 0), + SCC_GPIOB = _REG_BIT(0x50, 1), + SCC_GPIOC = _REG_BIT(0x50, 2), + SCC_GPIOD = _REG_BIT(0x50, 3), + SCC_GPIOE = _REG_BIT(0x50, 4), + SCC_GPIOF = _REG_BIT(0x50, 5), + SCC_GPIOG = _REG_BIT(0x50, 6), + SCC_GPIOH = _REG_BIT(0x50, 7), + SCC_GPIOI = _REG_BIT(0x50, 8), + SCC_CRC = _REG_BIT(0x50, 12), + SCC_FLTIF = _REG_BIT(0x50, 15), + SCC_SRAM1 = _REG_BIT(0x50, 16), + SCC_SRAM2 = _REG_BIT(0x50, 17), + SCC_BKPSRAM = _REG_BIT(0x50, 18), + SCC_SRAM3 = _REG_BIT(0x50, 19),/* F2xx, F3xx */ + SCC_DMA1 = _REG_BIT(0x50, 21), + SCC_DMA2 = _REG_BIT(0x50, 22), + SCC_ETHMAC = _REG_BIT(0x50, 25), + SCC_ETHMACTX = _REG_BIT(0x50, 26), + SCC_ETHMACRX = _REG_BIT(0x50, 27), + SCC_ETHMACPTP = _REG_BIT(0x50, 28), + SCC_OTGHS = _REG_BIT(0x50, 29), + SCC_OTGHSULPI = _REG_BIT(0x50, 30), + + /* AHB2 peripherals */ + SCC_DCMI = _REG_BIT(0x54, 0), + SCC_CRYP = _REG_BIT(0x54, 4), + SCC_HASH = _REG_BIT(0x54, 5), + SCC_RNG = _REG_BIT(0x54, 6), + SCC_OTGFS = _REG_BIT(0x54, 7), + + /* AHB3 peripherals */ + SCC_FSMC = _REG_BIT(0x58, 0), + + /* APB1 peripherals*/ + SCC_TIM2 = _REG_BIT(0x60, 0), + SCC_TIM3 = _REG_BIT(0x60, 1), + SCC_TIM4 = _REG_BIT(0x60, 2), + SCC_TIM5 = _REG_BIT(0x60, 3), + SCC_TIM6 = _REG_BIT(0x60, 4), + SCC_TIM7 = _REG_BIT(0x60, 5), + SCC_TIM12 = _REG_BIT(0x60, 6), + SCC_TIM13 = _REG_BIT(0x60, 7), + SCC_TIM14 = _REG_BIT(0x60, 8), + SCC_WWDG = _REG_BIT(0x60, 11), + SCC_SPI2 = _REG_BIT(0x60, 14), + SCC_SPI3 = _REG_BIT(0x60, 15), + SCC_USART2 = _REG_BIT(0x60, 17), + SCC_USART3 = _REG_BIT(0x60, 18), + SCC_UART4 = _REG_BIT(0x60, 19), + SCC_UART5 = _REG_BIT(0x60, 20), + SCC_I2C1 = _REG_BIT(0x60, 21), + SCC_I2C2 = _REG_BIT(0x60, 22), + SCC_I2C3 = _REG_BIT(0x60, 23), + SCC_CAN1 = _REG_BIT(0x60, 25), + SCC_CAN2 = _REG_BIT(0x60, 26), + SCC_PWR = _REG_BIT(0x60, 28), + SCC_DAC = _REG_BIT(0x60, 29), + SCC_UART7 = _REG_BIT(0x60, 30),/* F2xx, F3xx */ + SCC_UART8 = _REG_BIT(0x60, 31),/* F2xx, F3xx */ + + /* APB2 peripherals */ + SCC_TIM1 = _REG_BIT(0x64, 0), + SCC_TIM8 = _REG_BIT(0x64, 1), + SCC_USART1 = _REG_BIT(0x64, 4), + SCC_USART6 = _REG_BIT(0x64, 5), + SCC_ADC1 = _REG_BIT(0x64, 8), + SCC_ADC2 = _REG_BIT(0x64, 9), + SCC_ADC3 = _REG_BIT(0x64, 10), + SCC_SDIO = _REG_BIT(0x64, 11), + SCC_SPI1 = _REG_BIT(0x64, 12), + SCC_SPI4 = _REG_BIT(0x64, 13),/* F2xx, F3xx */ + SCC_SYSCFG = _REG_BIT(0x64, 14), + SCC_TIM9 = _REG_BIT(0x64, 16), + SCC_TIM10 = _REG_BIT(0x64, 17), + SCC_TIM11 = _REG_BIT(0x64, 18), + SCC_SPI5 = _REG_BIT(0x64, 20),/* F2xx, F3xx */ + SCC_SPI6 = _REG_BIT(0x64, 21),/* F2xx, F3xx */ +}; + +enum rcc_periph_rst { + /* AHB1 peripherals*/ + RST_GPIOA = _REG_BIT(0x10, 0), + RST_GPIOB = _REG_BIT(0x10, 1), + RST_GPIOC = _REG_BIT(0x10, 2), + RST_GPIOD = _REG_BIT(0x10, 3), + RST_GPIOE = _REG_BIT(0x10, 4), + RST_GPIOF = _REG_BIT(0x10, 5), + RST_GPIOG = _REG_BIT(0x10, 6), + RST_GPIOH = _REG_BIT(0x10, 7), + RST_GPIOI = _REG_BIT(0x10, 8), + RST_CRC = _REG_BIT(0x10, 12), + RST_DMA1 = _REG_BIT(0x10, 21), + RST_DMA2 = _REG_BIT(0x10, 22), + RST_ETHMAC = _REG_BIT(0x10, 25), + RST_OTGHS = _REG_BIT(0x10, 29), + + /* AHB2 peripherals */ + RST_DCMI = _REG_BIT(0x14, 0), + RST_CRYP = _REG_BIT(0x14, 4), + RST_HASH = _REG_BIT(0x14, 5), + RST_RNG = _REG_BIT(0x14, 6), + RST_OTGFS = _REG_BIT(0x14, 7), + + /* AHB3 peripherals */ + RST_FSMC = _REG_BIT(0x18, 0), + + /* APB1 peripherals*/ + RST_TIM2 = _REG_BIT(0x20, 0), + RST_TIM3 = _REG_BIT(0x20, 1), + RST_TIM4 = _REG_BIT(0x20, 2), + RST_TIM5 = _REG_BIT(0x20, 3), + RST_TIM6 = _REG_BIT(0x20, 4), + RST_TIM7 = _REG_BIT(0x20, 5), + RST_TIM12 = _REG_BIT(0x20, 6), + RST_TIM13 = _REG_BIT(0x20, 7), + RST_TIM14 = _REG_BIT(0x20, 8), + RST_WWDG = _REG_BIT(0x20, 11), + RST_SPI2 = _REG_BIT(0x20, 14), + RST_SPI3 = _REG_BIT(0x20, 15), + RST_USART2 = _REG_BIT(0x20, 17), + RST_USART3 = _REG_BIT(0x20, 18), + RST_UART4 = _REG_BIT(0x20, 19), + RST_UART5 = _REG_BIT(0x20, 20), + RST_I2C1 = _REG_BIT(0x20, 21), + RST_I2C2 = _REG_BIT(0x20, 22), + RST_I2C3 = _REG_BIT(0x20, 23), + RST_CAN1 = _REG_BIT(0x20, 25), + RST_CAN2 = _REG_BIT(0x20, 26), + RST_PWR = _REG_BIT(0x20, 28), + RST_DAC = _REG_BIT(0x20, 29), + RST_UART7 = _REG_BIT(0x20, 30),/* F2xx, F3xx */ + RST_UART8 = _REG_BIT(0x20, 31),/* F2xx, F3xx */ + + /* APB2 peripherals */ + RST_TIM1 = _REG_BIT(0x24, 0), + RST_TIM8 = _REG_BIT(0x24, 1), + RST_USART1 = _REG_BIT(0x24, 4), + RST_USART6 = _REG_BIT(0x24, 5), + RST_ADC = _REG_BIT(0x24, 8), + RST_SDIO = _REG_BIT(0x24, 11), + RST_SPI1 = _REG_BIT(0x24, 12), + RST_SPI4 = _REG_BIT(0x24, 13),/* F2xx, F3xx */ + RST_SYSCFG = _REG_BIT(0x24, 14), + RST_TIM9 = _REG_BIT(0x24, 16), + RST_TIM10 = _REG_BIT(0x24, 17), + RST_TIM11 = _REG_BIT(0x24, 18), + RST_SPI5 = _REG_BIT(0x24, 20),/* F2xx, F3xx */ + RST_SPI6 = _REG_BIT(0x24, 21),/* F2xx, F3xx */ +}; + +#undef _REG_BIT + +#include + +BEGIN_DECLS + +void rcc_osc_ready_int_clear(enum rcc_osc osc); +void rcc_osc_ready_int_enable(enum rcc_osc osc); +void rcc_osc_ready_int_disable(enum rcc_osc osc); +int rcc_osc_ready_int_flag(enum rcc_osc osc); +void rcc_css_int_clear(void); +int rcc_css_int_flag(void); +void rcc_wait_for_osc_ready(enum rcc_osc osc); +void rcc_wait_for_sysclk_status(enum rcc_osc osc); +void rcc_osc_on(enum rcc_osc osc); +void rcc_osc_off(enum rcc_osc osc); +void rcc_css_enable(void); +void rcc_css_disable(void); +void rcc_osc_bypass_enable(enum rcc_osc osc); +void rcc_osc_bypass_disable(enum rcc_osc osc); +void rcc_set_sysclk_source(uint32_t clk); +void rcc_set_pll_source(uint32_t pllsrc); +void rcc_set_ppre2(uint32_t ppre2); +void rcc_set_ppre1(uint32_t ppre1); +void rcc_set_hpre(uint32_t hpre); +void rcc_set_rtcpre(uint32_t rtcpre); +void rcc_set_main_pll_hsi(uint32_t pllm, uint32_t plln, uint32_t pllp, + uint32_t pllq); +void rcc_set_main_pll_hse(uint32_t pllm, uint32_t plln, uint32_t pllp, + uint32_t pllq); +uint32_t rcc_system_clock_source(void); +void rcc_clock_setup_hse_3v3(const clock_scale_t *clock); + +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/rng.h b/libopencm3/include/libopencm3/stm32/f4/rng.h new file mode 100644 index 0000000..6c3def6 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/rng.h @@ -0,0 +1,23 @@ +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_RNG_H +#define LIBOPENCM3_RNG_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/rtc.h b/libopencm3/include/libopencm3/stm32/f4/rtc.h new file mode 100644 index 0000000..555efcb --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/rtc.h @@ -0,0 +1,45 @@ +/** @defgroup rtc_defines RTC Defines + +@brief Defined Constants and Types for the STM32F4xx RTC + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_RTC_H +#define LIBOPENCM3_RTC_H + +#include + +BEGIN_DECLS + +void rtc_enable_wakeup_timer(void); +void rtc_disable_wakeup_timer(void); +void rtc_enable_wakeup_timer_interrupt(void); +void rtc_disable_wakeup_timer_interrupt(void); + +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/spi.h b/libopencm3/include/libopencm3/stm32/f4/spi.h new file mode 100644 index 0000000..2ddeb12 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/spi.h @@ -0,0 +1,37 @@ +/** @defgroup spi_defines SPI Defines + +@brief Defined Constants and Types for the STM32F4xx SPI + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_SPI_H +#define LIBOPENCM3_SPI_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/f4/syscfg.h b/libopencm3/include/libopencm3/stm32/f4/syscfg.h new file mode 100644 index 0000000..5f4fba4 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/syscfg.h @@ -0,0 +1,41 @@ +/** @defgroup syscfg_defines SYSCFG Defines + * + * @ingroup STM32F4xx_defines + * + * @brief Defined Constants and Types for the STM32F4xx Sysconfig + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2013 + * Frantisek Burian + * + * @date 13 January 2014 + * + * LGPL License Terms @ref lgpl_license + * */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_SYSCFG_H +#define LIBOPENCM3_SYSCFG_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/timer.h b/libopencm3/include/libopencm3/stm32/f4/timer.h new file mode 100644 index 0000000..604a83f --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/timer.h @@ -0,0 +1,39 @@ +/** @defgroup timer_defines Timer Defines + +@brief libopencm3 Defined Constants and Types for the STM32F4xx Timers + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@date 8 March 2013 + +@author @htmlonly © @endhtmlonly 2011 Fergus Noble + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_TIMER_H +#define LIBOPENCM3_TIMER_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/f4/usart.h b/libopencm3/include/libopencm3/stm32/f4/usart.h new file mode 100644 index 0000000..1332641 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/f4/usart.h @@ -0,0 +1,37 @@ +/** @defgroup usart_defines USART Defines + +@brief Defined Constants and Types for the STM32F4xx USART + +@ingroup STM32F4xx_defines + +@version 1.0.0 + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_USART_H +#define LIBOPENCM3_USART_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/flash.h b/libopencm3/include/libopencm3/stm32/flash.h new file mode 100644 index 0000000..36132df --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/flash.h @@ -0,0 +1,38 @@ +/* This provides unification of code over STM32F subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#if defined(STM32F0) +# include +#elif defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F3) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." +#endif + diff --git a/libopencm3/include/libopencm3/stm32/fsmc.h b/libopencm3/include/libopencm3/stm32/fsmc.h new file mode 100644 index 0000000..818251c --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/fsmc.h @@ -0,0 +1,308 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Uwe Hermann + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_FSMC_H +#define LIBOPENCM3_FSMC_H + +#include +#include + +#if defined(STM32F4) +# include +#endif + +/* --- Convenience macros -------------------------------------------------- */ + +#define FSMC_BANK1_BASE 0x60000000U /* NOR / PSRAM */ +#define FSMC_BANK2_BASE 0x70000000U /* NAND flash */ +#define FSMC_BANK3_BASE 0x80000000U /* NAND flash */ +#define FSMC_BANK4_BASE 0x90000000U /* PC card */ + +/* --- FSMC registers ------------------------------------------------------ */ + +/* SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCRx) */ +#define FSMC_BCR(x) MMIO32(FSMC_BASE + 0x00 + 8 * x) +#define FSMC_BCR1 FSMC_BCR(0) +#define FSMC_BCR2 FSMC_BCR(1) +#define FSMC_BCR3 FSMC_BCR(2) +#define FSMC_BCR4 FSMC_BCR(3) + +/* SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTRx) */ +#define FSMC_BTR(x) MMIO32(FSMC_BASE + 0x04 + 8 * x) +#define FSMC_BTR1 FSMC_BTR(0) +#define FSMC_BTR2 FSMC_BTR(1) +#define FSMC_BTR3 FSMC_BTR(2) +#define FSMC_BTR4 FSMC_BTR(3) + +/* SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTRx) */ +#define FSMC_BWTR(x) MMIO32(FSMC_BASE + 0x104 + 8 * x) +#define FSMC_BWTR1 FSMC_BWTR(0) +#define FSMC_BWTR2 FSMC_BWTR(1) +#define FSMC_BWTR3 FSMC_BWTR(2) +#define FSMC_BWTR4 FSMC_BWTR(3) + +/* PC Card/NAND Flash control registers 2..4 (FSMC_PCRx) */ +#define FSMC_PCR(x) MMIO32(FSMC_BASE + 0x40 + 0x20 * x) +#define FSMC_PCR2 FSMC_PCR(1) +#define FSMC_PCR3 FSMC_PCR(2) +#define FSMC_PCR4 FSMC_PCR(3) + +/* FIFO status and interrupt registers 2..4 (FSMC_SRx) */ +#define FSMC_SR(x) MMIO32(FSMC_BASE + 0x44 + 0x20 * x) +#define FSMC_SR2 FSMC_SR(1) +#define FSMC_SR3 FSMC_SR(2) +#define FSMC_SR4 FSMC_SR(3) + +/* Common memory space timing registers 2..4 (FSMC_PMEMx) */ +#define FSMC_PMEM(x) MMIO32(FSMC_BASE + 0x48 + 0x20 * x) +#define FSMC_PMEM2 FSMC_PMEM(1) +#define FSMC_PMEM3 FSMC_PMEM(2) +#define FSMC_PMEM4 FSMC_PMEM(3) + +/* Attribute memory space timing registers 2..4 (FSMC_PATTx) */ +#define FSMC_PATT(x) MMIO32(FSMC_BASE + 0x4c + 0x20 * x) +#define FSMC_PATT2 FSMC_PATT(1) +#define FSMC_PATT3 FSMC_PATT(2) +#define FSMC_PATT4 FSMC_PATT(3) + +/* I/O space timing register 4 (FSMC_PIO4) */ +#define FSMC_PIO4 MMIO32(FSMC_BASE + 0xb0) + +/* ECC result registers 2/3 (FSMC_ECCRx) */ +#define FSMC_ECCR(x) MMIO32(FSMC_BASE + 0x54 + 0x20 * x) +#define FSMC_ECCR2 FSMC_ECCR(1) +#define FSMC_ECCR3 FSMC_ECCR(2) + +/* --- FSMC_BCRx values ---------------------------------------------------- */ + +/* Bits [31:20]: Reserved. */ + +/* CBURSTRW: Write burst enable */ +#define FSMC_BCR_CBURSTRW (1 << 19) + +/* Bits [18:16]: Reserved. */ + +/* ASYNCWAIT: Wait signal during asynchronous transfers */ +#define FSMC_BCR_ASYNCWAIT (1 << 15) + +/* EXTMOD: Extended mode enable */ +#define FSMC_BCR_EXTMOD (1 << 14) + +/* WAITEN: Wait enable bit */ +#define FSMC_BCR_WAITEN (1 << 13) + +/* WREN: Write enable bit */ +#define FSMC_BCR_WREN (1 << 12) + +/* WAITCFG: Wait timing configuration */ +#define FSMC_BCR_WAITCFG (1 << 11) + +/* WRAPMOD: Wrapped burst mode support */ +#define FSMC_BCR_WRAPMOD (1 << 10) + +/* WAITPOL: Wait signal polarity bit */ +#define FSMC_BCR_WAITPOL (1 << 9) + +/* BURSTEN: Burst enable bit */ +#define FSMC_BCR_BURSTEN (1 << 8) + +/* Bit 7: Reserved. */ + +/* FACCEN: Flash access enable */ +#define FSMC_BCR_FACCEN (1 << 6) + +/* MWID[5:4]: Memory data bus width */ +#define FSMC_BCR_MWID (1 << 4) + +/* MTYP[3:2]: Memory type */ +#define FSMC_BCR_MTYP (1 << 2) + +/* MUXEN: Address/data multiplexing enable bit */ +#define FSMC_BCR_MUXEN (1 << 1) + +/* MBKEN: Memory bank enable bit */ +#define FSMC_BCR_MBKEN (1 << 0) + +/* --- FSMC_BTRx values ---------------------------------------------------- */ + +/* Bits [31:30]: Reserved. */ + +/* Same for read and write */ +#define FSMC_BTx_ACCMOD_A (0) +#define FSMC_BTx_ACCMOD_B (1) +#define FSMC_BTx_ACCMOD_C (2) +#define FSMC_BTx_ACCMOD_D (3) + +/* ACCMOD[29:28]: Access mode */ +#define FSMC_BTR_ACCMOD (1 << 28) +#define FSMC_BTR_ACCMODx(x) (((x) & 0x03) << 28) + +/* DATLAT[27:24]: Data latency (for synchronous burst NOR flash) */ +#define FSMC_BTR_DATLAT (1 << 24) +#define FSMC_BTR_DATLATx(x) (((x) & 0x0f) << 24) + +/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */ +#define FSMC_BTR_CLKDIV (1 << 20) +#define FSMC_BTR_CLKDIVx(x) (((x) & 0x0f) << 20) + +/* BUSTURN[19:16]: Bus turnaround phase duration */ +#define FSMC_BTR_BUSTURN (1 << 16) +#define FSMC_BTR_BUSTURNx(x) (((x) & 0x0f) << 16) + +/* DATAST[15:8]: Data-phase duration */ +#define FSMC_BTR_DATAST (1 << 8) +#define FSMC_BTR_DATASTx(x) (((x) & 0xff) << 8) + +/* ADDHLD[7:4]: Address-hold phase duration */ +#define FSMC_BTR_ADDHLD (1 << 4) +#define FSMC_BTR_ADDHLDx(x) (((x) & 0x0f) << 4) + +/* ADDSET[3:0]: Address setup phase duration */ +#define FSMC_BTR_ADDSET (1 << 0) +#define FSMC_BTR_ADDSETx(x) (((x) & 0x0f) << 0) + +/* --- FSMC_BWTRx values --------------------------------------------------- */ + +/* Bits [31:30]: Reserved. */ + +/* ACCMOD[29:28]: Access mode */ +#define FSMC_BWTR_ACCMOD (1 << 28) + +/* DATLAT[27:24]: Data latency (for synchronous burst NOR Flash) */ +#define FSMC_BWTR_DATLAT (1 << 24) + +/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */ +#define FSMC_BWTR_CLKDIV (1 << 20) + +/* Bits [19..16]: Reserved. */ + +/* DATAST[15:8]: Data-phase duration */ +#define FSMC_BWTR_DATAST (1 << 8) + +/* ADDHLD[7:4]: Address-hold phase duration */ +#define FSMC_BWTR_ADDHLD (1 << 4) + +/* ADDSET[3:0]: Address setup phase duration */ +#define FSMC_BWTR_ADDSET (1 << 0) + +/* --- FSMC_PCRx values ---------------------------------------------------- */ + +/* Bits [31:20]: Reserved. */ + +/* ECCPS[19:17]: ECC page size */ +#define FSMC_PCR_ECCPS (1 << 17) + +/* TAR[16:13]: ALE to RE delay */ +#define FSMC_PCR_TAR (1 << 13) + +/* TCLR[12:9]: CLE to RE delay */ +#define FSMC_PCR_TCLR (1 << 9) + +/* Bits [8..7]: Reserved. */ + +/* ECCEN: ECC computation logic enable bit */ +#define FSMC_PCR_ECCEN (1 << 6) + +/* PWID[5:4]: Databus width */ +#define FSMC_PCR_PWID (1 << 4) + +/* PTYP: Memory type */ +#define FSMC_PCR_PTYP (1 << 3) + +/* PBKEN: PC Card/NAND Flash memory bank enable bit */ +#define FSMC_PCR_PBKEN (1 << 2) + +/* PWAITEN: Wait feature enable bit */ +#define FSMC_PCR_PWAITEN (1 << 1) + +/* Bit 0: Reserved. */ + +/* --- FSMC_SRx values ----------------------------------------------------- */ + +/* Bits [31:7]: Reserved. */ + +/* FEMPT: FIFO empty */ +#define FSMC_SR_FEMPT (1 << 6) + +/* IFEN: Interrupt falling edge detection enable bit */ +#define FSMC_SR_IFEN (1 << 5) + +/* ILEN: Interrupt high-level detection enable bit */ +#define FSMC_SR_ILEN (1 << 4) + +/* IREN: Interrupt rising edge detection enable bit */ +#define FSMC_SR_IREN (1 << 3) + +/* IFS: Interrupt falling edge status */ +#define FSMC_SR_IFS (1 << 2) + +/* ILS: Interrupt high-level status */ +#define FSMC_SR_ILS (1 << 1) + +/* IRS: Interrupt rising edge status */ +#define FSMC_SR_IRS (1 << 0) + +/* --- FSMC_PMEMx values --------------------------------------------------- */ + +/* MEMHIZx[31:24]: Common memory x databus HiZ time */ +#define FSMC_PMEM_MEMHIZX (1 << 24) + +/* MEMHOLDx[23:16]: Common memory x hold time */ +#define FSMC_PMEM_MEMHOLDX (1 << 16) + +/* MEMWAITx[15:8]: Common memory x wait time */ +#define FSMC_PMEM_MEMWAITX (1 << 8) + +/* MEMSETx[7:0]: Common memory x setup time */ +#define FSMC_PMEM_MEMSETX (1 << 0) + +/* --- FSMC_PATTx values --------------------------------------------------- */ + +/* ATTHIZx[31:24]: Attribute memory x databus HiZ time */ +#define FSMC_PATT_ATTHIZX (1 << 24) + +/* ATTHOLDx[23:16]: Attribute memory x hold time */ +#define FSMC_PATT_ATTHOLDX (1 << 16) + +/* ATTWAITx[15:8]: Attribute memory x wait time */ +#define FSMC_PATT_ATTWAITX (1 << 8) + +/* ATTSETx[7:0]: Attribute memory x setup time */ +#define FSMC_PATT_ATTSETX (1 << 0) + +/* --- FSMC_PIO4 values ---------------------------------------------------- */ + +/* IOHIZx[31:24]: I/O x databus HiZ time */ +#define FSMC_PIO4_IOHIZX (1 << 24) + +/* IOHOLDx[23:16]: I/O x hold time */ +#define FSMC_PIO4_IOHOLDX (1 << 16) + +/* IOWAITx[15:8]: I/O x wait time */ +#define FSMC_PIO4_IOWAITX (1 << 8) + +/* IOSETx[7:0]: I/O x setup time */ +#define FSMC_PIO4_IOSETX (1 << 0) + +/* --- FSMC_ECCRx values --------------------------------------------------- */ + +/* ECCx[31:0]: ECC result */ +#define FSMC_ECCR_ECCX (1 << 0) + +#endif diff --git a/libopencm3/include/libopencm3/stm32/gpio.h b/libopencm3/include/libopencm3/stm32/gpio.h new file mode 100644 index 0000000..0560b5d --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/gpio.h @@ -0,0 +1,38 @@ +/* This provides unification of code over STM32F subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#if defined(STM32F0) +# include +#elif defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F3) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." +#endif + diff --git a/libopencm3/include/libopencm3/stm32/hash.h b/libopencm3/include/libopencm3/stm32/hash.h new file mode 100644 index 0000000..2659e68 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/hash.h @@ -0,0 +1,30 @@ +/* This provides unification of code over STM32F subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#if defined(STM32F2) +# include +#elif defined(STM32F4) +# include +#else +# error "hash processor is supported only" \ + "in stm32f21, stm32f41 and stm32f43 families." +#endif diff --git a/libopencm3/include/libopencm3/stm32/i2c.h b/libopencm3/include/libopencm3/stm32/i2c.h new file mode 100644 index 0000000..6048617 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/i2c.h @@ -0,0 +1,38 @@ +/* This provides unification of code over STM32F subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#if defined(STM32F0) +# include +#elif defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F3) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." +#endif + diff --git a/libopencm3/include/libopencm3/stm32/iwdg.h b/libopencm3/include/libopencm3/stm32/iwdg.h new file mode 100644 index 0000000..309d51d --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/iwdg.h @@ -0,0 +1,38 @@ +/* This provides unification of code over STM32F subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#if defined(STM32F0) +# include +#elif defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F3) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." +#endif + diff --git a/libopencm3/include/libopencm3/stm32/l1/adc.h b/libopencm3/include/libopencm3/stm32/l1/adc.h new file mode 100644 index 0000000..cd56d15 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/l1/adc.h @@ -0,0 +1,227 @@ +/** @defgroup adc_defines ADC Defines + +@brief Defined Constants and Types for the STM32L1xx Analog to +Digital Converters + +@ingroup STM32L1xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2013 Karl Palsson + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_ADC_H +#define LIBOPENCM3_ADC_H + +#include + +#define ADC_MAX_REGULAR_SEQUENCE 28 +/* 26 in L/M, but 32 in two banks for M+/H density */ +#define ADC_MAX_CHANNELS 32 + +/* ADC sample time register 3 (ADC_SMPR3) */ +#define ADC_SMPR3(block) MMIO32(block + 0x14) +#define ADC1_SMPR3 ADC_SMPR3(ADC1) + +/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */ +#define ADC_JOFR1(block) MMIO32(block + 0x18) +#define ADC_JOFR2(block) MMIO32(block + 0x1c) +#define ADC_JOFR3(block) MMIO32(block + 0x20) +#define ADC_JOFR4(block) MMIO32(block + 0x24) + +/* ADC watchdog high threshold register (ADC_HTR) */ +#define ADC_HTR(block) MMIO32(block + 0x28) + +/* ADC watchdog low threshold register (ADC_LTR) */ +#define ADC_LTR(block) MMIO32(block + 0x2c) + +/* ADC regular sequence register 1 (ADC_SQR1) */ +#define ADC_SQR1(block) MMIO32(block + 0x30) + +/* ADC regular sequence register 2 (ADC_SQR2) */ +#define ADC_SQR2(block) MMIO32(block + 0x34) + +/* ADC regular sequence register 3 (ADC_SQR3) */ +#define ADC_SQR3(block) MMIO32(block + 0x38) + +/* ADC regular sequence register 4 (ADC_SQR4) */ +#define ADC_SQR4(block) MMIO32(block + 0x3c) +#define ADC1_SQR4 ADC_SQR4(ADC1) + +/* ADC regular sequence register 5 (ADC_SQR5) */ +#define ADC_SQR5(block) MMIO32(block + 0x40) +#define ADC1_SQR5 ADC_SQR5(ADC1) + +/* ADC injected sequence register (ADC_JSQR) */ +#define ADC_JSQR(block) MMIO32(block + 0x44) + +/* ADC injected data register x (ADC_JDRx) (x=1..4) */ +#define ADC_JDR1(block) MMIO32(block + 0x48) +#define ADC_JDR2(block) MMIO32(block + 0x4c) +#define ADC_JDR3(block) MMIO32(block + 0x50) +#define ADC_JDR4(block) MMIO32(block + 0x54) + +/* ADC regular data register (ADC_DR) */ +#define ADC_DR(block) MMIO32(block + 0x58) + +/* ADC sample time register 0 (ADC_SMPR0) (high/med+ only) */ +#define ADC_SMPR0(block) MMIO32(block + 0x5c) +#define ADC1_SMPR0 ADC_SMPR0(ADC1) + +#define ADC_CSR MMIO32(ADC1 + 0x300) +#define ADC_CCR MMIO32(ADC1 + 0x304) + + +/* These are _not_ consistent unfortunately! */ +#define ADC_CHANNEL_TEMP ADC_CHANNEL16 +#define ADC_CHANNEL_VREFINT ADC_CHANNEL17 +#define ADC_CHANNEL_VBAT ADC_CHANNEL18 + +/* --- ADC_SR values ------------------------------------------------------- */ +#define ADC_SR_JCNR (1 << 9) +#define ADC_SR_RCNR (1 << 8) +#define ADC_SR_ADONS (1 << 6) +#define ADC_SR_OVR (1 << 5) + +/* --- ADC_CR1 values ------------------------------------------------------- */ +#define ADC_CR1_OVRIE (1 << 28) +/****************************************************************************/ +/** @defgroup adc_cr1_res ADC Resolution. +@ingroup adc_defines +@{*/ +#define ADC_CR1_RES_12_BIT 0 +#define ADC_CR1_RES_10_BIT 1 +#define ADC_CR1_RES_8_BIT 2 +#define ADC_CR1_RES_6_BIT 3 +/**@}*/ +#define ADC_CR1_RES_MASK (0x3) +#define ADC_CR1_RES_SHIFT 24 +#define ADC_CR1_PDI (1 << 17) +#define ADC_CR1_PDD (1 << 16) + +#define ADC_CR1_AWDCH_MAX 26 + +/* --- ADC_CR2 values ------------------------------------------------------- */ +/* SWSTART: */ /** Start conversion of regular channels. */ +#define ADC_CR2_SWSTART (1 << 30) + +/* EXTEN[1:0]: External trigger enable for regular channels. */ +/****************************************************************************/ +#define ADC_CR2_EXTEN_SHIFT 28 +#define ADC_CR2_EXTEN_MASK (0x3 << ADC_CR2_EXTEN_SHIFT) +/** @defgroup adc_trigger_polarity_regular ADC Trigger Polarity +@ingroup adc_defines +@{*/ +#define ADC_CR2_EXTEN_DISABLED (0x0 << ADC_CR2_EXTEN_SHIFT) +#define ADC_CR2_EXTEN_RISING_EDGE (0x1 << ADC_CR2_EXTEN_SHIFT) +#define ADC_CR2_EXTEN_FALLING_EDGE (0x2 << ADC_CR2_EXTEN_SHIFT) +#define ADC_CR2_EXTEN_BOTH_EDGES (0x3 << ADC_CR2_EXTEN_SHIFT) +/**@}*/ + +/* EXTSEL[3:0]: External event selection for regular group. */ +/****************************************************************************/ +#define ADC_CR2_EXTSEL_SHIFT 24 +#define ADC_CR2_EXTSEL_MASK (0xf << ADC_CR2_EXTSEL_SHIFT) +/** @defgroup adc_trigger_regular ADC Trigger Identifier for Regular group +@ingroup adc_defines + +@{*/ +#define ADC_CR2_EXTSEL_TIM9_CC2 (0 << ADC_CR2_EXTSEL_SHIFT) +#define ADC_CR2_EXTSEL_TIM9_TRGO (1 << ADC_CR2_EXTSEL_SHIFT) +#define ADC_CR2_EXTSEL_TIM2_CC3 (2 << ADC_CR2_EXTSEL_SHIFT) +#define ADC_CR2_EXTSEL_TIM2_CC2 (3 << ADC_CR2_EXTSEL_SHIFT) +#define ADC_CR2_EXTSEL_TIM3_TRGO (4 << ADC_CR2_EXTSEL_SHIFT) +#define ADC_CR2_EXTSEL_TIM4_CC4 (5 << ADC_CR2_EXTSEL_SHIFT) +#define ADC_CR2_EXTSEL_TIM2_TRGO (6 << ADC_CR2_EXTSEL_SHIFT) +#define ADC_CR2_EXTSEL_TIM3_CC1 (7 << ADC_CR2_EXTSEL_SHIFT) +#define ADC_CR2_EXTSEL_TIM3_CC3 (8 << ADC_CR2_EXTSEL_SHIFT) +#define ADC_CR2_EXTSEL_TIM4_TRGO (9 << ADC_CR2_EXTSEL_SHIFT) +#define ADC_CR2_EXTSEL_TIM6_TRGO (10 << ADC_CR2_EXTSEL_SHIFT) +/* reserved.... */ +#define ADC_CR2_EXTSEL_EXTI11 (15 << ADC_CR2_EXTSEL_SHIFT) +/**@}*/ + +#define ADC_CR2_JSWSTART (1 << 22) + +/* JEXTEN[1:0]: External trigger enable for injected channels. */ +/****************************************************************************/ +#define ADC_CR2_JEXTEN_SHIFT 20 +#define ADC_CR2_JEXTEN_MASK (0x3 << ADC_CR2_JEXTEN_SHIFT) +/** @defgroup adc_trigger_polarity_injected ADC Injected Trigger Polarity +@ingroup adc_defines +@{*/ +#define ADC_CR2_JEXTEN_DISABLED (0x0 << ADC_CR2_JEXTEN_SHIFT) +#define ADC_CR2_JEXTEN_RISING_EDGE (0x1 << ADC_CR2_JEXTEN_SHIFT) +#define ADC_CR2_JEXTEN_FALLING_EDGE (0x2 << ADC_CR2_JEXTEN_SHIFT) +#define ADC_CR2_JEXTEN_BOTH_EDGES (0x3 << ADC_CR2_JEXTEN_SHIFT) +/**@}*/ + +/* FIXME - add the values here */ +#define ADC_CR2_JEXTSEL_SHIFT 16 +#define ADC_CR2_JEXTSEL_MASK (0xf << ADC_CR2_JEXTSEL_SHIFT) + +#define ADC_CR2_EOCS (1 << 10) +#define ADC_CR2_DDS (1 << 9) +/* FIXME- add the values here */ +#define ADC_CR2_DELS_SHIFT 4 +#define ADC_CR2_DELS_MASK 0x7 + +#define ADC_CR2_ADC_CFG (1 << 2) + + + + +/* --- ADC_SMPRx generic values -------------------------------------------- */ +/****************************************************************************/ +/* ADC_SMPRG ADC Sample Time Selection for Channels */ +/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels +@ingroup adc_defines + +@{*/ +#define ADC_SMPR_SMP_4CYC 0x0 +#define ADC_SMPR_SMP_9CYC 0x1 +#define ADC_SMPR_SMP_16CYC 0x2 +#define ADC_SMPR_SMP_24CYC 0x3 +#define ADC_SMPR_SMP_48CYC 0x4 +#define ADC_SMPR_SMP_96CYC 0x5 +#define ADC_SMPR_SMP_192CYC 0x6 +#define ADC_SMPR_SMP_384CYC 0x7 +/**@}*/ + +#define ADC_SQR_MASK 0x1f +#define ADC_SQR_MAX_CHANNELS_REGULAR 28 /* m+/h only, otherwise 27 */ + +#define ADC_CCR_TSVREFE (1 << 23) + +BEGIN_DECLS + /* L1 specific, or not fully unified adc routines */ +void adc_enable_temperature_sensor(void); +void adc_disable_temperature_sensor(void); +void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, + uint32_t polarity); +void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, + uint32_t polarity); + +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/stm32/l1/crc.h b/libopencm3/include/libopencm3/stm32/l1/crc.h new file mode 100644 index 0000000..e019c34 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/l1/crc.h @@ -0,0 +1,38 @@ +/** @defgroup crc_defines CRC Defines + +@brief libopencm3 Defined Constants and Types for the STM32L1xx CRC +Generator + +@ingroup STM32L1xx_defines + +@version 1.0.0 + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_CRC_H +#define LIBOPENCM3_CRC_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/l1/dac.h b/libopencm3/include/libopencm3/stm32/l1/dac.h new file mode 100644 index 0000000..207c59d --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/l1/dac.h @@ -0,0 +1,37 @@ +/** @defgroup dac_defines DAC Defines + +@brief Defined Constants and Types for the STM32L1xx DAC + +@ingroup STM32L1xx_defines + +@version 1.0.0 + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DAC_H +#define LIBOPENCM3_DAC_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/l1/dma.h b/libopencm3/include/libopencm3/stm32/l1/dma.h new file mode 100644 index 0000000..c1728d1 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/l1/dma.h @@ -0,0 +1,42 @@ +/** @defgroup dma_defines DMA Defines + * + * @ingroup STM32L1xx_defines + * + * @brief Defined Constants and Types for the STM32L1xx DMA Controller + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2011 + * Fergus Noble + * @author @htmlonly © @endhtmlonly 2012 + * Ken Sarkies + * + * @date 18 October 2012 + * + * LGPL License Terms @ref lgpl_license + * */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_DMA_H +#define LIBOPENCM3_DMA_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/l1/doc-stm32l1.h b/libopencm3/include/libopencm3/stm32/l1/doc-stm32l1.h new file mode 100644 index 0000000..96bea00 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/l1/doc-stm32l1.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 STM32L1 + +@version 1.0.0 + +@date 12 November 2012 + +API documentation for ST Microelectronics STM32L1 Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup STM32L1xx STM32L1xx +Libraries for ST Microelectronics STM32L1xx series. + +@version 1.0.0 + +@date 12 November 2012 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup STM32L1xx_defines STM32L1xx Defines + +@brief Defined Constants and Types for the STM32L1xx series + +@version 1.0.0 + +@date 12 November 2012 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/libopencm3/include/libopencm3/stm32/l1/exti.h b/libopencm3/include/libopencm3/stm32/l1/exti.h new file mode 100644 index 0000000..2c14c95 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/l1/exti.h @@ -0,0 +1,41 @@ +/** @defgroup exti_defines EXTI Defines + * + * @brief Defined Constants and Types for the STM32L1xx External Interrupts + * + * + * @ingroup STM32L1xx_defines + * + * @author @htmlonly © @endhtmlonly 2013 + * Piotr Esden-Tempski + * + * @version 1.0.0 + * + * @date 14 January 2014 + * + * LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Piotr Esden-Tempski + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EXTI_H +#define LIBOPENCM3_EXTI_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/l1/flash.h b/libopencm3/include/libopencm3/stm32/l1/flash.h new file mode 100644 index 0000000..680de5c --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/l1/flash.h @@ -0,0 +1,156 @@ +/** @defgroup flash_defines FLASH Defines + * + * @ingroup STM32L1xx_defines + * + * @brief Defined Constants and Types for the STM32L1xx FLASH Memory + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2012 + * Karl Palsson + * + * @date 14 January 2014 + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * Copyright (C) 2010 Mark Butler + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* + * All extracted from PM0062 rev2, L15xx and L16xx Flash/EEPROM programming + * manual. + */ + +#ifndef LIBOPENCM3_FLASH_H +#define LIBOPENCM3_FLASH_H +/**@{*/ + +/* --- FLASH registers ----------------------------------------------------- */ + +#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) +#define FLASH_PECR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) +#define FLASH_PDKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) +#define FLASH_PEKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) +#define FLASH_PRGKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) +#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) +#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18) +#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1c) +#define FLASH_WRPR1 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) +#define FLASH_WRPR2 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x80) +#define FLASH_WRPR3 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x84) + +/* --- FLASH_ACR values ---------------------------------------------------- */ + +#define FLASH_ACR_RUNPD (1 << 4) +#define FLASH_ACR_SLEEPPD (1 << 3) +#define FLASH_ACR_ACC64 (1 << 2) +#define FLASH_ACR_PRFTEN (1 << 1) +/** @defgroup flash_latency FLASH Wait States +@ingroup flash_defines +@{*/ +#define FLASH_ACR_LATENCY_0WS 0x00 +#define FLASH_ACR_LATENCY_1WS 0x01 +/**@}*/ + +/* --- FLASH_PECR values. Program/erase control register */ +#define FLASH_PECR_OBL_LAUNCH (1 << 18) +#define FLASH_PECR_ERRIE (1 << 17) +#define FLASH_PECR_EOPIE (1 << 16) +#define FLASH_PECR_PARALLBANK (1 << 15) +#define FLASH_PECR_FPRG (1 << 10) +#define FLASH_PECR_ERASE (1 << 9) +#define FLASH_PECR_FTDW (1 << 8) +#define FLASH_PECR_FTDW (1 << 8) +#define FLASH_PECR_DATA (1 << 4) +#define FLASH_PECR_PROG (1 << 3) +#define FLASH_PECR_OPTLOCK (1 << 2) +#define FLASH_PECR_PRGLOCK (1 << 1) +#define FLASH_PECR_PELOCK (1 << 0) + +/* Power down key register (FLASH_PDKEYR) */ +#define FLASH_PDKEYR_PDKEY1 ((uint32_t)0x04152637) +#define FLASH_PDKEYR_PDKEY2 ((uint32_t)0xFAFBFCFD) + +/* Program/erase key register (FLASH_PEKEYR) */ +#define FLASH_PEKEYR_PEKEY1 ((uint32_t)0x89ABCDEF) +#define FLASH_PEKEYR_PEKEY2 ((uint32_t)0x02030405) + +/* Program memory key register (FLASH_PRGKEYR) */ +#define FLASH_PRGKEYR_PRGKEY1 ((uint32_t)0x8C9DAEBF) +#define FLASH_PRGKEYR_PRGKEY2 ((uint32_t)0x13141516) + +/* Option byte key register (FLASH_OPTKEYR) */ +#define FLASH_OPTKEYR_OPTKEY1 ((uint32_t)0xFBEAD9C8) +#define FLASH_OPTKEYR_OPTKEY2 ((uint32_t)0x24252627) + + +/* --- FLASH_SR values ----------------------------------------------------- */ +#define FLASH_SR_OPTVERRUSR (1 << 12) +#define FLASH_SR_OPTVERR (1 << 11) +#define FLASH_SR_SIZEERR (1 << 10) +#define FLASH_SR_PGAERR (1 << 9) +#define FLASH_SR_WRPERR (1 << 8) +#define FLASH_SR_READY (1 << 3) +#define FLASH_SR_ENDHV (1 << 2) +#define FLASH_SR_EOP (1 << 1) +#define FLASH_SR_BSY (1 << 0) + +/* --- FLASH_OBR values ----------------------------------------------------- */ +#define FLASH_OBR_BFB2 (1 << 23) +#define FLASH_OBR_NRST_STDBY (1 << 22) +#define FLASH_OBR_NRST_STOP (1 << 21) +#define FLASH_OBR_IWDG_SW (1 << 20) +#define FLASH_OBR_BOR_OFF (0x0 << 16) +#define FLASH_OBR_BOR_LEVEL_1 (0x8 << 16) +#define FLASH_OBR_BOR_LEVEL_2 (0x9 << 16) +#define FLASH_OBR_BOR_LEVEL_3 (0xa << 16) +#define FLASH_OBR_BOR_LEVEL_4 (0xb << 16) +#define FLASH_OBR_BOR_LEVEL_5 (0xc << 16) +#define FLASH_OBR_RDPRT_LEVEL_0 (0xaa) +#define FLASH_OBR_RDPRT_LEVEL_1 (0x00) +#define FLASH_OBR_RDPRT_LEVEL_2 (0xcc) + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void flash_64bit_enable(void); +void flash_64bit_disable(void); +void flash_prefetch_enable(void); +void flash_prefetch_disable(void); +void flash_set_ws(uint32_t ws); +void flash_unlock_pecr(void); +void flash_lock_pecr(void); +void flash_unlock_progmem(void); +void flash_lock_progmem(void); +void flash_unlock_option_bytes(void); +void flash_lock_option_bytes(void); +void flash_unlock(void); +void flash_lock(void); + +void eeprom_program_word(uint32_t address, uint32_t data); +void eeprom_program_words(uint32_t address, uint32_t *data, int length_in_words); + +END_DECLS +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/l1/gpio.h b/libopencm3/include/libopencm3/stm32/l1/gpio.h new file mode 100644 index 0000000..f2c607c --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/l1/gpio.h @@ -0,0 +1,263 @@ +/** @defgroup gpio_defines GPIO Defines + +@brief Defined Constants and Types for the STM32L1xx General Purpose I/O + +@ingroup STM32L1xx_defines + +@version 1.0.0 + +@date 1 July 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2012 Piotr Esden-Tempski + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#ifndef LIBOPENCM3_GPIO_H +#define LIBOPENCM3_GPIO_H + +#include + +/* --- Convenience macros -------------------------------------------------- */ + +/* GPIO port base addresses (for convenience) */ +/* GPIO port base addresses (for convenience) */ +/** @defgroup gpio_port_id GPIO Port IDs +@ingroup gpio_defines + +@{*/ +#define GPIOA GPIO_PORT_A_BASE +#define GPIOB GPIO_PORT_B_BASE +#define GPIOC GPIO_PORT_C_BASE +#define GPIOD GPIO_PORT_D_BASE +#define GPIOE GPIO_PORT_E_BASE +#define GPIOH GPIO_PORT_H_BASE +/**@}*/ + +/* --- GPIO registers ------------------------------------------------------ */ + +/* Port mode register (GPIOx_MODER) */ +#define GPIO_MODER(port) MMIO32(port + 0x00) +#define GPIOA_MODER GPIO_MODER(GPIOA) +#define GPIOB_MODER GPIO_MODER(GPIOB) +#define GPIOC_MODER GPIO_MODER(GPIOC) +#define GPIOD_MODER GPIO_MODER(GPIOD) +#define GPIOE_MODER GPIO_MODER(GPIOE) +#define GPIOH_MODER GPIO_MODER(GPIOH) + +/* Port output type register (GPIOx_OTYPER) */ +#define GPIO_OTYPER(port) MMIO32(port + 0x04) +#define GPIOA_OTYPER GPIO_OTYPER(GPIOA) +#define GPIOB_OTYPER GPIO_OTYPER(GPIOB) +#define GPIOC_OTYPER GPIO_OTYPER(GPIOC) +#define GPIOD_OTYPER GPIO_OTYPER(GPIOD) +#define GPIOE_OTYPER GPIO_OTYPER(GPIOE) +#define GPIOH_OTYPER GPIO_OTYPER(GPIOH) + +/* Port output speed register (GPIOx_OSPEEDR) */ +#define GPIO_OSPEEDR(port) MMIO32(port + 0x08) +#define GPIOA_OSPEEDR GPIO_OSPEEDR(GPIOA) +#define GPIOB_OSPEEDR GPIO_OSPEEDR(GPIOB) +#define GPIOC_OSPEEDR GPIO_OSPEEDR(GPIOC) +#define GPIOD_OSPEEDR GPIO_OSPEEDR(GPIOD) +#define GPIOE_OSPEEDR GPIO_OSPEEDR(GPIOE) +#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH) + +/* Port pull-up/pull-down register (GPIOx_PUPDR) */ +#define GPIO_PUPDR(port) MMIO32(port + 0x0c) +#define GPIOA_PUPDR GPIO_PUPDR(GPIOA) +#define GPIOB_PUPDR GPIO_PUPDR(GPIOB) +#define GPIOC_PUPDR GPIO_PUPDR(GPIOC) +#define GPIOD_PUPDR GPIO_PUPDR(GPIOD) +#define GPIOE_PUPDR GPIO_PUPDR(GPIOE) +#define GPIOH_PUPDR GPIO_PUPDR(GPIOH) + +/* Port input data register (GPIOx_IDR) */ +#define GPIO_IDR(port) MMIO32(port + 0x10) +#define GPIOA_IDR GPIO_IDR(GPIOA) +#define GPIOB_IDR GPIO_IDR(GPIOB) +#define GPIOC_IDR GPIO_IDR(GPIOC) +#define GPIOD_IDR GPIO_IDR(GPIOD) +#define GPIOE_IDR GPIO_IDR(GPIOE) +#define GPIOH_IDR GPIO_IDR(GPIOH) + +/* Port output data register (GPIOx_ODR) */ +#define GPIO_ODR(port) MMIO32(port + 0x14) +#define GPIOA_ODR GPIO_ODR(GPIOA) +#define GPIOB_ODR GPIO_ODR(GPIOB) +#define GPIOC_ODR GPIO_ODR(GPIOC) +#define GPIOD_ODR GPIO_ODR(GPIOD) +#define GPIOE_ODR GPIO_ODR(GPIOE) +#define GPIOH_ODR GPIO_ODR(GPIOH) + +/* Port bit set/reset register (GPIOx_BSRR) */ +#define GPIO_BSRR(port) MMIO32(port + 0x18) +#define GPIOA_BSRR GPIO_BSRR(GPIOA) +#define GPIOB_BSRR GPIO_BSRR(GPIOB) +#define GPIOC_BSRR GPIO_BSRR(GPIOC) +#define GPIOD_BSRR GPIO_BSRR(GPIOD) +#define GPIOE_BSRR GPIO_BSRR(GPIOE) +#define GPIOH_BSRR GPIO_BSRR(GPIOH) + +/* Port configuration lock register (GPIOx_LCKR) */ +#define GPIO_LCKR(port) MMIO32(port + 0x1C) +#define GPIOA_LCKR GPIO_LCKR(GPIOA) +#define GPIOB_LCKR GPIO_LCKR(GPIOB) +#define GPIOC_LCKR GPIO_LCKR(GPIOC) +#define GPIOD_LCKR GPIO_LCKR(GPIOD) +#define GPIOE_LCKR GPIO_LCKR(GPIOE) +#define GPIOH_LCKR GPIO_LCKR(GPIOH) + +/* Alternate function low register (GPIOx_AFRL) */ +#define GPIO_AFRL(port) MMIO32(port + 0x20) +#define GPIOA_AFRL GPIO_AFRL(GPIOA) +#define GPIOB_AFRL GPIO_AFRL(GPIOB) +#define GPIOC_AFRL GPIO_AFRL(GPIOC) +#define GPIOD_AFRL GPIO_AFRL(GPIOD) +#define GPIOE_AFRL GPIO_AFRL(GPIOE) +#define GPIOH_AFRL GPIO_AFRL(GPIOH) + +/* Alternate function high register (GPIOx_AFRH) */ +#define GPIO_AFRH(port) MMIO32(port + 0x24) +#define GPIOA_AFRH GPIO_AFRH(GPIOA) +#define GPIOB_AFRH GPIO_AFRH(GPIOB) +#define GPIOC_AFRH GPIO_AFRH(GPIOC) +#define GPIOD_AFRH GPIO_AFRH(GPIOD) +#define GPIOE_AFRH GPIO_AFRH(GPIOE) +#define GPIOH_AFRH GPIO_AFRH(GPIOH) + +/* --- GPIOx_MODER values-------------------------------------------- */ + +#define GPIO_MODE(n, mode) (mode << (2 * (n))) +#define GPIO_MODE_MASK(n) (0x3 << (2 * (n))) +/** @defgroup gpio_mode GPIO Pin Direction and Analog/Digital Mode +@ingroup gpio_defines +@{*/ +#define GPIO_MODE_INPUT 0x00 /* Default */ +#define GPIO_MODE_OUTPUT 0x01 +#define GPIO_MODE_AF 0x02 +#define GPIO_MODE_ANALOG 0x03 +/**@}*/ + +/* --- GPIOx_OTYPER values -------------------------------------------- */ +/* Output type (OTx values) */ +/** @defgroup gpio_output_type GPIO Output Pin Driver Type +@ingroup gpio_defines +@list Push Pull +@list Open Drain +@{*/ +#define GPIO_OTYPE_PP 0x0 +#define GPIO_OTYPE_OD 0x1 +/**@}*/ + +/* Output speed values */ +#define GPIO_OSPEED(n, speed) (speed << (2 * (n))) +#define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n))) +/** @defgroup gpio_speed GPIO Output Pin Speed +@ingroup gpio_defines +@{*/ +#define GPIO_OSPEED_400KHZ 0x0 +#define GPIO_OSPEED_2MHZ 0x1 +#define GPIO_OSPEED_10MHZ 0x2 +#define GPIO_OSPEED_40MHZ 0x3 +/**@}*/ + +/* --- GPIOx_PUPDR values ------------------------------------------- */ + +#define GPIO_PUPD(n, pupd) (pupd << (2 * (n))) +#define GPIO_PUPD_MASK(n) (0x3 << (2 * (n))) +/** @defgroup gpio_pup GPIO Output Pin Pullup +@ingroup gpio_defines +@{*/ +#define GPIO_PUPD_NONE 0x0 +#define GPIO_PUPD_PULLUP 0x1 +#define GPIO_PUPD_PULLDOWN 0x2 +/**@}*/ + +/* --- GPIO_IDR values ----------------------------------------------------- */ + +/* GPIO_IDR[15:0]: IDRy[15:0]: Port input data (y = 0..15) */ + +/* --- GPIO_ODR values ----------------------------------------------------- */ + +/* GPIO_ODR[15:0]: ODRy[15:0]: Port output data (y = 0..15) */ + +/* --- GPIO_BSRR values ---------------------------------------------------- */ + +/* GPIO_BSRR[31:16]: BRy: Port x reset bit y (y = 0..15) */ +/* GPIO_BSRR[15:0]: BSy: Port x set bit y (y = 0..15) */ + +/* --- GPIO_LCKR values ---------------------------------------------------- */ + +#define GPIO_LCKK (1 << 16) +/* GPIO_LCKR[15:0]: LCKy: Port x lock bit y (y = 0..15) */ + +/* --- GPIOx_AFRL/H values ------------------------------------------------- */ + +/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */ +/* See datasheet table 5, page 35 for the definitions */ + +#define GPIO_AFR(n, af) (af << ((n) * 4)) +#define GPIO_AFR_MASK(n) (0xf << ((n) * 4)) +/** @defgroup gpio_af_num Alternate Function Pin Selection +@ingroup gpio_defines +@{*/ +#define GPIO_AF0 0x0 +#define GPIO_AF1 0x1 +#define GPIO_AF2 0x2 +#define GPIO_AF3 0x3 +#define GPIO_AF4 0x4 +#define GPIO_AF5 0x5 +#define GPIO_AF6 0x6 +#define GPIO_AF7 0x7 +#define GPIO_AF8 0x8 +#define GPIO_AF9 0x9 +#define GPIO_AF10 0xa +#define GPIO_AF11 0xb +#define GPIO_AF12 0xc +#define GPIO_AF13 0xd +#define GPIO_AF14 0xe +#define GPIO_AF15 0xf +/**@}*/ + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +/* + * L1, like F2 and F4, has the "new" GPIO peripheral, so use that style + * however the number of ports is reduced and H port naming is different. + * TODO: this should all really be moved to a "common" gpio header + */ + +void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, + uint16_t gpios); +void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, + uint16_t gpios); +void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint16_t gpios); + +END_DECLS + +#endif +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/l1/i2c.h b/libopencm3/include/libopencm3/stm32/l1/i2c.h new file mode 100644 index 0000000..c2ed3f3 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/l1/i2c.h @@ -0,0 +1,37 @@ +/** @defgroup i2c_defines I2C Defines + +@brief Defined Constants and Types for the STM32L1xx I2C + +@ingroup STM32L1xx_defines + +@version 1.0.0 + +@date 12 October 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_I2C_H +#define LIBOPENCM3_I2C_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/l1/irq.json b/libopencm3/include/libopencm3/stm32/l1/irq.json new file mode 100644 index 0000000..abea8db --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/l1/irq.json @@ -0,0 +1,64 @@ +{ + "irqs": [ + "wwdg", + "pvd", + "tamper_stamp", + "rtc_wkup", + "flash", + "rcc", + "exti0", + "exti1", + "exti2", + "exti3", + "exti4", + "dma1_channel1", + "dma1_channel2", + "dma1_channel3", + "dma1_channel4", + "dma1_channel5", + "dma1_channel6", + "dma1_channel7", + "adc1", + "usb_hp", + "usb_lp", + "dac", + "comp", + "exti9_5", + "lcd", + "tim9", + "tim10", + "tim11", + "tim2", + "tim3", + "tim4", + "i2c1_ev", + "i2c1_er", + "i2c2_ev", + "i2c2_er", + "spi1", + "spi2", + "usart1", + "usart2", + "usart3", + "exti15_10", + "rtc_alarm", + "usb_fs_wakeup", + "tim6", + "tim7", + "sdio", + "tim5", + "spi3", + "uart4", + "uart5", + "dma2_ch1", + "dma2_ch2", + "dma2_ch3", + "dma2_ch4", + "dma2_ch5", + "aes", + "comp_acq" + ], + "partname_humanreadable": "STM32 L1 series", + "partname_doxygen": "STM32L1", + "includeguard": "LIBOPENCM3_STM32_L1_NVIC_H" +} \ No newline at end of file diff --git a/libopencm3/include/libopencm3/stm32/l1/iwdg.h b/libopencm3/include/libopencm3/stm32/l1/iwdg.h new file mode 100644 index 0000000..699849a --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/l1/iwdg.h @@ -0,0 +1,39 @@ +/** @defgroup iwdg_defines IWDG Defines + +@brief Defined Constants and Types for the STM32L1xx Independent Watchdog +Timer + +@ingroup STM32L1xx_defines + +@version 1.0.0 + +@date 18 August 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_IWDG_H +#define LIBOPENCM3_IWDG_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/l1/lcd.h b/libopencm3/include/libopencm3/stm32/l1/lcd.h new file mode 100644 index 0000000..0a4b02b --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/l1/lcd.h @@ -0,0 +1,231 @@ +/** @defgroup lcd_defines LCD Defines + * + * @ingroup STM32L1xx_defines + * + * @brief Defined Constants and Types for the STM32L1xx LCD Controller + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2014 + * Nikolay Merinov + * + * @date 2 March 2014 + * + * LGPL License Terms @ref lgpl_license + * */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ +#ifndef LIBOPENCM3_LCD_H +#define LIBOPENCM3_LCD_H + +#include +#include + +/* --- LCD registers ------------------------------------------------------ */ +/****************************************************************************/ +/** @defgroup lcd_reg_base LCD register base addresses +@ingroup lcd_defines +*/ +/* @{ */ +/* Control register */ +#define LCD_CR MMIO32(LCD_BASE + 0x00) +/* Frame control register */ +#define LCD_FCR MMIO32(LCD_BASE + 0x04) +/* Status register */ +#define LCD_SR MMIO32(LCD_BASE + 0x08) +/* Clear register */ +#define LCD_CLR MMIO32(LCD_BASE + 0x0C) +/* @} */ + +/* --- LCD display memory ------------------------------------------------- */ +/* Base address of display memory */ +#define LCD_RAM_BASE (LCD_BASE + 0x14) + +/* COM0 memory */ +#define LCD_RAM_COM0 MMIO64(LCD_RAM_BASE + 0x00) +/* COM1 memory */ +#define LCD_RAM_COM1 MMIO64(LCD_RAM_BASE + 0x08) +/* COM2 memory */ +#define LCD_RAM_COM2 MMIO64(LCD_RAM_BASE + 0x10) +/* COM3 memory */ +#define LCD_RAM_COM3 MMIO64(LCD_RAM_BASE + 0x18) +/* COM4 memory */ +#define LCD_RAM_COM4 MMIO64(LCD_RAM_BASE + 0x20) +/* COM5 memory */ +#define LCD_RAM_COM5 MMIO64(LCD_RAM_BASE + 0x28) +/* COM6 memory */ +#define LCD_RAM_COM6 MMIO64(LCD_RAM_BASE + 0x30) +/* COM7 memory */ +#define LCD_RAM_COM7 MMIO64(LCD_RAM_BASE + 0x38) + +/* --- LCD_CR values ------------------------------------------------------ */ +#define LCD_CR_LCDEN (1 << 0) +#define LCD_CR_VSEL (1 << 1) + +#define LCD_CR_DUTY_SHIFT 2 +#define LCD_CR_DUTY_MASK 0x7 +#define LCD_CR_DUTY_STATIC 0x0 +#define LCD_CR_DUTY_1_2 0x1 +#define LCD_CR_DUTY_1_3 0x2 +#define LCD_CR_DUTY_1_4 0x3 +#define LCD_CR_DUTY_1_8 0x4 + +#define LCD_CR_BIAS_SHIFT 5 +#define LCD_CR_BIAS_MASK 0x3 +#define LCD_CR_BIAS_1_4 0x0 +#define LCD_CR_BIAS_1_2 0x1 +#define LCD_CR_BIAS_1_3 0x2 + +#define LCD_CR_MUX_SEG (1 << 7) + +/* --- LCD_FCR values ------------------------------------------------------ */ +#define LCD_FCR_HD (1 << 0) +#define LCD_FCR_SOFIE (1 << 1) +#define LCD_FCR_UDDIE (1 << 3) + +#define LCD_FCR_PON_SHIFT 4 +#define LCD_FCR_PON_MASK 0x7 +#define LCD_FCR_PON_0 0x0 +#define LCD_FCR_PON_1 0x1 +#define LCD_FCR_PON_2 0x2 +#define LCD_FCR_PON_3 0x3 +#define LCD_FCR_PON_4 0x4 +#define LCD_FCR_PON_5 0x5 +#define LCD_FCR_PON_6 0x6 +#define LCD_FCR_PON_7 0x7 + +#define LCD_FCR_DEAD_SHIFT 7 +#define LCD_FCR_DEAD_MASK 0x7 +#define LCD_FCR_DEAD_NONE 0x0 +#define LCD_FCR_DEAD_1_PHASE 0x1 +#define LCD_FCR_DEAD_2_PHASE 0x2 +#define LCD_FCR_DEAD_3_PHASE 0x3 +#define LCD_FCR_DEAD_4_PHASE 0x4 +#define LCD_FCR_DEAD_5_PHASE 0x5 +#define LCD_FCR_DEAD_6_PHASE 0x6 +#define LCD_FCR_DEAD_7_PHASE 0x7 + +#define LCD_FCR_CC_SHIFT 10 +#define LCD_FCR_CC_MASK 0x7 +#define LCD_FCR_CC_0 0x0 +#define LCD_FCR_CC_1 0x1 +#define LCD_FCR_CC_2 0x2 +#define LCD_FCR_CC_3 0x3 +#define LCD_FCR_CC_4 0x4 +#define LCD_FCR_CC_5 0x5 +#define LCD_FCR_CC_6 0x6 +#define LCD_FCR_CC_7 0x7 + +#define LCD_FCR_BLINKF_SHIFT 13 +#define LCD_FCR_BLINKF_MASK 0x7 +#define LCD_FCR_BLINKF_8 0x0 +#define LCD_FCR_BLINKF_16 0x1 +#define LCD_FCR_BLINKF_32 0x2 +#define LCD_FCR_BLINKF_64 0x3 +#define LCD_FCR_BLINKF_128 0x4 +#define LCD_FCR_BLINKF_256 0x5 +#define LCD_FCR_BLINKF_512 0x6 +#define LCD_FCR_BLINKF_1024 0x7 + +#define LCD_FCR_BLINK_SHIFT 16 +#define LCD_FCR_BLINK_MASK 0x3 +#define LCD_FCR_BLINK_DISABLE 0x0 +#define LCD_FCR_BLINK_SEG0_COM0_ENABLE 0x1 +#define LCD_FCR_BLINK_SEG0_ENABLE 0x2 +#define LCD_FCR_BLINK_ALL_ENABLE 0x3 + +#define LCD_FCR_DIV_SHIFT 18 +#define LCD_FCR_DIV_MASK 0xF +#define LCD_FCR_DIV_16 0x0 +#define LCD_FCR_DIV_17 0x1 +#define LCD_FCR_DIV_18 0x2 +#define LCD_FCR_DIV_19 0x3 +#define LCD_FCR_DIV_20 0x4 +#define LCD_FCR_DIV_21 0x5 +#define LCD_FCR_DIV_22 0x6 +#define LCD_FCR_DIV_23 0x7 +#define LCD_FCR_DIV_24 0x8 +#define LCD_FCR_DIV_25 0x9 +#define LCD_FCR_DIV_26 0xA +#define LCD_FCR_DIV_27 0xB +#define LCD_FCR_DIV_28 0xC +#define LCD_FCR_DIV_29 0xD +#define LCD_FCR_DIV_30 0xE +#define LCD_FCR_DIV_31 0xF + +#define LCD_FCR_PS_SHIFT 22 +#define LCD_FCR_PS_MASK 0xF +#define LCD_FCR_PS_1 0x0 +#define LCD_FCR_PS_2 0x1 +#define LCD_FCR_PS_4 0x2 +#define LCD_FCR_PS_8 0x3 +#define LCD_FCR_PS_16 0x4 +#define LCD_FCR_PS_32 0x5 +#define LCD_FCR_PS_64 0x6 +#define LCD_FCR_PS_128 0x7 +#define LCD_FCR_PS_256 0x8 +#define LCD_FCR_PS_512 0x9 +#define LCD_FCR_PS_1024 0xA +#define LCD_FCR_PS_2048 0xB +#define LCD_FCR_PS_4096 0xC +#define LCD_FCR_PS_8192 0xD +#define LCD_FCR_PS_16384 0xE +#define LCD_FCR_PS_32768 0xF + +/* --- LCD_SR values ------------------------------------------------------ */ +#define LCD_SR_ENS (1 << 0) +#define LCD_SR_SOF (1 << 1) +#define LCD_SR_UDR (1 << 2) +#define LCD_SR_UDD (1 << 3) +#define LCD_SR_RDY (1 << 4) +#define LCD_SR_FCRSF (1 << 5) + +/* --- LCD_CLR values ----------------------------------------------------- */ +#define LCD_CLR_SOFC (1 << 1) +#define LCD_CLR_UDDC (1 << 3) + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void lcd_enable(void); +void lcd_update(void); + +void lcd_wait_for_lcd_enabled(void); +void lcd_wait_for_step_up_ready(void); +void lcd_wait_for_update_ready(void); + +int lcd_is_enabled(void); +int lcd_is_step_up_ready(void); +int lcd_is_for_update_ready(void); + +void lcd_set_contrast(uint8_t contrast); +void lcd_set_bias(uint8_t bias); +void lcd_set_duty(uint8_t duty); +void lcd_set_prescaler(uint8_t ps); +void lcd_set_divider(uint8_t div); +void lcd_enable_segment_multiplexing(void); +void lcd_disable_segment_multiplexing(void); +void lcd_set_refresh_frequency(uint32_t frequency); + +END_DECLS + +#endif +/**@}*/ diff --git a/libopencm3/include/libopencm3/stm32/l1/memorymap.h b/libopencm3/include/libopencm3/stm32/l1/memorymap.h new file mode 100644 index 0000000..abdb34d --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/l1/memorymap.h @@ -0,0 +1,126 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_MEMORYMAP_H +#define LIBOPENCM3_MEMORYMAP_H + +#include + +/* --- STM32 specific peripheral definitions ------------------------------- */ + +/* Memory map for all busses */ +#define PERIPH_BASE (0x40000000U) +#define INFO_BASE (0x1ff00000U) +#define PERIPH_BASE_APB1 (PERIPH_BASE + 0x00000) +#define PERIPH_BASE_APB2 (PERIPH_BASE + 0x10000) +#define PERIPH_BASE_AHB (PERIPH_BASE + 0x20000) + +/* Register boundary addresses */ + +/* APB1 */ +#define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) +#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) +#define TIM4_BASE (PERIPH_BASE_APB1 + 0x0800) +#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) +#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) +#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) +#define LCD_BASE (PERIPH_BASE_APB1 + 0x2400) +#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) +#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) +#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) +/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ +#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800) +#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00) +/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ +#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) +#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) +#define USART4_BASE (PERIPH_BASE_APB1 + 0x4c00) +#define USART5_BASE (PERIPH_BASE_APB1 + 0x5000) +#define I2C1_BASE (PERIPH_BASE_APB1 + 0x5400) +#define I2C2_BASE (PERIPH_BASE_APB1 + 0x5800) +#define USB_DEV_FS_BASE (PERIPH_BASE_APB1 + 0x5c00) +#define USB_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000) +/* gap */ +#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) +#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) +#define OPAMP_BASE (PERIPH_BASE_APB1 + 0x7c5c) +#define COMP_BASE (PERIPH_BASE_APB1 + 0x7c00) +#define ROUTING_BASE (PERIPH_BASE_APB1 + 0x7c04) + +/* APB2 */ +#define SYSCFG_BASE (PERIPH_BASE_APB2 + 0x0000) +#define EXTI_BASE (PERIPH_BASE_APB2 + 0x0400) +#define TIM9_BASE (PERIPH_BASE_APB2 + 0x0800) +#define TIM10_BASE (PERIPH_BASE_APB2 + 0x0c00) +#define TIM11_BASE (PERIPH_BASE_APB2 + 0x1000) +/* gap */ +#define ADC_BASE (PERIPH_BASE_APB2 + 0x2400) +/* ADC is the name in the L1 refman, but all other stm32's use ADC1 */ +#define ADC1_BASE ADC_BASE +/* gap */ +#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2c00) +#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000) +/* gap */ +#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) + +/* AHB */ +#define GPIO_PORT_A_BASE (PERIPH_BASE_AHB + 0x00000) +#define GPIO_PORT_B_BASE (PERIPH_BASE_AHB + 0x00400) +#define GPIO_PORT_C_BASE (PERIPH_BASE_AHB + 0x00800) +#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB + 0x00c00) +#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB + 0x01000) +#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB + 0x01400) +#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB + 0x01800) +#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB + 0x01c00) +/* gap */ +#define CRC_BASE (PERIPH_BASE_AHB + 0x03000) +/* gap */ +#define RCC_BASE (PERIPH_BASE_AHB + 0x03800) +#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x03c00) +/* gap */ +#define DMA1_BASE (PERIPH_BASE_AHB + 0x06000) +#define DMA2_BASE (PERIPH_BASE_AHB + 0x04000) + +/* PPIB */ +#define DBGMCU_BASE (PPBI_BASE + 0x00042000) + +/* FSMC */ +#define FSMC_BASE (PERIPH_BASE + 0x60000000) +/* AES */ +#define AES_BASE (PERIPH_BASE + 0x10000000) + +/* Device Electronic Signature */ +#define DESIG_FLASH_SIZE_BASE (INFO_BASE + 0x8004C) +#define DESIG_UNIQUE_ID_BASE (INFO_BASE + 0x80050) +#define DESIG_UNIQUE_ID0 MMIO32(DESIG_UNIQUE_ID_BASE) +#define DESIG_UNIQUE_ID1 MMIO32(DESIG_UNIQUE_ID_BASE + 4) +#define DESIG_UNIQUE_ID2 MMIO32(DESIG_UNIQUE_ID_BASE + 0x14) + +/* ST provided factory calibration values @ 3.0V */ +#define ST_VREFINT_CAL MMIO16(0x1FF80078) +#define ST_TSENSE_CAL1_30C MMIO16(0x1FF8007A) +#define ST_TSENSE_CAL2_110C MMIO16(0x1FF8007E) + +/* Make the map names match those for other families to allow commonality */ +#define SPI1_I2S_BASE SPI1_BASE +#define SPI2_I2S_BASE SPI2_BASE +#define SPI3_I2S_BASE SPI3_BASE + +#endif diff --git a/libopencm3/include/libopencm3/stm32/l1/pwr.h b/libopencm3/include/libopencm3/stm32/l1/pwr.h new file mode 100644 index 0000000..ddcdc07 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/l1/pwr.h @@ -0,0 +1,111 @@ +/** @defgroup pwr_defines PWR Defines + +@brief Defined Constants and Types for the STM32L1xx Power Control + +@ingroup STM32L1xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2011 Stephen Caudle +@author @htmlonly © @endhtmlonly 2012 Karl Palsson + +@date 1 July 2012 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Stephen Caudle + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_PWR_H +#define LIBOPENCM3_PWR_H + +#include + +/* + * This file extends the common STM32 version with definitions only + * applicable to the STM32L1 series of devices. + */ + +/* --- PWR_CR values ------------------------------------------------------- */ + +/* Bits [31:15]: Reserved */ + +/* LPRUN: Low power run mode */ +#define PWR_CR_LPRUN (1 << 14) + +/* VOS[12:11]: Regulator voltage scaling output selection */ +#define PWR_CR_VOS_LSB 11 +/** @defgroup pwr_vos Voltage Scaling Output level selection +@ingroup pwr_defines + +@{*/ +#define PWR_CR_VOS_RANGE1 (0x1 << PWR_CR_VOS_LSB) +#define PWR_CR_VOS_RANGE2 (0x2 << PWR_CR_VOS_LSB) +#define PWR_CR_VOS_RANGE3 (0x3 << PWR_CR_VOS_LSB) +/**@}*/ +#define PWR_CR_VOS_MASK (0x3 << PWR_CR_VOS_LSB) + +/* FWU: Fast wakeup */ +#define PWR_CR_FWU (1 << 10) + +/* ULP: Ultralow power mode */ +#define PWR_CR_ULP (1 << 9) + +/* LPSDSR: Low-power deepsleep/sleep/low power run */ +#define PWR_CR_LPSDSR (1 << 0) /* masks common PWR_CR_LPDS */ + +/* --- PWR_CSR values ------------------------------------------------------- */ + +/* Bits [31:11]: Reserved */ +/* EWUP3: Enable WKUP3 pin */ +#define PWR_CSR_EWUP3 (1 << 10) + +/* EWUP2: Enable WKUP2 pin */ +#define PWR_CSR_EWUP2 (1 << 9) + +/* EWUP1: Enable WKUP1 pin */ +#define PWR_CSR_EWUP1 PWR_CSR_EWUP + +/* REGLPF : Regulator LP flag */ +#define PWR_CSR_REGLPF (1 << 5) + +/* VOSF: Voltage Scaling select flag */ +#define PWR_CSR_VOSF (1 << 4) + +/* VREFINTRDYF: Internal voltage reference (VREFINT) ready flag */ +#define PWR_CSR_VREFINTRDYF (1 << 3) + + + +/* --- Function prototypes ------------------------------------------------- */ + +typedef enum { + RANGE1, + RANGE2, + RANGE3, +} vos_scale_t; + +BEGIN_DECLS + +void pwr_set_vos_scale(vos_scale_t scale); + +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/stm32/l1/rcc.h b/libopencm3/include/libopencm3/stm32/l1/rcc.h new file mode 100644 index 0000000..2b5883f --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/l1/rcc.h @@ -0,0 +1,612 @@ +/** @defgroup rcc_defines RCC Defines + * + * @ingroup STM32L1xx_defines + * + * @brief Defined Constants and Types for the STM32L1xx Reset and Clock + * Control + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2009 + * Federico Ruiz-Ugalde \ + * @author @htmlonly © @endhtmlonly 2009 + * Uwe Hermann + * @author @htmlonly © @endhtmlonly 2012 + * Karl Palsson + * + * @date 11 November 2012 + * + * LGPL License Terms @ref lgpl_license + * */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Uwe Hermann + * Copyright (C) 2009 Federico Ruiz-Ugalde + * Copyright (C) 2012 Karl Palsson + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + * + * Originally based on the F1 code, as it seemed most similar to the L1 + * TODO: very incomplete still! + */ + +/**@{*/ + +#ifndef LIBOPENCM3_RCC_H +#define LIBOPENCM3_RCC_H + +#include + +/* --- RCC registers ------------------------------------------------------- */ + +#define RCC_CR MMIO32(RCC_BASE + 0x00) +#define RCC_ICSCR MMIO32(RCC_BASE + 0x04) +#define RCC_CFGR MMIO32(RCC_BASE + 0x08) +#define RCC_CIR MMIO32(RCC_BASE + 0x0c) +#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x10) +#define RCC_APB2RSTR MMIO32(RCC_BASE + 0x14) +#define RCC_APB1RSTR MMIO32(RCC_BASE + 0x18) +#define RCC_AHBENR MMIO32(RCC_BASE + 0x1c) +#define RCC_APB2ENR MMIO32(RCC_BASE + 0x20) +#define RCC_APB1ENR MMIO32(RCC_BASE + 0x24) +#define RCC_AHBLPENR MMIO32(RCC_BASE + 0x28) +#define RCC_APB2LPENR MMIO32(RCC_BASE + 0x2c) +#define RCC_APB1LPENR MMIO32(RCC_BASE + 0x30) +#define RCC_CSR MMIO32(RCC_BASE + 0x34) + +/* --- RCC_CR values ------------------------------------------------------- */ + +/* RTCPRE[1:0] at 30:29 */ +#define RCC_CR_CSSON (1 << 28) +#define RCC_CR_PLLRDY (1 << 25) +#define RCC_CR_PLLON (1 << 24) +#define RCC_CR_HSEBYP (1 << 18) +#define RCC_CR_HSERDY (1 << 17) +#define RCC_CR_HSEON (1 << 16) +#define RCC_CR_MSIRDY (1 << 9) +#define RCC_CR_MSION (1 << 8) +#define RCC_CR_HSIRDY (1 << 1) +#define RCC_CR_HSION (1 << 0) + +#define RCC_CR_RTCPRE_DIV2 0 +#define RCC_CR_RTCPRE_DIV4 1 +#define RCC_CR_RTCPRE_DIV8 2 +#define RCC_CR_RTCPRE_DIV16 3 +#define RCC_CR_RTCPRE_SHIFT 29 +#define RCC_CR_RTCPRE_MASK 0x3 + +/* --- RCC_ICSCR values ---------------------------------------------------- */ + +#define RCC_ICSCR_MSITRIM_SHIFT 24 +#define RCC_ICSCR_MSITRIM_MASK 0xff +#define RCC_ICSCR_MSICAL_SHIFT 16 +#define RCC_ICSCR_MSICAL_MASK 0xff + +#define RCC_ICSCR_MSIRANGE_SHIFT 13 +#define RCC_ICSCR_MSIRANGE_MASK 0x7 +#define RCC_ICSCR_MSIRANGE_65KHZ 0x0 +#define RCC_ICSCR_MSIRANGE_131KHZ 0x1 +#define RCC_ICSCR_MSIRANGE_262KHZ 0x2 +#define RCC_ICSCR_MSIRANGE_524KHZ 0x3 +#define RCC_ICSCR_MSIRANGE_1MHZ 0x4 +#define RCC_ICSCR_MSIRANGE_2MHZ 0x5 +#define RCC_ICSCR_MSIRANGE_4MHZ 0x6 + +#define RCC_ICSCR_HSITRIM_SHIFT 8 +#define RCC_ICSCR_HSITRIM_MASK 0x1f +#define RCC_ICSCR_HSICAL_SHIFT 0 +#define RCC_ICSCR_HSICAL_MASK 0xff + +/* --- RCC_CFGR values ----------------------------------------------------- */ + +/* MCOPRE */ +#define RCC_CFGR_MCOPRE_DIV1 0 +#define RCC_CFGR_MCOPRE_DIV2 1 +#define RCC_CFGR_MCOPRE_DIV4 2 +#define RCC_CFGR_MCOPRE_DIV8 3 +#define RCC_CFGR_MCOPRE_DIV16 4 + +/* MCO: Microcontroller clock output */ +#define RCC_CFGR_MCO_NOCLK 0x0 +#define RCC_CFGR_MCO_SYSCLK 0x1 +#define RCC_CFGR_MCO_HSICLK 0x2 +#define RCC_CFGR_MCO_MSICLK 0x3 +#define RCC_CFGR_MCO_HSECLK 0x4 +#define RCC_CFGR_MCO_PLLCLK 0x5 +#define RCC_CFGR_MCO_LSICLK 0x6 +#define RCC_CFGR_MCO_LSECLK 0x7 + +/* PLL Output division selection */ +#define RCC_CFGR_PLLDIV_DIV2 0x1 +#define RCC_CFGR_PLLDIV_DIV3 0x2 +#define RCC_CFGR_PLLDIV_DIV4 0x3 +#define RCC_CFGR_PLLDIV_SHIFT 22 +#define RCC_CFGR_PLLDIV_MASK 0x3 + +/* PLLMUL: PLL multiplication factor */ +#define RCC_CFGR_PLLMUL_MUL3 0x0 +#define RCC_CFGR_PLLMUL_MUL4 0x1 +#define RCC_CFGR_PLLMUL_MUL6 0x2 +#define RCC_CFGR_PLLMUL_MUL8 0x3 +#define RCC_CFGR_PLLMUL_MUL12 0x4 +#define RCC_CFGR_PLLMUL_MUL16 0x5 +#define RCC_CFGR_PLLMUL_MUL24 0x6 +#define RCC_CFGR_PLLMUL_MUL32 0x7 +#define RCC_CFGR_PLLMUL_MUL48 0x8 +#define RCC_CFGR_PLLMUL_SHIFT 18 +#define RCC_CFGR_PLLMUL_MASK 0xf + +/* PLLSRC: PLL entry clock source */ +#define RCC_CFGR_PLLSRC_HSI_CLK 0x0 +#define RCC_CFGR_PLLSRC_HSE_CLK 0x1 + +/* PPRE2: APB high-speed prescaler (APB2) */ +#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0 +#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4 +#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5 +#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6 +#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7 + +/* PPRE1: APB low-speed prescaler (APB1) */ +#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0 +#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4 +#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5 +#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6 +#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7 + +/* HPRE: AHB prescaler */ +#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0 +#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8 +#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9 +#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa +#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb +#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc +#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd +#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe +#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf + +/* SWS: System clock switch status */ +#define RCC_CFGR_SWS_SYSCLKSEL_MSICLK 0x0 +#define RCC_CFGR_SWS_SYSCLKSEL_HSICLK 0x1 +#define RCC_CFGR_SWS_SYSCLKSEL_HSECLK 0x2 +#define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK 0x3 + +/* SW: System clock switch */ +#define RCC_CFGR_SW_SYSCLKSEL_MSICLK 0x0 +#define RCC_CFGR_SW_SYSCLKSEL_HSICLK 0x1 +#define RCC_CFGR_SW_SYSCLKSEL_HSECLK 0x2 +#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x3 + +/* --- RCC_CIR values ------------------------------------------------------ */ + +/* Clock security system interrupt clear bit */ +#define RCC_CIR_CSSC (1 << 23) + +/* OSC ready interrupt clear bits */ +#define RCC_CIR_MSIRDYC (1 << 21) +#define RCC_CIR_PLLRDYC (1 << 20) +#define RCC_CIR_HSERDYC (1 << 19) +#define RCC_CIR_HSIRDYC (1 << 18) +#define RCC_CIR_LSERDYC (1 << 17) +#define RCC_CIR_LSIRDYC (1 << 16) + +/* OSC ready interrupt enable bits */ +#define RCC_CIR_MSIRDYIE (1 << 13) +#define RCC_CIR_PLLRDYIE (1 << 12) +#define RCC_CIR_HSERDYIE (1 << 11) +#define RCC_CIR_HSIRDYIE (1 << 10) +#define RCC_CIR_LSERDYIE (1 << 9) +#define RCC_CIR_LSIRDYIE (1 << 8) + +/* Clock security system interrupt flag bit */ +#define RCC_CIR_CSSF (1 << 7) + +/* OSC ready interrupt flag bits */ +#define RCC_CIR_MSIRDYF (1 << 5) /* (**) */ +#define RCC_CIR_PLLRDYF (1 << 4) +#define RCC_CIR_HSERDYF (1 << 3) +#define RCC_CIR_HSIRDYF (1 << 2) +#define RCC_CIR_LSERDYF (1 << 1) +#define RCC_CIR_LSIRDYF (1 << 0) + +/* --- RCC_AHBRSTR values ------------------------------------------------- */ +#define RCC_AHBRSTR_DMA1RST (1 << 24) +#define RCC_AHBRSTR_FLITFRST (1 << 15) +#define RCC_AHBRSTR_CRCRST (1 << 12) +#define RCC_AHBRSTR_GPIOHRST (1 << 5) +#define RCC_AHBRSTR_GPIOERST (1 << 4) +#define RCC_AHBRSTR_GPIODRST (1 << 3) +#define RCC_AHBRSTR_GPIOCRST (1 << 2) +#define RCC_AHBRSTR_GPIOBRST (1 << 1) +#define RCC_AHBRSTR_GPIOARST (1 << 0) + +/* --- RCC_APB2RSTR values ------------------------------------------------- */ + +#define RCC_APB2RSTR_USART1RST (1 << 14) +#define RCC_APB2RSTR_SPI1RST (1 << 12) +#define RCC_APB2RSTR_ADC1RST (1 << 9) +#define RCC_APB2RSTR_TIM11RST (1 << 4) +#define RCC_APB2RSTR_TIM10RST (1 << 3) +#define RCC_APB2RSTR_TIM9RST (1 << 2) +#define RCC_APB2RSTR_SYSCFGRST (1 << 0) + +/* --- RCC_APB1RSTR values ------------------------------------------------- */ + +#define RCC_APB1RSTR_COMPRST (1 << 31) +#define RCC_APB1RSTR_DACRST (1 << 29) +#define RCC_APB1RSTR_PWRRST (1 << 28) +#define RCC_APB1RSTR_USBRST (1 << 23) +#define RCC_APB1RSTR_I2C2RST (1 << 22) +#define RCC_APB1RSTR_I2C1RST (1 << 21) +#define RCC_APB1RSTR_USART3RST (1 << 18) +#define RCC_APB1RSTR_USART2RST (1 << 17) +#define RCC_APB1RSTR_SPI2RST (1 << 14) +#define RCC_APB1RSTR_WWDGRST (1 << 11) +#define RCC_APB1RSTR_LCDRST (1 << 9) +#define RCC_APB1RSTR_TIM7RST (1 << 5) +#define RCC_APB1RSTR_TIM6RST (1 << 4) +#define RCC_APB1RSTR_TIM5RST (1 << 3) +#define RCC_APB1RSTR_TIM4RST (1 << 2) +#define RCC_APB1RSTR_TIM3RST (1 << 1) +#define RCC_APB1RSTR_TIM2RST (1 << 0) + +/* --- RCC_AHBENR values --------------------------------------------------- */ + +/** @defgroup rcc_ahbenr_en RCC_AHBENR enable values +@ingroup STM32L1xx_rcc_defines + +@{*/ +#define RCC_AHBENR_DMA1EN (1 << 24) +#define RCC_AHBENR_FLITFEN (1 << 15) +#define RCC_AHBENR_CRCEN (1 << 12) +#define RCC_AHBENR_GPIOHEN (1 << 5) +#define RCC_AHBENR_GPIOEEN (1 << 4) +#define RCC_AHBENR_GPIODEN (1 << 3) +#define RCC_AHBENR_GPIOCEN (1 << 2) +#define RCC_AHBENR_GPIOBEN (1 << 1) +#define RCC_AHBENR_GPIOAEN (1 << 0) +/*@}*/ + +/* --- RCC_APB2ENR values -------------------------------------------------- */ + +/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values +@ingroup STM32L1xx_rcc_defines + +@{*/ +#define RCC_APB2ENR_USART1EN (1 << 14) +#define RCC_APB2ENR_SPI1EN (1 << 12) +#define RCC_APB2ENR_ADC1EN (1 << 9) +#define RCC_APB2ENR_TIM11EN (1 << 4) +#define RCC_APB2ENR_TIM10EN (1 << 3) +#define RCC_APB2ENR_TIM9EN (1 << 2) +#define RCC_APB2ENR_SYSCFGEN (1 << 0) +/*@}*/ + +/* --- RCC_APB1ENR values -------------------------------------------------- */ + +/** @defgroup rcc_apb1enr_en RCC_APB1ENR enable values +@ingroup STM32L1xx_rcc_defines + +@{*/ +#define RCC_APB1ENR_COMPEN (1 << 31) +#define RCC_APB1ENR_DACEN (1 << 29) +#define RCC_APB1ENR_PWREN (1 << 28) +#define RCC_APB1ENR_USBEN (1 << 23) +#define RCC_APB1ENR_I2C2EN (1 << 22) +#define RCC_APB1ENR_I2C1EN (1 << 21) +#define RCC_APB1ENR_USART3EN (1 << 18) +#define RCC_APB1ENR_USART2EN (1 << 17) +#define RCC_APB1ENR_SPI2EN (1 << 14) +#define RCC_APB1ENR_WWDGEN (1 << 11) +#define RCC_APB1ENR_LCDEN (1 << 9) +#define RCC_APB1ENR_TIM7EN (1 << 5) +#define RCC_APB1ENR_TIM6EN (1 << 4) +#define RCC_APB1ENR_TIM4EN (1 << 2) +#define RCC_APB1ENR_TIM3EN (1 << 1) +#define RCC_APB1ENR_TIM2EN (1 << 0) +/*@}*/ + +/* --- RCC_AHBLPENR -------------------------------------------------------- */ +#define RCC_AHBLPENR_DMA1LPEN (1 << 24) +#define RCC_AHBLPENR_SRAMLPEN (1 << 16) +#define RCC_AHBLPENR_FLITFLPEN (1 << 15) +#define RCC_AHBLPENR_CRCLPEN (1 << 12) +#define RCC_AHBLPENR_GPIOHLPEN (1 << 5) +#define RCC_AHBLPENR_GPIOELPEN (1 << 4) +#define RCC_AHBLPENR_GPIODLPEN (1 << 3) +#define RCC_AHBLPENR_GPIOCLPEN (1 << 2) +#define RCC_AHBLPENR_GPIOBLPEN (1 << 1) +#define RCC_AHBLPENR_GPIOALPEN (1 << 0) + +#define RCC_APB2LPENR_USART1LPEN (1 << 14) +#define RCC_APB2LPENR_SPI1LPEN (1 << 12) +#define RCC_APB2LPENR_ADC1LPEN (1 << 9) +#define RCC_APB2LPENR_TIM11LPEN (1 << 4) +#define RCC_APB2LPENR_TIM10LPEN (1 << 3) +#define RCC_APB2LPENR_TIM9LPEN (1 << 2) +#define RCC_APB2LPENR_SYSCFGLPEN (1 << 0) + +#define RCC_APB1LPENR_COMPLPEN (1 << 31) +#define RCC_APB1LPENR_DACLPEN (1 << 29) +#define RCC_APB1LPENR_PWRLPEN (1 << 28) +#define RCC_APB1LPENR_USBLPEN (1 << 23) +#define RCC_APB1LPENR_I2C2LPEN (1 << 22) +#define RCC_APB1LPENR_I2C1LPEN (1 << 21) +#define RCC_APB1LPENR_USART3LPEN (1 << 18) +#define RCC_APB1LPENR_USART2LPEN (1 << 17) +#define RCC_APB1LPENR_SPI2LPEN (1 << 14) +#define RCC_APB1LPENR_WWDGLPEN (1 << 11) +#define RCC_APB1LPENR_LCDLPEN (1 << 9) +#define RCC_APB1LPENR_TIM7LPEN (1 << 5) +#define RCC_APB1LPENR_TIM6LPEN (1 << 4) +#define RCC_APB1LPENR_TIM4LPEN (1 << 2) +#define RCC_APB1LPENR_TIM3LPEN (1 << 1) +#define RCC_APB1LPENR_TIM2LPEN (1 << 0) + + +/* --- RCC_CSR values ------------------------------------------------------ */ + +#define RCC_CSR_LPWRRSTF (1 << 31) +#define RCC_CSR_WWDGRSTF (1 << 30) +#define RCC_CSR_IWDGRSTF (1 << 29) +#define RCC_CSR_SFTRSTF (1 << 28) +#define RCC_CSR_PORRSTF (1 << 27) +#define RCC_CSR_PINRSTF (1 << 26) +#define RCC_CSR_OBLRSTF (1 << 25) +#define RCC_CSR_RMVF (1 << 24) +#define RCC_CSR_RTCRST (1 << 23) +#define RCC_CSR_RTCEN (1 << 22) +#define RCC_CSR_RTCSEL_SHIFT (16) +#define RCC_CSR_RTCSEL_MASK (0x3) +#define RCC_CSR_RTCSEL_NONE (0x0) +#define RCC_CSR_RTCSEL_LSE (0x1) +#define RCC_CSR_RTCSEL_LSI (0x2) +#define RCC_CSR_RTCSEL_HSI (0x3) +#define RCC_CSR_LSECSSD (1 << 12) +#define RCC_CSR_LSECSSON (1 << 11) +#define RCC_CSR_LSEBYP (1 << 10) +#define RCC_CSR_LSERDY (1 << 9) +#define RCC_CSR_LSEON (1 << 8) +#define RCC_CSR_LSIRDY (1 << 1) +#define RCC_CSR_LSION (1 << 0) + +typedef struct { + uint8_t pll_mul; + uint16_t pll_div; + uint8_t pll_source; + uint32_t flash_config; + uint8_t hpre; + uint8_t ppre1; + uint8_t ppre2; + vos_scale_t voltage_scale; + uint32_t apb1_frequency; + uint32_t apb2_frequency; + uint8_t msi_range; +} clock_scale_t; + +typedef enum { + CLOCK_VRANGE1_HSI_PLL_24MHZ, + CLOCK_VRANGE1_HSI_PLL_32MHZ, + CLOCK_VRANGE1_HSI_RAW_16MHZ, + CLOCK_VRANGE1_HSI_RAW_4MHZ, + CLOCK_VRANGE1_MSI_RAW_4MHZ, + CLOCK_VRANGE1_MSI_RAW_2MHZ, + CLOCK_CONFIG_END +} clock_config_entry_t; + +extern const clock_scale_t clock_config[CLOCK_CONFIG_END]; + + +/* --- Variable definitions ------------------------------------------------ */ +extern uint32_t rcc_ppre1_frequency; +extern uint32_t rcc_ppre2_frequency; + +/* --- Function prototypes ------------------------------------------------- */ + +typedef enum { + PLL, HSE, HSI, MSI, LSE, LSI +} osc_t; + +#define _REG_BIT(base, bit) (((base) << 5) + (bit)) + +enum rcc_periph_clken { + /* AHB peripherals */ + RCC_GPIOA = _REG_BIT(0x1c, 0), + RCC_GPIOB = _REG_BIT(0x1c, 1), + RCC_GPIOC = _REG_BIT(0x1c, 2), + RCC_GPIOD = _REG_BIT(0x1c, 3), + RCC_GPIOE = _REG_BIT(0x1c, 4), + RCC_GPIOH = _REG_BIT(0x1c, 5), + RCC_GPIOF = _REG_BIT(0x1c, 6), + RCC_GPIOG = _REG_BIT(0x1c, 7), + RCC_CRC = _REG_BIT(0x1c, 12), + RCC_FLITF = _REG_BIT(0x1c, 15), + RCC_DMA1 = _REG_BIT(0x1c, 24), + RCC_DMA2 = _REG_BIT(0x1c, 25), + RCC_AES = _REG_BIT(0x1c, 27), + RCC_FSMC = _REG_BIT(0x1c, 30), + + /* APB2 peripherals */ + RCC_SYSCFG = _REG_BIT(0x20, 0), + RCC_TIM9 = _REG_BIT(0x20, 2), + RCC_TIM10 = _REG_BIT(0x20, 3), + RCC_TIM11 = _REG_BIT(0x20, 4), + RCC_ADC1 = _REG_BIT(0x20, 9), + RCC_SDIO = _REG_BIT(0x20, 11), + RCC_SPI1 = _REG_BIT(0x20, 12), + RCC_USART1 = _REG_BIT(0x20, 14), + + /* APB1 peripherals*/ + RCC_TIM2 = _REG_BIT(0x24, 0), + RCC_TIM3 = _REG_BIT(0x24, 1), + RCC_TIM4 = _REG_BIT(0x24, 2), + RCC_TIM5 = _REG_BIT(0x24, 3), + RCC_TIM6 = _REG_BIT(0x24, 4), + RCC_TIM7 = _REG_BIT(0x24, 5), + RCC_LCD = _REG_BIT(0x24, 9), + RCC_WWDG = _REG_BIT(0x24, 11), + RCC_SPI2 = _REG_BIT(0x24, 14), + RCC_SPI3 = _REG_BIT(0x24, 15), + RCC_USART2 = _REG_BIT(0x24, 17), + RCC_USART3 = _REG_BIT(0x24, 18), + RCC_UART4 = _REG_BIT(0x24, 19), + RCC_UART5 = _REG_BIT(0x24, 20), + RCC_I2C1 = _REG_BIT(0x24, 21), + RCC_I2C2 = _REG_BIT(0x24, 22), + RCC_USB = _REG_BIT(0x24, 23), + RCC_PWR = _REG_BIT(0x24, 28), + RCC_DAC = _REG_BIT(0x24, 29), + RCC_COMP = _REG_BIT(0x24, 31), + + /* AHB peripherals */ + SCC_GPIOA = _REG_BIT(0x28, 0), + SCC_GPIOB = _REG_BIT(0x28, 1), + SCC_GPIOC = _REG_BIT(0x28, 2), + SCC_GPIOD = _REG_BIT(0x28, 3), + SCC_GPIOE = _REG_BIT(0x28, 4), + SCC_GPIOH = _REG_BIT(0x28, 5), + SCC_GPIOF = _REG_BIT(0x28, 6), + SCC_GPIOG = _REG_BIT(0x28, 7), + SCC_CRC = _REG_BIT(0x28, 12), + SCC_FLITF = _REG_BIT(0x28, 15), + SCC_SRAM = _REG_BIT(0x28, 16), + SCC_DMA1 = _REG_BIT(0x28, 24), + SCC_DMA2 = _REG_BIT(0x28, 25), + SCC_AES = _REG_BIT(0x28, 27), + SCC_FSMC = _REG_BIT(0x28, 30), + + /* APB2 peripherals */ + SCC_SYSCFG = _REG_BIT(0x2c, 0), + SCC_TIM9 = _REG_BIT(0x2c, 2), + SCC_TIM10 = _REG_BIT(0x2c, 3), + SCC_TIM11 = _REG_BIT(0x2c, 4), + SCC_ADC1 = _REG_BIT(0x2c, 9), + SCC_SDIO = _REG_BIT(0x2c, 11), + SCC_SPI1 = _REG_BIT(0x2c, 12), + SCC_USART1 = _REG_BIT(0x2c, 14), + + /* APB1 peripherals*/ + SCC_TIM2 = _REG_BIT(0x24, 0), + SCC_TIM3 = _REG_BIT(0x24, 1), + SCC_TIM4 = _REG_BIT(0x24, 2), + SCC_TIM5 = _REG_BIT(0x24, 3), + SCC_TIM6 = _REG_BIT(0x24, 4), + SCC_TIM7 = _REG_BIT(0x24, 5), + SCC_LCD = _REG_BIT(0x24, 9), + SCC_WWDG = _REG_BIT(0x24, 11), + SCC_SPI2 = _REG_BIT(0x24, 14), + SCC_SPI3 = _REG_BIT(0x24, 15), + SCC_USART2 = _REG_BIT(0x24, 17), + SCC_USART3 = _REG_BIT(0x24, 18), + SCC_UART4 = _REG_BIT(0x24, 19), + SCC_UART5 = _REG_BIT(0x24, 20), + SCC_I2C1 = _REG_BIT(0x24, 21), + SCC_I2C2 = _REG_BIT(0x24, 22), + SCC_USB = _REG_BIT(0x24, 23), + SCC_PWR = _REG_BIT(0x24, 28), + SCC_DAC = _REG_BIT(0x24, 29), + SCC_COMP = _REG_BIT(0x24, 31), +}; + +enum rcc_periph_rst { + /* AHB peripherals */ + RST_GPIOA = _REG_BIT(0x10, 0), + RST_GPIOB = _REG_BIT(0x10, 1), + RST_GPIOC = _REG_BIT(0x10, 2), + RST_GPIOD = _REG_BIT(0x10, 3), + RST_GPIOE = _REG_BIT(0x10, 4), + RST_GPIOH = _REG_BIT(0x10, 5), + RST_GPIOF = _REG_BIT(0x10, 6), + RST_GPIOG = _REG_BIT(0x10, 7), + RST_CRC = _REG_BIT(0x10, 12), + RST_FLITF = _REG_BIT(0x10, 15), + RST_DMA1 = _REG_BIT(0x10, 24), + RST_DMA2 = _REG_BIT(0x10, 25), + RST_AES = _REG_BIT(0x10, 27), + RST_FSMC = _REG_BIT(0x10, 30), + + /* APB2 peripherals */ + RST_SYSCFG = _REG_BIT(0x14, 0), + RST_TIM9 = _REG_BIT(0x14, 2), + RST_TIM10 = _REG_BIT(0x14, 3), + RST_TIM11 = _REG_BIT(0x14, 4), + RST_ADC1 = _REG_BIT(0x14, 9), + RST_SDIO = _REG_BIT(0x14, 11), + RST_SPI1 = _REG_BIT(0x14, 12), + RST_USART1 = _REG_BIT(0x14, 14), + + /* APB1 peripherals*/ + RST_TIM2 = _REG_BIT(0x18, 0), + RST_TIM3 = _REG_BIT(0x18, 1), + RST_TIM4 = _REG_BIT(0x18, 2), + RST_TIM5 = _REG_BIT(0x18, 3), + RST_TIM6 = _REG_BIT(0x18, 4), + RST_TIM7 = _REG_BIT(0x18, 5), + RST_LCD = _REG_BIT(0x18, 9), + RST_WWDG = _REG_BIT(0x18, 11), + RST_SPI2 = _REG_BIT(0x18, 14), + RST_SPI3 = _REG_BIT(0x18, 15), + RST_USART2 = _REG_BIT(0x18, 17), + RST_USART3 = _REG_BIT(0x18, 18), + RST_UART4 = _REG_BIT(0x18, 19), + RST_UART5 = _REG_BIT(0x18, 20), + RST_I2C1 = _REG_BIT(0x18, 21), + RST_I2C2 = _REG_BIT(0x18, 22), + RST_USB = _REG_BIT(0x18, 23), + RST_PWR = _REG_BIT(0x18, 28), + RST_DAC = _REG_BIT(0x18, 29), + RST_COMP = _REG_BIT(0x18, 31), +}; +#include + +BEGIN_DECLS + +void rcc_osc_ready_int_clear(osc_t osc); +void rcc_osc_ready_int_enable(osc_t osc); +void rcc_osc_ready_int_disable(osc_t osc); +int rcc_osc_ready_int_flag(osc_t osc); +void rcc_css_int_clear(void); +int rcc_css_int_flag(void); +void rcc_wait_for_osc_ready(osc_t osc); +void rcc_wait_for_sysclk_status(osc_t osc); +void rcc_osc_on(osc_t osc); +void rcc_osc_off(osc_t osc); +void rcc_css_enable(void); +void rcc_css_disable(void); +void rcc_osc_bypass_enable(osc_t osc); +void rcc_osc_bypass_disable(osc_t osc); +void rcc_set_sysclk_source(uint32_t clk); +void rcc_set_pll_configuration(uint32_t source, uint32_t multiplier, + uint32_t divisor); +void rcc_set_pll_source(uint32_t pllsrc); +void rcc_set_adcpre(uint32_t adcpre); +void rcc_set_ppre2(uint32_t ppre2); +void rcc_set_ppre1(uint32_t ppre1); +void rcc_set_hpre(uint32_t hpre); +void rcc_set_usbpre(uint32_t usbpre); +void rcc_set_rtcpre(uint32_t rtcpre); +uint32_t rcc_system_clock_source(void); +void rcc_rtc_select_clock(uint32_t clock); +void rcc_clock_setup_msi(const clock_scale_t *clock); +void rcc_clock_setup_hsi(const clock_scale_t *clock); +void rcc_clock_setup_pll(const clock_scale_t *clock); +void rcc_backupdomain_reset(void); + +END_DECLS + +/**@}*/ + +#endif diff --git a/libopencm3/include/libopencm3/stm32/l1/rtc.h b/libopencm3/include/libopencm3/stm32/l1/rtc.h new file mode 100644 index 0000000..3ba885c --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/l1/rtc.h @@ -0,0 +1,36 @@ +/** @defgroup rtc_defines RTC Defines + +@brief Defined Constants and Types for the STM32L1xx RTC + +@ingroup STM32L1xx_defines + +@version 1.0.0 + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_RTC_H +#define LIBOPENCM3_RTC_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/l1/spi.h b/libopencm3/include/libopencm3/stm32/l1/spi.h new file mode 100644 index 0000000..0db17fc --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/l1/spi.h @@ -0,0 +1,37 @@ +/** @defgroup spi_defines SPI Defines + +@brief Defined Constants and Types for the STM32L1xx SPI + +@ingroup STM32L1xx_defines + +@version 1.0.0 + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_SPI_H +#define LIBOPENCM3_SPI_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/l1/syscfg.h b/libopencm3/include/libopencm3/stm32/l1/syscfg.h new file mode 100644 index 0000000..b2e4991 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/l1/syscfg.h @@ -0,0 +1,41 @@ +/** @defgroup syscfg_defines SYSCFG Defines + * + * @ingroup STM32L1xx_defines + * + * @brief Defined Constants and Types for the STM32L1xx Sysconfig + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2013 + * Frantisek Burian + * + * @date 13 January 2014 + * + * LGPL License Terms @ref lgpl_license + * */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Frantisek Burian + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_SYSCFG_H +#define LIBOPENCM3_SYSCFG_H + +#include + +#endif diff --git a/libopencm3/include/libopencm3/stm32/l1/timer.h b/libopencm3/include/libopencm3/stm32/l1/timer.h new file mode 100644 index 0000000..fbe1504 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/l1/timer.h @@ -0,0 +1,89 @@ +/** @defgroup timer_defines Timer Defines + +@brief libopencm3 Defined Constants and Types for the STM32L1xx Timers + +@ingroup STM32L1xx_defines + +@version 1.0.0 + +@date 8 March 2013 + +@author @htmlonly © @endhtmlonly 2011 Fergus Noble + +LGPL License Terms @ref lgpl_license +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_TIMER_H +#define LIBOPENCM3_TIMER_H + +#include + +/* + * TIM2 and TIM5 are now 32bit and the following registers are now 32-bit wide: + * CNT, ARR, CCR1, CCR2, CCR3, CCR4 + */ + +/* Timer 2/3 option register (TIMx_OR) */ +#define TIM_OR(tim_base) MMIO32(tim_base + 0x50) +#define TIM2_OR TIM_OR(TIM2) +#define TIM3_OR TIM_OR(TIM3) + +/* --- TIMx_OR values ---------------------------------------------------- */ + +/* ITR1_RMP */ +/****************************************************************************/ +/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal +Trigger 1 Remap +@ingroup timer_defines + +@{*/ +/** Internal Trigger 1 remapped to timer 10 output compare */ +#define TIM2_OR_ITR1_RMP_TIM10_OC (0x0 << 0) +/** Internal Trigger 1 remapped to timer 5 TGO */ +#define TIM2_OR_ITR1_RMP_TIM5_TGO (0x1 << 0) +/**@}*/ +#define TIM3_OR_ITR1_RMP_MASK (0x1 << 0) + +/* --- TIMx_OR values ---------------------------------------------------- */ + +/* ITR2_RMP */ +/****************************************************************************/ +/** @defgroup tim3_opt_trigger_remap TIM3_OR Timer 3 Option Register Internal Trigger 2 Remap +@ingroup timer_defines + +@{*/ +/** Internal Trigger 1 remapped to timer 11 output compare */ +#define TIM3_OR_ITR2_RMP_TIM8_TRGOU (0x0 << 0) +/** Internal Trigger 1 remapped to timer 5 TGO */ +#define TIM3_OR_ITR2_RMP_PTP (0x1 << 0) +/**@}*/ +#define TIM3_OR_ITR2_RMP_MASK (0x1 << 0) + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void timer_set_option(uint32_t timer_peripheral, uint32_t option); + +END_DECLS + +#endif diff --git a/libopencm3/include/libopencm3/stm32/l1/usart.h b/libopencm3/include/libopencm3/stm32/l1/usart.h new file mode 100644 index 0000000..6fdce0e --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/l1/usart.h @@ -0,0 +1,37 @@ +/** @defgroup usart_defines USART Defines + +@brief Defined Constants and Types for the STM32L1xx USART + +@ingroup STM32L1xx_defines + +@version 1.0.0 + +@date 5 December 2012 + +LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_USART_H +#define LIBOPENCM3_USART_H + +#include + +#endif + diff --git a/libopencm3/include/libopencm3/stm32/memorymap.h b/libopencm3/include/libopencm3/stm32/memorymap.h new file mode 100644 index 0000000..cf4a580 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/memorymap.h @@ -0,0 +1,39 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Fergus Noble + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_MEMORYMAP_COMMON_H +#define LIBOPENCM3_MEMORYMAP_COMMON_H + +#if defined(STM32F0) +# include +#elif defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F3) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." +#endif + +#endif /* LIBOPENCM3_MEMORYMAP_COMMON_H */ diff --git a/libopencm3/include/libopencm3/stm32/otg_fs.h b/libopencm3/include/libopencm3/stm32/otg_fs.h new file mode 100644 index 0000000..29a5a3f --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/otg_fs.h @@ -0,0 +1,350 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* + * This file covers definitions for the USB OTG FS peripheral. + * This is the USB core included in the F105, F107, F2, F4 devices + */ + +#ifndef LIBOPENCM3_OTG_FS_H +#define LIBOPENCM3_OTG_FS_H + +#include +#include + +/* Core Global Control and Status Registers */ +#define OTG_FS_GOTGCTL MMIO32(USB_OTG_FS_BASE + 0x000) +#define OTG_FS_GOTGINT MMIO32(USB_OTG_FS_BASE + 0x004) +#define OTG_FS_GAHBCFG MMIO32(USB_OTG_FS_BASE + 0x008) +#define OTG_FS_GUSBCFG MMIO32(USB_OTG_FS_BASE + 0x00C) +#define OTG_FS_GRSTCTL MMIO32(USB_OTG_FS_BASE + 0x010) +#define OTG_FS_GINTSTS MMIO32(USB_OTG_FS_BASE + 0x014) +#define OTG_FS_GINTMSK MMIO32(USB_OTG_FS_BASE + 0x018) +#define OTG_FS_GRXSTSR MMIO32(USB_OTG_FS_BASE + 0x01C) +#define OTG_FS_GRXSTSP MMIO32(USB_OTG_FS_BASE + 0x020) +#define OTG_FS_GRXFSIZ MMIO32(USB_OTG_FS_BASE + 0x024) +#define OTG_FS_GNPTXFSIZ MMIO32(USB_OTG_FS_BASE + 0x028) +#define OTG_FS_GNPTXSTS MMIO32(USB_OTG_FS_BASE + 0x02C) +#define OTG_FS_GCCFG MMIO32(USB_OTG_FS_BASE + 0x038) +#define OTG_FS_CID MMIO32(USB_OTG_FS_BASE + 0x03C) +#define OTG_FS_HPTXFSIZ MMIO32(USB_OTG_FS_BASE + 0x100) +#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + 0x104 \ + + 4*(x-1)) + +/* Host-mode Control and Status Registers */ +#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400) +#define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + 0x404) +#define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + 0x408) +#define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + 0x410) +#define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + 0x414) +#define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + 0x418) +#define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + 0x440) +#define OTG_FS_HCCHARx MMIO32(USB_OTG_FS_BASE + 0x500) +#define OTG_FS_HCINTx MMIO32(USB_OTG_FS_BASE + 0x508) +#define OTG_FS_HCINTMSKx MMIO32(USB_OTG_FS_BASE + 0x50C) +#define OTG_FS_HCTSIZx MMIO32(USB_OTG_FS_BASE + 0x510) + +/* Device-mode Control and Status Registers */ +#define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + 0x800) +#define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + 0x804) +#define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + 0x808) +#define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + 0x810) +#define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + 0x814) +#define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + 0x818) +#define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + 0x81C) +#define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + 0x828) +#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + 0x82C) +#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + 0x834) +#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + 0x900) +#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + \ + 0x20*(x)) +#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + 0xB00) +#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + \ + 0x20*(x)) +#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + \ + 0x20*(x)) +#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + \ + 0x20*(x)) +#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0x910) +#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0xB10) +#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + \ + 0x20*(x)) +#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + \ + 0x20*(x)) +#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + \ + 0x20*(x)) + +/* Power and clock gating control and status register */ +#define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00) + +/* Data FIFO */ +#define OTG_FS_FIFO(x) (&MMIO32(USB_OTG_FS_BASE \ + + (((x) + 1) \ + << 12))) + +/* Global CSRs */ +/* OTG_FS USB control registers (OTG_HS_GOTGCTL) */ +#define OTG_FS_GOTGCTL_BSVLD (1 << 19) +#define OTG_FS_GOTGCTL_ASVLD (1 << 18) +#define OTG_FS_GOTGCTL_DBCT (1 << 17) +#define OTG_FS_GOTGCTL_CIDSTS (1 << 16) +#define OTG_FS_GOTGCTL_DHNPEN (1 << 11) +#define OTG_FS_GOTGCTL_HSHNPEN (1 << 10) +#define OTG_FS_GOTGCTL_HNPRQ (1 << 9) +#define OTG_FS_GOTGCTL_HNGSCS (1 << 8) +#define OTG_FS_GOTGCTL_SRQ (1 << 1) +#define OTG_FS_GOTGCTL_SRQSCS (1 << 0) + +/* OTG_FS AHB configuration register (OTG_FS_GAHBCFG) */ +#define OTG_FS_GAHBCFG_GINT 0x0001 +#define OTG_FS_GAHBCFG_TXFELVL 0x0080 +#define OTG_FS_GAHBCFG_PTXFELVL 0x0100 + +/* OTG_FS USB configuration register (OTG_FS_GUSBCFG) */ +#define OTG_FS_GUSBCFG_TOCAL 0x00000003 +#define OTG_FS_GUSBCFG_SRPCAP 0x00000100 +#define OTG_FS_GUSBCFG_HNPCAP 0x00000200 +#define OTG_FS_GUSBCFG_TRDT_MASK (0xf << 10) +#define OTG_FS_GUSBCFG_TRDT_16BIT (0x5 << 10) +#define OTG_FS_GUSBCFG_TRDT_8BIT (0x9 << 10) +#define OTG_FS_GUSBCFG_NPTXRWEN 0x00004000 +#define OTG_FS_GUSBCFG_FHMOD 0x20000000 +#define OTG_FS_GUSBCFG_FDMOD 0x40000000 +#define OTG_FS_GUSBCFG_CTXPKT 0x80000000 +#define OTG_FS_GUSBCFG_PHYSEL (1 << 7) + +/* OTG_FS reset register (OTG_FS_GRSTCTL) */ +#define OTG_FS_GRSTCTL_AHBIDL (1 << 31) +/* Bits 30:11 - Reserved */ +#define OTG_FS_GRSTCTL_TXFNUM_MASK (0x1f << 6) +#define OTG_FS_GRSTCTL_TXFFLSH (1 << 5) +#define OTG_FS_GRSTCTL_RXFFLSH (1 << 4) +/* Bit 3 - Reserved */ +#define OTG_FS_GRSTCTL_FCRST (1 << 2) +#define OTG_FS_GRSTCTL_HSRST (1 << 1) +#define OTG_FS_GRSTCTL_CSRST (1 << 0) + +/* OTG_FS interrupt status register (OTG_FS_GINTSTS) */ +#define OTG_FS_GINTSTS_WKUPINT (1 << 31) +#define OTG_FS_GINTSTS_SRQINT (1 << 30) +#define OTG_FS_GINTSTS_DISCINT (1 << 29) +#define OTG_FS_GINTSTS_CIDSCHG (1 << 28) +/* Bit 27 - Reserved */ +#define OTG_FS_GINTSTS_PTXFE (1 << 26) +#define OTG_FS_GINTSTS_HCINT (1 << 25) +#define OTG_FS_GINTSTS_HPRTINT (1 << 24) +/* Bits 23:22 - Reserved */ +#define OTG_FS_GINTSTS_IPXFR (1 << 21) +#define OTG_FS_GINTSTS_INCOMPISOOUT (1 << 21) +#define OTG_FS_GINTSTS_IISOIXFR (1 << 20) +#define OTG_FS_GINTSTS_OEPINT (1 << 19) +#define OTG_FS_GINTSTS_IEPINT (1 << 18) +/* Bits 17:16 - Reserved */ +#define OTG_FS_GINTSTS_EOPF (1 << 15) +#define OTG_FS_GINTSTS_ISOODRP (1 << 14) +#define OTG_FS_GINTSTS_ENUMDNE (1 << 13) +#define OTG_FS_GINTSTS_USBRST (1 << 12) +#define OTG_FS_GINTSTS_USBSUSP (1 << 11) +#define OTG_FS_GINTSTS_ESUSP (1 << 10) +/* Bits 9:8 - Reserved */ +#define OTG_FS_GINTSTS_GONAKEFF (1 << 7) +#define OTG_FS_GINTSTS_GINAKEFF (1 << 6) +#define OTG_FS_GINTSTS_NPTXFE (1 << 5) +#define OTG_FS_GINTSTS_RXFLVL (1 << 4) +#define OTG_FS_GINTSTS_SOF (1 << 3) +#define OTG_FS_GINTSTS_OTGINT (1 << 2) +#define OTG_FS_GINTSTS_MMIS (1 << 1) +#define OTG_FS_GINTSTS_CMOD (1 << 0) + +/* OTG_FS interrupt mask register (OTG_FS_GINTMSK) */ +#define OTG_FS_GINTMSK_MMISM 0x00000002 +#define OTG_FS_GINTMSK_OTGINT 0x00000004 +#define OTG_FS_GINTMSK_SOFM 0x00000008 +#define OTG_FS_GINTMSK_RXFLVLM 0x00000010 +#define OTG_FS_GINTMSK_NPTXFEM 0x00000020 +#define OTG_FS_GINTMSK_GINAKEFFM 0x00000040 +#define OTG_FS_GINTMSK_GONAKEFFM 0x00000080 +#define OTG_FS_GINTMSK_ESUSPM 0x00000400 +#define OTG_FS_GINTMSK_USBSUSPM 0x00000800 +#define OTG_FS_GINTMSK_USBRST 0x00001000 +#define OTG_FS_GINTMSK_ENUMDNEM 0x00002000 +#define OTG_FS_GINTMSK_ISOODRPM 0x00004000 +#define OTG_FS_GINTMSK_EOPFM 0x00008000 +#define OTG_FS_GINTMSK_EPMISM 0x00020000 +#define OTG_FS_GINTMSK_IEPINT 0x00040000 +#define OTG_FS_GINTMSK_OEPINT 0x00080000 +#define OTG_FS_GINTMSK_IISOIXFRM 0x00100000 +#define OTG_FS_GINTMSK_IISOOXFRM 0x00200000 +#define OTG_FS_GINTMSK_IPXFRM 0x00200000 +#define OTG_FS_GINTMSK_PRTIM 0x01000000 +#define OTG_FS_GINTMSK_HCIM 0x02000000 +#define OTG_FS_GINTMSK_PTXFEM 0x04000000 +#define OTG_FS_GINTMSK_CIDSCHGM 0x10000000 +#define OTG_FS_GINTMSK_DISCINT 0x20000000 +#define OTG_FS_GINTMSK_SRQIM 0x40000000 +#define OTG_FS_GINTMSK_WUIM 0x80000000 + +/* OTG_FS Receive Status Pop Register (OTG_FS_GRXSTSP) */ +/* Bits 31:25 - Reserved */ +#define OTG_FS_GRXSTSP_FRMNUM_MASK (0xf << 21) +#define OTG_FS_GRXSTSP_PKTSTS_MASK (0xf << 17) +#define OTG_FS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17) +#define OTG_FS_GRXSTSP_PKTSTS_OUT (0x2 << 17) +#define OTG_FS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17) +#define OTG_FS_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17) +#define OTG_FS_GRXSTSP_PKTSTS_SETUP (0x6 << 17) +#define OTG_FS_GRXSTSP_DPID_MASK (0x3 << 15) +#define OTG_FS_GRXSTSP_DPID_DATA0 (0x0 << 15) +#define OTG_FS_GRXSTSP_DPID_DATA1 (0x2 << 15) +#define OTG_FS_GRXSTSP_DPID_DATA2 (0x1 << 15) +#define OTG_FS_GRXSTSP_DPID_MDATA (0x3 << 15) +#define OTG_FS_GRXSTSP_BCNT_MASK (0x7ff << 4) +#define OTG_FS_GRXSTSP_EPNUM_MASK (0xf << 0) + +/* OTG_FS general core configuration register (OTG_FS_GCCFG) */ +/* Bits 31:22 - Reserved */ +#define OTG_FS_GCCFG_NOVBUSSENS (1 << 21) +#define OTG_FS_GCCFG_SOFOUTEN (1 << 20) +#define OTG_FS_GCCFG_VBUSBSEN (1 << 19) +#define OTG_FS_GCCFG_VBUSASEN (1 << 18) +/* Bit 17 - Reserved */ +#define OTG_FS_GCCFG_PWRDWN (1 << 16) +/* Bits 15:0 - Reserved */ + + +/* Device-mode CSRs */ +/* OTG_FS device control register (OTG_FS_DCTL) */ +/* Bits 31:12 - Reserved */ +#define OTG_FS_DCTL_POPRGDNE (1 << 11) +#define OTG_FS_DCTL_CGONAK (1 << 10) +#define OTG_FS_DCTL_SGONAK (1 << 9) +#define OTG_FS_DCTL_SGINAK (1 << 8) +#define OTG_FS_DCTL_TCTL_MASK (7 << 4) +#define OTG_FS_DCTL_GONSTS (1 << 3) +#define OTG_FS_DCTL_GINSTS (1 << 2) +#define OTG_FS_DCTL_SDIS (1 << 1) +#define OTG_FS_DCTL_RWUSIG (1 << 0) + +/* OTG_FS device configuration register (OTG_FS_DCFG) */ +#define OTG_FS_DCFG_DSPD 0x0003 +#define OTG_FS_DCFG_NZLSOHSK 0x0004 +#define OTG_FS_DCFG_DAD 0x07F0 +#define OTG_FS_DCFG_PFIVL 0x1800 + +/* OTG_FS Device IN Endpoint Common Interrupt Mask Register (OTG_FS_DIEPMSK) */ +/* Bits 31:10 - Reserved */ +#define OTG_FS_DIEPMSK_BIM (1 << 9) +#define OTG_FS_DIEPMSK_TXFURM (1 << 8) +/* Bit 7 - Reserved */ +#define OTG_FS_DIEPMSK_INEPNEM (1 << 6) +#define OTG_FS_DIEPMSK_INEPNMM (1 << 5) +#define OTG_FS_DIEPMSK_ITTXFEMSK (1 << 4) +#define OTG_FS_DIEPMSK_TOM (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_FS_DIEPMSK_EPDM (1 << 1) +#define OTG_FS_DIEPMSK_XFRCM (1 << 0) + +/* OTG_FS Device OUT Endpoint Common Interrupt Mask Register (OTG_FS_DOEPMSK) */ +/* Bits 31:10 - Reserved */ +#define OTG_FS_DOEPMSK_BOIM (1 << 9) +#define OTG_FS_DOEPMSK_OPEM (1 << 8) +/* Bit 7 - Reserved */ +#define OTG_FS_DOEPMSK_B2BSTUP (1 << 6) +/* Bit 5 - Reserved */ +#define OTG_FS_DOEPMSK_OTEPDM (1 << 4) +#define OTG_FS_DOEPMSK_STUPM (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_FS_DOEPMSK_EPDM (1 << 1) +#define OTG_FS_DOEPMSK_XFRCM (1 << 0) + +/* OTG_FS Device Control IN Endpoint 0 Control Register (OTG_FS_DIEPCTL0) */ +#define OTG_FS_DIEPCTL0_EPENA (1 << 31) +#define OTG_FS_DIEPCTL0_EPDIS (1 << 30) +/* Bits 29:28 - Reserved */ +#define OTG_FS_DIEPCTLX_SD0PID (1 << 28) +#define OTG_FS_DIEPCTL0_SNAK (1 << 27) +#define OTG_FS_DIEPCTL0_CNAK (1 << 26) +#define OTG_FS_DIEPCTL0_TXFNUM_MASK (0xf << 22) +#define OTG_FS_DIEPCTL0_STALL (1 << 21) +/* Bit 20 - Reserved */ +#define OTG_FS_DIEPCTL0_EPTYP_MASK (0x3 << 18) +#define OTG_FS_DIEPCTL0_NAKSTS (1 << 17) +/* Bit 16 - Reserved */ +#define OTG_FS_DIEPCTL0_USBAEP (1 << 15) +/* Bits 14:2 - Reserved */ +#define OTG_FS_DIEPCTL0_MPSIZ_MASK (0x3 << 0) +#define OTG_FS_DIEPCTL0_MPSIZ_64 (0x0 << 0) +#define OTG_FS_DIEPCTL0_MPSIZ_32 (0x1 << 0) +#define OTG_FS_DIEPCTL0_MPSIZ_16 (0x2 << 0) +#define OTG_FS_DIEPCTL0_MPSIZ_8 (0x3 << 0) + +/* OTG_FS Device Control OUT Endpoint 0 Control Register (OTG_FS_DOEPCTL0) */ +#define OTG_FS_DOEPCTL0_EPENA (1 << 31) +#define OTG_FS_DOEPCTL0_EPDIS (1 << 30) +/* Bits 29:28 - Reserved */ +#define OTG_FS_DOEPCTLX_SD0PID (1 << 28) +#define OTG_FS_DOEPCTL0_SNAK (1 << 27) +#define OTG_FS_DOEPCTL0_CNAK (1 << 26) +/* Bits 25:22 - Reserved */ +#define OTG_FS_DOEPCTL0_STALL (1 << 21) +#define OTG_FS_DOEPCTL0_SNPM (1 << 20) +#define OTG_FS_DOEPCTL0_EPTYP_MASK (0x3 << 18) +#define OTG_FS_DOEPCTL0_NAKSTS (1 << 17) +/* Bit 16 - Reserved */ +#define OTG_FS_DOEPCTL0_USBAEP (1 << 15) +/* Bits 14:2 - Reserved */ +#define OTG_FS_DOEPCTL0_MPSIZ_MASK (0x3 << 0) +#define OTG_FS_DOEPCTL0_MPSIZ_64 (0x0 << 0) +#define OTG_FS_DOEPCTL0_MPSIZ_32 (0x1 << 0) +#define OTG_FS_DOEPCTL0_MPSIZ_16 (0x2 << 0) +#define OTG_FS_DOEPCTL0_MPSIZ_8 (0x3 << 0) + +/* OTG_FS Device IN Endpoint Interrupt Register (OTG_FS_DIEPINTx) */ +/* Bits 31:8 - Reserved */ +#define OTG_FS_DIEPINTX_TXFE (1 << 7) +#define OTG_FS_DIEPINTX_INEPNE (1 << 6) +/* Bit 5 - Reserved */ +#define OTG_FS_DIEPINTX_ITTXFE (1 << 4) +#define OTG_FS_DIEPINTX_TOC (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_FS_DIEPINTX_EPDISD (1 << 1) +#define OTG_FS_DIEPINTX_XFRC (1 << 0) + +/* OTG_FS Device IN Endpoint Interrupt Register (OTG_FS_DOEPINTx) */ +/* Bits 31:7 - Reserved */ +#define OTG_FS_DOEPINTX_B2BSTUP (1 << 6) +/* Bit 5 - Reserved */ +#define OTG_FS_DOEPINTX_OTEPDIS (1 << 4) +#define OTG_FS_DOEPINTX_STUP (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_FS_DOEPINTX_EPDISD (1 << 1) +#define OTG_FS_DOEPINTX_XFRC (1 << 0) + +/* OTG_FS Device OUT Endpoint 0 Transfer Size Register (OTG_FS_DOEPTSIZ0) */ +/* Bit 31 - Reserved */ +#define OTG_FS_DIEPSIZ0_STUPCNT_1 (0x1 << 29) +#define OTG_FS_DIEPSIZ0_STUPCNT_2 (0x2 << 29) +#define OTG_FS_DIEPSIZ0_STUPCNT_3 (0x3 << 29) +#define OTG_FS_DIEPSIZ0_STUPCNT_MASK (0x3 << 29) +/* Bits 28:20 - Reserved */ +#define OTG_FS_DIEPSIZ0_PKTCNT (1 << 19) +/* Bits 18:7 - Reserved */ +#define OTG_FS_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0) + +#endif diff --git a/libopencm3/include/libopencm3/stm32/otg_hs.h b/libopencm3/include/libopencm3/stm32/otg_hs.h new file mode 100644 index 0000000..b685145 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/otg_hs.h @@ -0,0 +1,398 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_OTG_HS_H +#define LIBOPENCM3_OTG_HS_H + +#include +#include + +/* Core Global Control and Status Registers */ +#define OTG_GOTGCTL 0x000 +#define OTG_GOTGIN 0x004 +#define OTG_GAHBCFG 0x008 +#define OTG_GUSBCFG 0x00C +#define OTG_GRSTCTL 0x010 +#define OTG_GINTSTS 0x014 +#define OTG_GINTMSK 0x018 +#define OTG_GRXSTSR 0x01C +#define OTG_GRXSTSP 0x020 +#define OTG_GRXFSIZ 0x024 +#define OTG_GNPTXFSIZ 0x028 +#define OTG_GNPTXSTS 0x02C +#define OTG_GCCFG 0x038 +#define OTG_CID 0x03C +#define OTG_HPTXFSIZ 0x100 +#define OTG_DIEPTXF(x) (0x104 + 4*(x-1)) + +/* Host-mode Control and Status Registers */ +#define OTG_HCFG 0x400 +#define OTG_HFIR 0x404 +#define OTG_HFNUM 0x408 +#define OTG_HPTXSTS 0x410 +#define OTG_HAINT 0x414 +#define OTG_HAINTMSK 0x418 +#define OTG_HPRT 0x440 +#define OTG_HCCHARx 0x500 +#define OTG_HCINTx 0x508 +#define OTG_HCINTMSKx 0x50C +#define OTG_HCTSIZx 0x510 + +/* Device-mode Control and Status Registers */ +#define OTG_DCFG 0x800 +#define OTG_DCTL 0x804 +#define OTG_DSTS 0x808 +#define OTG_DIEPMSK 0x810 +#define OTG_DOEPMSK 0x814 +#define OTG_DAINT 0x818 +#define OTG_DAINTMSK 0x81C +#define OTG_DVBUSDIS 0x828 +#define OTG_DVBUSPULSE 0x82C +#define OTG_DIEPEMPMSK 0x834 +#define OTG_DIEPCTL0 0x900 +#define OTG_DIEPCTL(x) (0x900 + 0x20*(x)) +#define OTG_DOEPCTL0 0xB00 +#define OTG_DOEPCTL(x) (0xB00 + 0x20*(x)) +#define OTG_DIEPINT(x) (0x908 + 0x20*(x)) +#define OTG_DOEPINT(x) (0xB08 + 0x20*(x)) +#define OTG_DIEPTSIZ0 0x910 +#define OTG_DOEPTSIZ0 0xB10 +#define OTG_DIEPTSIZ(x) (0x910 + 0x20*(x)) +#define OTG_DTXFSTS(x) (0x918 + 0x20*(x)) +#define OTG_DOEPTSIZ(x) (0xB10 + 0x20*(x)) + +/* Power and clock gating control and status register */ +#define OTG_PCGCCTL 0xE00 + +/* Data FIFO */ +#define OTG_FIFO(x) (((x) + 1) << 12) + +/***********************************************************************/ + +/* Core Global Control and Status Registers */ +#define OTG_HS_GOTGCTL MMIO32(USB_OTG_HS_BASE + OTG_GOTGCTL) +#define OTG_HS_GOTGINT MMIO32(USB_OTG_HS_BASE + OTG_GOTGINT) +#define OTG_HS_GAHBCFG MMIO32(USB_OTG_HS_BASE + OTG_GAHBCFG) +#define OTG_HS_GUSBCFG MMIO32(USB_OTG_HS_BASE + OTG_GUSBCFG) +#define OTG_HS_GRSTCTL MMIO32(USB_OTG_HS_BASE + OTG_GRSTCTL) +#define OTG_HS_GINTSTS MMIO32(USB_OTG_HS_BASE + OTG_GINTSTS) +#define OTG_HS_GINTMSK MMIO32(USB_OTG_HS_BASE + OTG_GINTMSK) +#define OTG_HS_GRXSTSR MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSR) +#define OTG_HS_GRXSTSP MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSP) +#define OTG_HS_GRXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GRXFSIZ) +#define OTG_HS_GNPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GNPTXFSIZ) +#define OTG_HS_GNPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_GNPTXSTS) +#define OTG_HS_GCCFG MMIO32(USB_OTG_HS_BASE + OTG_GCCFG) +#define OTG_HS_CID MMIO32(USB_OTG_HS_BASE + OTG_CID) +#define OTG_HS_HPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_HPTXFSIZ) +#define OTG_HS_DIEPTXF(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPTXF(x)) + +/* Host-mode Control and Status Registers */ +#define OTG_HS_HCFG MMIO32(USB_OTG_HS_BASE + OTG_HCFG) +#define OTG_HS_HFIR MMIO32(USB_OTG_HS_BASE + OTG_HFIR) +#define OTG_HS_HFNUM MMIO32(USB_OTG_HS_BASE + OTG_HFNUM) +#define OTG_HS_HPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_HPTXSTS) +#define OTG_HS_HAINT MMIO32(USB_OTG_HS_BASE + OTG_HAINT) +#define OTG_HS_HAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_HAINTMSK) +#define OTG_HS_HPRT MMIO32(USB_OTG_HS_BASE + OTG_HPRT) +#define OTG_HS_HCCHARx MMIO32(USB_OTG_HS_BASE + OTG_HCCHARx) +#define OTG_HS_HCINTx MMIO32(USB_OTG_HS_BASE + OTG_HCINTx) +#define OTG_HS_HCINTMSKx MMIO32(USB_OTG_HS_BASE + OTG_HCINTMSKx) +#define OTG_HS_HCTSIZx MMIO32(USB_OTG_HS_BASE + OTG_HCTSIZx) + +/* Device-mode Control and Status Registers */ +#define OTG_HS_DCFG MMIO32(USB_OTG_HS_BASE + OTG_DCFG) +#define OTG_HS_DCTL MMIO32(USB_OTG_HS_BASE + OTG_DCTL) +#define OTG_HS_DSTS MMIO32(USB_OTG_HS_BASE + OTG_DSTS) +#define OTG_HS_DIEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPMSK) +#define OTG_HS_DOEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DOEPMSK) +#define OTG_HS_DAINT MMIO32(USB_OTG_HS_BASE + OTG_DAINT) +#define OTG_HS_DAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_DAINTMSK) +#define OTG_HS_DVBUSDIS MMIO32(USB_OTG_HS_BASE + OTG_DVBUSDIS) +#define OTG_HS_DVBUSPULSE MMIO32(USB_OTG_HS_BASE + OTG_DVBUSPULSE) +#define OTG_HS_DIEPEMPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPEMPMSK) +#define OTG_HS_DIEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL0) +#define OTG_HS_DIEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL(x)) +#define OTG_HS_DOEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL0) +#define OTG_HS_DOEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL(x)) +#define OTG_HS_DIEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPINT(x)) +#define OTG_HS_DOEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPINT(x)) +#define OTG_HS_DIEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ0) +#define OTG_HS_DOEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ0) +#define OTG_HS_DIEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \ + OTG_DIEPTSIZ(x)) +#define OTG_HS_DTXFSTS(x) MMIO32(USB_OTG_HS_BASE + OTG_DTXFSTS(x)) +#define OTG_HS_DOEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \ + OTG_DOEPTSIZ(x)) + +/* Power and clock gating control and status register */ +#define OTG_HS_PCGCCTL MMIO32(USB_OTG_HS_BASE + OTG_PCGCCTL) + +/* Data FIFO */ +#define OTG_HS_FIFO(x) (&MMIO32(USB_OTG_HS_BASE + OTG_FIFO(x))) + +/* Global CSRs */ +/* OTG_HS USB control registers (OTG_FS_GOTGCTL) */ +#define OTG_HS_GOTGCTL_BSVLD (1 << 19) +#define OTG_HS_GOTGCTL_ASVLD (1 << 18) +#define OTG_HS_GOTGCTL_DBCT (1 << 17) +#define OTG_HS_GOTGCTL_CIDSTS (1 << 16) +#define OTG_HS_GOTGCTL_DHNPEN (1 << 11) +#define OTG_HS_GOTGCTL_HSHNPEN (1 << 10) +#define OTG_HS_GOTGCTL_HNPRQ (1 << 9) +#define OTG_HS_GOTGCTL_HNGSCS (1 << 8) +#define OTG_HS_GOTGCTL_SRQ (1 << 1) +#define OTG_HS_GOTGCTL_SRQSCS (1 << 0) + +/* OTG_FS AHB configuration register (OTG_HS_GAHBCFG) */ +#define OTG_HS_GAHBCFG_GINT 0x0001 +#define OTG_HS_GAHBCFG_TXFELVL 0x0080 +#define OTG_HS_GAHBCFG_PTXFELVL 0x0100 + +/* OTG_FS USB configuration register (OTG_HS_GUSBCFG) */ +#define OTG_HS_GUSBCFG_TOCAL 0x00000003 +#define OTG_HS_GUSBCFG_SRPCAP 0x00000100 +#define OTG_HS_GUSBCFG_HNPCAP 0x00000200 +#define OTG_HS_GUSBCFG_TRDT_MASK (0xf << 10) +#define OTG_HS_GUSBCFG_TRDT_16BIT (0x5 << 10) +#define OTG_HS_GUSBCFG_TRDT_8BIT (0x9 << 10) +#define OTG_HS_GUSBCFG_NPTXRWEN 0x00004000 +#define OTG_HS_GUSBCFG_FHMOD 0x20000000 +#define OTG_HS_GUSBCFG_FDMOD 0x40000000 +#define OTG_HS_GUSBCFG_CTXPKT 0x80000000 +#define OTG_HS_GUSBCFG_PHYSEL (1 << 6) + +/* OTG_FS reset register (OTG_HS_GRSTCTL) */ +#define OTG_HS_GRSTCTL_AHBIDL (1 << 31) +/* Bits 30:11 - Reserved */ +#define OTG_HS_GRSTCTL_TXFNUM_MASK (0x1f << 6) +#define OTG_HS_GRSTCTL_TXFFLSH (1 << 5) +#define OTG_HS_GRSTCTL_RXFFLSH (1 << 4) +/* Bit 3 - Reserved */ +#define OTG_HS_GRSTCTL_FCRST (1 << 2) +#define OTG_HS_GRSTCTL_HSRST (1 << 1) +#define OTG_HS_GRSTCTL_CSRST (1 << 0) + +/* OTG_FS interrupt status register (OTG_HS_GINTSTS) */ +#define OTG_HS_GINTSTS_WKUPINT (1 << 31) +#define OTG_HS_GINTSTS_SRQINT (1 << 30) +#define OTG_HS_GINTSTS_DISCINT (1 << 29) +#define OTG_HS_GINTSTS_CIDSCHG (1 << 28) +/* Bit 27 - Reserved */ +#define OTG_HS_GINTSTS_PTXFE (1 << 26) +#define OTG_HS_GINTSTS_HCINT (1 << 25) +#define OTG_HS_GINTSTS_HPRTINT (1 << 24) +/* Bits 23:22 - Reserved */ +#define OTG_HS_GINTSTS_IPXFR (1 << 21) +#define OTG_HS_GINTSTS_INCOMPISOOUT (1 << 21) +#define OTG_HS_GINTSTS_IISOIXFR (1 << 20) +#define OTG_HS_GINTSTS_OEPINT (1 << 19) +#define OTG_HS_GINTSTS_IEPINT (1 << 18) +/* Bits 17:16 - Reserved */ +#define OTG_HS_GINTSTS_EOPF (1 << 15) +#define OTG_HS_GINTSTS_ISOODRP (1 << 14) +#define OTG_HS_GINTSTS_ENUMDNE (1 << 13) +#define OTG_HS_GINTSTS_USBRST (1 << 12) +#define OTG_HS_GINTSTS_USBSUSP (1 << 11) +#define OTG_HS_GINTSTS_ESUSP (1 << 10) +/* Bits 9:8 - Reserved */ +#define OTG_HS_GINTSTS_GONAKEFF (1 << 7) +#define OTG_HS_GINTSTS_GINAKEFF (1 << 6) +#define OTG_HS_GINTSTS_NPTXFE (1 << 5) +#define OTG_HS_GINTSTS_RXFLVL (1 << 4) +#define OTG_HS_GINTSTS_SOF (1 << 3) +#define OTG_HS_GINTSTS_OTGINT (1 << 2) +#define OTG_HS_GINTSTS_MMIS (1 << 1) +#define OTG_HS_GINTSTS_CMOD (1 << 0) + +/* OTG_FS interrupt mask register (OTG_HS_GINTMSK) */ +#define OTG_HS_GINTMSK_MMISM 0x00000002 +#define OTG_HS_GINTMSK_OTGINT 0x00000004 +#define OTG_HS_GINTMSK_SOFM 0x00000008 +#define OTG_HS_GINTMSK_RXFLVLM 0x00000010 +#define OTG_HS_GINTMSK_NPTXFEM 0x00000020 +#define OTG_HS_GINTMSK_GINAKEFFM 0x00000040 +#define OTG_HS_GINTMSK_GONAKEFFM 0x00000080 +#define OTG_HS_GINTMSK_ESUSPM 0x00000400 +#define OTG_HS_GINTMSK_USBSUSPM 0x00000800 +#define OTG_HS_GINTMSK_USBRST 0x00001000 +#define OTG_HS_GINTMSK_ENUMDNEM 0x00002000 +#define OTG_HS_GINTMSK_ISOODRPM 0x00004000 +#define OTG_HS_GINTMSK_EOPFM 0x00008000 +#define OTG_HS_GINTMSK_EPMISM 0x00020000 +#define OTG_HS_GINTMSK_IEPINT 0x00040000 +#define OTG_HS_GINTMSK_OEPINT 0x00080000 +#define OTG_HS_GINTMSK_IISOIXFRM 0x00100000 +#define OTG_HS_GINTMSK_IISOOXFRM 0x00200000 +#define OTG_HS_GINTMSK_IPXFRM 0x00200000 +#define OTG_HS_GINTMSK_PRTIM 0x01000000 +#define OTG_HS_GINTMSK_HCIM 0x02000000 +#define OTG_HS_GINTMSK_PTXFEM 0x04000000 +#define OTG_HS_GINTMSK_CIDSCHGM 0x10000000 +#define OTG_HS_GINTMSK_DISCINT 0x20000000 +#define OTG_HS_GINTMSK_SRQIM 0x40000000 +#define OTG_HS_GINTMSK_WUIM 0x80000000 + +/* OTG_FS Receive Status Pop Register (OTG_HS_GRXSTSP) */ +/* Bits 31:25 - Reserved */ +#define OTG_HS_GRXSTSP_FRMNUM_MASK (0xf << 21) +#define OTG_HS_GRXSTSP_PKTSTS_MASK (0xf << 17) +#define OTG_HS_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17) +#define OTG_HS_GRXSTSP_PKTSTS_OUT (0x2 << 17) +#define OTG_HS_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17) +#define OTG_HS_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17) +#define OTG_HS_GRXSTSP_PKTSTS_SETUP (0x6 << 17) +#define OTG_HS_GRXSTSP_DPID_MASK (0x3 << 15) +#define OTG_HS_GRXSTSP_DPID_DATA0 (0x0 << 15) +#define OTG_HS_GRXSTSP_DPID_DATA1 (0x2 << 15) +#define OTG_HS_GRXSTSP_DPID_DATA2 (0x1 << 15) +#define OTG_HS_GRXSTSP_DPID_MDATA (0x3 << 15) +#define OTG_HS_GRXSTSP_BCNT_MASK (0x7ff << 4) +#define OTG_HS_GRXSTSP_EPNUM_MASK (0xf << 0) + +/* OTG_FS general core configuration register (OTG_HS_GCCFG) */ +/* Bits 31:21 - Reserved */ +#define OTG_HS_GCCFG_SOFOUTEN (1 << 20) +#define OTG_HS_GCCFG_VBUSBSEN (1 << 19) +#define OTG_HS_GCCFG_VBUSASEN (1 << 18) +/* Bit 17 - Reserved */ +#define OTG_HS_GCCFG_PWRDWN (1 << 16) +/* Bits 15:0 - Reserved */ + + +/* Device-mode CSRs */ +/* OTG_FS device control register (OTG_HS_DCTL) */ +/* Bits 31:12 - Reserved */ +#define OTG_HS_DCTL_POPRGDNE (1 << 11) +#define OTG_HS_DCTL_CGONAK (1 << 10) +#define OTG_HS_DCTL_SGONAK (1 << 9) +#define OTG_HS_DCTL_SGINAK (1 << 8) +#define OTG_HS_DCTL_TCTL_MASK (7 << 4) +#define OTG_HS_DCTL_GONSTS (1 << 3) +#define OTG_HS_DCTL_GINSTS (1 << 2) +#define OTG_HS_DCTL_SDIS (1 << 1) +#define OTG_HS_DCTL_RWUSIG (1 << 0) + +/* OTG_FS device configuration register (OTG_HS_DCFG) */ +#define OTG_HS_DCFG_DSPD 0x0003 +#define OTG_HS_DCFG_NZLSOHSK 0x0004 +#define OTG_HS_DCFG_DAD 0x07F0 +#define OTG_HS_DCFG_PFIVL 0x1800 + +/* OTG_FS Device IN Endpoint Common Interrupt Mask Register (OTG_HS_DIEPMSK) */ +/* Bits 31:10 - Reserved */ +#define OTG_HS_DIEPMSK_BIM (1 << 9) +#define OTG_HS_DIEPMSK_TXFURM (1 << 8) +/* Bit 7 - Reserved */ +#define OTG_HS_DIEPMSK_INEPNEM (1 << 6) +#define OTG_HS_DIEPMSK_INEPNMM (1 << 5) +#define OTG_HS_DIEPMSK_ITTXFEMSK (1 << 4) +#define OTG_HS_DIEPMSK_TOM (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_HS_DIEPMSK_EPDM (1 << 1) +#define OTG_HS_DIEPMSK_XFRCM (1 << 0) + +/* OTG_FS Device OUT Endpoint Common Interrupt Mask Register (OTG_HS_DOEPMSK) */ +/* Bits 31:10 - Reserved */ +#define OTG_HS_DOEPMSK_BOIM (1 << 9) +#define OTG_HS_DOEPMSK_OPEM (1 << 8) +/* Bit 7 - Reserved */ +#define OTG_HS_DOEPMSK_B2BSTUP (1 << 6) +/* Bit 5 - Reserved */ +#define OTG_HS_DOEPMSK_OTEPDM (1 << 4) +#define OTG_HS_DOEPMSK_STUPM (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_HS_DOEPMSK_EPDM (1 << 1) +#define OTG_HS_DOEPMSK_XFRCM (1 << 0) + +/* OTG_FS Device Control IN Endpoint 0 Control Register (OTG_HS_DIEPCTL0) */ +#define OTG_HS_DIEPCTL0_EPENA (1 << 31) +#define OTG_HS_DIEPCTL0_EPDIS (1 << 30) +/* Bits 29:28 - Reserved */ +#define OTG_HS_DIEPCTLX_SD0PID (1 << 28) +#define OTG_HS_DIEPCTL0_SNAK (1 << 27) +#define OTG_HS_DIEPCTL0_CNAK (1 << 26) +#define OTG_HS_DIEPCTL0_TXFNUM_MASK (0xf << 22) +#define OTG_HS_DIEPCTL0_STALL (1 << 21) +/* Bit 20 - Reserved */ +#define OTG_HS_DIEPCTL0_EPTYP_MASK (0x3 << 18) +#define OTG_HS_DIEPCTL0_NAKSTS (1 << 17) +/* Bit 16 - Reserved */ +#define OTG_HS_DIEPCTL0_USBAEP (1 << 15) +/* Bits 14:2 - Reserved */ +#define OTG_HS_DIEPCTL0_MPSIZ_MASK (0x3 << 0) +#define OTG_HS_DIEPCTL0_MPSIZ_64 (0x0 << 0) +#define OTG_HS_DIEPCTL0_MPSIZ_32 (0x1 << 0) +#define OTG_HS_DIEPCTL0_MPSIZ_16 (0x2 << 0) +#define OTG_HS_DIEPCTL0_MPSIZ_8 (0x3 << 0) + +/* OTG_FS Device Control OUT Endpoint 0 Control Register (OTG_HS_DOEPCTL0) */ +#define OTG_HS_DOEPCTL0_EPENA (1 << 31) +#define OTG_HS_DOEPCTL0_EPDIS (1 << 30) +/* Bits 29:28 - Reserved */ +#define OTG_HS_DOEPCTLX_SD0PID (1 << 28) +#define OTG_HS_DOEPCTL0_SNAK (1 << 27) +#define OTG_HS_DOEPCTL0_CNAK (1 << 26) +/* Bits 25:22 - Reserved */ +#define OTG_HS_DOEPCTL0_STALL (1 << 21) +#define OTG_HS_DOEPCTL0_SNPM (1 << 20) +#define OTG_HS_DOEPCTL0_EPTYP_MASK (0x3 << 18) +#define OTG_HS_DOEPCTL0_NAKSTS (1 << 17) +/* Bit 16 - Reserved */ +#define OTG_HS_DOEPCTL0_USBAEP (1 << 15) +/* Bits 14:2 - Reserved */ +#define OTG_HS_DOEPCTL0_MPSIZ_MASK (0x3 << 0) +#define OTG_HS_DOEPCTL0_MPSIZ_64 (0x0 << 0) +#define OTG_HS_DOEPCTL0_MPSIZ_32 (0x1 << 0) +#define OTG_HS_DOEPCTL0_MPSIZ_16 (0x2 << 0) +#define OTG_HS_DOEPCTL0_MPSIZ_8 (0x3 << 0) + +/* OTG_FS Device IN Endpoint Interrupt Register (OTG_HS_DIEPINTx) */ +/* Bits 31:8 - Reserved */ +#define OTG_HS_DIEPINTX_TXFE (1 << 7) +#define OTG_HS_DIEPINTX_INEPNE (1 << 6) +/* Bit 5 - Reserved */ +#define OTG_HS_DIEPINTX_ITTXFE (1 << 4) +#define OTG_HS_DIEPINTX_TOC (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_HS_DIEPINTX_EPDISD (1 << 1) +#define OTG_HS_DIEPINTX_XFRC (1 << 0) + +/* OTG_FS Device IN Endpoint Interrupt Register (OTG_HS_DOEPINTx) */ +/* Bits 31:7 - Reserved */ +#define OTG_HS_DOEPINTX_B2BSTUP (1 << 6) +/* Bit 5 - Reserved */ +#define OTG_HS_DOEPINTX_OTEPDIS (1 << 4) +#define OTG_HS_DOEPINTX_STUP (1 << 3) +/* Bit 2 - Reserved */ +#define OTG_HS_DOEPINTX_EPDISD (1 << 1) +#define OTG_HS_DOEPINTX_XFRC (1 << 0) + +/* OTG_FS Device OUT Endpoint 0 Transfer Size Register (OTG_HS_DOEPTSIZ0) */ +/* Bit 31 - Reserved */ +#define OTG_HS_DIEPSIZ0_STUPCNT_1 (0x1 << 29) +#define OTG_HS_DIEPSIZ0_STUPCNT_2 (0x2 << 29) +#define OTG_HS_DIEPSIZ0_STUPCNT_3 (0x3 << 29) +#define OTG_HS_DIEPSIZ0_STUPCNT_MASK (0x3 << 29) +/* Bits 28:20 - Reserved */ +#define OTG_HS_DIEPSIZ0_PKTCNT (1 << 19) +/* Bits 18:7 - Reserved */ +#define OTG_HS_DIEPSIZ0_XFRSIZ_MASK (0x7f << 0) + +#endif diff --git a/libopencm3/include/libopencm3/stm32/pwr.h b/libopencm3/include/libopencm3/stm32/pwr.h new file mode 100644 index 0000000..b15fcac --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/pwr.h @@ -0,0 +1,38 @@ +/* This provides unification of code over STM32F subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#if defined(STM32F0) +# include +#elif defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F3) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." +#endif + diff --git a/libopencm3/include/libopencm3/stm32/rcc.h b/libopencm3/include/libopencm3/stm32/rcc.h new file mode 100644 index 0000000..1eba465 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/rcc.h @@ -0,0 +1,38 @@ +/* This provides unification of code over STM32F subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#if defined(STM32F0) +# include +#elif defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F3) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." +#endif + diff --git a/libopencm3/include/libopencm3/stm32/rtc.h b/libopencm3/include/libopencm3/stm32/rtc.h new file mode 100644 index 0000000..9b9dd24 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/rtc.h @@ -0,0 +1,36 @@ +/* This provides unification of code over STM32 subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#if defined(STM32F0) +# include +#elif defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." +#endif + diff --git a/libopencm3/include/libopencm3/stm32/sdio.h b/libopencm3/include/libopencm3/stm32/sdio.h new file mode 100644 index 0000000..6695f87 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/sdio.h @@ -0,0 +1,425 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Felix Held + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_SDIO_H +#define LIBOPENCM3_SDIO_H + +#include +#include + +/* --- SDIO registers ------------------------------------------------------ */ + +/* SDIO power control register (SDIO_POWER) */ +#define SDIO_POWER MMIO32(SDIO_BASE + 0x00) + +/* SDI clock control register (SDIO_CLKCR) */ +#define SDIO_CLKCR MMIO32(SDIO_BASE + 0x04) + +/* SDIO argument register (SDIO_ARG) */ +#define SDIO_ARG MMIO32(SDIO_BASE + 0x08) + +/* SDIO command register (SDIO_CMD) */ +#define SDIO_CMD MMIO32(SDIO_BASE + 0x0C) + +/* SDIO command response register (SDIO_RESPCMD) */ +#define SDIO_RESPCMD MMIO32(SDIO_BASE + 0x10) + +/* SDIO response 1..4 register (SDIO_RESPx) */ +#define SDIO_RESP1 MMIO32(SDIO_BASE + 0x14) +#define SDIO_RESP2 MMIO32(SDIO_BASE + 0x18) +#define SDIO_RESP3 MMIO32(SDIO_BASE + 0x1C) +#define SDIO_RESP4 MMIO32(SDIO_BASE + 0x20) + +/* SDIO data timer register (SDIO_DTIMER) */ +#define SDIO_DTIMER MMIO32(SDIO_BASE + 0x24) + +/* SDIO data length register (SDIO_DLEN) */ +#define SDIO_DLEN MMIO32(SDIO_BASE + 0x28) + +/* SDIO data control register (SDIO_DCTRL) */ +#define SDIO_DCTRL MMIO32(SDIO_BASE + 0x2C) + +/* SDIO data counter register (SDIO_DCOUNT) */ +/* read only, write has no effect */ +#define SDIO_DCOUNT MMIO32(SDIO_BASE + 0x30) + +/* SDIO status register (SDIO_STA) */ +#define SDIO_STA MMIO32(SDIO_BASE + 0x34) + +/* SDIO interrupt clear register (SDIO_ICR) */ +#define SDIO_ICR MMIO32(SDIO_BASE + 0x38) + +/* SDIO mask register (SDIO_MASK) */ +#define SDIO_MASK MMIO32(SDIO_BASE + 0x3C) + +/* SDIO FIFO counter register (SDIO_FIFOCNT) */ +#define SDIO_FIFOCNT MMIO32(SDIO_BASE + 0x48) + +/* SDIO data FIFO register (SDIO_FIFO) */ +/* the SDIO data FIFO is 32 32bit words long, beginning at this address */ +#define SDIO_FIFO MMIO32(SDIO_BASE + 0x80) + + +/* --- SDIO_POWER values --------------------------------------------------- */ + +#define SDIO_POWER_PWRCTRL_SHIFT 0 +#define SDIO_POWER_PWRCTRL_PWROFF (0x0 << SDIO_POWER_PWRCTRL_SHIFT) +/* what does "10: Reserved power-up" mean? */ +#define SDIO_POWER_PWRCTRL_RSVPWRUP (0x2 << SDIO_POWER_PWRCTRL_SHIFT) +#define SDIO_POWER_PWRCTRL_PWRON (0x3 << SDIO_POWER_PWRCTRL_SHIFT) + + +/* --- SDIO_POWER values --------------------------------------------------- */ + +/* HWFC_EN: HW Flow Control enable */ +#define SDIO_CLKCR_HWFC_EN (1 << 14) + +/* NEGEDGE: SDIO_CK dephasing selection bit */ +#define SDIO_CLKCR_NEGEDGE (1 << 13) + +/* WIDBUS: Wide bus mode enable bit */ +/* set the width of the data bus */ +#define SDIO_CLKCR_WIDBUS_SHIFT 11 +#define SDIO_CLKCR_WIDBUS_1 (0x0 << SDIO_CLKCR_WIDBUS_SHIFT) +#define SDIO_CLKCR_WIDBUS_4 (0x1 << SDIO_CLKCR_WIDBUS_SHIFT) +#define SDIO_CLKCR_WIDBUS_8 (0x2 << SDIO_CLKCR_WIDBUS_SHIFT) + +/* BYPASS: Clock divider bypass enable bit */ +#define SDIO_CLKCR_BYPASS (1 << 10) + +/* PWRSAV: Power saving configuration bit */ +#define SDIO_CLKCR_PWRSAV (1 << 9) + +/* CLKEN: Clock enable bit */ +#define SDIO_CLKCR_CLKEN (1 << 8) + +/* CLKDIV: Clock divide factor */ +#define SDIO_CLKCR_CLKDIV_SHIFT 0 +#define SDIO_CLKCR_CLKDIV_MSK (0xFF << SDIO_CLKCR_CLKDIV_SHIFT) + + +/* --- SDIO_CMD values ---------------------------------------------------- */ + +/* ATACMD: CE-ATA command */ +#define SDIO_CMD_ATACMD (1 << 14) + +/* nIEN: not Interrupt Enable */ +#define SDIO_CMD_NIEN (1 << 13) + +/* ENCMDcompl: Enable CMD completion */ +#define SDIO_CMD_ENCMDCOMPL (1 << 12) + +/* SDIOSuspend: SD I/O suspend command */ +#define SDIO_CMD_SDIOSUSPEND (1 << 11) + +/* CPSMEN: Command path state machine (CPSM) Enable bit */ +#define SDIO_CMD_CPSMEN (1 << 10) + +/* WAITPEND: CPSM Waits for ends of data transfer (CmdPend internal signal) */ +#define SDIO_CMD_WAITPEND (1 << 9) + +/* WAITINT: CPSM waits for interrupt request */ +#define SDIO_CMD_WAITINT (1 << 8) + +/* WAITRESP: Wait for response bits */ +#define SDIO_CMD_WAITRESP_SHIFT 6 +/* 00: No response, expect CMDSENT flag */ +#define SDIO_CMD_WAITRESP_NO_0 (0x0 << SDIO_CMD_WAITRESP_SHIFT) +/* 01: Short response, expect CMDREND or CCRCFAIL flag */ +#define SDIO_CMD_WAITRESP_SHORT (0x1 << SDIO_CMD_WAITRESP_SHIFT) +/* 10: No response, expect CMDSENT flag */ +#define SDIO_CMD_WAITRESP_NO_2 (0x2 << SDIO_CMD_WAITRESP_SHIFT) +/* 11: Long response, expect CMDREND or CCRCFAIL flag */ +#define SDIO_CMD_WAITRESP_LONG (0x3 << SDIO_CMD_WAITRESP_SHIFT) + +/* CMDINDEX: Command index */ +#define SDIO_CMD_CMDINDEX_SHIFT 0 +#define SDIO_CMD_CMDINDEX_MSK (0x3F << SDIO_CMD_CMDINDEX_SHIFT) + + +/* --- SDIO_RESPCMD values ------------------------------------------------ */ + +#define SDIO_RESPCMD_SHIFT 0 +#define SDIO_RESPCMD_MSK (0x3F << SDIO_RESPCMD_SHIFT) + + +/* --- SDIO_DCTRL values -------------------------------------------------- */ + +/* SDIOEN: SD I/O enable functions */ +#define SDIO_DCTRL_SDIOEN (1 << 11) + +/* RWMOD: Read wait mode */ +/* 0: Read Wait control stopping SDIO_D2 + * 1: Read Wait control using SDIO_CK + */ +#define SDIO_DCTRL_RWMOD (1 << 10) + +/* RWSTOP: Read wait stop */ +/* 0: Read wait in progress if RWSTART bit is set + * 1: Enable for read wait stop if RWSTART bit is set + */ +#define SDIO_DCTRL_RWSTOP (1 << 9) + +/* RWSTART: Read wait start */ +#define SDIO_DCTRL_RWSTART (1 << 8) + +/* DBLOCKSIZE: Data block size */ +/* SDIO_DCTRL_DBLOCKSIZE_n + * block size is 2**n bytes with 0<=n<=14 + */ +#define SDIO_DCTRL_DBLOCKSIZE_SHIFT 4 +#define SDIO_DCTRL_DBLOCKSIZE_0 (0x0 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +#define SDIO_DCTRL_DBLOCKSIZE_1 (0x1 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +#define SDIO_DCTRL_DBLOCKSIZE_2 (0x2 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +#define SDIO_DCTRL_DBLOCKSIZE_3 (0x3 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +#define SDIO_DCTRL_DBLOCKSIZE_4 (0x4 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +#define SDIO_DCTRL_DBLOCKSIZE_5 (0x5 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +#define SDIO_DCTRL_DBLOCKSIZE_6 (0x6 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +#define SDIO_DCTRL_DBLOCKSIZE_7 (0x7 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +#define SDIO_DCTRL_DBLOCKSIZE_8 (0x8 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +#define SDIO_DCTRL_DBLOCKSIZE_9 (0x9 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +#define SDIO_DCTRL_DBLOCKSIZE_10 (0xA << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +#define SDIO_DCTRL_DBLOCKSIZE_11 (0xB << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +#define SDIO_DCTRL_DBLOCKSIZE_12 (0xC << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +#define SDIO_DCTRL_DBLOCKSIZE_13 (0xD << SDIO_DCTRL_DBLOCKSIZE_SHIFT) +#define SDIO_DCTRL_DBLOCKSIZE_14 (0xE << SDIO_DCTRL_DBLOCKSIZE_SHIFT) + +/* DMAEN: DMA enable bit */ +#define SDIO_DCTRL_DMAEN (1 << 3) + +/* DTMODE: Data transfer mode selection 1: Stream or SDIO multi byte transfer */ +#define SDIO_DCTRL_DTMODE (1 << 2) + +/* DTDIR: Data transfer direction selection */ +/* 0: From controller to card. + * 1: From card to controller. + */ +#define SDIO_DCTRL_DTDIR (1 << 1) + +/* DTEN: Data transfer enabled bit */ +#define SDIO_DCTRL_DTEN (1 << 0) + + +/* --- SDIO_STA values ---------------------------------------------------- */ + +/* CEATAEND: CE-ATA command completion signal received for CMD61 */ +#define SDIO_STA_CEATAEND (1 << 23) + +/* SDIOIT: SDIO interrupt received */ +#define SDIO_STA_SDIOIT (1 << 22) + +/* RXDAVL: Data available in receive FIFO */ +#define SDIO_STA_RXDAVL (1 << 21) + +/* TXDAVL: Data available in transmit FIFO */ +#define SDIO_STA_TXDAVL (1 << 20) + +/* RXFIFOE: Receive FIFO empty */ +#define SDIO_STA_RXFIFOE (1 << 19) + +/* TXFIFOE: Transmit FIFO empty */ +/* HW Flow Control enabled -> TXFIFOE signals becomes activated when the FIFO + * contains 2 words. + */ +#define SDIO_STA_TXFIFOE (1 << 18) + +/* RXFIFOF: Receive FIFO full */ +/* HW Flow Control enabled => RXFIFOF signals becomes activated 2 words before + * the FIFO is full. + */ +#define SDIO_STA_RXFIFOF (1 << 17) + +/* TXFIFOF: Transmit FIFO full */ +#define SDIO_STA_TXFIFOF (1 << 16) + +/* RXFIFOHF: Receive FIFO half full: there are at least 8 words in the FIFO */ +#define SDIO_STA_RXFIFOHF (1 << 15) + +/* TXFIFOHE: Transmit FIFO half empty: at least 8 words can be written into + * the FIFO + */ +#define SDIO_STA_TXFIFOHE (1 << 14) + +/* RXACT: Data receive in progress */ +#define SDIO_STA_RXACT (1 << 13) + +/* TXACT: Data transmit in progress */ +#define SDIO_STA_TXACT (1 << 12) + +/* CMDACT: Command transfer in progress */ +#define SDIO_STA_CMDACT (1 << 11) + +/* DBCKEND: Data block sent/received (CRC check passed) */ +#define SDIO_STA_DBCKEND (1 << 10) + +/* STBITERR: Start bit not detected on all data signals in wide bus mode */ +#define SDIO_STA_STBITERR (1 << 9) + +/* DATAEND: Data end (data counter, SDIDCOUNT, is zero) */ +#define SDIO_STA_DATAEND (1 << 8) + +/* CMDSENT: Command sent (no response required) */ +#define SDIO_STA_CMDSENT (1 << 7) + +/* CMDREND: Command response received (CRC check passed) */ +#define SDIO_STA_CMDREND (1 << 6) + +/* RXOVERR: Received FIFO overrun error */ +#define SDIO_STA_RXOVERR (1 << 5) + +/* TXUNDERR: Transmit FIFO underrun error */ +#define SDIO_STA_TXUNDERR (1 << 4) + +/* DTIMEOUT: Data timeout */ +#define SDIO_STA_DTIMEOUT (1 << 3) + +/* CTIMEOUT: Command response timeout */ +#define SDIO_STA_CTIMEOUT (1 << 2) + +/* DCRCFAIL: Data block sent/received (CRC check failed) */ +#define SDIO_STA_DCRCFAIL (1 << 1) + +/* CCRCFAIL: Command response received (CRC check failed) */ +#define SDIO_STA_CCRCFAIL (1 << 0) + + +/* --- SDIO_ICR values ---------------------------------------------------- */ + +/* CEATAENDC: CEATAEND flag clear bit */ +#define SDIO_ICR_CEATAENDC (1 << 23) + +/* SDIOITC: SDIOIT flag clear bit */ +#define SDIO_ICR_SDIOITC (1 << 22) + +/* DBCKENDC: DBCKEND flag clear bit */ +#define SDIO_ICR_DBCKENDC (1 << 10) + +/* STBITERRC: STBITERR flag clear bit */ +#define SDIO_ICR_STBITERRC (1 << 9) + +/* DATAENDC: DATAEND flag clear bit */ +#define SDIO_ICR_DATAENDC (1 << 8) + +/* CMDSENTC: CMDSENT flag clear bit */ +#define SDIO_ICR_CMDSENTC (1 << 7) + +/* CMDRENDC: CMDREND flag clear bit */ +#define SDIO_ICR_CMDRENDC (1 << 6) + +/* RXOVERRC: RXOVERR flag clear bit */ +#define SDIO_ICR_RXOVERRC (1 << 5) + +/* TXUNDERRC: TXUNDERR flag clear bit */ +#define SDIO_ICR_TXUNDERRC (1 << 4) + +/* DTIMEOUTC: DTIMEOUT flag clear bit */ +#define SDIO_ICR_DTIMEOUTC (1 << 3) + +/* CTIMEOUTC: CTIMEOUT flag clear bit */ +#define SDIO_ICR_CTIMEOUTC (1 << 2) + +/* DCRCFAILC: DCRCFAIL flag clear bit */ +#define SDIO_ICR_DCRCFAILC (1 << 1) + +/* CCRCFAILC: CCRCFAIL flag clear bit */ +#define SDIO_ICR_CCRCFAILC (1 << 0) + + +/* --- SDIO_MASK values --------------------------------------------------- */ + +/* CEATAENDIE: CE-ATA command completion signal received interrupt enable */ +#define SDIO_MASK_CEATAENDIE (1 << 23) + +/* SDIOITIE: SDIO mode interrupt received interrupt enable */ +#define SDIO_MASK_SDIOITIE (1 << 22) + +/* RXDAVLIE: Data available in Rx FIFO interrupt enable */ +#define SDIO_MASK_RXDAVLIE (1 << 21) + +/* TXDAVLIE: Data available in Tx FIFO interrupt enable */ +#define SDIO_MASK_TXDAVLIE (1 << 20) + +/* RXFIFOEIE: Rx FIFO empty interrupt enable */ +#define SDIO_MASK_RXFIFOEIE (1 << 19) + +/* TXFIFOEIE: Tx FIFO empty interrupt enable */ +#define SDIO_MASK_TXFIFOEIE (1 << 18) + +/* RXFIFOFIE: Rx FIFO full interrupt enable */ +#define SDIO_MASK_RXFIFOFIE (1 << 17) + +/* TXFIFOFIE: Tx FIFO full interrupt enable */ +#define SDIO_MASK_TXFIFOFIE (1 << 16) + +/* RXFIFOHFIE: Rx FIFO half full interrupt enable */ +#define SDIO_MASK_RXFIFOHFIE (1 << 15) + +/* TXFIFOHEIE: Tx FIFO half empty interrupt enable */ +#define SDIO_MASK_TXFIFOHEIE (1 << 14) + +/* RXACTIE: Data receive acting interrupt enable */ +#define SDIO_MASK_RXACTIE (1 << 13) + +/* TXACTIE: Data transmit acting interrupt enable */ +#define SDIO_MASK_TXACTIE (1 << 12) + +/* CMDACTIE: Command acting interrupt enable */ +#define SDIO_MASK_CMDACTIE (1 << 11) + +/* DBCKENDIE: Data block end interrupt enable */ +#define SDIO_MASK_DBCKENDIE (1 << 10) + +/* STBITERRIE: Start bit error interrupt enable */ +#define SDIO_MASK_STBITERRIE (1 << 9) + +/* DATAENDIE: Data end interrupt enable */ +#define SDIO_MASK_DATAENDIE (1 << 8) + +/* CMDSENTIE: Command sent interrupt enable */ +#define SDIO_MASK_CMDSENTIE (1 << 7) + +/* CMDRENDIE: Command response received interrupt enable */ +#define SDIO_MASK_CMDRENDIE (1 << 6) + +/* RXOVERRIE: Rx FIFO overrun error interrupt enable */ +#define SDIO_MASK_RXOVERRIE (1 << 5) + +/* TXUNDERRIE: Tx FIFO underrun error interrupt enable */ +#define SDIO_MASK_TXUNDERRIE (1 << 4) + +/* DTIMEOUTIE: Data timeout interrupt enable */ +#define SDIO_MASK_DTIMEOUTIE (1 << 3) + +/* CTIMEOUTIE: Command timeout interrupt enable */ +#define SDIO_MASK_CTIMEOUTIE (1 << 2) + +/* DCRCFAILIE: Data CRC fail interrupt enable */ +#define SDIO_MASK_DCRCFAILIE (1 << 1) + +/* CCRCFAILIE: Command CRC fail interrupt enable */ +#define SDIO_MASK_CCRCFAILIE (1 << 0) + + +/* --- Function prototypes ------------------------------------------------- */ + + +/* TODO */ + + +#endif diff --git a/libopencm3/include/libopencm3/stm32/spi.h b/libopencm3/include/libopencm3/stm32/spi.h new file mode 100644 index 0000000..9d0234e --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/spi.h @@ -0,0 +1,38 @@ +/* This provides unification of code over STM32F subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#if defined(STM32F0) +# include +#elif defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F3) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." +#endif + diff --git a/libopencm3/include/libopencm3/stm32/syscfg.h b/libopencm3/include/libopencm3/stm32/syscfg.h new file mode 100644 index 0000000..2113857 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/syscfg.h @@ -0,0 +1,36 @@ +/* This provides unification of code over STM32F subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#if defined(STM32F0) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F3) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." +#endif + diff --git a/libopencm3/include/libopencm3/stm32/timer.h b/libopencm3/include/libopencm3/stm32/timer.h new file mode 100644 index 0000000..96f9985 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/timer.h @@ -0,0 +1,40 @@ +/* This provides unification of code over STM32F subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Piotr Esden-Tempski + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#if defined(STM32F0) +# include +#elif defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F3) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." +#endif + diff --git a/libopencm3/include/libopencm3/stm32/tools.h b/libopencm3/include/libopencm3/stm32/tools.h new file mode 100644 index 0000000..e172433 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/tools.h @@ -0,0 +1,65 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Piotr Esden-Tempski + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_TOOLS_H +#define LIBOPENCM3_TOOLS_H + +/* + * Register accessors / manipulators + */ + +/* Get register content. */ +#define GET_REG(REG) ((uint16_t) *REG) + +/* Set register content. */ +#define SET_REG(REG, VAL) (*REG = (uint16_t)VAL) + +/* Clear register bit. */ +#define CLR_REG_BIT(REG, BIT) SET_REG(REG, (~BIT)) + +/* Clear register bit masking out some bits that must not be touched. */ +#define CLR_REG_BIT_MSK(REG, MSK, BIT) \ + SET_REG(REG, (GET_REG(REG) & MSK & (~BIT))) + +/* Get masked out bit value. */ +#define GET_REG_BIT(REG, BIT) (GET_REG(REG) & BIT) + +/* + * Set/reset a bit in a masked window by using toggle mechanism. + * + * This means that we look at the bits in the bit window designated by + * the mask. If the bit in the masked window is not matching the + * bit mask BIT then we write 1 and if the bit in the masked window is + * matching the bit mask BIT we write 0. + * + * TODO: We may need a faster implementation of that one? + */ +#define TOG_SET_REG_BIT_MSK(REG, MSK, BIT) \ +do { \ + register uint16_t toggle_mask = GET_REG(REG) & (MSK); \ + register uint16_t bit_selector; \ + for (bit_selector = 1; bit_selector; bit_selector <<= 1) { \ + if ((bit_selector & (BIT)) != 0) { \ + toggle_mask ^= bit_selector; \ + } \ + } \ + SET_REG(REG, toggle_mask); \ +} while (0) + +#endif diff --git a/libopencm3/include/libopencm3/stm32/tsc.h b/libopencm3/include/libopencm3/stm32/tsc.h new file mode 100644 index 0000000..26971f0 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/tsc.h @@ -0,0 +1,28 @@ +/* This provides unification of code over STM32F subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#if defined(STM32F0) +# include +#else +# error "stm32 family not defined." +#endif + diff --git a/libopencm3/include/libopencm3/stm32/usart.h b/libopencm3/include/libopencm3/stm32/usart.h new file mode 100644 index 0000000..c85652f --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/usart.h @@ -0,0 +1,38 @@ +/* This provides unification of code over STM32F subfamilies */ + +/* + * This file is part of the libopencm3 project. + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#include +#include + +#if defined(STM32F0) +# include +#elif defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F3) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include +#else +# error "stm32 family not defined." +#endif + diff --git a/libopencm3/include/libopencm3/stm32/usb.h b/libopencm3/include/libopencm3/stm32/usb.h new file mode 100644 index 0000000..ca5c294 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/usb.h @@ -0,0 +1,303 @@ +/** @defgroup adc_defines USB Defines + +@brief Defined Constants and Types for the STM32F1xx USB Module + +@ingroup STM32F1xx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2009 +Piotr Esden-Tempski + +@date 11 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Piotr Esden-Tempski + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#ifndef LIBOPENCM3_USB_H +#define LIBOPENCM3_USB_H + +#include +#include +#include + +/* --- USB base addresses -------------------------------------------------- */ + +/* USB packet buffer memory base address. */ +#define USB_PMA_BASE 0x40006000L + +/* --- USB general registers ----------------------------------------------- */ + +/* USB Control register */ +#define USB_CNTR_REG (&MMIO32(USB_DEV_FS_BASE + 0x40)) +/* USB Interrupt status register */ +#define USB_ISTR_REG (&MMIO32(USB_DEV_FS_BASE + 0x44)) +/* USB Frame number register */ +#define USB_FNR_REG (&MMIO32(USB_DEV_FS_BASE + 0x48)) +/* USB Device address register */ +#define USB_DADDR_REG (&MMIO32(USB_DEV_FS_BASE + 0x4C)) +/* USB Buffer table address register */ +#define USB_BTABLE_REG (&MMIO32(USB_DEV_FS_BASE + 0x50)) + +#define USB_LPMCSR_REG (&MMIO32(USB_DEV_FS_BASE + 0x54)) +#define USB_BDCR_REG (&MMIO32(USB_DEV_FS_BASE + 0x58)) + +/* USB EP register */ +#define USB_EP_REG(EP) (&MMIO32(USB_DEV_FS_BASE) + (EP)) + +/* --- USB control register masks / bits ----------------------------------- */ + +/* Interrupt mask bits, set to 1 to enable interrupt generation */ +#define USB_CNTR_CTRM 0x8000 +#define USB_CNTR_PMAOVRM 0x4000 +#define USB_CNTR_ERRM 0x2000 +#define USB_CNTR_WKUPM 0x1000 +#define USB_CNTR_SUSPM 0x0800 +#define USB_CNTR_RESETM 0x0400 +#define USB_CNTR_SOFM 0x0200 +#define USB_CNTR_ESOFM 0x0100 + +/* Request/Force bits */ +#define USB_CNTR_L1REQM 0x0080 /* F0 port */ +#define USB_CNTR_L1RESUME 0x0020 /* F0 port */ +#define USB_CNTR_RESUME 0x0010 /* Resume request */ +#define USB_CNTR_FSUSP 0x0008 /* Force suspend */ +#define USB_CNTR_LP_MODE 0x0004 /* Low-power mode */ +#define USB_CNTR_PWDN 0x0002 /* Power down */ +#define USB_CNTR_FRES 0x0001 /* Force reset */ + +/* --- USB interrupt status register masks / bits -------------------------- */ + +#define USB_ISTR_CTR 0x8000 /* Correct Transfer */ +#define USB_ISTR_PMAOVR 0x4000 /* Packet Memory Area Over / Underrun */ +#define USB_ISTR_ERR 0x2000 /* Error */ +#define USB_ISTR_WKUP 0x1000 /* Wake up */ +#define USB_ISTR_SUSP 0x0800 /* Suspend mode request */ +#define USB_ISTR_RESET 0x0400 /* USB RESET request */ +#define USB_ISTR_SOF 0x0200 /* Start Of Frame */ +#define USB_ISTR_ESOF 0x0100 /* Expected Start Of Frame */ +#define USB_ISTR_L1REQ 0x0080 +#define USB_ISTR_DIR 0x0010 /* Direction of transaction */ +#define USB_ISTR_EP_ID 0x000F /* Endpoint Identifier */ + +/* --- USB interrupt status register manipulators -------------------------- */ + +/* Note: CTR is read only! */ +#define USB_CLR_ISTR_PMAOVR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_PMAOVR) +#define USB_CLR_ISTR_ERR() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ERR) +#define USB_CLR_ISTR_WKUP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_WKUP) +#define USB_CLR_ISTR_SUSP() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SUSP) +#define USB_CLR_ISTR_RESET() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_RESET) +#define USB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF) +#define USB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF) + +/* --- USB device address register masks / bits ---------------------------- */ + +#define USB_DADDR_ENABLE 0x0080 +#define USB_DADDR_ADDR 0x007F + +#define USB_LPMCSR_BESL_SHIFT 4 +#define USB_LPMCSR_BESL (15 << USB_LPMCSR_BESL_SHIFT) + +#define USB_LPMCSR_REMWAKE (1 << 3) +#define USB_LPMCSR_LPMACK (1 << 1) +#define USB_LPMCSR_LPMEN (1 << 0) + +#define USB_BDCR_DPPU (1 << 15) +#define USB_BDCR_PS2DET (1 << 7) +#define USB_BDCR_SDET (1 << 6) +#define USB_BDCR_PDET (1 << 5) +#define USB_BDCR_DCDET (1 << 4) +#define USB_BDCR_SDEN (1 << 3) +#define USB_BDCR_PDEN (1 << 2) +#define USB_BDCR_DCDEN (1 << 1) +#define USB_BDCR_BCDEN (1 << 0) + +/* --- USB device address register manipulators ---------------------------- */ + +/* --- USB endpoint register offsets --------------------------------------- */ + +#define USB_EP0 0 +#define USB_EP1 1 +#define USB_EP2 2 +#define USB_EP3 3 +#define USB_EP4 4 +#define USB_EP5 5 +#define USB_EP6 6 +#define USB_EP7 7 + +/* --- USB endpoint register masks / bits ---------------------------------- */ + +/* Masks and toggle bits */ +#define USB_EP_RX_CTR 0x8000 /* Correct transfer RX */ +#define USB_EP_RX_DTOG 0x4000 /* Data toggle RX */ +#define USB_EP_RX_STAT 0x3000 /* Endpoint status for RX */ + +#define USB_EP_SETUP 0x0800 /* Setup transaction completed */ +#define USB_EP_TYPE 0x0600 /* Endpoint type */ +#define USB_EP_KIND 0x0100 /* Endpoint kind. + * When set and type=bulk -> double buffer + * When set and type=control -> status out + */ + +#define USB_EP_TX_CTR 0x0080 /* Correct transfer TX */ +#define USB_EP_TX_DTOG 0x0040 /* Data toggle TX */ +#define USB_EP_TX_STAT 0x0030 /* Endpoint status for TX */ + +#define USB_EP_ADDR 0x000F /* Endpoint Address */ + +/* Masking all toggle bits */ +#define USB_EP_NTOGGLE_MSK (USB_EP_RX_CTR | \ + USB_EP_SETUP | \ + USB_EP_TYPE | \ + USB_EP_KIND | \ + USB_EP_TX_CTR | \ + USB_EP_ADDR) + +/* All non toggle bits plus EP_RX toggle bits */ +#define USB_EP_RX_STAT_TOG_MSK (USB_EP_RX_STAT | USB_EP_NTOGGLE_MSK) +/* All non toggle bits plus EP_TX toggle bits */ +#define USB_EP_TX_STAT_TOG_MSK (USB_EP_TX_STAT | USB_EP_NTOGGLE_MSK) + +/* Endpoint status bits for USB_EP_RX_STAT bit field */ +#define USB_EP_RX_STAT_DISABLED 0x0000 +#define USB_EP_RX_STAT_STALL 0x1000 +#define USB_EP_RX_STAT_NAK 0x2000 +#define USB_EP_RX_STAT_VALID 0x3000 + +/* Endpoint status bits for USB_EP_TX_STAT bit field */ +#define USB_EP_TX_STAT_DISABLED 0x0000 +#define USB_EP_TX_STAT_STALL 0x0010 +#define USB_EP_TX_STAT_NAK 0x0020 +#define USB_EP_TX_STAT_VALID 0x0030 + +/* Endpoint type bits for USB_EP_TYPE bit field */ +#define USB_EP_TYPE_BULK 0x0000 +#define USB_EP_TYPE_CONTROL 0x0200 +#define USB_EP_TYPE_ISO 0x0400 +#define USB_EP_TYPE_INTERRUPT 0x0600 + +/* --- USB endpoint register manipulators ---------------------------------- */ + +/* + * Set USB endpoint tx/rx status. + * + * USB status field is changed using an awkward toggle mechanism, that + * is why we use some helper macros for that. + */ +#define USB_SET_EP_RX_STAT(EP, STAT) \ + TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_RX_STAT_TOG_MSK, STAT) + +#define USB_SET_EP_TX_STAT(EP, STAT) \ + TOG_SET_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_TX_STAT_TOG_MSK, STAT) + +/* + * Macros for clearing and setting USB endpoint register bits that do + * not use the toggle mechanism. + * + * Because the register contains some bits that use the toggle + * mechanism we need a helper macro here. Otherwise the code gets really messy. + */ +#define USB_CLR_EP_NTOGGLE_BIT(EP, BIT) \ + CLR_REG_BIT_MSK(USB_EP_REG(EP), USB_EP_NTOGGLE_MSK, BIT) + +#define USB_CLR_EP_RX_CTR(EP) \ + USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_RX_CTR) + +#define USB_CLR_EP_TX_CTR(EP) \ + USB_CLR_EP_NTOGGLE_BIT(EP, USB_EP_TX_CTR) + +#define USB_SET_EP_TYPE(EP, TYPE) \ + SET_REG(USB_EP_REG(EP), \ + (GET_REG(USB_EP_REG(EP)) & \ + (USB_EP_NTOGGLE_MSK & \ + (~USB_EP_TYPE))) | TYPE) + +#define USB_SET_EP_KIND(EP) \ + SET_REG(USB_EP_REG(EP), \ + (GET_REG(USB_EP_REG(EP)) & \ + (USB_EP_NTOGGLE_MSK & \ + (~USB_EP_KIND))) | USB_EP_KIND) + +#define USB_CLR_EP_KIND(EP) \ + SET_REG(USB_EP_REG(EP), \ + (GET_REG(USB_EP_REG(EP)) & \ + (USB_EP_NTOGGLE_MSK & (~USB_EP_KIND)))) + +#define USB_SET_EP_STAT_OUT(EP) USB_SET_EP_KIND(EP) +#define USB_CLR_EP_STAT_OUT(EP) USB_CLR_EP_KIND(EP) + +#define USB_SET_EP_ADDR(EP, ADDR) \ + SET_REG(USB_EP_REG(EP), \ + ((GET_REG(USB_EP_REG(EP)) & \ + (USB_EP_NTOGGLE_MSK & \ + (~USB_EP_ADDR))) | ADDR)) + +/* Macros for clearing DTOG bits */ +#define USB_CLR_EP_TX_DTOG(EP) \ + SET_REG(USB_EP_REG(EP), \ + GET_REG(USB_EP_REG(EP)) & \ + (USB_EP_NTOGGLE_MSK | USB_EP_TX_DTOG)) + +#define USB_CLR_EP_RX_DTOG(EP) \ + SET_REG(USB_EP_REG(EP), \ + GET_REG(USB_EP_REG(EP)) & \ + (USB_EP_NTOGGLE_MSK | USB_EP_RX_DTOG)) + +/* --- USB BTABLE registers ------------------------------------------------ */ + +#define USB_GET_BTABLE GET_REG(USB_BTABLE_REG) + +#define USB_EP_TX_ADDR(EP) \ + ((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 0) * 2)) + +#define USB_EP_TX_COUNT(EP) \ + ((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 2) * 2)) + +#define USB_EP_RX_ADDR(EP) \ + ((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 4) * 2)) + +#define USB_EP_RX_COUNT(EP) \ + ((uint32_t *)(USB_PMA_BASE + (USB_GET_BTABLE + EP * 8 + 6) * 2)) + +/* --- USB BTABLE manipulators --------------------------------------------- */ + +#define USB_GET_EP_TX_ADDR(EP) GET_REG(USB_EP_TX_ADDR(EP)) +#define USB_GET_EP_TX_COUNT(EP) GET_REG(USB_EP_TX_COUNT(EP)) +#define USB_GET_EP_RX_ADDR(EP) GET_REG(USB_EP_RX_ADDR(EP)) +#define USB_GET_EP_RX_COUNT(EP) GET_REG(USB_EP_RX_COUNT(EP)) +#define USB_SET_EP_TX_ADDR(EP, ADDR) SET_REG(USB_EP_TX_ADDR(EP), ADDR) +#define USB_SET_EP_TX_COUNT(EP, COUNT) SET_REG(USB_EP_TX_COUNT(EP), COUNT) +#define USB_SET_EP_RX_ADDR(EP, ADDR) SET_REG(USB_EP_RX_ADDR(EP), ADDR) +#define USB_SET_EP_RX_COUNT(EP, COUNT) SET_REG(USB_EP_RX_COUNT(EP), COUNT) + +#define USB_GET_EP_TX_BUFF(EP) \ + (USB_PMA_BASE + (uint8_t *)(USB_GET_EP_TX_ADDR(EP) * 2)) + +#define USB_GET_EP_RX_BUFF(EP) \ + (USB_PMA_BASE + (uint8_t *)(USB_GET_EP_RX_ADDR(EP) * 2)) + +#endif + +/**@}*/ + diff --git a/libopencm3/include/libopencm3/stm32/usb_desc.h b/libopencm3/include/libopencm3/stm32/usb_desc.h new file mode 100644 index 0000000..fa87264 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/usb_desc.h @@ -0,0 +1,101 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2009 Piotr Esden-Tempski + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_USB_DESC +#define LIBOPENCM3_USB_DESC + +/* Descriptor types */ +#define USB_DT_DEVICE 0x01 +#define USB_DT_CONF 0x02 +#define USB_DT_STRING 0x03 +#define USB_DT_INTERFACE 0x04 +#define USB_DT_ENDPOINT 0x05 + +struct usb_desc_head { + uint8_t length; /* Descriptor size 0x012 */ + uint8_t type; /* Descriptor type ID */ +}; + +struct usb_device_desc { + struct usb_desc_head h; /* Size 0x12, ID 0x01 */ + uint16_t bcd_usb; /* USB Version */ + uint8_t class; /* Device class */ + uint8_t sub_class; /* Subclass code */ + uint8_t protocol; /* Protocol code */ + uint8_t max_psize; /* Maximum packet size -> 64bytes */ + uint16_t vendor; /* Vendor number */ + uint16_t product; /* Device number */ + uint16_t bcd_dev; /* Device version */ + uint8_t man_desc; /* Index of manufacturer string desc */ + uint8_t prod_desc; /* Index of product string desc */ + uint8_t sn_desc; /* Index of serial number string desc */ + uint8_t num_conf; /* Number of possible configurations */ +}; + +struct usb_conf_desc_header { + struct usb_desc_head h; /* Size 0x09, Id 0x02 */ + uint16_t tot_leng; /* Total length of data */ + uint8_t num_int; /* Number of interfaces */ + uint8_t conf_val; /* Configuration selector */ + uint8_t conf_desc; /* Index of conf string desc */ + uint8_t attr; /* Attribute bitmap: + * 7 : Bus powered + * 6 : Self powered + * 5 : Remote wakeup + * 4..0 : Reserved -> 0000 + */ + uint8_t max_power; /* Maximum power consumption in 2mA steps */ +}; + +struct usb_int_desc_header { + struct usb_desc_head h; /* Size 0x09, Id 0x04 */ + uint8_t iface_num; /* Interface id number */ + uint8_t alt_setting; /* Alternative setting selector */ + uint8_t num_endp; /* Endpoints used */ + uint8_t class; /* Interface class */ + uint8_t sub_class; /* Subclass code */ + uint8_t protocol; /* Protocol code */ + uint8_t iface_desc; /* Index of interface string desc */ +}; + +struct usb_ep_desc { + struct usb_desc_head h; /* Size 0x07, Id 0x05 */ + uint8_t ep_addr; /* Endpoint address: + 0..3 : Endpoint Number + 4..6 : Reserved -> 0 + 7 : Direction 0=out 1=in */ + uint8_t ep_attr; /* Endpoint attributes */ + uint16_t max_psize; /* Maximum packet size -> 64bytes */ + uint8_t interval; /* Interval for polling endpoint + data. Ignored for bulk & control + endpoints. */ +}; + +struct usb_conf_desc { + struct usb_conf_desc_header cdh; + struct usb_int_desc_header idh; + struct usb_ep_desc ep[]; +}; + +struct usb_string_desc { + struct usb_desc_head h; /* Size > 0x02, Id 0x03 */ + uint16_t string[]; /* String UTF16 encoded */ +}; + +#endif diff --git a/libopencm3/include/libopencm3/stm32/wwdg.h b/libopencm3/include/libopencm3/stm32/wwdg.h new file mode 100644 index 0000000..ef75f09 --- /dev/null +++ b/libopencm3/include/libopencm3/stm32/wwdg.h @@ -0,0 +1,83 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Thomas Otto + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_WWDG_H +#define LIBOPENCM3_WWDG_H + +#include +#include + +/* --- WWDG registers ------------------------------------------------------ */ + +/* Control register (WWDG_CR) */ +#define WWDG_CR MMIO32(WWDG_BASE + 0x00) + +/* Configuration register (WWDG_CFR) */ +#define WWDG_CFR MMIO32(WWDG_BASE + 0x04) + +/* Status register (WWDG_SR) */ +#define WWDG_SR MMIO32(WWDG_BASE + 0x08) + +/* --- WWDG_CR values ------------------------------------------------------ */ + +/* Bits [31:8]: Reserved */ + +/* WDGA: Activation bit */ +#define WWDG_CR_WDGA (1 << 7) + +/* T[6:0]: 7-bit counter (MSB to LSB) */ +#define WWDG_CR_T_LSB 0 +#define WWDG_CR_T0 (1 << 0) +#define WWDG_CR_T1 (1 << 1) +#define WWDG_CR_T2 (1 << 2) +#define WWDG_CR_T3 (1 << 3) +#define WWDG_CR_T4 (1 << 4) +#define WWDG_CR_T5 (1 << 5) +#define WWDG_CR_T6 (1 << 6) + +/* --- WWDG_CFR values ----------------------------------------------------- */ + +/* Bits [31:10]: Reserved */ + +/* EWI: Early wakeup interrupt */ +#define WWDG_CFR_EWI (1 << 9) + +/* WDGTB[8:7]: Timer base */ +#define WWDG_CFR_WDGTB_LSB 7 +#define WWDG_CFR_WDGTB_CK_DIV1 0x0 +#define WWDG_CFR_WDGTB_CK_DIV2 0x1 +#define WWDG_CFR_WDGTB_CK_DIV4 0x2 +#define WWDG_CFR_WDGTB_CK_DIV8 0x3 + +/* W[6:0]: 7-bit window value */ +#define WWDG_CFG_W_LSB 0 +#define WWDG_CFG_W (1 << 0) + +/* --- WWDG_SR values ------------------------------------------------------ */ + +/* Bits [31:1]: Reserved */ + +/* EWIF: Early wakeup interrupt flag */ +#define WWDG_SR_EWIF (1 << 0) + +/* --- WWDG function prototypes---------------------------------------------- */ + +/* TODO */ + +#endif diff --git a/libopencm3/include/libopencm3/usb/cdc.h b/libopencm3/include/libopencm3/usb/cdc.h new file mode 100644 index 0000000..20b7836 --- /dev/null +++ b/libopencm3/include/libopencm3/usb/cdc.h @@ -0,0 +1,162 @@ +/** @defgroup usb_cdc_defines USB CDC Type Definitions + +@brief Defined Constants and Types for the USB CDC Type Definitions + +@ingroup USB_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 +Gareth McMullin + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#ifndef __CDC_H +#define __CDC_H + +/* Definitions of Communications Device Class from + * "Universal Serial Bus Class Definitions for Communications Devices + * Revision 1.2" + */ + +/* Table 2: Communications Device Class Code */ +#define USB_CLASS_CDC 0x02 + +/* Table 4: Class Subclass Code */ +#define USB_CDC_SUBCLASS_DLCM 0x01 +#define USB_CDC_SUBCLASS_ACM 0x02 +/* ... */ + +/* Table 5 Communications Interface Class Control Protocol Codes */ +#define USB_CDC_PROTOCOL_NONE 0x00 +#define USB_CDC_PROTOCOL_AT 0x01 +/* ... */ + +/* Table 6: Data Interface Class Code */ +#define USB_CLASS_DATA 0x0A + +/* Table 12: Type Values for the bDescriptorType Field */ +#define CS_INTERFACE 0x24 +#define CS_ENDPOINT 0x25 + +/* Table 13: bDescriptor SubType in Communications Class Functional + * Descriptors */ +#define USB_CDC_TYPE_HEADER 0x00 +#define USB_CDC_TYPE_CALL_MANAGEMENT 0x01 +#define USB_CDC_TYPE_ACM 0x02 +/* ... */ +#define USB_CDC_TYPE_UNION 0x06 +/* ... */ + +/* Table 15: Class-Specific Descriptor Header Format */ +struct usb_cdc_header_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint16_t bcdCDC; +} __attribute__((packed)); + +/* Table 16: Union Interface Functional Descriptor */ +struct usb_cdc_union_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bControlInterface; + uint8_t bSubordinateInterface0; + /* ... */ +} __attribute__((packed)); + + +/* Definitions for Abstract Control Model devices from: + * "Universal Serial Bus Communications Class Subclass Specification for + * PSTN Devices" + */ + +/* Table 3: Call Management Functional Descriptor */ +struct usb_cdc_call_management_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bmCapabilities; + uint8_t bDataInterface; +} __attribute__((packed)); + +/* Table 4: Abstract Control Management Functional Descriptor */ +struct usb_cdc_acm_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bmCapabilities; +} __attribute__((packed)); + +/* Table 13: Class-Specific Request Codes for PSTN subclasses */ +/* ... */ +#define USB_CDC_REQ_SET_LINE_CODING 0x20 +/* ... */ +#define USB_CDC_REQ_SET_CONTROL_LINE_STATE 0x22 +/* ... */ + +/* Table 17: Line Coding Structure */ +struct usb_cdc_line_coding { + uint32_t dwDTERate; + uint8_t bCharFormat; + uint8_t bParityType; + uint8_t bDataBits; +} __attribute__((packed)); + +enum usb_cdc_line_coding_bCharFormat { + USB_CDC_1_STOP_BITS = 0, + USB_CDC_1_5_STOP_BITS = 1, + USB_CDC_2_STOP_BITS = 2, +}; + +enum usb_cdc_line_coding_bParityType { + USB_CDC_NO_PARITY = 0, + USB_CDC_ODD_PARITY = 1, + USB_CDC_EVEN_PARITY = 2, + USB_CDC_MARK_PARITY = 3, + USB_CDC_SPACE_PARITY = 4, +}; + +/* Table 30: Class-Specific Notification Codes for PSTN subclasses */ +/* ... */ +#define USB_CDC_NOTIFY_SERIAL_STATE 0x20 +/* ... */ + +/* Notification Structure */ +struct usb_cdc_notification { + uint8_t bmRequestType; + uint8_t bNotification; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} __attribute__((packed)); + +#endif + +/**@}*/ + diff --git a/libopencm3/include/libopencm3/usb/dfu.h b/libopencm3/include/libopencm3/usb/dfu.h new file mode 100644 index 0000000..b7f028c --- /dev/null +++ b/libopencm3/include/libopencm3/usb/dfu.h @@ -0,0 +1,102 @@ +/** @defgroup usb_dfu_defines USB DFU Type Definitions + +@brief Defined Constants and Types for the USB DFU Type Definitions + +@ingroup USB_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 +Gareth McMullin + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#ifndef __DFU_H +#define __DFU_H + +enum dfu_req { + DFU_DETACH, + DFU_DNLOAD, + DFU_UPLOAD, + DFU_GETSTATUS, + DFU_CLRSTATUS, + DFU_GETSTATE, + DFU_ABORT, +}; + +enum dfu_status { + DFU_STATUS_OK, + DFU_STATUS_ERR_TARGET, + DFU_STATUS_ERR_FILE, + DFU_STATUS_ERR_WRITE, + DFU_STATUS_ERR_ERASE, + DFU_STATUS_ERR_CHECK_ERASED, + DFU_STATUS_ERR_PROG, + DFU_STATUS_ERR_VERIFY, + DFU_STATUS_ERR_ADDRESS, + DFU_STATUS_ERR_NOTDONE, + DFU_STATUS_ERR_FIRMWARE, + DFU_STATUS_ERR_VENDOR, + DFU_STATUS_ERR_USBR, + DFU_STATUS_ERR_POR, + DFU_STATUS_ERR_UNKNOWN, + DFU_STATUS_ERR_STALLEDPKT, +}; + +enum dfu_state { + STATE_APP_IDLE, + STATE_APP_DETACH, + STATE_DFU_IDLE, + STATE_DFU_DNLOAD_SYNC, + STATE_DFU_DNBUSY, + STATE_DFU_DNLOAD_IDLE, + STATE_DFU_MANIFEST_SYNC, + STATE_DFU_MANIFEST, + STATE_DFU_MANIFEST_WAIT_RESET, + STATE_DFU_UPLOAD_IDLE, + STATE_DFU_ERROR, +}; + +#define DFU_FUNCTIONAL 0x21 +struct usb_dfu_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bmAttributes; +#define USB_DFU_CAN_DOWNLOAD 0x01 +#define USB_DFU_CAN_UPLOAD 0x02 +#define USB_DFU_MANIFEST_TOLERANT 0x04 +#define USB_DFU_WILL_DETACH 0x08 + + uint16_t wDetachTimeout; + uint16_t wTransferSize; + uint16_t bcdDFUVersion; +} __attribute__((packed)); + +#endif + +/**@}*/ + diff --git a/libopencm3/include/libopencm3/usb/doc-usb.h b/libopencm3/include/libopencm3/usb/doc-usb.h new file mode 100644 index 0000000..faa01b1 --- /dev/null +++ b/libopencm3/include/libopencm3/usb/doc-usb.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 Generic USB + +@version 1.0.0 + +@date 10 March 2013 + +API documentation for Generic USB. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup USB Generic USB +Libraries for Generic USB. + +@version 1.0.0 + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup USB_defines Generic USB Defines + +@brief Defined Constants and Types for Generic USB. + +@version 1.0.0 + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/libopencm3/include/libopencm3/usb/hid.h b/libopencm3/include/libopencm3/usb/hid.h new file mode 100644 index 0000000..87f4924 --- /dev/null +++ b/libopencm3/include/libopencm3/usb/hid.h @@ -0,0 +1,59 @@ +/** @defgroup usb_hid_defines USB HID Type Definitions + +@brief Defined Constants and Types for the USB HID Type Definitions + +@ingroup USB_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 +Gareth McMullin + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#ifndef __HID_H +#define __HID_H + +#include + +#define USB_CLASS_HID 3 + +#define USB_DT_HID 0x21 +#define USB_DT_REPORT 0x22 + +struct usb_hid_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdHID; + uint8_t bCountryCode; + uint8_t bNumDescriptors; +} __attribute__((packed)); + +#endif + +/**@}*/ + diff --git a/libopencm3/include/libopencm3/usb/msc.h b/libopencm3/include/libopencm3/usb/msc.h new file mode 100644 index 0000000..cf9c54a --- /dev/null +++ b/libopencm3/include/libopencm3/usb/msc.h @@ -0,0 +1,93 @@ +/** @defgroup usb_msc_defines USB MSC Type Definitions + +@brief Defined Constants and Types for the USB MSC Type Definitions + +@ingroup USB_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2013 +Weston Schmidt +Pavol Rusnak + +@date 27 June 2013 + +LGPL License Terms @ref lgpl_license +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Weston Schmidt + * Copyright (C) 2013 Pavol Rusnak + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#ifndef __MSC_H +#define __MSC_H + +typedef struct _usbd_mass_storage usbd_mass_storage; + +/* Definitions of Mass Storage Class from: + * + * (A) "Universal Serial Bus Mass Storage Class Bulk-Only Transport + * Revision 1.0" + * + * (B) "Universal Serial Bus Mass Storage Class Specification Overview + * Revision 1.0" + */ + +/* (A) Table 4.5: Mass Storage Device Class Code */ +#define USB_CLASS_MSC 0x08 + +/* (B) Table 2.1: Class Subclass Code */ +#define USB_MSC_SUBCLASS_RBC 0x01 +#define USB_MSC_SUBCLASS_ATAPI 0x02 +#define USB_MSC_SUBCLASS_UFI 0x04 +#define USB_MSC_SUBCLASS_SCSI 0x06 +#define USB_MSC_SUBCLASS_LOCKABLE 0x07 +#define USB_MSC_SUBCLASS_IEEE1667 0x08 + +/* (B) Table 3.1 Mass Storage Interface Class Control Protocol Codes */ +#define USB_MSC_PROTOCOL_CBI 0x00 +#define USB_MSC_PROTOCOL_CBI_ALT 0x01 +#define USB_MSC_PROTOCOL_BBB 0x50 + +/* (B) Table 4.1 Mass Storage Request Codes */ +#define USB_MSC_REQ_CODES_ADSC 0x00 +#define USB_MSC_REQ_CODES_GET 0xFC +#define USB_MSC_REQ_CODES_PUT 0xFD +#define USB_MSC_REQ_CODES_GML 0xFE +#define USB_MSC_REQ_CODES_BOMSR 0xFF + +/* (A) Table 3.1/3.2 Class-Specific Request Codes */ +#define USB_MSC_REQ_BULK_ONLY_RESET 0xFF +#define USB_MSC_REQ_GET_MAX_LUN 0xFE + +usbd_mass_storage *usb_msc_init(usbd_device *usbd_dev, + uint8_t ep_in, uint8_t ep_in_size, + uint8_t ep_out, uint8_t ep_out_size, + const char *vendor_id, + const char *product_id, + const char *product_revision_level, + const uint32_t block_count, + int (*read_block)(uint32_t lba, uint8_t *copy_to), + int (*write_block)(uint32_t lba, const uint8_t *copy_from)); + +#endif + +/**@}*/ diff --git a/libopencm3/include/libopencm3/usb/usbd.h b/libopencm3/include/libopencm3/usb/usbd.h new file mode 100644 index 0000000..b50c65d --- /dev/null +++ b/libopencm3/include/libopencm3/usb/usbd.h @@ -0,0 +1,120 @@ +/** @defgroup usb_driver_defines USB Drivers + +@brief Defined Constants and Types for the USB Drivers + +@ingroup USB_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 +Gareth McMullin + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#ifndef __USBD_H +#define __USBD_H + +#include + +BEGIN_DECLS + + +enum usbd_request_return_codes { + USBD_REQ_NOTSUPP = 0, + USBD_REQ_HANDLED = 1, + USBD_REQ_NEXT_CALLBACK = 2, +}; + +typedef struct _usbd_driver usbd_driver; +typedef struct _usbd_device usbd_device; + +extern const usbd_driver stm32f103_usb_driver; +extern const usbd_driver stm32f107_usb_driver; +extern const usbd_driver stm32f207_usb_driver; +#define otgfs_usb_driver stm32f107_usb_driver +#define otghs_usb_driver stm32f207_usb_driver + +/* */ +extern usbd_device * usbd_init(const usbd_driver *driver, + const struct usb_device_descriptor *dev, + const struct usb_config_descriptor *conf, + const char **strings, int num_strings, + uint8_t *control_buffer, + uint16_t control_buffer_size); + +extern void usbd_register_reset_callback(usbd_device *usbd_dev, + void (*callback)(void)); +extern void usbd_register_suspend_callback(usbd_device *usbd_dev, + void (*callback)(void)); +extern void usbd_register_resume_callback(usbd_device *usbd_dev, + void (*callback)(void)); +extern void usbd_register_sof_callback(usbd_device *usbd_dev, + void (*callback)(void)); + +typedef int (*usbd_control_callback)(usbd_device *usbd_dev, + struct usb_setup_data *req, uint8_t **buf, uint16_t *len, + void (**complete)(usbd_device *usbd_dev, + struct usb_setup_data *req)); + +/* */ +extern int usbd_register_control_callback(usbd_device *usbd_dev, uint8_t type, + uint8_t type_mask, + usbd_control_callback callback); + +/* */ +extern int usbd_register_set_config_callback(usbd_device *usbd_dev, + void (*callback)(usbd_device *usbd_dev, uint16_t wValue)); + +/* Functions to be provided by the hardware abstraction layer */ +extern void usbd_poll(usbd_device *usbd_dev); +extern void usbd_disconnect(usbd_device *usbd_dev, bool disconnected); + +extern void usbd_ep_setup(usbd_device *usbd_dev, uint8_t addr, uint8_t type, + uint16_t max_size, + void (*callback)(usbd_device *usbd_dev, uint8_t ep)); + +extern uint16_t usbd_ep_write_packet(usbd_device *usbd_dev, uint8_t addr, + const void *buf, uint16_t len); + +extern uint16_t usbd_ep_read_packet(usbd_device *usbd_dev, uint8_t addr, + void *buf, uint16_t len); + +extern void usbd_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, + uint8_t stall); +extern uint8_t usbd_ep_stall_get(usbd_device *usbd_dev, uint8_t addr); + +extern void usbd_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak); + +/* Optional */ +extern void usbd_cable_connect(usbd_device *usbd_dev, uint8_t on); + +END_DECLS + +#endif + +/**@}*/ + diff --git a/libopencm3/include/libopencm3/usb/usbstd.h b/libopencm3/include/libopencm3/usb/usbstd.h new file mode 100644 index 0000000..f85ec82 --- /dev/null +++ b/libopencm3/include/libopencm3/usb/usbstd.h @@ -0,0 +1,255 @@ +/** @defgroup usb_type_defines USB Standard Structure Definitions + +@brief Defined Constants and Types for the USB Standard Structure +Definitions + +@ingroup USB_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2010 +Gareth McMullin + +@date 10 March 2013 + +A set of structure definitions for the USB control structures +defined in chapter 9 of the "Univeral Serial Bus Specification Revision 2.0" +Available from the USB Implementers Forum - http://www.usb.org/ + +LGPL License Terms @ref lgpl_license +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2010 Gareth McMullin + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#ifndef __USBSTD_H +#define __USBSTD_H + +#include +#include + +/* + * This file contains structure definitions for the USB control structures + * defined in chapter 9 of the "Univeral Serial Bus Specification Revision 2.0" + * Available from the USB Implementers Forum - http://www.usb.org/ + */ + +/* USB Setup Data structure - Table 9-2 */ +struct usb_setup_data { + uint8_t bmRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} __attribute__((packed)); + +/* Class Definition */ +#define USB_CLASS_VENDOR 0xFF + +/* bmRequestType bit definitions */ +#define USB_REQ_TYPE_IN 0x80 +#define USB_REQ_TYPE_STANDARD 0x00 +#define USB_REQ_TYPE_CLASS 0x20 +#define USB_REQ_TYPE_VENDOR 0x40 +#define USB_REQ_TYPE_DEVICE 0x00 +#define USB_REQ_TYPE_INTERFACE 0x01 +#define USB_REQ_TYPE_ENDPOINT 0x02 + +#define USB_REQ_TYPE_DIRECTION 0x80 +#define USB_REQ_TYPE_TYPE 0x60 +#define USB_REQ_TYPE_RECIPIENT 0x1F + +/* USB Standard Request Codes - Table 9-4 */ +#define USB_REQ_GET_STATUS 0 +#define USB_REQ_CLEAR_FEATURE 1 +/* Reserved for future use: 2 */ +#define USB_REQ_SET_FEATURE 3 +/* Reserved for future use: 3 */ +#define USB_REQ_SET_ADDRESS 5 +#define USB_REQ_GET_DESCRIPTOR 6 +#define USB_REQ_SET_DESCRIPTOR 7 +#define USB_REQ_GET_CONFIGURATION 8 +#define USB_REQ_SET_CONFIGURATION 9 +#define USB_REQ_GET_INTERFACE 10 +#define USB_REQ_SET_INTERFACE 11 +#define USB_REQ_SET_SYNCH_FRAME 12 + +/* USB Descriptor Types - Table 9-5 */ +#define USB_DT_DEVICE 1 +#define USB_DT_CONFIGURATION 2 +#define USB_DT_STRING 3 +#define USB_DT_INTERFACE 4 +#define USB_DT_ENDPOINT 5 +#define USB_DT_DEVICE_QUALIFIER 6 +#define USB_DT_OTHER_SPEED_CONFIGURATION 7 +#define USB_DT_INTERFACE_POWER 8 +/* From ECNs */ +#define USB_DT_OTG 9 +#define USB_DT_DEBUG 10 +#define USB_DT_INTERFACE_ASSOCIATION 11 + +/* USB Standard Feature Selectors - Table 9-6 */ +#define USB_FEAT_ENDPOINT_HALT 0 +#define USB_FEAT_DEVICE_REMOTE_WAKEUP 1 +#define USB_FEAT_TEST_MODE 2 + +/* Information Returned by a GetStatus() Request to a Device - Figure 9-4 */ +#define USB_DEV_STATUS_SELF_POWERED 0x01 +#define USB_DEV_STATUS_REMOTE_WAKEUP 0x02 + +/* USB Standard Device Descriptor - Table 9-8 */ +struct usb_device_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint16_t idVendor; + uint16_t idProduct; + uint16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} __attribute__((packed)); + +#define USB_DT_DEVICE_SIZE sizeof(struct usb_device_descriptor) + +/* USB Device_Qualifier Descriptor - Table 9-9 + * Not used in this implementation. + */ +struct usb_device_qualifier_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint8_t bNumConfigurations; + uint8_t bReserved; +} __attribute__((packed)); + +/* USB Standard Configuration Descriptor - Table 9-10 */ +struct usb_config_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t bMaxPower; + + /* Descriptor ends here. The following are used internally: */ + const struct usb_interface { + int num_altsetting; + const struct usb_iface_assoc_descriptor *iface_assoc; + const struct usb_interface_descriptor *altsetting; + } *interface; +} __attribute__((packed)); +#define USB_DT_CONFIGURATION_SIZE 9 + +/* USB Configuration Descriptor bmAttributes bit definitions */ +#define USB_CONFIG_ATTR_SELF_POWERED 0x40 +#define USB_CONFIG_ATTR_REMOTE_WAKEUP 0x20 + +/* Other Speed Configuration is the same as Configuration Descriptor. + * - Table 9-11 + */ + +/* USB Standard Interface Descriptor - Table 9-12 */ +struct usb_interface_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; + + /* Descriptor ends here. The following are used internally: */ + const struct usb_endpoint_descriptor *endpoint; + const void *extra; + int extralen; +} __attribute__((packed)); +#define USB_DT_INTERFACE_SIZE 9 + +/* USB Standard Endpoint Descriptor - Table 9-13 */ +struct usb_endpoint_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint16_t wMaxPacketSize; + uint8_t bInterval; +} __attribute__((packed)); +#define USB_DT_ENDPOINT_SIZE sizeof(struct usb_endpoint_descriptor) + +/* USB Endpoint Descriptor bmAttributes bit definitions */ +#define USB_ENDPOINT_ATTR_CONTROL 0x00 +#define USB_ENDPOINT_ATTR_ISOCHRONOUS 0x01 +#define USB_ENDPOINT_ATTR_BULK 0x02 +#define USB_ENDPOINT_ATTR_INTERRUPT 0x03 + +#define USB_ENDPOINT_ATTR_NOSYNC 0x00 +#define USB_ENDPOINT_ATTR_ASYNC 0x04 +#define USB_ENDPOINT_ATTR_ADAPTIVE 0x08 +#define USB_ENDPOINT_ATTR_SYNC 0x0C + +#define USB_ENDPOINT_ATTR_DATA 0x00 +#define USB_ENDPOINT_ATTR_FEEDBACK 0x10 +#define USB_ENDPOINT_ATTR_IMPLICIT_FEEDBACK_DATA 0x20 + +/* Table 9-15 specifies String Descriptor Zero. + * Table 9-16 specified UNICODE String Descriptor. + */ +struct usb_string_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wData[]; +} __attribute__((packed)); + +/* From ECN: Interface Association Descriptors, Table 9-Z */ +struct usb_iface_assoc_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bFirstInterface; + uint8_t bInterfaceCount; + uint8_t bFunctionClass; + uint8_t bFunctionSubClass; + uint8_t bFunctionProtocol; + uint8_t iFunction; +} __attribute__((packed)); +#define USB_DT_INTERFACE_ASSOCIATION_SIZE \ + sizeof(struct usb_iface_assoc_descriptor) + +enum usb_language_id { + USB_LANGID_ENGLISH_US = 0x409, +}; +#endif + +/**@}*/ + diff --git a/libopencm3/include/libopencmsis/core_cm3.h b/libopencm3/include/libopencmsis/core_cm3.h new file mode 100644 index 0000000..c54137b --- /dev/null +++ b/libopencm3/include/libopencmsis/core_cm3.h @@ -0,0 +1,183 @@ +/* big fat FIXME: this should use a consistent structure, and reference + * functionality from libopencm3 instead of copypasting. + * + * particularly unimplemented features are FIXME'd extra + * */ + +/* the original core_cm3.h is nonfree by arm; this provides libopencm3 variant + * of the symbols efm32lib needs of CMSIS. */ + +#ifndef OPENCMSIS_CORECM3_H +#define OPENCMSIS_CORECM3_H + +#include +#include +#include +#include +#include +#include + +/* needed by system_efm32.h:196, guessing */ +#define __INLINE inline +/* new since emlib 3.0 */ +#define __STATIC_INLINE static inline + +/* needed around efm32tg840f32.h:229. comparing the efm32lib definitions to the + * libopencm3 ones, "volatile" is all that's missing. */ +#define __IO volatile +#define __O volatile +#define __I volatile + +/* -> style access for what is defined in libopencm3/stm32/f1/scb.h / + * cm3/memorymap.h, as it's needed by efm32lib/inc/efm32_emu.h */ + +/* from cm3/scb.h */ +#define SCB_SCR_SLEEPDEEP_Msk SCB_SCR_SLEEPDEEP + +/* structure as in, for example, + * DeviceSupport/EnergyMicro/EFM32/efm32tg840f32.h, data from + * libopencm3/cm3/scb.h. FIXME incomplete. */ +typedef struct { + __IO uint32_t CPUID; + __IO uint32_t ICSR; + __IO uint32_t VTOR; + __IO uint32_t AIRCR; + __IO uint32_t SCR; + __IO uint32_t CCR; + __IO uint8_t SHPR[12]; /* FIXME: how is this properly indexed? */ + __IO uint32_t SHCSR; +} SCB_TypeDef; +#define SCB ((SCB_TypeDef *) SCB_BASE) + +/* needed by efm32_emu.h, guessing and taking the implementation used in + * lightswitch-interrupt.c */ +#define __WFI() __asm__("wfi") + +/* needed by efm32_cmu.h, probably it's just what gcc provides anyway */ +#define __CLZ(div) __builtin_clz(div) + +/* needed by efm32_aes.c. __builtin_bswap32 does the same thing as the rev + * instruction according to https://bugzilla.mozilla.org/show_bug.cgi?id=600106 + */ +#define __REV(x) __builtin_bswap32(x) + +/* stubs for efm32_dbg.h */ +typedef struct { + uint32_t DHCSR; + uint32_t DEMCR; /* needed by efm32tg stk trace.c */ +} CoreDebug_TypeDef; +/* FIXME let's just hope writes to flash are protected */ +#define CoreDebug ((CoreDebug_TypeDef *) 0) +#define CoreDebug_DHCSR_C_DEBUGEN_Msk 0 +#define CoreDebug_DEMCR_TRCENA_Msk 0 + +/* stubs for efm32_dma */ + +static inline void NVIC_ClearPendingIRQ(uint8_t irqn) +{ + nvic_clear_pending_irq(irqn); +} +static inline void NVIC_EnableIRQ(uint8_t irqn) +{ + nvic_enable_irq(irqn); +} +static inline void NVIC_DisableIRQ(uint8_t irqn) +{ + nvic_disable_irq(irqn); +} + +/* stubs for efm32_int */ + +static inline void __enable_irq(void) +{ + cm_enable_interrupts(); +} +static inline void __disable_irq(void) +{ + cm_disable_interrupts(); +} + +/* stubs for efm32_mpu FIXME */ + +#define SCB_SHCSR_MEMFAULTENA_Msk 0 + +typedef struct { + uint32_t CTRL; + uint32_t RNR; + uint32_t RBAR; + uint32_t RASR; +} MPU_TypeDef; +/* FIXME struct at NULL */ +#define MPU ((MPU_TypeDef *) 0) +#define MPU_CTRL_ENABLE_Msk 0 +#define MPU_RASR_XN_Pos 0 +#define MPU_RASR_AP_Pos 0 +#define MPU_RASR_TEX_Pos 0 +#define MPU_RASR_S_Pos 0 +#define MPU_RASR_C_Pos 0 +#define MPU_RASR_B_Pos 0 +#define MPU_RASR_SRD_Pos 0 +#define MPU_RASR_SIZE_Pos 0 +#define MPU_RASR_ENABLE_Pos 0 + +/* required for the blink example */ + +/* if if (SysTick_Config(CMU_ClockFreqGet(cmuClock_CORE) / 1000)) while (1) ; + * configures the sys ticks to 1ms, then the argument to SysTick_Config + * describes how many cycles to wait between two systicks. + * + * the endless loop part looks like an "if it returns an error condition, + * rather loop here than continue"; every other solution would involve things + * that are dark magic to my understanding. + * + * implementation more or less copypasted from lib/stm32/systick.c, FIXME until + * the generic cm3 functionality is moved out from stm32 and can be used here + * easily (systick_set_reload, systick_interrupt_enable, systick_counter_enable + * and systick_set_clocksource). + * + * modified for CMSIS style array as the powertest example needs it. + * */ + +/* from d0002_efm32_cortex-m3_reference_manual.pdf section 4.4 */ +typedef struct { + uint32_t CTRL; + uint32_t LOAD; + uint32_t VAL; + uint32_t CALIB; +} SysTick_TypeDef; +#define SysTick ((SysTick_TypeDef *) SYS_TICK_BASE) + +static inline uint32_t SysTick_Config(uint32_t n_ticks) +{ + /* constant from systick_set_reload -- as this returns something that's + * not void, this is the only possible error condition */ + if (n_ticks & ~0x00FFFFFF) { + return 1; + } + + systick_set_reload(n_ticks); + systick_set_clocksource(true); + systick_interrupt_enable(); + systick_counter_enable(); + + return 0; +} + +/* stubs for efm32tg stk trace.c */ +typedef struct { + uint32_t LAR; + uint32_t TCR; +} ITM_TypeDef; +/* FIXME struct at NULL */ +#define ITM ((ITM_TypeDef *) 0) + +/* blink.h expects the isr for systicks to be named SysTick_Handler. with this, + * its Systick_Handler function gets renamed to the weak symbol exported by + * vector.c */ + +#define SysTick_Handler sys_tick_handler +/* FIXME: this needs to be done for all of the 14 hard vectors */ + +#include + +#endif diff --git a/libopencm3/include/libopencmsis/dispatch/irqhandlers.h b/libopencm3/include/libopencmsis/dispatch/irqhandlers.h new file mode 100644 index 0000000..ad64306 --- /dev/null +++ b/libopencm3/include/libopencmsis/dispatch/irqhandlers.h @@ -0,0 +1,50 @@ +#if defined(STM32F0) +# include +#elif defined(STM32F1) +# include +#elif defined(STM32F2) +# include +#elif defined(STM32F3) +# include +#elif defined(STM32F4) +# include +#elif defined(STM32L1) +# include + +#elif defined(EFM32TG) +# include +#elif defined(EFM32G) +# include +#elif defined(EFM32LG) +# include +#elif defined(EFM32GG) +# include + +#elif defined(LPC13XX) +# include +#elif defined(LPC17XX) +# include +#elif defined(LPC43XX_M4) +# include +#elif defined(LPC43XX_M0) +# include + +#elif defined(SAM3A) +# include +#elif defined(SAM3N) +# include +#elif defined(SAM3S) +# include +#elif defined(SAM3U) +# include +#elif defined(SAM3X) +# include + +#elif defined(LM3S) || defined(LM4F) +/* Yes, we use the same interrupt table for both LM3S and LM4F */ +# include + +#else +# warning"no chipset defined; user interrupts are not redirected" + +#endif -- cgit v1.2.3