From 0780df86a9ec88bf8810f7fef1d241030dc1b655 Mon Sep 17 00:00:00 2001 From: fishsoupisgood Date: Thu, 17 May 2018 09:17:21 +0100 Subject: first version for rob - supports only 44.1kHz --- .gitignore | 7 + Makefile | 70 ++++++++++ bmc_decoder.vhd | 89 +++++++++++++ ccd.vhd | 49 +++++++ clock_recovery.vhd | 82 ++++++++++++ counter.vhd | 45 +++++++ dflipflop.vhd | 35 +++++ pll100.vhd | 365 +++++++++++++++++++++++++++++++++++++++++++++++++++++ pll200.vhd | 365 +++++++++++++++++++++++++++++++++++++++++++++++++++++ spdif.qpf | 30 +++++ spdif.qsf | 53 ++++++++ spdif.sdc | 15 +++ spdif.vhd | 157 +++++++++++++++++++++++ spdif_decoder.vhd | 143 +++++++++++++++++++++ tools/vhdl-pretty | 60 +++++++++ tools/wrap | 15 +++ 16 files changed, 1580 insertions(+) create mode 100644 .gitignore create mode 100644 Makefile create mode 100644 bmc_decoder.vhd create mode 100644 ccd.vhd create mode 100644 clock_recovery.vhd create mode 100644 counter.vhd create mode 100644 dflipflop.vhd create mode 100644 pll100.vhd create mode 100644 pll200.vhd create mode 100644 spdif.qpf create mode 100644 spdif.qsf create mode 100644 spdif.sdc create mode 100644 spdif.vhd create mode 100644 spdif_decoder.vhd create mode 100755 tools/vhdl-pretty create mode 100755 tools/wrap diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..996c7c0 --- /dev/null +++ b/.gitignore @@ -0,0 +1,7 @@ +ans.stamp +asm.stamp +fit.stamp +db/ +incremental_db/ +output_files/ +*.orig diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..2373f0c --- /dev/null +++ b/Makefile @@ -0,0 +1,70 @@ +PROJ=spdif + +SRCS=$(wildcard *.vhd *.v *.qsf *.qpf ) +TIDY_SRC= bmc_decoder.vhd ccd.vhd clock_recovery.vhd counter.vhd dflipflop.vhd spdif_decoder.vhd spdif.vhd + +SOF=${PROJ}.sof +POF=${PROJ}.pof +JIC=${PROJ}.jic + +default: load_sof.stamp sim.stamp + + + +sta.stamp:asm.stamp + tools/wrap quartus_sta ${PROJ} -c ${PROJ} + touch $@ + +asm.stamp:fit.stamp + tools/wrap quartus_asm --read_settings_files=off --write_settings_files=off ${PROJ} -c ${PROJ} + touch $@ + +${POF} ${SOF}:asm.stamp + +fit.stamp: ans.stamp + tools/wrap quartus_fit --read_settings_files=off --write_settings_files=off ${PROJ} -c ${PROJ} + touch $@ + +ans.stamp: ${SRCS} + tools/wrap quartus_map --read_settings_files=on --write_settings_files=off ${PROJ} -c ${PROJ} + touch $@ + +sim.stamp: fit.stamp + tools/wrap quartus_eda ${PROJ} --simulation --tool=modelsim --format=verilog + + +load_sof.stamp: ${SOF} + tools/wrap quartus_pgm -m JTAG -o "p;${SOF}" + +#flash: ${POF} +# tools/wrap quartus_pgm -m AS -o "p;${POF}" + +quartus: + tools/wrap quartus ${PROJ}.qpf + +jtagd: + sudo killall jtagd || true + sudo tools/wrap jtagd + +clean: + /bin/rm -rf ${BSP_DIR} db incremental_db src/obj simulation output_files + /bin/rm -f ${SOPC_FILE} src/Makefile elf.flash sof.flash *.stamp ${SOF} ${ELF} *.rpt *.html *.summary *.pin *.jdi *.qws *.pof *.smsg + /bin/rm -f src/${PROJ}.objdump src/${PROJ}.map + /bin/rm -f sopc_builder_log.txt src/*~ SDIF/*~ + /bin/rm -f sim.stamp *.orig + + + +${JIC}:${SOF} + tools/wrap quartus_cpf -c ${PROJ}.cof + + +flash:${JIC} + tools/wrap quartus_pgm -m JTAG -o "ip;${JIC}" + tools/wrap quartus_pgm -m JTAG -o "p;${SOF}" + + + +tidy: + for i in ${TIDY_SRC}; do tools/vhdl-pretty < $$i > $$i.pp && mv -f $$i $$i.orig && mv $$i.pp $$i ; done + diff --git a/bmc_decoder.vhd b/bmc_decoder.vhd new file mode 100644 index 0000000..93eff8d --- /dev/null +++ b/bmc_decoder.vhd @@ -0,0 +1,89 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.numeric_std.all; + + +-- clk wants to be so that the small feature is 3 ticks + +entity bmc_decoder is + port + ( + n_reset : in std_logic; + clk : in std_logic; + spdif : in std_logic; + ready : out std_logic; + e : out std_logic; + d : out std_logic; + l : out std_logic + ); +end bmc_decoder; + + +architecture rtl of bmc_decoder is + signal last_spdif : std_logic; + signal edge : std_logic; + signal ticks : std_logic_vector(7 downto 0); + signal last_was_one : std_logic; + signal ready_buf : std_logic; +begin + + edge <= last_spdif xor spdif; + + process(n_reset, clk, spdif, edge, ticks) + begin + if n_reset = '0' then + ticks <= (others => '0'); + last_was_one <= '0'; + ready_buf <= '0'; + elsif rising_edge(clk) then + last_spdif <= spdif; + + if edge = '1' then + ticks <= (others => '0'); + if ticks < 1 then + ready_buf <= '1'; + e <= '1'; + d <= '1'; + l <= '0'; + last_was_one <= '0'; + elsif ticks < 4 then + if last_was_one = '0' then + last_was_one <= '1'; + ready_buf <= '1'; + e <= '0'; + d <= '1'; + l <= '0'; + else + last_was_one <= '0'; + end if; + elsif ticks < 7 then + last_was_one <= '0'; + ready_buf <= '1'; + e <= '0'; + l <= '0'; + d <= '0'; + elsif ticks < 10 then + last_was_one <= '0'; + ready_buf <= '1'; + e <= '0'; + d <= '0'; + l <= '1'; + else + ready_buf <= '1'; + e <= '1'; + d <= '0'; + l <= '1'; + last_was_one <= '0'; + end if; + else + ticks <= ticks + 1; + ready_buf <= '0'; + end if; + end if; + end process; + + ready <= ready_buf; + +end rtl; + diff --git a/ccd.vhd b/ccd.vhd new file mode 100644 index 0000000..966369f --- /dev/null +++ b/ccd.vhd @@ -0,0 +1,49 @@ + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.numeric_std.all; + +entity ccd is + port + ( + n_reset : in std_logic; + clk : in std_logic; + d : in std_logic; + q : out std_logic + ); +end ccd; + + +architecture rtl of ccd is + + component dflipflop is + port ( + n_reset : in std_logic; + clk : in std_logic; + d : in std_logic; + q : out std_logic + ); + end component; + + signal d1 : + std_logic; +begin + + dff1 : + dflipflop port map ( + n_reset => n_reset, + d => d, + clk => clk, + q => d1 + ); + dff2 : + dflipflop port map ( + n_reset => n_reset, + d => d1, + clk => not clk, + q => q + ); + +end rtl; diff --git a/clock_recovery.vhd b/clock_recovery.vhd new file mode 100644 index 0000000..91de224 --- /dev/null +++ b/clock_recovery.vhd @@ -0,0 +1,82 @@ + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.numeric_std.all; + +entity clock_recovery is + port + ( + n_reset : in std_logic; + + clk : in std_logic; + d_in : in std_logic; + clk_out : out std_logic + ); +end clock_recovery; + +architecture rtl of clock_recovery is + + + signal qish : + std_logic; + signal od : + std_logic; + signal edge : + std_logic; + signal period : + std_logic_vector(15 downto 0); + signal divisor : + std_logic_vector(15 downto 0); + signal counter : + std_logic_vector(15 downto 0); +begin + + + process(clk, d_in, od, n_reset) + begin + if n_reset = '0' then + od <= '0'; + elsif RISING_EDGE(clk) then + od <= d_in; + end if; + end process; + + edge <= d_in xor od; + divisor <= x"0007"; + + process(edge, n_reset, clk, divisor, counter, qish, period) + begin + if n_reset = '0' then + period <= (others => '0'); + counter <= (others => '0'); + qish <= '0'; + elsif RISING_EDGE(clk) then + if edge = '0' then + period <= period +1; + + if counter < divisor then + counter <= counter + 1; + else + counter <= (others => '0'); + qish <= not qish; + end if; + else + period <= (others => '0'); + counter <= (others => '0'); + qish <= '0'; +-- if period '0'); + clk : in std_logic; + n_reset : in std_logic; + clk_out : out std_logic + ); +end counter; + + +architecture rtl of counter is + + signal d : + std_logic_vector (15 downto 0); + signal q : + std_logic; +begin + + clk_out <= q; + process (clk, d, q, divisor, n_reset) + begin + if n_reset = '0' then + d <= (others => '0'); + q <= '0'; + elsif RISING_EDGE(clk) then + + if d < divisor then + d <= d + 1; + else + d <= (others => '0'); + q <= not q; + end if; + end if; + end process; + +end rtl; + diff --git a/dflipflop.vhd b/dflipflop.vhd new file mode 100644 index 0000000..c83d1d3 --- /dev/null +++ b/dflipflop.vhd @@ -0,0 +1,35 @@ + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.numeric_std.all; + +entity dflipflop is + port + ( + n_reset : in std_logic; + clk : in std_logic; + d : in std_logic; + q : out std_logic + ); +end dflipflop; + + +architecture rtl of dflipflop is + signal qish : + std_logic; +begin + + process(clk, d, n_reset) + begin + if n_reset = '0' then + qish <= '0'; + elsif RISING_EDGE(clk) then + qish <= d; + end if; + end process; + + q <= qish; +end rtl; + diff --git a/pll100.vhd b/pll100.vhd new file mode 100644 index 0000000..184e624 --- /dev/null +++ b/pll100.vhd @@ -0,0 +1,365 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll200.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 222 10/21/2009 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll100 IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll100; + + +ARCHITECTURE SYN2 OF pll200 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + gate_lock_signal : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + invalid_lock_multiplier : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + valid_lock_multiplier : NATURAL + ); + PORT ( + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC ; + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= To_stdlogicvector(sub_wire5_bv); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + locked <= sub_wire2; + sub_wire3 <= inclk0; + sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; + + altpll_component : altpll + GENERIC MAP ( + clk0_divide_by => 1, + clk0_duty_cycle => 50, + clk0_multiply_by => 2, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + gate_lock_signal => "NO", + inclk0_input_frequency => 41666, + intended_device_family => "Cyclone II", + invalid_lock_multiplier => 5, + lpm_hint => "CBX_MODULE_PREFIX=pll200", + lpm_type => "altpll", + operation_mode => "NORMAL", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_UNUSED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + valid_lock_multiplier => 1 + ) + PORT MAP ( + inclk => sub_wire4, + areset => areset, + clk => sub_wire0, + locked => sub_wire2 + ); + + + +END SYN2; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "200.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "200.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "312.000" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "200.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll200.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" +-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" +-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll200.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll200.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll200.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll200.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll200.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll200_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/pll200.vhd b/pll200.vhd new file mode 100644 index 0000000..ab2858f --- /dev/null +++ b/pll200.vhd @@ -0,0 +1,365 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: pll200.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 222 10/21/2009 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY pll200 IS + PORT + ( + areset : IN STD_LOGIC := '0'; + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC ; + locked : OUT STD_LOGIC + ); +END pll200; + + +ARCHITECTURE SYN OF pll200 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC ; + SIGNAL sub_wire3 : STD_LOGIC ; + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0); + + + + COMPONENT altpll + GENERIC ( + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + gate_lock_signal : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + invalid_lock_multiplier : NATURAL; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + valid_lock_multiplier : NATURAL + ); + PORT ( + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + locked : OUT STD_LOGIC ; + areset : IN STD_LOGIC ; + clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire5_bv(0 DOWNTO 0) <= "0"; + sub_wire5 <= To_stdlogicvector(sub_wire5_bv); + sub_wire1 <= sub_wire0(0); + c0 <= sub_wire1; + locked <= sub_wire2; + sub_wire3 <= inclk0; + sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3; + + altpll_component : altpll + GENERIC MAP ( + clk0_divide_by => 1, + clk0_duty_cycle => 50, + clk0_multiply_by => 4, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + gate_lock_signal => "NO", + inclk0_input_frequency => 41666, + intended_device_family => "Cyclone II", + invalid_lock_multiplier => 5, + lpm_hint => "CBX_MODULE_PREFIX=pll200", + lpm_type => "altpll", + operation_mode => "NORMAL", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_USED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_USED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_UNUSED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + valid_lock_multiplier => 1 + ) + PORT MAP ( + inclk => sub_wire4, + areset => areset, + clk => sub_wire0, + locked => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "200.000000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "200.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "312.000" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "200.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll200.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1" +-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]" +-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" +-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll200.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll200.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll200.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll200.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll200.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll200_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/spdif.qpf b/spdif.qpf new file mode 100644 index 0000000..f64db1f --- /dev/null +++ b/spdif.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2012 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 32-bit +# Version 12.0 Build 178 05/31/2012 SJ Web Edition +# Date created = 21:48:38 September 12, 2013 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "12.0" +DATE = "21:48:38 September 12, 2013" + +# Revisions + +PROJECT_REVISION = "spdif" diff --git a/spdif.qsf b/spdif.qsf new file mode 100644 index 0000000..b57bdf8 --- /dev/null +++ b/spdif.qsf @@ -0,0 +1,53 @@ +# + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C5T144C8 +set_global_assignment -name TOP_LEVEL_ENTITY spdif +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "14:33:12 MAY 03, 2018" +set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + +set_location_assignment PIN_3 -to n_leds[0] +set_location_assignment PIN_7 -to n_leds[1] +set_location_assignment PIN_9 -to n_leds[2] +set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to n_leds[0] +set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to n_leds[1] +set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to n_leds[2] +set_location_assignment PIN_17 -to xtal_50mhz +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_location_assignment PIN_143 -to spdif_in +set_location_assignment PIN_73 -to n_rst_in + +set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to spdif_in +set_location_assignment PIN_112 -to n_mute_out +set_location_assignment PIN_114 -to n_stby_out +set_location_assignment PIN_41 -to dbg1 +set_location_assignment PIN_101 -to dbg2 +set_global_assignment -name VHDL_FILE ccd.vhd +set_global_assignment -name VHDL_FILE clock_recovery.vhd +set_global_assignment -name VHDL_FILE counter.vhd +set_global_assignment -name VHDL_FILE dflipflop.vhd +set_global_assignment -name VHDL_FILE pll100.vhd +set_global_assignment -name VHDL_FILE pll200.vhd +set_global_assignment -name VHDL_FILE spdif.vhd +set_global_assignment -name VHDL_FILE bmc_decoder.vhd +set_global_assignment -name VHDL_FILE spdif_decoder.vhd +set_global_assignment -name SOURCE_FILE db/spdif.cmp.rdb +set_global_assignment -name SDC_FILE spdif.sdc + +set_location_assignment PIN_103 -to dbg3 +set_location_assignment PIN_104 -to dbg4 +set_location_assignment PIN_113 -to dbg5 +set_location_assignment PIN_115 -to dbg6 +set_location_assignment PIN_118 -to dbg7 +set_location_assignment PIN_119 -to dbg8 +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS OUTPUT DRIVING GROUND" diff --git a/spdif.sdc b/spdif.sdc new file mode 100644 index 0000000..f74ef07 --- /dev/null +++ b/spdif.sdc @@ -0,0 +1,15 @@ +# +# Design Timing Constraints Definitions +# + +set_time_format -unit ns -decimal_places 3 + +############################################################################## +# Create Input reference clocks +create_clock -name {xtal_50mhz} -period 20.000 -waveform { 0.000 10.000 } [get_ports { xtal_50mhz }] + +############################################################################## +# Now that we have created the custom clocks which will be base clocks, +# derive_pll_clock is used to calculate all remaining clocks for PLLs +derive_pll_clocks -create_base_clocks +derive_clock_uncertainty \ No newline at end of file diff --git a/spdif.vhd b/spdif.vhd new file mode 100644 index 0000000..cb55844 --- /dev/null +++ b/spdif.vhd @@ -0,0 +1,157 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.numeric_std.all; + +entity spdif is + port ( + xtal_50mhz : in std_logic; + spdif_in : in std_logic; + n_rst_in : in std_logic; + + n_leds : out std_logic_vector(2 downto 0); + n_mute_out : out std_logic; + n_stby_out : out std_logic; + + dbg1 : out std_logic; + dbg2 : out std_logic; + dbg3 : out std_logic; + dbg4 : out std_logic; + dbg5 : out std_logic; + dbg6 : out std_logic; + dbg7 : out std_logic; + dbg8 : out std_logic + ); +end spdif; + + +architecture rtl of spdif is + component ccd is + port + ( + n_reset : in std_logic; + clk : in std_logic; + d : in std_logic; + q : out std_logic + ); + end component; + + component pll100 is + port ( + areset : in std_logic := '0'; + inclk0 : in std_logic := '0'; + c0 : out std_logic; + locked : out std_logic + ); + end component; + component pll200 is + port ( + areset : in std_logic := '0'; + inclk0 : in std_logic := '0'; + c0 : out std_logic; + locked : out std_logic + ); + end component; + component counter is + port + ( + divisor : in std_logic_vector (15 downto 0); + clk : in std_logic; + n_reset : in std_logic; + clk_out : out std_logic + ); + end component; + + + component spdif_decoder is + port + ( + n_reset : in std_logic; + clk : in std_logic; + spdif : in std_logic; + bmc_ready : out std_logic; + bmc_e : out std_logic; + bmc_l : out std_logic; + bmc_d : out std_logic; + sof : out std_logic; + bna : out std_logic; + d : out std_logic_vector(26 downto 0); + ready : out std_logic + ); + end component; + + signal n_reset : + std_logic; + signal clk_200mhz : + std_logic; +-- signal clk_100mhz : +-- std_logic; + signal spdif_clkd1 : + std_logic; + signal clk1 : + std_logic; + signal d1 : std_logic_vector(26 downto 0); + signal bna1 : std_logic; + signal sof1 : std_logic; + +begin + n_reset <= n_rst_in; + + + pll1 : + pll200 port map ( + areset => not n_reset, + inclk0 => xtal_50mhz, + c0 => clk_200mhz + ); + +-- pll2 : +-- pll200 port map ( +-- areset => not n_reset, +-- inclk0 => xtal_50mhz, +-- c0 => clk_100mhz +-- ); + + div1 : counter port map ( + n_reset => n_reset, + clk => clk_200mhz, + divisor => x"000c", + clk_out => clk1 + ); + + b1 : + ccd port map ( + n_reset => n_reset, + clk => clk1, + d => spdif_in, + q => spdif_clkd1 + ); + + dec1 : spdif_decoder port map ( + n_reset => n_reset, + clk => clk1, + spdif => spdif_clkd1, + bmc_ready => dbg3, + bmc_e => dbg4, + bmc_l => dbg5, + bmc_d => dbg6, + bna => bna1, + d => d1, + ready => dbg7 + ); + + dbg8 <= bna1; + + + dbg1 <= spdif_clkd1; + dbg2 <= clk1; + + + n_leds(0) <= d1(9); + n_leds(1) <= d1(10); + n_leds(2) <= d1(11); + + n_mute_out <= '0'; + n_stby_out <= '0'; + +end rtl; diff --git a/spdif_decoder.vhd b/spdif_decoder.vhd new file mode 100644 index 0000000..d9e8a23 --- /dev/null +++ b/spdif_decoder.vhd @@ -0,0 +1,143 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.numeric_std.all; + + +-- clk wants to be so that the small feature is 3 ticks + +entity spdif_decoder is + generic ( + Z24 : std_logic_vector(23 downto 0) := (others => '0'); + Z32 : std_logic_vector(31 downto 0) := (others => '0') + ); + + port + ( + n_reset : in std_logic; + clk : in std_logic; + spdif : in std_logic; + bmc_ready : out std_logic; + bmc_e : out std_logic; + bmc_l : out std_logic; + bmc_d : out std_logic; + sof : out std_logic; + bna : out std_logic; + d : out std_logic_vector(26 downto 0); + ready : out std_logic + ); +end spdif_decoder; + + +architecture rtl of spdif_decoder is + + component bmc_decoder is + port + ( + n_reset : in std_logic; + clk : in std_logic; + spdif : in std_logic; + ready : out std_logic; + e : out std_logic; + l : out std_logic; + d : out std_logic + ); + end component; + + + signal b_ready : std_logic; + signal b_e : std_logic; + signal b_l : std_logic; + signal b_d : std_logic; + + signal parity : std_logic; + + signal e_sr : std_logic_vector(31 downto 0); + signal d_sr : std_logic_vector(31 downto 0); + signal l_sr : std_logic_vector(31 downto 0); + + signal d_buf : std_logic_vector(26 downto 0); + signal sof_buf : std_logic; + signal ready_buf : std_logic; + signal bna_buf : std_logic; +begin + + bmc : + bmc_decoder port map ( + n_reset => n_reset, + clk => clk, + spdif => spdif, + ready => b_ready, + e => b_e, + l => b_l, + d => b_d + ); + + bmc_ready <= b_ready; + bmc_e <= b_e; + bmc_l <= b_l; + bmc_d <= b_d; + + + process (clk, b_ready, b_e, b_l, b_d, n_reset) + begin + if n_reset = '0' then + e_sr <= (others => '0'); + d_sr <= (others => '0'); + l_sr <= (others => '0'); + elsif rising_edge(clk) then + if (b_ready = '1') then + e_sr <= b_e & e_sr(31 downto 1); + d_sr <= b_d & d_sr(31 downto 1); + l_sr <= b_l & l_sr(31 downto 1); + end if; + end if; + end process; + + +-- parity<=xor_reduce(d_sr(31 downto 4)); + parity <= '1'; + + process (clk, b_ready, e_sr, l_sr, d_sr, parity, n_reset) + begin + if n_reset = '0' then + d_buf <= (others => '0'); + sof_buf <= '0'; + bna_buf <= '0'; + ready_buf <= '0'; + elsif rising_edge(clk) then + if (b_ready = '1') and (parity = '1') and (e_sr = Z32) then + if (d_sr(2 downto 0) = "010") and (l_sr(2 downto 0) = "101") then --B code + d_buf <= d_sr(29 downto 3); + sof_buf <= '1'; + bna_buf <= '0'; + ready_buf <= '1'; + elsif (d_sr(2 downto 0) = "001") and (l_sr(2 downto 0) = "110") then --M code + d_buf <= d_sr(29 downto 3); + sof_buf <= '0'; + bna_buf <= '0'; + ready_buf <= '1'; + elsif (d_sr(3 downto 0) = "0010") and (l_sr(3 downto 0) = "1000") then --W code + d_buf <= d_sr(30 downto 4); + sof_buf <= '0'; + bna_buf <= '1'; + ready_buf <= '1'; + else + ready_buf <= '0'; + end if; + else + ready_buf <= '0'; + end if; + end if; + + end process; + + d <= d_buf; + ready <= ready_buf; + sof <= sof_buf; + bna <= bna_buf; + + + +end rtl; + diff --git a/tools/vhdl-pretty b/tools/vhdl-pretty new file mode 100755 index 0000000..c514b85 --- /dev/null +++ b/tools/vhdl-pretty @@ -0,0 +1,60 @@ +#! /bin/sh +":"; exec emacs --no-site-file --script "$0" -- "$0" "$@" # -*-emacs-lisp-*- +; vim: noai:ts=4:sw=4:syntax=lisp + +(setq arg0 (file-truename (car (cdr argv)))) +(setq args (cdr (cdr argv))) +(setq argv nil) + +; Parse the command line arguments, +; --xxx -> ("xxx" t) +; --no-xxx -> ("xxx" nil) +; --xxx=123 -> ("xxx" 123) +; --xxx=abc -> ("xxx" "abc") +; --xxx='abc 123' -> ("xxx" "abc 123") +; --xxx=abc=123 -> ("xxx" "abc=123") +(setq args + (mapcar + (lambda (arg) + (cond + ((string-match "^--no-\\([^=]*\\)$" arg) + (list (intern (match-string 1 arg)) nil)) + ((string-match "^--\\([^=]*\\)$" arg) + (list (intern (match-string 1 arg)) t)) + ((string-match "^--\\([^=]*\\)=\\([\"']?\\)\\([0-9]+\\)\\2$" arg) + (list (intern (match-string 1 arg)) (string-to-number (match-string 3 arg)))) + ((string-match "^--\\([^=]*\\)=\\([\"']?\\)\\(.+?\\)\\2$" arg) + (list (intern (match-string 1 arg)) (match-string 3 arg))) + (t nil) + )) + args)) + +; Read stdin into buffer +(defun insert-standard-input () + "insert contents from standard input" + (condition-case nil + (let (line) + (while (setq line (read-from-minibuffer "")) + (insert line "\n"))) + (error nil))) + +(insert-standard-input) +(goto-char (point-min)) + +; Load library +(setq basedir (concat (file-name-directory arg0) "vhdl-mode")) +(setq load-path (cons basedir load-path)) +(load-library "vhdl-mode") + +; Default customisation +(vhdl-set-style "IEEE") + +; Customisation from cmdline +(mapc (lambda (arg) (customize-set-variable (car arg) (car (cdr arg)))) args) + +; Turn on mode and beautify +(vhdl-mode) +(vhdl-beautify-region (point-min) (point-max)) + +; Output buffer to stdout +(princ (buffer-string)) diff --git a/tools/wrap b/tools/wrap new file mode 100755 index 0000000..26a0640 --- /dev/null +++ b/tools/wrap @@ -0,0 +1,15 @@ +#!/bin/bash + +AD=/software/apps/altera/quartus_ii_13.0sp1 +if [ $(uname -m ) == "x86_64" ]; then + LL=linux64 +else + LL=linux +fi +QUARTUS_ROOTDIR="${AD}/quartus" +PATH="${AD}/quartus/bin:${AD}/quartus/sopc_builder/bin:${AD}/nios2eds/sdk2/bin:${AD}/nios2eds/bin:${AD}/nios2eds/bin/gnu/H-i686-pc-linux-gnu/bin:${PATH}" +LD_LIBRARY_PATH="${AD}/quartus/${LL}:${LD_LIBRARY_PATH}" + +export LD_LIBRARY_PATH PATH QUARTUS_ROOTDIR + +"$@" -- cgit v1.2.3