From 5749bc2572e4be1acea0d428e8d928a95b170701 Mon Sep 17 00:00:00 2001 From: root Date: Tue, 29 May 2018 16:14:18 +0100 Subject: new pinout and led --- spdif.qsf | 14 ++++++++++---- spdif.vhd | 11 ++++++++--- 2 files changed, 18 insertions(+), 7 deletions(-) diff --git a/spdif.qsf b/spdif.qsf index 1cb54fa..c00aff2 100644 --- a/spdif.qsf +++ b/spdif.qsf @@ -20,15 +20,20 @@ set_global_assignment -name FAMILY "Cyclone II" set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to n_leds[0] set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to n_leds[1] set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to n_leds[2] + set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to led_r + set_instance_assignment -name OUTPUT_PIN_LOAD 100 -to led_g set_location_assignment PIN_17 -to xtal_50mhz set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" - set_location_assignment PIN_143 -to spdif_in + set_location_assignment PIN_72 -to spdif_in set_location_assignment PIN_73 -to n_rst_in set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4 set_instance_assignment -name WEAK_PULL_UP_RESISTOR OFF -to spdif_in - set_location_assignment PIN_112 -to n_mute_out - set_location_assignment PIN_114 -to n_stby_out + set_location_assignment PIN_71 -to n_mute_out + + set_location_assignment PIN_57 -to led_r + set_location_assignment PIN_59 -to led_g + set_global_assignment -name VHDL_FILE ccd.vhd set_global_assignment -name VHDL_FILE counter.vhd set_global_assignment -name VHDL_FILE dflipflop.vhd @@ -48,6 +53,7 @@ set_global_assignment -name FAMILY "Cyclone II" set_location_assignment PIN_103 -to dbg[2] set_location_assignment PIN_104 -to dbg[3] set_location_assignment PIN_113 -to dbg[4] + set_location_assignment PIN_114 -to n_stby_out set_location_assignment PIN_115 -to dbg[5] set_location_assignment PIN_118 -to dbg[6] set_location_assignment PIN_119 -to dbg[7] @@ -57,4 +63,4 @@ set_global_assignment -name FAMILY "Cyclone II" set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)" set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top diff --git a/spdif.vhd b/spdif.vhd index ce2f584..60c0526 100644 --- a/spdif.vhd +++ b/spdif.vhd @@ -9,6 +9,8 @@ entity spdif is spdif_in : in std_logic; n_rst_in : in std_logic; + led_r : out std_logic; + led_g : out std_logic; n_leds : out std_logic_vector(2 downto 0); n_mute_out : out std_logic; n_stby_out : out std_logic; @@ -118,9 +120,9 @@ begin -- mute => mute3 -- ); - mute1 <= '1'; - mute3 <= '1'; - mute <= mute1 and mute2 and mute3; + mute1 <= '1'; + mute3 <= '1'; + mute <= mute1 and mute2 and mute3; n_mute_out <= not mute; n_stby_out <= not mute; @@ -129,6 +131,9 @@ begin n_leds(1) <= mute2; n_leds(2) <= mute3; + led_r <= mute; + led_g <= not mute; + end rtl; -- cgit v1.2.3