From 0780df86a9ec88bf8810f7fef1d241030dc1b655 Mon Sep 17 00:00:00 2001 From: fishsoupisgood Date: Thu, 17 May 2018 09:17:21 +0100 Subject: first version for rob - supports only 44.1kHz --- dflipflop.vhd | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 dflipflop.vhd (limited to 'dflipflop.vhd') diff --git a/dflipflop.vhd b/dflipflop.vhd new file mode 100644 index 0000000..c83d1d3 --- /dev/null +++ b/dflipflop.vhd @@ -0,0 +1,35 @@ + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.numeric_std.all; + +entity dflipflop is + port + ( + n_reset : in std_logic; + clk : in std_logic; + d : in std_logic; + q : out std_logic + ); +end dflipflop; + + +architecture rtl of dflipflop is + signal qish : + std_logic; +begin + + process(clk, d, n_reset) + begin + if n_reset = '0' then + qish <= '0'; + elsif RISING_EDGE(clk) then + qish <= d; + end if; + end process; + + q <= qish; +end rtl; + -- cgit v1.2.3