uboot-lantiq: update to v2013.10

Patches created from tree:
git@github.com:danielschwierzeck/u-boot-lantiq.git
v2013.10..u-boot-lantiq-v2013.10-openwrt4

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

SVN-Revision: 40482

1 files changed, 0 insertions, 248 deletions

diff --git a/package/boot/uboot-lantiq/patches/0028-MIPS-add-board-support-for-Arcadyan-ARV4519.patch b/package/boot/uboot-lantiq/patches/0028-MIPS-add-board-support-for-Arcadyan-ARV4519.patch
deleted file mode 100644
index 4698e6787d..0000000000
--- a/package/boot/uboot-lantiq/patches/0028-MIPS-add-board-support-for-Arcadyan-ARV4519.patch
+++ /dev/null
@@ -1,248 +0,0 @@
-From 4a738c02a7190756e01ba58c93c4b07bc6d6c2aa Mon Sep 17 00:00:00 2001
-From: Luka Perkov <luka@openwrt.org>
-Date: Wed, 29 Aug 2012 22:08:42 +0200
-Subject: MIPS: add board support for Arcadyan ARV4519
-
-Signed-off-by: Luka Perkov <luka@openwrt.org>
-Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
-
---- /dev/null
-+++ b/board/arcadyan/arv4519pw/Makefile
-@@ -0,0 +1,29 @@
-+#
-+# This file is released under the terms of GPL v2 and any later version.
-+# See the file COPYING in the root directory of the source tree for details.
-+#
-+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
-+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
-+#
-+
-+include $(TOPDIR)/config.mk
-+
-+LIB	= $(obj)lib$(BOARD).o
-+
-+COBJS	= $(BOARD).o
-+
-+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-+OBJS	:= $(addprefix $(obj),$(COBJS))
-+SOBJS	:= $(addprefix $(obj),$(SOBJS))
-+
-+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-+
-+#########################################################################
-+
-+# defines $(obj).depend target
-+include $(SRCTREE)/rules.mk
-+
-+sinclude $(obj).depend
-+
-+#########################################################################
---- /dev/null
-+++ b/board/arcadyan/arv4519pw/arv4519pw.c
-@@ -0,0 +1,52 @@
-+/*
-+ * This file is released under the terms of GPL v2 and any later version.
-+ * See the file COPYING in the root directory of the source tree for details.
-+ *
-+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>
-+ */
-+
-+#include <common.h>
-+#include <switch.h>
-+#include <asm/gpio.h>
-+#include <asm/lantiq/eth.h>
-+#include <asm/lantiq/reset.h>
-+#include <asm/lantiq/chipid.h>
-+
-+int board_early_init_f(void)
-+{
-+	return 0;
-+}
-+
-+int checkboard(void)
-+{
-+	puts("Board: " CONFIG_BOARD_NAME "\n");
-+	ltq_chip_print_info();
-+
-+	return 0;
-+}
-+
-+static const struct ltq_eth_port_config eth_port_config[] = {
-+	/* MAC0: Atheros ar8216 switch */
-+	{ 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_NONE },
-+};
-+
-+static const struct ltq_eth_board_config eth_board_config = {
-+	.ports = eth_port_config,
-+	.num_ports = ARRAY_SIZE(eth_port_config),
-+};
-+
-+int board_eth_init(bd_t *bis)
-+{
-+	return ltq_eth_initialize(&eth_board_config);
-+}
-+
-+static struct switch_device ar8216_dev = {
-+	.name = "ar8216",
-+	.cpu_port = 0,
-+	.port_mask = 0xF,
-+};
-+
-+int board_switch_init(void)
-+{
-+	return switch_device_register(&ar8216_dev);
-+}
---- /dev/null
-+++ b/board/arcadyan/arv4519pw/config.mk
-@@ -0,0 +1,8 @@
-+#
-+# This file is released under the terms of GPL v2 and any later version.
-+# See the file COPYING in the root directory of the source tree for details.
-+#
-+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
-+#
-+
-+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
---- /dev/null
-+++ b/board/arcadyan/arv4519pw/ddr_settings.h
-@@ -0,0 +1,56 @@
-+/*
-+ * This file is released under the terms of GPL v2 and any later version.
-+ * See the file COPYING in the root directory of the source tree for details.
-+ *
-+ * generated with lantiq_ram_extract_magic.awk
-+ *
-+ * Copyright (C) 2011 Luka Perkov <luka@openwrt.org>
-+ */
-+
-+#define MC_DC00_VALUE	0x1B1B
-+#define MC_DC01_VALUE	0x0
-+#define MC_DC02_VALUE	0x0
-+#define MC_DC03_VALUE	0x0
-+#define MC_DC04_VALUE	0x0
-+#define MC_DC05_VALUE	0x200
-+#define MC_DC06_VALUE	0x605
-+#define MC_DC07_VALUE	0x303
-+#define MC_DC08_VALUE	0x102
-+#define MC_DC09_VALUE	0x70A
-+#define MC_DC10_VALUE	0x203
-+#define MC_DC11_VALUE	0xC02
-+#define MC_DC12_VALUE	0x1C8
-+#define MC_DC13_VALUE	0x1
-+#define MC_DC14_VALUE	0x0
-+#define MC_DC15_VALUE	0x131
-+#define MC_DC16_VALUE	0xC800
-+#define MC_DC17_VALUE	0xD
-+#define MC_DC18_VALUE	0x301
-+#define MC_DC19_VALUE	0x200
-+#define MC_DC20_VALUE	0xA04
-+#define MC_DC21_VALUE	0x1700
-+#define MC_DC22_VALUE	0x1717
-+#define MC_DC23_VALUE	0x0
-+#define MC_DC24_VALUE	0x5A
-+#define MC_DC25_VALUE	0x0
-+#define MC_DC26_VALUE	0x0
-+#define MC_DC27_VALUE	0x0
-+#define MC_DC28_VALUE	0x510
-+#define MC_DC29_VALUE	0x4E20
-+#define MC_DC30_VALUE	0x8235
-+#define MC_DC31_VALUE	0x0
-+#define MC_DC32_VALUE	0x0
-+#define MC_DC33_VALUE	0x0
-+#define MC_DC34_VALUE	0x0
-+#define MC_DC35_VALUE	0x0
-+#define MC_DC36_VALUE	0x0
-+#define MC_DC37_VALUE	0x0
-+#define MC_DC38_VALUE	0x0
-+#define MC_DC39_VALUE	0x0
-+#define MC_DC40_VALUE	0x0
-+#define MC_DC41_VALUE	0x0
-+#define MC_DC42_VALUE	0x0
-+#define MC_DC43_VALUE	0x0
-+#define MC_DC44_VALUE	0x0
-+#define MC_DC45_VALUE	0x500
-+#define MC_DC46_VALUE	0x0
---- a/boards.cfg
-+++ b/boards.cfg
-@@ -438,6 +438,8 @@ vct_premium                  mips
- vct_premium_onenand          mips        mips32      vct                 micronas       -           vct:VCT_PREMIUM,VCT_ONENAND
- vct_premium_onenand_small    mips        mips32      vct                 micronas       -           vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE
- vct_premium_small            mips        mips32      vct                 micronas       -           vct:VCT_PREMIUM,VCT_SMALL_IMAGE
-+arv4519pw_ram                mips        mips32      arv4519pw           arcadyan       danube      arv4519pw:SYS_BOOT_RAM
-+arv4519pw_nor                mips        mips32      arv4519pw           arcadyan       danube      arv4519pw:SYS_BOOT_NOR
- arv7518pw_ram                mips        mips32      arv7518pw           arcadyan       danube      arv7518pw:SYS_BOOT_RAM
- arv7518pw_nor                mips        mips32      arv7518pw           arcadyan       danube      arv7518pw:SYS_BOOT_NOR
- dbau1000                     mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1000
---- /dev/null
-+++ b/include/configs/arv4519pw.h
-@@ -0,0 +1,69 @@
-+/*
-+ * This file is released under the terms of GPL v2 and any later version.
-+ * See the file COPYING in the root directory of the source tree for details.
-+ *
-+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>
-+ */
-+
-+#ifndef __CONFIG_H
-+#define __CONFIG_H
-+
-+#define CONFIG_MACH_TYPE	"ARV4519PW"
-+#define CONFIG_IDENT_STRING	" "CONFIG_MACH_TYPE
-+#define CONFIG_BOARD_NAME	"Arcadyan ARV4519PW"
-+
-+/* Configure SoC */
-+#define CONFIG_LTQ_SUPPORT_UART		/* Enable ASC and UART */
-+#define CONFIG_LTQ_SUPPORT_ETHERNET	/* Enable ethernet */
-+#define CONFIG_LTQ_SUPPORT_NOR_FLASH	/* Have a parallel NOR flash */
-+
-+/* Switch devices */
-+#define CONFIG_SWITCH_MULTI
-+#define CONFIG_SWITCH_AR8216
-+
-+/* Environment */
-+#if defined(CONFIG_SYS_BOOT_NOR)
-+#define CONFIG_ENV_IS_IN_FLASH
-+#define CONFIG_ENV_OVERWRITE
-+#define CONFIG_ENV_OFFSET		(192 * 1024)
-+#define CONFIG_ENV_SIZE			(64 * 1024)
-+#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
-+#else
-+#define CONFIG_ENV_IS_NOWHERE
-+#define CONFIG_ENV_SIZE			(2 * 1024)
-+#endif
-+
-+#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR
-+
-+/* Console */
-+#define CONFIG_LTQ_ADVANCED_CONSOLE
-+#define CONFIG_BAUDRATE			115200
-+#define CONFIG_CONSOLE_ASC		1
-+#define CONFIG_CONSOLE_DEV		"ttyLTQ1"
-+
-+/* Commands */
-+#define CONFIG_CMD_PING
-+
-+/* Pull in default board configs for Lantiq XWAY Danube */
-+#include <asm/lantiq/config.h>
-+#include <asm/arch/config.h>
-+
-+/* Compression */
-+#define CONFIG_LZMA
-+
-+/* Auto boot */
-+#define CONFIG_BOOTDELAY		2
-+
-+/* Environment configuration */
-+#define CONFIG_BOOTCOMMAND			\
-+	"run addeth; bootm ${kernel_addr}"
-+
-+#define CONFIG_ENV_UPDATE_UBOOT_NOR		\
-+	"update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
-+
-+#define CONFIG_EXTRA_ENV_SETTINGS		\
-+	CONFIG_ENV_LANTIQ_DEFAULTS		\
-+	CONFIG_ENV_UPDATE_UBOOT_NOR		\
-+	"kernel_addr=0xB0040000\0"
-+
-+#endif /* __CONFIG_H */