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author | Felix Fietkau <nbd@openwrt.org> | 2015-06-02 08:47:21 +0000 |
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committer | Felix Fietkau <nbd@openwrt.org> | 2015-06-02 08:47:21 +0000 |
commit | 913ca8200ac4ec8e642acfab1929c0946dab8be3 (patch) | |
tree | a29bc564ded1acc65727ff8a43e7fe56d7f458b7 /package/kernel/mac80211/patches/379-ath9k-fix-DMA-stop-sequence-for-AR9003.patch | |
parent | 91467cec6fe874b0d6ee67d0814e07ce0b420c87 (diff) | |
download | master-31e0f0ae-913ca8200ac4ec8e642acfab1929c0946dab8be3.tar.gz master-31e0f0ae-913ca8200ac4ec8e642acfab1929c0946dab8be3.tar.bz2 master-31e0f0ae-913ca8200ac4ec8e642acfab1929c0946dab8be3.zip |
ath9k: fix an issue with stopping rx/tx dma on AR93xx
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45874
Diffstat (limited to 'package/kernel/mac80211/patches/379-ath9k-fix-DMA-stop-sequence-for-AR9003.patch')
-rw-r--r-- | package/kernel/mac80211/patches/379-ath9k-fix-DMA-stop-sequence-for-AR9003.patch | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/package/kernel/mac80211/patches/379-ath9k-fix-DMA-stop-sequence-for-AR9003.patch b/package/kernel/mac80211/patches/379-ath9k-fix-DMA-stop-sequence-for-AR9003.patch new file mode 100644 index 0000000000..814b0d7a4a --- /dev/null +++ b/package/kernel/mac80211/patches/379-ath9k-fix-DMA-stop-sequence-for-AR9003.patch @@ -0,0 +1,33 @@ +From: Felix Fietkau <nbd@openwrt.org> +Date: Tue, 2 Jun 2015 10:35:46 +0200 +Subject: [PATCH] ath9k: fix DMA stop sequence for AR9003+ + +AR93xx and newer needs to stop rx before tx to avoid getting the DMA +engine or MAC into a stuck state. +This should reduce/fix the occurence of "Failed to stop Tx DMA" logspam. + +Cc: stable@vger.kernel.org +Signed-off-by: Felix Fietkau <nbd@openwrt.org> +--- + +--- a/drivers/net/wireless/ath/ath9k/main.c ++++ b/drivers/net/wireless/ath/ath9k/main.c +@@ -216,11 +216,13 @@ static bool ath_prepare_reset(struct ath + ath_stop_ani(sc); + ath9k_hw_disable_interrupts(ah); + +- if (!ath_drain_all_txq(sc)) +- ret = false; +- +- if (!ath_stoprecv(sc)) +- ret = false; ++ if (AR_SREV_9300_20_OR_LATER(ah)) { ++ ret &= ath_stoprecv(sc); ++ ret &= ath_drain_all_txq(sc); ++ } else { ++ ret &= ath_drain_all_txq(sc); ++ ret &= ath_stoprecv(sc); ++ } + + return ret; + } |