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author | Gabor Juhos <juhosg@openwrt.org> | 2011-11-14 17:43:11 +0000 |
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committer | Gabor Juhos <juhosg@openwrt.org> | 2011-11-14 17:43:11 +0000 |
commit | aa0c8c4885dc6a5bc4650c55673000d862bf2612 (patch) | |
tree | 9381e3448071805e8228628d7d7516e6a1de946f /target/linux/ar71xx/files/drivers/mtd | |
parent | 62a7795afd032c31571efcfefb5b7e4aa4df086c (diff) | |
download | master-31e0f0ae-aa0c8c4885dc6a5bc4650c55673000d862bf2612.tar.gz master-31e0f0ae-aa0c8c4885dc6a5bc4650c55673000d862bf2612.tar.bz2 master-31e0f0ae-aa0c8c4885dc6a5bc4650c55673000d862bf2612.zip |
ar71xx: add AR71XX_ prefix to GPIO_REG_* defines
SVN-Revision: 29123
Diffstat (limited to 'target/linux/ar71xx/files/drivers/mtd')
-rw-r--r-- | target/linux/ar71xx/files/drivers/mtd/nand/rb750_nand.c | 76 |
1 files changed, 40 insertions, 36 deletions
diff --git a/target/linux/ar71xx/files/drivers/mtd/nand/rb750_nand.c b/target/linux/ar71xx/files/drivers/mtd/nand/rb750_nand.c index 831df14ec8..b6adb41d99 100644 --- a/target/linux/ar71xx/files/drivers/mtd/nand/rb750_nand.c +++ b/target/linux/ar71xx/files/drivers/mtd/nand/rb750_nand.c @@ -75,13 +75,14 @@ static void rb750_nand_write(const u8 *buf, unsigned len) { void __iomem *base = ar71xx_gpio_base; u32 out; + u32 t; unsigned i; /* set data lines to output mode */ - __raw_writel(__raw_readl(base + GPIO_REG_OE) | RB750_NAND_DATA_BITS, - base + GPIO_REG_OE); + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(t | RB750_NAND_DATA_BITS, base + AR71XX_GPIO_REG_OE); - out = __raw_readl(base + GPIO_REG_OUT); + out = __raw_readl(base + AR71XX_GPIO_REG_OUT); out &= ~(RB750_NAND_DATA_BITS | RB750_NAND_NWE); for (i = 0; i != len; i++) { u32 data; @@ -89,18 +90,18 @@ static void rb750_nand_write(const u8 *buf, unsigned len) data = buf[i]; data <<= RB750_NAND_DATA_SHIFT; data |= out; - __raw_writel(data, base + GPIO_REG_OUT); + __raw_writel(data, base + AR71XX_GPIO_REG_OUT); - __raw_writel(data | RB750_NAND_NWE, base + GPIO_REG_OUT); + __raw_writel(data | RB750_NAND_NWE, base + AR71XX_GPIO_REG_OUT); /* flush write */ - __raw_readl(base + GPIO_REG_OUT); + __raw_readl(base + AR71XX_GPIO_REG_OUT); } /* set data lines to input mode */ - __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~RB750_NAND_DATA_BITS, - base + GPIO_REG_OE); + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(t & ~RB750_NAND_DATA_BITS, base + AR71XX_GPIO_REG_OE); /* flush write */ - __raw_readl(base + GPIO_REG_OE); + __raw_readl(base + AR71XX_GPIO_REG_OE); } static int rb750_nand_read_verify(u8 *read_buf, unsigned len, @@ -113,15 +114,16 @@ static int rb750_nand_read_verify(u8 *read_buf, unsigned len, u8 data; /* activate RE line */ - __raw_writel(RB750_NAND_NRE, base + GPIO_REG_CLEAR); + __raw_writel(RB750_NAND_NRE, base + AR71XX_GPIO_REG_CLEAR); /* flush write */ - __raw_readl(base + GPIO_REG_CLEAR); + __raw_readl(base + AR71XX_GPIO_REG_CLEAR); /* read input lines */ - data = __raw_readl(base + GPIO_REG_IN) >> RB750_NAND_DATA_SHIFT; + data = __raw_readl(base + AR71XX_GPIO_REG_IN) >> + RB750_NAND_DATA_SHIFT; /* deactivate RE line */ - __raw_writel(RB750_NAND_NRE, base + GPIO_REG_SET); + __raw_writel(RB750_NAND_NRE, base + AR71XX_GPIO_REG_SET); if (read_buf) read_buf[i] = data; @@ -136,8 +138,9 @@ static void rb750_nand_select_chip(struct mtd_info *mtd, int chip) { void __iomem *base = ar71xx_gpio_base; u32 func; + u32 t; - func = __raw_readl(base + GPIO_REG_FUNC); + func = __raw_readl(base + AR71XX_GPIO_REG_FUNC); if (chip >= 0) { /* disable latch */ rb750_latch_change(RB750_LVC573_LE, 0); @@ -147,27 +150,27 @@ static void rb750_nand_select_chip(struct mtd_info *mtd, int chip) AR724X_GPIO_FUNC_SPI_EN); /* set input mode for data lines */ - __raw_writel(__raw_readl(base + GPIO_REG_OE) & - ~RB750_NAND_INPUT_BITS, - base + GPIO_REG_OE); + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(t & ~RB750_NAND_INPUT_BITS, + base + AR71XX_GPIO_REG_OE); /* deactivate RE and WE lines */ __raw_writel(RB750_NAND_NRE | RB750_NAND_NWE, - base + GPIO_REG_SET); + base + AR71XX_GPIO_REG_SET); /* flush write */ - (void) __raw_readl(base + GPIO_REG_SET); + (void) __raw_readl(base + AR71XX_GPIO_REG_SET); /* activate CE line */ - __raw_writel(RB750_NAND_NCE, base + GPIO_REG_CLEAR); + __raw_writel(RB750_NAND_NCE, base + AR71XX_GPIO_REG_CLEAR); } else { /* deactivate CE line */ - __raw_writel(RB750_NAND_NCE, base + GPIO_REG_SET); + __raw_writel(RB750_NAND_NCE, base + AR71XX_GPIO_REG_SET); /* flush write */ - (void) __raw_readl(base + GPIO_REG_SET); + (void) __raw_readl(base + AR71XX_GPIO_REG_SET); - __raw_writel(__raw_readl(base + GPIO_REG_OE) | - RB750_NAND_IO0 | RB750_NAND_RDY, - base + GPIO_REG_OE); + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(t | RB750_NAND_IO0 | RB750_NAND_RDY, + base + AR71XX_GPIO_REG_OE); /* restore alternate functions */ ar71xx_gpio_function_setup(AR724X_GPIO_FUNC_SPI_EN, @@ -182,7 +185,7 @@ static int rb750_nand_dev_ready(struct mtd_info *mtd) { void __iomem *base = ar71xx_gpio_base; - return !!(__raw_readl(base + GPIO_REG_IN) & RB750_NAND_RDY); + return !!(__raw_readl(base + AR71XX_GPIO_REG_IN) & RB750_NAND_RDY); } static void rb750_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, @@ -192,15 +195,15 @@ static void rb750_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, void __iomem *base = ar71xx_gpio_base; u32 t; - t = __raw_readl(base + GPIO_REG_OUT); + t = __raw_readl(base + AR71XX_GPIO_REG_OUT); t &= ~(RB750_NAND_CLE | RB750_NAND_ALE); t |= (ctrl & NAND_CLE) ? RB750_NAND_CLE : 0; t |= (ctrl & NAND_ALE) ? RB750_NAND_ALE : 0; - __raw_writel(t, base + GPIO_REG_OUT); + __raw_writel(t, base + AR71XX_GPIO_REG_OUT); /* flush write */ - __raw_readl(base + GPIO_REG_OUT); + __raw_readl(base + AR71XX_GPIO_REG_OUT); } if (cmd != NAND_CMD_NONE) { @@ -235,23 +238,24 @@ static void __init rb750_nand_gpio_init(void) { void __iomem *base = ar71xx_gpio_base; u32 out; + u32 t; - out = __raw_readl(base + GPIO_REG_OUT); + out = __raw_readl(base + AR71XX_GPIO_REG_OUT); /* setup output levels */ __raw_writel(RB750_NAND_NCE | RB750_NAND_NRE | RB750_NAND_NWE, - base + GPIO_REG_SET); + base + AR71XX_GPIO_REG_SET); __raw_writel(RB750_NAND_ALE | RB750_NAND_CLE, - base + GPIO_REG_CLEAR); + base + AR71XX_GPIO_REG_CLEAR); /* setup input lines */ - __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~(RB750_NAND_INPUT_BITS), - base + GPIO_REG_OE); + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(t & ~(RB750_NAND_INPUT_BITS), base + AR71XX_GPIO_REG_OE); /* setup output lines */ - __raw_writel(__raw_readl(base + GPIO_REG_OE) | RB750_NAND_OUTPUT_BITS, - base + GPIO_REG_OE); + t = __raw_readl(base + AR71XX_GPIO_REG_OE); + __raw_writel(t | RB750_NAND_OUTPUT_BITS, base + AR71XX_GPIO_REG_OE); rb750_latch_change(~out & RB750_NAND_IO0, out & RB750_NAND_IO0); } |