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author | Gabor Juhos <juhosg@openwrt.org> | 2009-05-02 19:59:19 +0000 |
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committer | Gabor Juhos <juhosg@openwrt.org> | 2009-05-02 19:59:19 +0000 |
commit | 1de7321026a71ec8249e2e3df7a7c5c8cdf65f9f (patch) | |
tree | f5ddb0452dffc986234401fbfa23d7a62377a61c /target/linux/ar71xx/patches-2.6.30/902-mips_clocksource_init_war.patch | |
parent | 1a24fcd9ecdeb5256c80ccde1530943d15b7a9a6 (diff) | |
download | master-31e0f0ae-1de7321026a71ec8249e2e3df7a7c5c8cdf65f9f.tar.gz master-31e0f0ae-1de7321026a71ec8249e2e3df7a7c5c8cdf65f9f.tar.bz2 master-31e0f0ae-1de7321026a71ec8249e2e3df7a7c5c8cdf65f9f.zip |
add experimental support for 2.6.30
SVN-Revision: 15561
Diffstat (limited to 'target/linux/ar71xx/patches-2.6.30/902-mips_clocksource_init_war.patch')
-rw-r--r-- | target/linux/ar71xx/patches-2.6.30/902-mips_clocksource_init_war.patch | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-2.6.30/902-mips_clocksource_init_war.patch b/target/linux/ar71xx/patches-2.6.30/902-mips_clocksource_init_war.patch new file mode 100644 index 0000000000..03a66ff133 --- /dev/null +++ b/target/linux/ar71xx/patches-2.6.30/902-mips_clocksource_init_war.patch @@ -0,0 +1,56 @@ +--- a/arch/mips/kernel/cevt-r4k.c ++++ b/arch/mips/kernel/cevt-r4k.c +@@ -15,6 +15,22 @@ + #include <asm/cevt-r4k.h> + + /* ++ * Compare interrupt can be routed and latched outside the core, ++ * so a single execution hazard barrier may not be enough to give ++ * it time to clear as seen in the Cause register. 4 time the ++ * pipeline depth seems reasonably conservative, and empirically ++ * works better in configurations with high CPU/bus clock ratios. ++ */ ++ ++#define compare_change_hazard() \ ++ do { \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ irq_disable_hazard(); \ ++ } while (0) ++ ++/* + * The SMTC Kernel for the 34K, 1004K, et. al. replaces several + * of these routines with SMTC-specific variants. + */ +@@ -30,6 +46,7 @@ static int mips_next_event(unsigned long + cnt = read_c0_count(); + cnt += delta; + write_c0_compare(cnt); ++ compare_change_hazard(); + res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; + return res; + } +@@ -99,22 +116,6 @@ static int c0_compare_int_pending(void) + return (read_c0_cause() >> cp0_compare_irq) & 0x100; + } + +-/* +- * Compare interrupt can be routed and latched outside the core, +- * so a single execution hazard barrier may not be enough to give +- * it time to clear as seen in the Cause register. 4 time the +- * pipeline depth seems reasonably conservative, and empirically +- * works better in configurations with high CPU/bus clock ratios. +- */ +- +-#define compare_change_hazard() \ +- do { \ +- irq_disable_hazard(); \ +- irq_disable_hazard(); \ +- irq_disable_hazard(); \ +- irq_disable_hazard(); \ +- } while (0) +- + int c0_compare_int_usable(void) + { + unsigned int delta; |