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author | Gabor Juhos <juhosg@openwrt.org> | 2012-10-28 19:52:02 +0000 |
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committer | Gabor Juhos <juhosg@openwrt.org> | 2012-10-28 19:52:02 +0000 |
commit | e4db63fd64b1716715ac7289dc6f1fc48593d4af (patch) | |
tree | c5493128b26209a31354c173a6c020f4cbf37ef6 /target/linux/ar71xx/patches-3.6/505-MIPS-ath79-add-ath79_gpio_function_select.patch | |
parent | 87186c5ed4681ba9830c072f4487e206147c973d (diff) | |
download | master-31e0f0ae-e4db63fd64b1716715ac7289dc6f1fc48593d4af.tar.gz master-31e0f0ae-e4db63fd64b1716715ac7289dc6f1fc48593d4af.tar.bz2 master-31e0f0ae-e4db63fd64b1716715ac7289dc6f1fc48593d4af.zip |
ar71xx: add initial support for 3.6
The nand subtarget is not working yet.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 33983
Diffstat (limited to 'target/linux/ar71xx/patches-3.6/505-MIPS-ath79-add-ath79_gpio_function_select.patch')
-rw-r--r-- | target/linux/ar71xx/patches-3.6/505-MIPS-ath79-add-ath79_gpio_function_select.patch | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-3.6/505-MIPS-ath79-add-ath79_gpio_function_select.patch b/target/linux/ar71xx/patches-3.6/505-MIPS-ath79-add-ath79_gpio_function_select.patch new file mode 100644 index 0000000000..6b09fc0a9b --- /dev/null +++ b/target/linux/ar71xx/patches-3.6/505-MIPS-ath79-add-ath79_gpio_function_select.patch @@ -0,0 +1,47 @@ +--- a/arch/mips/ath79/common.h ++++ b/arch/mips/ath79/common.h +@@ -26,6 +26,7 @@ void ath79_ddr_wb_flush(unsigned int reg + void ath79_gpio_function_enable(u32 mask); + void ath79_gpio_function_disable(u32 mask); + void ath79_gpio_function_setup(u32 set, u32 clear); ++void ath79_gpio_output_select(unsigned gpio, u8 val); + void ath79_gpio_init(void); + + #endif /* __ATH79_COMMON_H */ +--- a/arch/mips/ath79/gpio.c ++++ b/arch/mips/ath79/gpio.c +@@ -184,6 +184,34 @@ void ath79_gpio_function_setup(u32 set, + spin_unlock_irqrestore(&ath79_gpio_lock, flags); + } + ++void __init ath79_gpio_output_select(unsigned gpio, u8 val) ++{ ++ void __iomem *base = ath79_gpio_base; ++ unsigned long flags; ++ unsigned int reg; ++ u32 t, s; ++ ++ BUG_ON(!soc_is_ar934x()); ++ ++ if (gpio >= AR934X_GPIO_COUNT) ++ return; ++ ++ reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4); ++ s = 8 * (gpio % 4); ++ ++ spin_lock_irqsave(&ath79_gpio_lock, flags); ++ ++ t = __raw_readl(base + reg); ++ t &= ~(0xff << s); ++ t |= val << s; ++ __raw_writel(t, base + reg); ++ ++ /* flush write */ ++ (void) __raw_readl(base + reg); ++ ++ spin_unlock_irqrestore(&ath79_gpio_lock, flags); ++} ++ + void __init ath79_gpio_init(void) + { + int err; |