diff options
author | Jonas Gorski <jogo@openwrt.org> | 2014-07-12 12:31:47 +0000 |
---|---|---|
committer | Jonas Gorski <jogo@openwrt.org> | 2014-07-12 12:31:47 +0000 |
commit | 2b6403722bad259bb23312437359a1849a0e0d12 (patch) | |
tree | 560d14f0b26144627ea39252ea83030453a2351f /target/linux/brcm63xx/patches-3.10/323-MIPS-BCM63XX-add-cpu-argument-to-dispatch-internal.patch | |
parent | ba9d2f397a9046c5d75a689fedd745ff96e7864b (diff) | |
download | master-31e0f0ae-2b6403722bad259bb23312437359a1849a0e0d12.tar.gz master-31e0f0ae-2b6403722bad259bb23312437359a1849a0e0d12.tar.bz2 master-31e0f0ae-2b6403722bad259bb23312437359a1849a0e0d12.zip |
brcm63xx: update irq affinity code to latest version
Reduces code size a bit and sets affinity to boot cpu by default.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 41591
Diffstat (limited to 'target/linux/brcm63xx/patches-3.10/323-MIPS-BCM63XX-add-cpu-argument-to-dispatch-internal.patch')
-rw-r--r-- | target/linux/brcm63xx/patches-3.10/323-MIPS-BCM63XX-add-cpu-argument-to-dispatch-internal.patch | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/target/linux/brcm63xx/patches-3.10/323-MIPS-BCM63XX-add-cpu-argument-to-dispatch-internal.patch b/target/linux/brcm63xx/patches-3.10/323-MIPS-BCM63XX-add-cpu-argument-to-dispatch-internal.patch new file mode 100644 index 0000000000..395dc13d8d --- /dev/null +++ b/target/linux/brcm63xx/patches-3.10/323-MIPS-BCM63XX-add-cpu-argument-to-dispatch-internal.patch @@ -0,0 +1,70 @@ +From 43ebef8162adfa7789cb915e60e46103965d7efd Mon Sep 17 00:00:00 2001 +From: Jonas Gorski <jogo@openwrt.org> +Date: Fri, 26 Apr 2013 11:21:16 +0200 +Subject: [PATCH 06/10] MIPS: BCM63XX: add cpu argument to dispatch internal + +Signed-off-by: Jonas Gorski <jogo@openwrt.org> +--- + arch/mips/bcm63xx/irq.c | 18 ++++++++++-------- + 1 file changed, 10 insertions(+), 8 deletions(-) + +--- a/arch/mips/bcm63xx/irq.c ++++ b/arch/mips/bcm63xx/irq.c +@@ -19,9 +19,10 @@ + #include <bcm63xx_io.h> + #include <bcm63xx_irq.h> + ++ + static u32 irq_stat_addr[2]; + static u32 irq_mask_addr[2]; +-static void (*dispatch_internal)(void); ++static void (*dispatch_internal)(int cpu); + static int is_ext_irq_cascaded; + static unsigned int ext_irq_count; + static unsigned int ext_irq_start, ext_irq_end; +@@ -54,19 +55,20 @@ static inline void handle_internal(int i + */ + + #define BUILD_IPIC_INTERNAL(width) \ +-void __dispatch_internal_##width(void) \ ++void __dispatch_internal_##width(int cpu) \ + { \ + u32 pending[width / 32]; \ + unsigned int src, tgt; \ + bool irqs_pending = false; \ +- static unsigned int i; \ ++ static unsigned int i[2]; \ ++ unsigned int *next = &i[cpu]; \ + \ + /* read registers in reverse order */ \ + for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \ + u32 val; \ + \ +- val = bcm_readl(irq_stat_addr[0] + src * sizeof(u32)); \ +- val &= bcm_readl(irq_mask_addr[0] + src * sizeof(u32)); \ ++ val = bcm_readl(irq_stat_addr[cpu] + src * sizeof(u32)); \ ++ val &= bcm_readl(irq_mask_addr[cpu] + src * sizeof(u32)); \ + pending[--tgt] = val; \ + \ + if (val) \ +@@ -77,9 +79,9 @@ void __dispatch_internal_##width(void) + return; \ + \ + while (1) { \ +- unsigned int to_call = i; \ ++ unsigned int to_call = *next; \ + \ +- i = (i + 1) & (width - 1); \ ++ *next = (*next + 1) & (width - 1); \ + if (pending[to_call / 32] & (1 << (to_call & 0x1f))) { \ + handle_internal(to_call); \ + break; \ +@@ -129,7 +131,7 @@ asmlinkage void plat_irq_dispatch(void) + if (cause & CAUSEF_IP1) + do_IRQ(1); + if (cause & CAUSEF_IP2) +- dispatch_internal(); ++ dispatch_internal(0); + if (!is_ext_irq_cascaded) { + if (cause & CAUSEF_IP3) + do_IRQ(IRQ_EXT_0); |