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author | John Crispin <john@openwrt.org> | 2012-08-03 08:53:02 +0000 |
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committer | John Crispin <john@openwrt.org> | 2012-08-03 08:53:02 +0000 |
commit | 060b161ca6f18e0e022da1483723ad2e9335bca7 (patch) | |
tree | dc652c26bed4d4b79395a6daafaa5da59000e940 /target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h | |
parent | 162e272b4b2b770cd5eb97006bb4ff99b09bd8de (diff) | |
download | master-31e0f0ae-060b161ca6f18e0e022da1483723ad2e9335bca7.tar.gz master-31e0f0ae-060b161ca6f18e0e022da1483723ad2e9335bca7.tar.bz2 master-31e0f0ae-060b161ca6f18e0e022da1483723ad2e9335bca7.zip |
cleanup patches
SVN-Revision: 32953
Diffstat (limited to 'target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h')
-rw-r--r-- | target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h new file mode 100644 index 0000000000..bca8df9fd5 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h @@ -0,0 +1,35 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2010 Lantiq + */ +#ifndef __SVIP_IRQ_H +#define __SVIP_IRQ_H + +#define IM_NUM 6 + +#define INT_NUM_IRQ0 8 +#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) +#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32) +#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32) +#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32) +#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32) +#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32) +#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0) + +#define INT_NUM_IM5_IRL0 (INT_NUM_IRQ0 + 160) +#define MIPS_CPU_TIMER_IRQ (INT_NUM_IM5_IRL0 + 2) + +#endif |