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| author | Imre Kaloz <kaloz@openwrt.org> | 2014-06-17 15:13:10 +0000 |
|---|---|---|
| committer | Imre Kaloz <kaloz@openwrt.org> | 2014-06-17 15:13:10 +0000 |
| commit | d775e4ef00e08c839a41e101552be171ff638d3d (patch) | |
| tree | 4024679a777f738166057959372d0706830fcd7e /target/linux/mvebu/patches-3.14/011-pxa3xx_nand_clean_error_handling.patch | |
| parent | 099d998fcf21c80e25a9518607285d1437d89be9 (diff) | |
| download | master-31e0f0ae-d775e4ef00e08c839a41e101552be171ff638d3d.tar.gz master-31e0f0ae-d775e4ef00e08c839a41e101552be171ff638d3d.tar.bz2 master-31e0f0ae-d775e4ef00e08c839a41e101552be171ff638d3d.zip | |
preliminary support for the WRT1900AC (work in progress)
SVN-Revision: 41232
Diffstat (limited to 'target/linux/mvebu/patches-3.14/011-pxa3xx_nand_clean_error_handling.patch')
| -rw-r--r-- | target/linux/mvebu/patches-3.14/011-pxa3xx_nand_clean_error_handling.patch | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/target/linux/mvebu/patches-3.14/011-pxa3xx_nand_clean_error_handling.patch b/target/linux/mvebu/patches-3.14/011-pxa3xx_nand_clean_error_handling.patch new file mode 100644 index 0000000000..06757e803e --- /dev/null +++ b/target/linux/mvebu/patches-3.14/011-pxa3xx_nand_clean_error_handling.patch @@ -0,0 +1,78 @@ +From eee0166d8ead9d719d794df3e66acd8f83630e05 Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> +Date: Wed, 14 May 2014 14:58:07 -0300 +Subject: mtd: nand: pxa3xx: Clean pxa_ecc_init() error handling + +Let's make pxa_ecc_init() return a negative errno on error or zero +if succesful, which is standard kernel practice. Also, report the +selected ECC strength and step size, which is important information. + +Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> +Signed-off-by: Brian Norris <computersforpeace@gmail.com> + +--- a/drivers/mtd/nand/pxa3xx_nand.c ++++ b/drivers/mtd/nand/pxa3xx_nand.c +@@ -1355,7 +1355,6 @@ static int pxa_ecc_init(struct pxa3xx_na + ecc->mode = NAND_ECC_HW; + ecc->size = 512; + ecc->strength = 1; +- return 1; + + } else if (strength == 1 && ecc_stepsize == 512 && page_size == 512) { + info->chunk_size = 512; +@@ -1364,7 +1363,6 @@ static int pxa_ecc_init(struct pxa3xx_na + ecc->mode = NAND_ECC_HW; + ecc->size = 512; + ecc->strength = 1; +- return 1; + + /* + * Required ECC: 4-bit correction per 512 bytes +@@ -1379,7 +1377,6 @@ static int pxa_ecc_init(struct pxa3xx_na + ecc->size = info->chunk_size; + ecc->layout = &ecc_layout_2KB_bch4bit; + ecc->strength = 16; +- return 1; + + } else if (strength == 4 && ecc_stepsize == 512 && page_size == 4096) { + info->ecc_bch = 1; +@@ -1390,7 +1387,6 @@ static int pxa_ecc_init(struct pxa3xx_na + ecc->size = info->chunk_size; + ecc->layout = &ecc_layout_4KB_bch4bit; + ecc->strength = 16; +- return 1; + + /* + * Required ECC: 8-bit correction per 512 bytes +@@ -1405,8 +1401,15 @@ static int pxa_ecc_init(struct pxa3xx_na + ecc->size = info->chunk_size; + ecc->layout = &ecc_layout_4KB_bch8bit; + ecc->strength = 16; +- return 1; ++ } else { ++ dev_err(&info->pdev->dev, ++ "ECC strength %d at page size %d is not supported\n", ++ strength, page_size); ++ return -ENODEV; + } ++ ++ dev_info(&info->pdev->dev, "ECC strength %d, ECC step size %d\n", ++ ecc->strength, ecc->size); + return 0; + } + +@@ -1528,12 +1531,8 @@ KEEP_CONFIG: + + ret = pxa_ecc_init(info, &chip->ecc, ecc_strength, + ecc_step, mtd->writesize); +- if (!ret) { +- dev_err(&info->pdev->dev, +- "ECC strength %d at page size %d is not supported\n", +- ecc_strength, mtd->writesize); +- return -ENODEV; +- } ++ if (ret) ++ return ret; + + /* calculate addressing information */ + if (mtd->writesize >= 2048) |