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author | John Crispin <john@openwrt.org> | 2014-11-26 09:00:08 +0000 |
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committer | John Crispin <john@openwrt.org> | 2014-11-26 09:00:08 +0000 |
commit | 72b58f2eb12ad4aa0c59481d0911dc5e39180eb5 (patch) | |
tree | be51e2d36c4175443bd3ab42824df80c6b9a2efe /target/linux/oxnas/files/arch/arm/mach-oxnas/fiq.S | |
parent | 40da7aae54ad7f098064f18e28eb8201afedfd5c (diff) | |
download | master-31e0f0ae-72b58f2eb12ad4aa0c59481d0911dc5e39180eb5.tar.gz master-31e0f0ae-72b58f2eb12ad4aa0c59481d0911dc5e39180eb5.tar.bz2 master-31e0f0ae-72b58f2eb12ad4aa0c59481d0911dc5e39180eb5.zip |
add new target 'oxnas'
This is the oxnas target previously developed at
http://gitorious.org/openwrt-oxnas
Basically, this consolidates the changes and addtionas from
http://github.org/kref/linux-oxnas
into a new OpenWrt hardware target 'oxnas' adding support for
PLX Technology NAS7820/NAS7821/NAS7825/...
formally known as
Oxford Semiconductor OXE810SE/OXE815/OX820/...
For now there are 4 supported boards:
Cloud Engines Pogoplug V3 (without PCIe)
fully supported
Cloud Engines Pogoplug Pro (with PCIe)
fully supported
MitraStar STG-212
aka ZyXEL NSA-212,
aka Medion Akoya P89625 / P89636 / P89626 / P89630,
aka Medion MD 86407 / MD 86805 / MD 86517 / MD 86587
fully supported, see http://wiki.openwrt.org/toh/medion/md86587
Shuttle KD-20
partially supported (S-ATA driver lacks support for 2nd port)
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
SVN-Revision: 43388
Diffstat (limited to 'target/linux/oxnas/files/arch/arm/mach-oxnas/fiq.S')
-rw-r--r-- | target/linux/oxnas/files/arch/arm/mach-oxnas/fiq.S | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/target/linux/oxnas/files/arch/arm/mach-oxnas/fiq.S b/target/linux/oxnas/files/arch/arm/mach-oxnas/fiq.S new file mode 100644 index 0000000000..6acd5a7394 --- /dev/null +++ b/target/linux/oxnas/files/arch/arm/mach-oxnas/fiq.S @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2012 Gateworks Corporation + * Chris Lang <clang@gateworks.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <linux/linkage.h> +#include <asm/assembler.h> +#include <asm/asm-offsets.h> + +#define D_CACHE_LINE_SIZE 32 + + .text + +/* + * R8 - DMA Start Address + * R9 - DMA Length + * R10 - DMA Direction + * R11 - DMA type + * R12 - fiq_buffer Address +*/ + + .global ox820_fiq_end +ENTRY(ox820_fiq_start) + str r8, [r13] + + ldmia r12, {r8, r9, r10} + and r11, r10, #0x3000000 + and r10, r10, #0xff + + teq r11, #0x1000000 + beq ox820_dma_map_area + teq r11, #0x2000000 + beq ox820_dma_unmap_area + /* fall through */ +ox820_dma_flush_range: + bic r8, r8, #D_CACHE_LINE_SIZE - 1 +1: + mcr p15, 0, r8, c7, c14, 1 @ clean & invalidate D line + add r8, r8, #D_CACHE_LINE_SIZE + cmp r8, r9 + blo 1b + /* fall through */ +ox820_fiq_exit: + mov r8, #0 + str r8, [r12, #8] + mcr p15, 0, r8, c7, c10, 4 @ drain write buffer + subs pc, lr, #4 + +ox820_dma_map_area: + add r9, r9, r8 + teq r10, #DMA_FROM_DEVICE + beq ox820_dma_inv_range + teq r10, #DMA_TO_DEVICE + bne ox820_dma_flush_range + /* fall through */ +ox820_dma_clean_range: + bic r8, r8, #D_CACHE_LINE_SIZE - 1 +1: + mcr p15, 0, r8, c7, c10, 1 @ clean D line + add r8, r8, #D_CACHE_LINE_SIZE + cmp r8, r9 + blo 1b + b ox820_fiq_exit + +ox820_dma_unmap_area: + add r9, r9, r8 + teq r10, #DMA_TO_DEVICE + beq ox820_fiq_exit + /* fall through */ +ox820_dma_inv_range: + tst r8, #D_CACHE_LINE_SIZE - 1 + bic r8, r8, #D_CACHE_LINE_SIZE - 1 + mcrne p15, 0, r8, c7, c10, 1 @ clean D line + tst r9, #D_CACHE_LINE_SIZE - 1 + bic r9, r9, #D_CACHE_LINE_SIZE - 1 + mcrne p15, 0, r9, c7, c14, 1 @ clean & invalidate D line +1: + mcr p15, 0, r8, c7, c6, 1 @ invalidate D line + add r8, r8, #D_CACHE_LINE_SIZE + cmp r8, r9 + blo 1b + b ox820_fiq_exit + +ox820_fiq_end: |