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author | Gabor Juhos <juhosg@openwrt.org> | 2010-04-11 17:47:30 +0000 |
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committer | Gabor Juhos <juhosg@openwrt.org> | 2010-04-11 17:47:30 +0000 |
commit | de18353622a4d245f8b407a6f214cfbe53ec9706 (patch) | |
tree | ed8de0f1d0b0537fdc59ea114bb0a6438e600212 /target/linux/ramips/patches-2.6.32 | |
parent | b4bb5ebfaa8d3cffe46f9516ab103a36131ac2cc (diff) | |
download | master-31e0f0ae-de18353622a4d245f8b407a6f214cfbe53ec9706.tar.gz master-31e0f0ae-de18353622a4d245f8b407a6f214cfbe53ec9706.tar.bz2 master-31e0f0ae-de18353622a4d245f8b407a6f214cfbe53ec9706.zip |
ramips: nuke clocksource init patch
SVN-Revision: 20802
Diffstat (limited to 'target/linux/ramips/patches-2.6.32')
-rw-r--r-- | target/linux/ramips/patches-2.6.32/002-mips-clocksource-init-war.patch | 56 |
1 files changed, 0 insertions, 56 deletions
diff --git a/target/linux/ramips/patches-2.6.32/002-mips-clocksource-init-war.patch b/target/linux/ramips/patches-2.6.32/002-mips-clocksource-init-war.patch deleted file mode 100644 index 894eed1e5b..0000000000 --- a/target/linux/ramips/patches-2.6.32/002-mips-clocksource-init-war.patch +++ /dev/null @@ -1,56 +0,0 @@ ---- a/arch/mips/kernel/cevt-r4k.c -+++ b/arch/mips/kernel/cevt-r4k.c -@@ -16,6 +16,22 @@ - #include <asm/cevt-r4k.h> - - /* -+ * Compare interrupt can be routed and latched outside the core, -+ * so a single execution hazard barrier may not be enough to give -+ * it time to clear as seen in the Cause register. 4 time the -+ * pipeline depth seems reasonably conservative, and empirically -+ * works better in configurations with high CPU/bus clock ratios. -+ */ -+ -+#define compare_change_hazard() \ -+ do { \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ irq_disable_hazard(); \ -+ } while (0) -+ -+/* - * The SMTC Kernel for the 34K, 1004K, et. al. replaces several - * of these routines with SMTC-specific variants. - */ -@@ -31,6 +47,7 @@ static int mips_next_event(unsigned long - cnt = read_c0_count(); - cnt += delta; - write_c0_compare(cnt); -+ compare_change_hazard(); - res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; - return res; - } -@@ -100,22 +117,6 @@ static int c0_compare_int_pending(void) - return (read_c0_cause() >> cp0_compare_irq) & 0x100; - } - --/* -- * Compare interrupt can be routed and latched outside the core, -- * so a single execution hazard barrier may not be enough to give -- * it time to clear as seen in the Cause register. 4 time the -- * pipeline depth seems reasonably conservative, and empirically -- * works better in configurations with high CPU/bus clock ratios. -- */ -- --#define compare_change_hazard() \ -- do { \ -- irq_disable_hazard(); \ -- irq_disable_hazard(); \ -- irq_disable_hazard(); \ -- irq_disable_hazard(); \ -- } while (0) -- - int c0_compare_int_usable(void) - { - unsigned int delta; |