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author | Lars-Peter Clausen <lars@metafoo.de> | 2010-08-04 13:33:55 +0000 |
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committer | Lars-Peter Clausen <lars@metafoo.de> | 2010-08-04 13:33:55 +0000 |
commit | 1980190a5a96fba4d36be8f8037ba9925c263b57 (patch) | |
tree | 5be4947af9799c165de22a46b0db260d2d6d3d91 /target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/head.S | |
parent | f312e1580b6053bc87c931dbd588197d77c9f691 (diff) | |
download | master-31e0f0ae-1980190a5a96fba4d36be8f8037ba9925c263b57.tar.gz master-31e0f0ae-1980190a5a96fba4d36be8f8037ba9925c263b57.tar.bz2 master-31e0f0ae-1980190a5a96fba4d36be8f8037ba9925c263b57.zip |
Drop 2.6.32 patches
SVN-Revision: 22485
Diffstat (limited to 'target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/head.S')
-rw-r--r-- | target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/head.S | 85 |
1 files changed, 0 insertions, 85 deletions
diff --git a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/head.S b/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/head.S deleted file mode 100644 index d9700eb502..0000000000 --- a/target/linux/xburst/files-2.6.32/arch/mips/boot/compressed/head.S +++ /dev/null @@ -1,85 +0,0 @@ -/* - * linux/arch/mips/boot/compressed/head.S - * - * Copyright (C) 2005-2008 Ingenic Semiconductor Inc. - */ - -#include <asm/asm.h> -#include <asm/cacheops.h> -#include <asm/cachectl.h> -#include <asm/regdef.h> - -#define IndexInvalidate_I 0x00 -#define IndexWriteBack_D 0x01 - - .set noreorder - LEAF(startup) -startup: - move s0, a0 /* Save the boot loader transfered args */ - move s1, a1 - move s2, a2 - move s3, a3 - - la a0, _edata - la a1, _end -1: sw zero, 0(a0) /* Clear BSS section */ - bne a1, a0, 1b - addu a0, 4 - - la sp, (.stack + 8192) - - la a0, __image_begin - la a1, IMAGESIZE - la a2, LOADADDR - la ra, 1f - la k0, decompress_kernel - jr k0 - nop -1: - - move a0, s0 - move a1, s1 - move a2, s2 - move a3, s3 - li k0, KERNEL_ENTRY - jr k0 - nop -2: - b 32 - END(startup) - - - LEAF(flushcaches) - la t0, 1f - la t1, 0xa0000000 - or t0, t0, t1 - jr t0 - nop -1: - li k0, 0x80000000 # start address - li k1, 0x80004000 # end address (16KB I-Cache) - subu k1, 128 - -2: - .set mips3 - cache IndexWriteBack_D, 0(k0) - cache IndexWriteBack_D, 32(k0) - cache IndexWriteBack_D, 64(k0) - cache IndexWriteBack_D, 96(k0) - cache IndexInvalidate_I, 0(k0) - cache IndexInvalidate_I, 32(k0) - cache IndexInvalidate_I, 64(k0) - cache IndexInvalidate_I, 96(k0) - .set mips0 - - bne k0, k1, 2b - addu k0, k0, 128 - la t0, 3f - jr t0 - nop -3: - jr ra - nop - END(flushcaches) - - .comm .stack,4096*2,4 |