| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
|
|
|
| |
prevent compiler errors with gcc 4.9
increase reproducibility
Signed-off-by: Dirk Neukirchen <dirkneukirchen@web.de>
SVN-Revision: 46858
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
in the ATU. This created problems in the case of a system where two ports/devices share a MAC address (e.g. Linksys WRT1900AC eth0/eth1).
This also clears any bootloader-set FDB defaults. This had
caused issues creating port-based VLANs when mappings
overlapped previous VLANs. Packets destined to a port
not in the default port group flooded all ports.
Tested on a 88E6171 (Linksys EA4500) and 88E6172 ('1900AC)
Signed-off-by: Claudio Leite <leitec@staticky.com>
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
SVN-Revision: 46699
|
|
|
|
|
|
|
|
|
|
| |
no-op since 2.6.35
removed in Kernel 4.1
see https://lwn.net/Articles/380931/
Signed-off-by: Dirk Neukirchen <dirkneukirchen@web.de>
SVN-Revision: 46671
|
|
|
|
|
|
|
|
|
|
| |
In addition to the update this also fixes compile problems with kernel 4.1.
This closes #20323.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 46609
|
|
|
|
|
|
|
|
| |
Add swconfig attributes for flushing the ARL table globally or per port.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 46382
|
|
|
|
|
|
|
|
|
|
| |
If a link goes down, don't flush the complete ARL table.
Only flush the entries for the respective port.
Don't touch ARL table if a link goes up.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 46381
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Adds functions for flushing ARL table entries per port.
Successfully tested on AR8327. Implementation for AR8216/AR8236/AR8316
is based on the AR8236 datasheet and assumes that the three chips
share a common ATU register layout.
Compile-tested only for AR8216/AR8236/AR8316.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 46380
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Adds the chip-specific part of reading ARL table for AR8216/AR8236/AR8316.
It's based on the AR8236 datasheet and compile-tested only as I couldn't
find datasheets for AR8216/AR8316 and don't own devices with these chips.
The existing ar8216_atu_flush implementation was used for all three
chip types, therefore I guess they share a common ATU register layout.
More testing would be appreciated.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 46379
|
|
|
|
|
|
|
|
|
| |
To improve reproducibility, prevent the inclusion of timestamps
in the gzip header.
Signed-off-by: Reiner Herrmann <reiner@reiner-h.de>
SVN-Revision: 46361
|
|
|
|
|
|
|
|
|
| |
The position of the nvram header file on brcm47xx changed with kernel
version 4.1.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
SVN-Revision: 46170
|
|
|
|
|
|
|
|
|
|
|
| |
On two tested devices: Netgear R6250 (BCM53011 rev 2) and Luxul XWC-1000
(BCM53011 rev 3) it was possible to use port 7 and eth1 (instead of port
5 and eth0). It seems BCM53011 just like BCM53012 has 8 ports and
usually 3 of them are connected to the SoC.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 46104
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
AR8337 supports a configuration bit to swap MAC0 and MAC6.
Currently this is set in general if an AR8337 is detected and causes
issues with devices using an AR8334 (internally an AR8337, just
less chip pins).
And it might even cause issues with AR8337-based devices with
different board designs.
Swapping the MAC's however isn't needed for AR8337 in general.
It's just needed in case of certain board designs (affected devices
seem to be based on Atheros reference board AP135/136-010).
Therefore this configuration bit should be moved to platform data.
The patch includes the needed changes to the device initialization
code of affected devices. Hopefully I didn't miss any ..
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 45970
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
On device reset the sizes for the vlan and port tables were wrongly
calculated based on the pointer size instead of the struct size. This
causes buffer overruns on 64 bit targets, resulting in panics.
Fix this by dereferencing the pointers.
Reported-by: Fedor Konstantinov <blmink@mink.su>
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45938
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
At least on my b53 chip, the mask is 3 bits wide, and because
of this some STP states are not set properly and discarded when read.
Maybe for some other chips it makes sense to have just 2 bits width,
but I don't have other versions around to test/validate.
If that's the case then maybe we could add another STP state mask.
Signed-off-by: Alexandru Ardelean <ardeleanalex@gmail.com>
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45937
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This chipset has at least 8 usable ports, e.g. Netgear R8000 has ports
5, 7 and 8 connected to Ethernet interfaces:
vlan1ports=0 1 2 3 5 7 8*
vlan2ports=4 8u
Port 6 seems to be always disabled.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45676
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
On BCM5301X there are two different cases to handle: CPU port 8 vs. any
other one. Support for CPU port 8 was already partially implemented but
it lacked setting some extra bit for 2G speed. It also will need to be
extended to implement "SMP dual core 3 GMAC setup". That's the reason
for handling it in separated code block.
This patch also adds overriding CPU port state for port other than 8. It
requires using recently defined GMII_PORT registers.
It was tested for regressions on BCM53011 revs 2 & 3. It was also
confirmed to fix switch on some internal Broadcom board.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45402
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
* properly enclose macro arguments in paranthesis on use
* remove trailing white space
* convert C99 // comments
* add missing blank lines after declaration
* remove braces from single statement blocks
* split lines > 80 chars (except for one)
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 45356
|
|
|
|
|
|
|
|
| |
They are also present on some BCM63xx switches.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45355
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Use the latest version of the yaffs code. Fetched from the
yaffs2 git tree and it is based on the following commit:
commit 7e5cf0fa1b694f835cdc184a8395b229fa29f9ae
Author: Charles Manning <cdhmanning@gmail.com>
Date: Thu Aug 7 11:25:05 2014 +1200
yaffs-direct: Basic tests. Add lpthread flag for background gc support
Signed-off-by: Charles Manning <cdhmanning@gmail.com>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
SVN-Revision: 45188
|
|
|
|
|
|
|
| |
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 44875
|
|
|
|
|
|
|
|
|
|
|
| |
If this option is enabled, the FIT image format will be detected and
split by the mtdsplit code. Detection is based upon the FDT magic, which
will trigger the parsing and detection of the rootfs, ending-up in the
creation of the 2 new partitions.
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
SVN-Revision: 44792
|
|
|
|
|
|
|
|
|
|
| |
It will now actually enable the mib counters instead of enabling rx/tx for
the first switch port.
Reported-by: Daniel Gonzalez <dgcbueu@gmail.com>
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 44788
|
|
|
|
|
|
| |
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
SVN-Revision: 44617
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
For bcm63xx integrated switches, broadcom changed the data endianess
to match the system endianess. But this only applies to within one word,
which causes 48/64 bit values to be still split into their "litte endian"
groups.
E.g. 48 bit values (with 5 being the most significant byte) aligned
0x00 ..01 or 0123
0x04 2345 45..
will become
0x00 ..10 resp. 3210
0x04 5432 54..
Likewise for 64 bit values.
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 44568
|
|
|
|
|
|
| |
Signed-off-by: Nicolas Thill <nico@openwrt.org>
SVN-Revision: 44444
|
|
|
|
|
|
|
|
| |
We obviously can't use sizeof(*buf) which is always 1.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 44424
|
|
|
|
|
|
| |
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 44415
|
|
|
|
|
|
|
|
|
| |
We shouldn't read data directly into the header struct, as some devices
(e.g. Edimax) need more bytes due to some extra header.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 44414
|
|
|
|
|
|
| |
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 44413
|
|
|
|
|
|
|
|
|
|
| |
Some devices have uImage headers after some extra headers (e.g. Edimax
devices). To support such cases our verify callback function should be
allowed to return header offset, not just a boolean value.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 44412
|
|
|
|
|
|
|
|
| |
drivers/net/phy/adm6996.c:881:5: warning: format '%lu' expects argument of type 'long unsigned int', but argument 5 has type 'u32' [-Wformat=]
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 44333
|
|
|
|
|
|
|
|
| |
This reverts commit f7873071561d82e75ba2dc46433a2982fef8ac6f.
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 44245
|
|
|
|
|
|
| |
Signed-off-by: Christian Mehlis <christian@m3hlis.de>
SVN-Revision: 44237
|
|
|
|
|
|
|
|
|
|
|
| |
The board is already supported by OpenWrt. WNR1000v2/WNR1000v2-VC are
pretty much the same as WNR2000v3/WNR612v2, therefore the same
initialization code and flash layout is used.
Signed-off-by: Ștefan Rusu <saltwaterc@gmail.com>
Tested-by: Douglas Fraser <1dsfraser@gmail.com>
SVN-Revision: 44221
|
|
|
|
|
|
|
|
|
| |
Prefix the exported mii_xxx32 functions with ar8xxx_
to avoid kernel namespace pollution.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 44105
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add global read-only swconfig attribute "arl_table" to display the
address resolution table.
So far the chip-specific part is implemented for AR8327/AR8337 only
as I don't have the datasheets for the other AR8XXX chips.
Successfully tested on TL-WDR4300 (AR8327rev2)
and TL-WDR4900 (AR8327rev4).
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 44104
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Until a few years ago the page switch wait time was set to msleep(1)
what was changed to usleep_range(1000, 2000) later.
I can not imagine that a low-level operation like switching page
on register level takes so much time.
Most likely the value of 1ms was initially set to check whether
it fixes an issue and then remained w/o further checking whether
also a smaller value would be sufficient.
Now the wait time is set to 5us and I successfully tested this on
AR8327. IMHO 5us should be plenty of time for all supported chips.
However I couldn't test this due to missing hardware.
If other chips should need a longer wait time we can add the
wait time as a parameter to the ar8xxx_chip struct.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 44103
|
|
|
|
|
|
|
|
|
|
| |
Check for switch port link changes and
- flush ATU in case of a change
- report link change via syslog
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 44102
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The functionality to flush the address translation table contains two bugs
which luckily compensate each other.
1. Just setting the operation is not sufficient to perform the flushing.
The "active" bit needs to be set to actually trigger an action.
For the vtu operations this is implemented correctly.
2. ar8xxx_phy_read_status is called every 2s by the phy state machine
to check for link changes. This would have caused an ATU flush
every 2s.
Fix the chip-specific ATU flush functions and remove the ATU flush call
from ar8xxx_phy_read_status.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 44101
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
autonegatiation too
The swconfig get_link attribute (at least) on AR8327/AR8337 doesn't
consider the autonegotiated flow control.
AR8327/AR8337 provide the info about autonegotiated rx/tx flow control
in bits 10 and 11 of the port status register.
Use these values to display info about autonegotiated rx/tx flow
control as part of the get_link attribute.
Successfully tested on TL-WDR4900 (AR8327 rev.4) and
TL-WDR4300 (AR8327 rev.2).
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 44023
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
AR8327/AR8337 allow to read the result of EEE autonegotiation.
If EEE is autonegotiated between the link partners, display
this as part of the swconfig get_link attribute.
eee100: 100MBit EEE supported by both link partners
eee1000: 1GBit EEE supported by both link partners
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 44022
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Users reported network issues with AR8327 which turned out to be caused
by EEE not working correctly with certain link partners (ticket 14597).
The workaround was to disable EEE on all ports (changeset 41577).
The issue was with certain link partners only, therefore this patch
allows to control usage of EEE per port via swconfig.
Still the default is to initially disable EEE on all ports.
Successfully tested on a TL-WDR4900 (AR8327 rev.4)
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 44021
|
|
|
|
|
|
|
|
| |
Introduce ar8xxx_reg_clear complementing ar8xxx_reg_set.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 44004
|
|
|
|
|
|
|
|
| |
Replace ar8xxx_rmw with ar8xxx_reg_set where appropriate.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 44003
|
|
|
|
|
|
|
|
| |
Define all switch_addr structs as const.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 44002
|
|
|
|
|
|
|
|
|
|
| |
Since the driver doesn't know anything about (M)STP
we just hard-set the ports to be enabled if they are
part of the VLAN.
Signed-off-by: Claudio Leite <leitec@staticky.com>
SVN-Revision: 43938
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
- eliminate MV_CPUPORT; not necessary since we define
the CPU port(s) via Device Tree
- add STU and expand VTU operations
- update register names to match those of 88E61xx rather than
mvswitch's 88E6060
- use more consistent formatting
Signed-off-by: Claudio Leite <leitec@staticky.com>
SVN-Revision: 43937
|
|
|
|
|
|
|
|
| |
Recognizes 88E6171/6172/6176 at the moment.
Signed-off-by: Claudio Leite <leitec@staticky.com>
SVN-Revision: 43936
|
|
|
|
|
|
|
|
|
| |
In preparation for properly supporting switches
beyond the 88E6171.
Signed-off-by: Claudio Leite <leitec@staticky.com>
SVN-Revision: 43935
|
|
|
|
|
|
|
|
|
|
| |
Move all AR8327/AR8337-specific driver code into a separate source file
ar8327.c and adjust patches so that ar8327.c is compiled if
CONFIG_AR8216_PHY is set.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
SVN-Revision: 43845
|