openwrt/em-br6478acv2/lede/master-31e0f0ae - Edimax BR-6578AC V2 base from https://github.com/ulli-kroll/lede.git

	Commit message (Collapse)	Author	Age	Files	Lines
*	move files to files-3.7	John Crispin	2013-04-03	1	-133/+0
\| \| \| \| \| \|	Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 36161
*	ramips/rt305x: add initial support for Rt5350 SoC	Gabor Juhos	2012-09-12	1	-0/+21
\| \| \| \| \| \| \| \| \| \| \| \| \|	Somehow detecting the RAM size in common/setup.c doesn't work here, it always detects 64M and then crashes on devices with less RAM. Probably using MEMC_REG_SDRAM_CFG1 to know the RAM size is how it could be, for now I use the mem=32M kernel parameter to get stuff working. Signed-off-by: Daniel Golle <dgolle@allnet.de> SVN-Revision: 33381
*	uart_clk on Rt3352F is always 40MHz	John Crispin	2012-07-24	1	-1/+1
\| \| \| \| \| \| \| \| \|	Currently, sys_clk/10 is used which is just wrong. cpu_clk/10 would work for systems with 400MHz CPU clock. Signed-off-by: Daniel Golle <dgolle@allnet.de> SVN-Revision: 32812
*	ramips: rt305x: fix CPU clock detection on RT3352	Gabor Juhos	2012-04-21	1	-12/+31
\| \| \| \|	SVN-Revision: 31401
*	ramips: rt305x: rename SYSTEM_CONFIG_* defines to RT305X_SYSCFG_*	Gabor Juhos	2012-03-11	1	-3/+3
\| \| \| \|	SVN-Revision: 30889
*	ramips: implement clock API for RT305X	Gabor Juhos	2011-01-26	1	-0/+93
	SVN-Revision: 25124