From bef829efa5b00d909136593931290345f88ca4e6 Mon Sep 17 00:00:00 2001 From: Felix Fietkau Date: Sat, 24 Jan 2015 22:45:28 +0000 Subject: ralink: fix ethernet feature TSO not work * fix TSO features verify on mt7621 firewrt board * improve tx clean up. no need to access uncached memory. also use TX_DTX register instead of read tx ring DONE bit * mt7621 need napi weight 64 to get more performance * remove netif_receive_skb, after kernel version 3.7 tcp4_gro_receive can handle tcp checksum. on rt2880 use iperf tcp LAN to WAN throughput test. with gro 135 Mbits/sec. without gro 80.4Mbits/sec. Signed-off-by: michael lee SVN-Revision: 44118 --- .../drivers/net/ethernet/ralink/ralink_soc_eth.h | 33 ++++++++++++++++------ 1 file changed, 25 insertions(+), 8 deletions(-) (limited to 'target/linux/ramips/files/drivers/net/ethernet/ralink/ralink_soc_eth.h') diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/ralink_soc_eth.h b/target/linux/ramips/files/drivers/net/ethernet/ralink/ralink_soc_eth.h index 8433c3cc12..8c204768b7 100644 --- a/target/linux/ramips/files/drivers/net/ethernet/ralink/ralink_soc_eth.h +++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/ralink_soc_eth.h @@ -51,7 +51,7 @@ enum fe_work_flag { FE_FLAG_MAX }; -#define FE_DRV_VERSION "0.1.1" +#define FE_DRV_VERSION "0.1.2" /* power of 2 to let NEXT_TX_DESP_IDX work */ #ifdef CONFIG_SOC_MT7621 @@ -322,11 +322,12 @@ struct fe_rx_dma { unsigned int rxd4; } __packed __aligned(4); -#define TX_DMA_PLEN0_MASK ((0x3fff) << 16) -#define TX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) -#define TX_DMA_PLEN1(_x) ((_x) & 0x3fff) -#define TX_DMA_GET_PLEN0(_x) (((_x) >> 16 ) & 0x3fff) -#define TX_DMA_GET_PLEN1(_x) ((_x) & 0x3fff) +#define TX_DMA_BUF_LEN 0x3fff +#define TX_DMA_PLEN0_MASK (TX_DMA_BUF_LEN << 16) +#define TX_DMA_PLEN0(_x) (((_x) & TX_DMA_BUF_LEN) << 16) +#define TX_DMA_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN) +#define TX_DMA_GET_PLEN0(_x) (((_x) >> 16 ) & TX_DMA_BUF_LEN) +#define TX_DMA_GET_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN) #define TX_DMA_LS1 BIT(14) #define TX_DMA_LS0 BIT(30) #define TX_DMA_DONE BIT(31) @@ -401,7 +402,6 @@ struct fe_soc_data u32 rx_int; u32 tx_int; u32 checksum_bit; - u32 tx_udf_bit; }; #define FE_FLAG_PADDING_64B BIT(0) @@ -410,6 +410,7 @@ struct fe_soc_data #define FE_FLAG_RX_2B_OFFSET BIT(3) #define FE_FLAG_RX_SG_DMA BIT(4) #define FE_FLAG_RX_VLAN_CTAG BIT(5) +#define FE_FLAG_NAPI_WEIGHT BIT(6) #define FE_STAT_REG_DECLARE \ _FE(tx_bytes) \ @@ -434,6 +435,22 @@ FE_STAT_REG_DECLARE #undef _FE }; +enum fe_tx_flags { + FE_TX_FLAGS_SINGLE0 = 0x01, + FE_TX_FLAGS_PAGE0 = 0x02, + FE_TX_FLAGS_PAGE1 = 0x04, +}; + +struct fe_tx_buf +{ + struct sk_buff *skb; + u32 flags; + DEFINE_DMA_UNMAP_ADDR(dma_addr0); + DEFINE_DMA_UNMAP_LEN(dma_len0); + DEFINE_DMA_UNMAP_ADDR(dma_addr1); + DEFINE_DMA_UNMAP_LEN(dma_len1); +}; + struct fe_priv { spinlock_t page_lock; @@ -454,7 +471,7 @@ struct fe_priv struct napi_struct rx_napi; struct fe_tx_dma *tx_dma; - struct sk_buff **tx_skb; + struct fe_tx_buf *tx_buf; dma_addr_t tx_phys; unsigned int tx_free_idx; -- cgit v1.2.3