From c0a15a57bda510fac081d536013d16446baf6813 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Mon, 16 Mar 2015 07:41:24 +0000 Subject: sunxi: drop 3.14 support Signed-off-by: John Crispin SVN-Revision: 44824 --- .../114-dt-sun7i-rename-clocknodes.patch | 127 --------------------- 1 file changed, 127 deletions(-) delete mode 100644 target/linux/sunxi/patches-3.14/114-dt-sun7i-rename-clocknodes.patch (limited to 'target/linux/sunxi/patches-3.14/114-dt-sun7i-rename-clocknodes.patch') diff --git a/target/linux/sunxi/patches-3.14/114-dt-sun7i-rename-clocknodes.patch b/target/linux/sunxi/patches-3.14/114-dt-sun7i-rename-clocknodes.patch deleted file mode 100644 index a8a6993e99..0000000000 --- a/target/linux/sunxi/patches-3.14/114-dt-sun7i-rename-clocknodes.patch +++ /dev/null @@ -1,127 +0,0 @@ -From c57b781689bba48dad635caf005962cc9c8e5e3d Mon Sep 17 00:00:00 2001 -From: Chen-Yu Tsai -Date: Mon, 3 Feb 2014 09:51:44 +0800 -Subject: [PATCH] ARM: dts: sun7i: rename clock node names to clk@N - -Device tree naming conventions state that node names should match -node function. Change fully functioning clock nodes to match and -add clock-output-names to all sunxi clock nodes. - -Signed-off-by: Chen-Yu Tsai -Signed-off-by: Maxime Ripard ---- - arch/arm/boot/dts/sun7i-a20.dtsi | 25 +++++++++++++++++-------- - 1 file changed, 17 insertions(+), 8 deletions(-) - ---- a/arch/arm/boot/dts/sun7i-a20.dtsi -+++ b/arch/arm/boot/dts/sun7i-a20.dtsi -@@ -62,11 +62,12 @@ - #size-cells = <1>; - ranges; - -- osc24M: osc24M@01c20050 { -+ osc24M: clk@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-osc-clk"; - reg = <0x01c20050 0x4>; - clock-frequency = <24000000>; -+ clock-output-names = "osc24M"; - }; - - osc32k: clk@0 { -@@ -76,21 +77,23 @@ - clock-output-names = "osc32k"; - }; - -- pll1: pll1@01c20000 { -+ pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; -+ clock-output-names = "pll1"; - }; - -- pll4: pll4@01c20018 { -+ pll4: clk@01c20018 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-pll1-clk"; - reg = <0x01c20018 0x4>; - clocks = <&osc24M>; -+ clock-output-names = "pll4"; - }; - -- pll5: pll5@01c20020 { -+ pll5: clk@01c20020 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-pll5-clk"; - reg = <0x01c20020 0x4>; -@@ -98,7 +101,7 @@ - clock-output-names = "pll5_ddr", "pll5_other"; - }; - -- pll6: pll6@01c20028 { -+ pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-pll6-clk"; - reg = <0x01c20028 0x4>; -@@ -111,6 +114,7 @@ - compatible = "allwinner,sun4i-cpu-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>; -+ clock-output-names = "cpu"; - }; - - axi: axi@01c20054 { -@@ -118,6 +122,7 @@ - compatible = "allwinner,sun4i-axi-clk"; - reg = <0x01c20054 0x4>; - clocks = <&cpu>; -+ clock-output-names = "axi"; - }; - - ahb: ahb@01c20054 { -@@ -125,9 +130,10 @@ - compatible = "allwinner,sun4i-ahb-clk"; - reg = <0x01c20054 0x4>; - clocks = <&axi>; -+ clock-output-names = "ahb"; - }; - -- ahb_gates: ahb_gates@01c20060 { -+ ahb_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun7i-a20-ahb-gates-clk"; - reg = <0x01c20060 0x8>; -@@ -152,9 +158,10 @@ - compatible = "allwinner,sun4i-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb>; -+ clock-output-names = "apb0"; - }; - -- apb0_gates: apb0_gates@01c20068 { -+ apb0_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun7i-a20-apb0-gates-clk"; - reg = <0x01c20068 0x4>; -@@ -170,6 +177,7 @@ - compatible = "allwinner,sun4i-apb1-mux-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&osc32k>; -+ clock-output-names = "apb1_mux"; - }; - - apb1: apb1@01c20058 { -@@ -177,9 +185,10 @@ - compatible = "allwinner,sun4i-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&apb1_mux>; -+ clock-output-names = "apb1"; - }; - -- apb1_gates: apb1_gates@01c2006c { -+ apb1_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun7i-a20-apb1-gates-clk"; - reg = <0x01c2006c 0x4>; -- cgit v1.2.3