From 608ad4b6932f72995144bc72a31b1e0843a5bb28 Mon Sep 17 00:00:00 2001 From: Luka Perkov Date: Tue, 11 Feb 2014 02:07:41 +0000 Subject: mvebu: backport mainline patches from kernel 3.12 This is a backport of the patches accepted to the Linux mainline related to mvebu SoC (Armada XP and Armada 370) between Linux v3.11, and Linux v3.12. This work mainly covers: * Ground work for sharing the pxa nand driver(drivers/mtd/nand/pxa3xx_nand.c) between the PXA family,and the Armada family. * Further updates to the mvebu MBus. * Work and ground work for enabling MSI on the Armada family. * some phy / mdio bus initialization related work. * Device tree binding documentation update. Signed-off-by: Seif Mazareeb CC: Luka Perkov git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39565 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- ...elocate-Armada-370-XP-PCIe-device-tree-no.patch | 1370 ++++++++++++++++++++ 1 file changed, 1370 insertions(+) create mode 100644 target/linux/mvebu/patches-3.10/0059-ARM-mvebu-Relocate-Armada-370-XP-PCIe-device-tree-no.patch (limited to 'target/linux/mvebu/patches-3.10/0059-ARM-mvebu-Relocate-Armada-370-XP-PCIe-device-tree-no.patch') diff --git a/target/linux/mvebu/patches-3.10/0059-ARM-mvebu-Relocate-Armada-370-XP-PCIe-device-tree-no.patch b/target/linux/mvebu/patches-3.10/0059-ARM-mvebu-Relocate-Armada-370-XP-PCIe-device-tree-no.patch new file mode 100644 index 0000000000..a7ce3ed7ff --- /dev/null +++ b/target/linux/mvebu/patches-3.10/0059-ARM-mvebu-Relocate-Armada-370-XP-PCIe-device-tree-no.patch @@ -0,0 +1,1370 @@ +From db5029d82c4f0685438ea38eb3fbaadac46a22ba Mon Sep 17 00:00:00 2001 +From: Ezequiel Garcia +Date: Wed, 12 Jun 2013 18:02:19 -0300 +Subject: [PATCH 059/203] ARM: mvebu: Relocate Armada 370/XP PCIe device tree + nodes + +Now that mbus has been added to the device tree, it's possible to +move the PCIe nodes out of internal registers, placing it directly +below the mbus. This is a more accurate representation of the +hardware. + +Moving the PCIe nodes, we now need to introduce an extra cell to +encode the window target ID and attribute. Since this depends on +the PCIe port, we split the ranges translation entries, to correspond +to each MBus window. + +Signed-off-by: Thomas Petazzoni +Signed-off-by: Ezequiel Garcia +Tested-by: Andrew Lunn +Tested-by: Sebastian Hesselbarth +--- + arch/arm/boot/dts/armada-370-mirabox.dts | 32 +- + arch/arm/boot/dts/armada-370-xp.dtsi | 2 + + arch/arm/boot/dts/armada-370.dtsi | 101 +++--- + arch/arm/boot/dts/armada-xp-db.dts | 67 ++-- + arch/arm/boot/dts/armada-xp-gp.dts | 42 +-- + arch/arm/boot/dts/armada-xp-mv78230.dtsi | 222 ++++++------ + arch/arm/boot/dts/armada-xp-mv78260.dtsi | 261 ++++++++------- + arch/arm/boot/dts/armada-xp-mv78460.dtsi | 409 ++++++++++++----------- + arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 18 +- + 9 files changed, 612 insertions(+), 542 deletions(-) + +--- a/arch/arm/boot/dts/armada-370-mirabox.dts ++++ b/arch/arm/boot/dts/armada-370-mirabox.dts +@@ -28,6 +28,22 @@ + ranges = ; + ++ pcie-controller { ++ status = "okay"; ++ ++ /* Internal mini-PCIe connector */ ++ pcie@1,0 { ++ /* Port 0, Lane 0 */ ++ status = "okay"; ++ }; ++ ++ /* Connected on the PCB to a USB 3.0 XHCI controller */ ++ pcie@2,0 { ++ /* Port 1, Lane 0 */ ++ status = "okay"; ++ }; ++ }; ++ + internal-regs { + serial@12000 { + clock-frequency = <200000000>; +@@ -123,22 +139,6 @@ + reg = <0x25>; + }; + }; +- +- pcie-controller { +- status = "okay"; +- +- /* Internal mini-PCIe connector */ +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +- +- /* Connected on the PCB to a USB 3.0 XHCI controller */ +- pcie@2,0 { +- /* Port 1, Lane 0 */ +- status = "okay"; +- }; +- }; + }; + }; + }; +--- a/arch/arm/boot/dts/armada-370-xp.dtsi ++++ b/arch/arm/boot/dts/armada-370-xp.dtsi +@@ -35,6 +35,8 @@ + #size-cells = <1>; + controller = <&mbusc>; + interrupt-parent = <&mpic>; ++ pcie-mem-aperture = <0xe0000000 0x8000000>; ++ pcie-io-aperture = <0xe8000000 0x100000>; + + devbus-bootcs { + compatible = "marvell,mvebu-devbus"; +--- a/arch/arm/boot/dts/armada-370.dtsi ++++ b/arch/arm/boot/dts/armada-370.dtsi +@@ -36,6 +36,59 @@ + reg = ; + }; + ++ pcie-controller { ++ compatible = "marvell,armada-370-pcie"; ++ status = "disabled"; ++ device_type = "pci"; ++ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ bus-range = <0x00 0xff>; ++ ++ ranges = ++ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 ++ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 ++ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ ++ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ ++ 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ ++ 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>; ++ ++ pcie@1,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; ++ reg = <0x0800 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 ++ 0x81000000 0 0 0x81000000 0x1 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 58>; ++ marvell,pcie-port = <0>; ++ marvell,pcie-lane = <0>; ++ clocks = <&gateclk 5>; ++ status = "disabled"; ++ }; ++ ++ pcie@2,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; ++ reg = <0x1000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 ++ 0x81000000 0 0 0x81000000 0x2 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 62>; ++ marvell,pcie-port = <1>; ++ marvell,pcie-lane = <0>; ++ clocks = <&gateclk 9>; ++ status = "disabled"; ++ }; ++ }; ++ + internal-regs { + system-controller@18200 { + compatible = "marvell,armada-370-xp-system-controller"; +@@ -174,54 +227,6 @@ + 0x18304 0x4>; + status = "okay"; + }; +- +- pcie-controller { +- compatible = "marvell,armada-370-pcie"; +- status = "disabled"; +- device_type = "pci"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- bus-range = <0x00 0xff>; +- +- ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ +- 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ +- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ +- 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ +- +- pcie@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 58>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 5>; +- status = "disabled"; +- }; +- +- pcie@2,0 { +- device_type = "pci"; +- assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; +- reg = <0x1000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 62>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 9>; +- status = "disabled"; +- }; +- }; + }; + }; + }; +--- a/arch/arm/boot/dts/armada-xp-db.dts ++++ b/arch/arm/boot/dts/armada-xp-db.dts +@@ -62,6 +62,39 @@ + }; + }; + ++ pcie-controller { ++ status = "okay"; ++ ++ /* ++ * All 6 slots are physically present as ++ * standard PCIe slots on the board. ++ */ ++ pcie@1,0 { ++ /* Port 0, Lane 0 */ ++ status = "okay"; ++ }; ++ pcie@2,0 { ++ /* Port 0, Lane 1 */ ++ status = "okay"; ++ }; ++ pcie@3,0 { ++ /* Port 0, Lane 2 */ ++ status = "okay"; ++ }; ++ pcie@4,0 { ++ /* Port 0, Lane 3 */ ++ status = "okay"; ++ }; ++ pcie@9,0 { ++ /* Port 2, Lane 0 */ ++ status = "okay"; ++ }; ++ pcie@10,0 { ++ /* Port 3, Lane 0 */ ++ status = "okay"; ++ }; ++ }; ++ + internal-regs { + serial@12000 { + clock-frequency = <250000000>; +@@ -155,40 +188,6 @@ + spi-max-frequency = <20000000>; + }; + }; +- +- pcie-controller { +- status = "okay"; +- +- /* +- * All 6 slots are physically present as +- * standard PCIe slots on the board. +- */ +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +- pcie@2,0 { +- /* Port 0, Lane 1 */ +- status = "okay"; +- }; +- pcie@3,0 { +- /* Port 0, Lane 2 */ +- status = "okay"; +- }; +- pcie@4,0 { +- /* Port 0, Lane 3 */ +- status = "okay"; +- }; +- pcie@9,0 { +- /* Port 2, Lane 0 */ +- status = "okay"; +- }; +- pcie@10,0 { +- /* Port 3, Lane 0 */ +- status = "okay"; +- }; +- }; +- + }; + }; + }; +--- a/arch/arm/boot/dts/armada-xp-gp.dts ++++ b/arch/arm/boot/dts/armada-xp-gp.dts +@@ -71,6 +71,27 @@ + }; + }; + ++ pcie-controller { ++ status = "okay"; ++ ++ /* ++ * The 3 slots are physically present as ++ * standard PCIe slots on the board. ++ */ ++ pcie@1,0 { ++ /* Port 0, Lane 0 */ ++ status = "okay"; ++ }; ++ pcie@9,0 { ++ /* Port 2, Lane 0 */ ++ status = "okay"; ++ }; ++ pcie@10,0 { ++ /* Port 3, Lane 0 */ ++ status = "okay"; ++ }; ++ }; ++ + internal-regs { + serial@12000 { + clock-frequency = <250000000>; +@@ -154,27 +175,6 @@ + spi-max-frequency = <108000000>; + }; + }; +- +- pcie-controller { +- status = "okay"; +- +- /* +- * The 3 slots are physically present as +- * standard PCIe slots on the board. +- */ +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +- pcie@9,0 { +- /* Port 2, Lane 0 */ +- status = "okay"; +- }; +- pcie@10,0 { +- /* Port 3, Lane 0 */ +- status = "okay"; +- }; +- }; + }; + }; + }; +--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi +@@ -44,6 +44,124 @@ + }; + + soc { ++ /* ++ * MV78230 has 2 PCIe units Gen2.0: One unit can be ++ * configured as x4 or quad x1 lanes. One unit is ++ * x4/x1. ++ */ ++ pcie-controller { ++ compatible = "marvell,armada-xp-pcie"; ++ status = "disabled"; ++ device_type = "pci"; ++ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ bus-range = <0x00 0xff>; ++ ++ ranges = ++ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ ++ 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ ++ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ ++ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ ++ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ ++ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ ++ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ ++ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ ++ 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ ++ 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ ++ 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ ++ 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ ++ 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ ++ 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ ++ 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>; ++ ++ pcie@1,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; ++ reg = <0x0800 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 ++ 0x81000000 0 0 0x81000000 0x1 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 58>; ++ marvell,pcie-port = <0>; ++ marvell,pcie-lane = <0>; ++ clocks = <&gateclk 5>; ++ status = "disabled"; ++ }; ++ ++ pcie@2,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; ++ reg = <0x1000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 ++ 0x81000000 0 0 0x81000000 0x2 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 59>; ++ marvell,pcie-port = <0>; ++ marvell,pcie-lane = <1>; ++ clocks = <&gateclk 6>; ++ status = "disabled"; ++ }; ++ ++ pcie@3,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; ++ reg = <0x1800 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 ++ 0x81000000 0 0 0x81000000 0x3 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 60>; ++ marvell,pcie-port = <0>; ++ marvell,pcie-lane = <2>; ++ clocks = <&gateclk 7>; ++ status = "disabled"; ++ }; ++ ++ pcie@4,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; ++ reg = <0x2000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 ++ 0x81000000 0 0 0x81000000 0x4 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 61>; ++ marvell,pcie-port = <0>; ++ marvell,pcie-lane = <3>; ++ clocks = <&gateclk 8>; ++ status = "disabled"; ++ }; ++ ++ pcie@9,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; ++ reg = <0x4800 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 ++ 0x81000000 0 0 0x81000000 0x9 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 99>; ++ marvell,pcie-port = <2>; ++ marvell,pcie-lane = <0>; ++ clocks = <&gateclk 26>; ++ status = "disabled"; ++ }; ++ }; ++ + internal-regs { + pinctrl { + compatible = "marvell,mv78230-pinctrl"; +@@ -79,108 +197,6 @@ + }; + + /* +- * MV78230 has 2 PCIe units Gen2.0: One unit can be +- * configured as x4 or quad x1 lanes. One unit is +- * x1 only. +- */ +- pcie-controller { +- compatible = "marvell,armada-xp-pcie"; +- status = "disabled"; +- device_type = "pci"; +- +-#address-cells = <3>; +-#size-cells = <2>; +- +- bus-range = <0x00 0xff>; +- +- ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ +- 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */ +- 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */ +- 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */ +- 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ +- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ +- 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ +- +- pcie@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 58>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 5>; +- status = "disabled"; +- }; +- +- pcie@2,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; +- reg = <0x1000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 59>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <1>; +- clocks = <&gateclk 6>; +- status = "disabled"; +- }; +- +- pcie@3,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; +- reg = <0x1800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 60>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <2>; +- clocks = <&gateclk 7>; +- status = "disabled"; +- }; +- +- pcie@4,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; +- reg = <0x2000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 61>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <3>; +- clocks = <&gateclk 8>; +- status = "disabled"; +- }; +- +- pcie@5,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; +- reg = <0x2800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 62>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 9>; +- status = "disabled"; +- }; +- }; + }; + }; + }; +--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi +@@ -45,6 +45,145 @@ + }; + + soc { ++ /* ++ * MV78260 has 3 PCIe units Gen2.0: Two units can be ++ * configured as x4 or quad x1 lanes. One unit is ++ * x4/x1. ++ */ ++ pcie-controller { ++ compatible = "marvell,armada-xp-pcie"; ++ status = "disabled"; ++ device_type = "pci"; ++ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ bus-range = <0x00 0xff>; ++ ++ ranges = ++ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ ++ 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ ++ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ ++ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ ++ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ ++ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ ++ 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ ++ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ ++ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ ++ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ ++ 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ ++ 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ ++ 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ ++ 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ ++ 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ ++ 0x82000000 0x9 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ ++ 0x81000000 0x9 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ ++ 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ ++ 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; ++ ++ pcie@1,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; ++ reg = <0x0800 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 ++ 0x81000000 0 0 0x81000000 0x1 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 58>; ++ marvell,pcie-port = <0>; ++ marvell,pcie-lane = <0>; ++ clocks = <&gateclk 5>; ++ status = "disabled"; ++ }; ++ ++ pcie@2,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; ++ reg = <0x1000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 ++ 0x81000000 0 0 0x81000000 0x2 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 59>; ++ marvell,pcie-port = <0>; ++ marvell,pcie-lane = <1>; ++ clocks = <&gateclk 6>; ++ status = "disabled"; ++ }; ++ ++ pcie@3,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; ++ reg = <0x1800 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 ++ 0x81000000 0 0 0x81000000 0x3 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 60>; ++ marvell,pcie-port = <0>; ++ marvell,pcie-lane = <2>; ++ clocks = <&gateclk 7>; ++ status = "disabled"; ++ }; ++ ++ pcie@4,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; ++ reg = <0x2000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 ++ 0x81000000 0 0 0x81000000 0x4 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 61>; ++ marvell,pcie-port = <0>; ++ marvell,pcie-lane = <3>; ++ clocks = <&gateclk 8>; ++ status = "disabled"; ++ }; ++ ++ pcie@9,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; ++ reg = <0x4800 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 ++ 0x81000000 0 0 0x81000000 0x9 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 99>; ++ marvell,pcie-port = <2>; ++ marvell,pcie-lane = <0>; ++ clocks = <&gateclk 26>; ++ status = "disabled"; ++ }; ++ ++ pcie@10,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82000800 0 0x82000 0 0x2000>; ++ reg = <0x5000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 ++ 0x81000000 0 0 0x81000000 0xa 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 103>; ++ marvell,pcie-port = <3>; ++ marvell,pcie-lane = <0>; ++ clocks = <&gateclk 27>; ++ status = "disabled"; ++ }; ++ }; ++ + internal-regs { + pinctrl { + compatible = "marvell,mv78260-pinctrl"; +@@ -98,177 +237,6 @@ + status = "disabled"; + }; + +- /* +- * MV78260 has 3 PCIe units Gen2.0: Two units can be +- * configured as x4 or quad x1 lanes. One unit is +- * x4 only. +- */ +- pcie-controller { +- compatible = "marvell,armada-xp-pcie"; +- status = "disabled"; +- device_type = "pci"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- bus-range = <0x00 0xff>; +- +- ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ +- 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */ +- 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */ +- 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */ +- 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */ +- 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ +- 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */ +- 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */ +- 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */ +- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ +- 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ +- +- pcie@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 58>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 5>; +- status = "disabled"; +- }; +- +- pcie@2,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x44000 0 0x2000>; +- reg = <0x1000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 59>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <1>; +- clocks = <&gateclk 6>; +- status = "disabled"; +- }; +- +- pcie@3,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x48000 0 0x2000>; +- reg = <0x1800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 60>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <2>; +- clocks = <&gateclk 7>; +- status = "disabled"; +- }; +- +- pcie@4,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>; +- reg = <0x2000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 61>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <3>; +- clocks = <&gateclk 8>; +- status = "disabled"; +- }; +- +- pcie@5,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; +- reg = <0x2800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 62>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 9>; +- status = "disabled"; +- }; +- +- pcie@6,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x84000 0 0x2000>; +- reg = <0x3000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 63>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <1>; +- clocks = <&gateclk 10>; +- status = "disabled"; +- }; +- +- pcie@7,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x88000 0 0x2000>; +- reg = <0x3800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 64>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <2>; +- clocks = <&gateclk 11>; +- status = "disabled"; +- }; +- +- pcie@8,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>; +- reg = <0x4000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 65>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <3>; +- clocks = <&gateclk 12>; +- status = "disabled"; +- }; +- +- pcie@9,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x42000 0 0x2000>; +- reg = <0x4800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 99>; +- marvell,pcie-port = <2>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 26>; +- status = "disabled"; +- }; +- }; + }; + }; + }; +--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi ++++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi +@@ -60,6 +60,227 @@ + }; + + soc { ++ /* ++ * MV78460 has 4 PCIe units Gen2.0: Two units can be ++ * configured as x4 or quad x1 lanes. Two units are ++ * x4/x1. ++ */ ++ pcie-controller { ++ compatible = "marvell,armada-xp-pcie"; ++ status = "disabled"; ++ device_type = "pci"; ++ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ bus-range = <0x00 0xff>; ++ ++ ranges = ++ <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */ ++ 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */ ++ 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */ ++ 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */ ++ 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */ ++ 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */ ++ 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */ ++ 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */ ++ 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */ ++ 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */ ++ 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ ++ 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */ ++ 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */ ++ 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */ ++ 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */ ++ 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */ ++ 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */ ++ 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */ ++ ++ 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */ ++ 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */ ++ 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */ ++ 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */ ++ 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */ ++ 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */ ++ 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */ ++ 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */ ++ ++ 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */ ++ 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */ ++ ++ 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */ ++ 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>; ++ ++ pcie@1,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; ++ reg = <0x0800 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 ++ 0x81000000 0 0 0x81000000 0x1 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 58>; ++ marvell,pcie-port = <0>; ++ marvell,pcie-lane = <0>; ++ clocks = <&gateclk 5>; ++ status = "disabled"; ++ }; ++ ++ pcie@2,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; ++ reg = <0x1000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 ++ 0x81000000 0 0 0x81000000 0x2 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 59>; ++ marvell,pcie-port = <0>; ++ marvell,pcie-lane = <1>; ++ clocks = <&gateclk 6>; ++ status = "disabled"; ++ }; ++ ++ pcie@3,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; ++ reg = <0x1800 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 ++ 0x81000000 0 0 0x81000000 0x3 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 60>; ++ marvell,pcie-port = <0>; ++ marvell,pcie-lane = <2>; ++ clocks = <&gateclk 7>; ++ status = "disabled"; ++ }; ++ ++ pcie@4,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; ++ reg = <0x2000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 ++ 0x81000000 0 0 0x81000000 0x4 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 61>; ++ marvell,pcie-port = <0>; ++ marvell,pcie-lane = <3>; ++ clocks = <&gateclk 8>; ++ status = "disabled"; ++ }; ++ ++ pcie@5,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; ++ reg = <0x2800 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0 ++ 0x81000000 0 0 0x81000000 0x5 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 62>; ++ marvell,pcie-port = <1>; ++ marvell,pcie-lane = <0>; ++ clocks = <&gateclk 9>; ++ status = "disabled"; ++ }; ++ ++ pcie@6,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; ++ reg = <0x3000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0 ++ 0x81000000 0 0 0x81000000 0x6 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 63>; ++ marvell,pcie-port = <1>; ++ marvell,pcie-lane = <1>; ++ clocks = <&gateclk 10>; ++ status = "disabled"; ++ }; ++ ++ pcie@7,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; ++ reg = <0x3800 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0 ++ 0x81000000 0 0 0x81000000 0x7 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 64>; ++ marvell,pcie-port = <1>; ++ marvell,pcie-lane = <2>; ++ clocks = <&gateclk 11>; ++ status = "disabled"; ++ }; ++ ++ pcie@8,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; ++ reg = <0x4000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0 ++ 0x81000000 0 0 0x81000000 0x8 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 65>; ++ marvell,pcie-port = <1>; ++ marvell,pcie-lane = <3>; ++ clocks = <&gateclk 12>; ++ status = "disabled"; ++ }; ++ ++ pcie@9,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; ++ reg = <0x4800 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0 ++ 0x81000000 0 0 0x81000000 0x9 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 99>; ++ marvell,pcie-port = <2>; ++ marvell,pcie-lane = <0>; ++ clocks = <&gateclk 26>; ++ status = "disabled"; ++ }; ++ ++ pcie@10,0 { ++ device_type = "pci"; ++ assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; ++ reg = <0x5000 0 0 0 0>; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ #interrupt-cells = <1>; ++ ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0 ++ 0x81000000 0 0 0x81000000 0xa 0 1 0>; ++ interrupt-map-mask = <0 0 0 0>; ++ interrupt-map = <0 0 0 0 &mpic 103>; ++ marvell,pcie-port = <3>; ++ marvell,pcie-lane = <0>; ++ clocks = <&gateclk 27>; ++ status = "disabled"; ++ }; ++ }; ++ + internal-regs { + pinctrl { + compatible = "marvell,mv78460-pinctrl"; +@@ -112,194 +333,6 @@ + clocks = <&gateclk 1>; + status = "disabled"; + }; +- +- /* +- * MV78460 has 4 PCIe units Gen2.0: Two units can be +- * configured as x4 or quad x1 lanes. Two units are +- * x4/x1. +- */ +- pcie-controller { +- compatible = "marvell,armada-xp-pcie"; +- status = "disabled"; +- device_type = "pci"; +- +- #address-cells = <3>; +- #size-cells = <2>; +- +- bus-range = <0x00 0xff>; +- +- ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */ +- 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */ +- 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */ +- 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */ +- 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */ +- 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */ +- 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */ +- 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */ +- 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */ +- 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */ +- 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */ +- 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */ +- +- pcie@1,0 { +- device_type = "pci"; +- assigned-addresses = <0x82000800 0 0x40000 0 0x2000>; +- reg = <0x0800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 58>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 5>; +- status = "disabled"; +- }; +- +- pcie@2,0 { +- device_type = "pci"; +- assigned-addresses = <0x82001000 0 0x44000 0 0x2000>; +- reg = <0x1000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 59>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <1>; +- clocks = <&gateclk 6>; +- status = "disabled"; +- }; +- +- pcie@3,0 { +- device_type = "pci"; +- assigned-addresses = <0x82001800 0 0x48000 0 0x2000>; +- reg = <0x1800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 60>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <2>; +- clocks = <&gateclk 7>; +- status = "disabled"; +- }; +- +- pcie@4,0 { +- device_type = "pci"; +- assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>; +- reg = <0x2000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 61>; +- marvell,pcie-port = <0>; +- marvell,pcie-lane = <3>; +- clocks = <&gateclk 8>; +- status = "disabled"; +- }; +- +- pcie@5,0 { +- device_type = "pci"; +- assigned-addresses = <0x82002800 0 0x80000 0 0x2000>; +- reg = <0x2800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 62>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 9>; +- status = "disabled"; +- }; +- +- pcie@6,0 { +- device_type = "pci"; +- assigned-addresses = <0x82003000 0 0x84000 0 0x2000>; +- reg = <0x3000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 63>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <1>; +- clocks = <&gateclk 10>; +- status = "disabled"; +- }; +- +- pcie@7,0 { +- device_type = "pci"; +- assigned-addresses = <0x82003800 0 0x88000 0 0x2000>; +- reg = <0x3800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 64>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <2>; +- clocks = <&gateclk 11>; +- status = "disabled"; +- }; +- +- pcie@8,0 { +- device_type = "pci"; +- assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>; +- reg = <0x4000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 65>; +- marvell,pcie-port = <1>; +- marvell,pcie-lane = <3>; +- clocks = <&gateclk 12>; +- status = "disabled"; +- }; +- pcie@9,0 { +- device_type = "pci"; +- assigned-addresses = <0x82004800 0 0x42000 0 0x2000>; +- reg = <0x4800 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 99>; +- marvell,pcie-port = <2>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 26>; +- status = "disabled"; +- }; +- +- pcie@10,0 { +- device_type = "pci"; +- assigned-addresses = <0x82005000 0 0x82000 0 0x2000>; +- reg = <0x5000 0 0 0 0>; +- #address-cells = <3>; +- #size-cells = <2>; +- #interrupt-cells = <1>; +- ranges; +- interrupt-map-mask = <0 0 0 0>; +- interrupt-map = <0 0 0 0 &mpic 103>; +- marvell,pcie-port = <3>; +- marvell,pcie-lane = <0>; +- clocks = <&gateclk 27>; +- status = "disabled"; +- }; +- }; + }; + }; + }; +--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts ++++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +@@ -59,6 +59,15 @@ + }; + }; + ++ pcie-controller { ++ status = "okay"; ++ /* Internal mini-PCIe connector */ ++ pcie@1,0 { ++ /* Port 0, Lane 0 */ ++ status = "okay"; ++ }; ++ }; ++ + internal-regs { + serial@12000 { + clock-frequency = <250000000>; +@@ -172,15 +181,6 @@ + usb@51000 { + status = "okay"; + }; +- +- pcie-controller { +- status = "okay"; +- /* Internal mini-PCIe connector */ +- pcie@1,0 { +- /* Port 0, Lane 0 */ +- status = "okay"; +- }; +- }; + }; + }; + }; -- cgit v1.2.3