From 1a2238d1bddc823df06f67312d96ccf9de2893cc Mon Sep 17 00:00:00 2001 From: root Date: Sat, 19 Dec 2015 13:13:57 +0000 Subject: CFE from danitool [without hostTools dir]: https://mega.nz/#!mwZyFK7a!CPT3BKC8dEw29kubtdYxhB91G9vIIismTkgzQ3iUy3k --- shared/broadcom/include/bcm963xx/6368_common.h | 270 +++++++++++++++++++++++++ 1 file changed, 270 insertions(+) create mode 100755 shared/broadcom/include/bcm963xx/6368_common.h (limited to 'shared/broadcom/include/bcm963xx/6368_common.h') diff --git a/shared/broadcom/include/bcm963xx/6368_common.h b/shared/broadcom/include/bcm963xx/6368_common.h new file mode 100755 index 0000000..1df5be5 --- /dev/null +++ b/shared/broadcom/include/bcm963xx/6368_common.h @@ -0,0 +1,270 @@ +/* +<:copyright-broadcom + + Copyright (c) 2007 Broadcom Corporation + All Rights Reserved + No portions of this material may be reproduced in any form without the + written permission of: + Broadcom Corporation + 16215 Alton Parkway + Irvine, California 92619 + All information contained in this document is Broadcom Corporation + company private, proprietary, and trade secret. + +:> +*/ +/***********************************************************************/ +/* */ +/* MODULE: 6368_common.h */ +/* DATE: 02/06/07 */ +/* PURPOSE: Define addresses of major hardware components of */ +/* BCM6368 */ +/* */ +/***********************************************************************/ +#ifndef __BCM6368_MAP_COMMON_H +#define __BCM6368_MAP_COMMON_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define PERF_BASE 0xb0000000 /* chip control registers */ +#define TIMR_BASE 0xb0000040 /* timer registers */ +#define NAND_INTR_BASE 0xb0000070 /* nand interrupt control registers */ +#define GPIO_BASE 0xb0000080 /* gpio registers */ +#define UART_BASE 0xb0000100 /* uart registers */ +#define UART1_BASE 0xb0000120 /* uart registers */ +#define NAND_REG_BASE 0xb0000200 +#define NAND_SEC_BASE 0xb0000300 +#define OTP_BASE 0xb0000400 +#define UBUS_STAT_BASE 0xb0000500 +#define NAND_CACHE_BASE 0xb0000600 +#define SPI_BASE 0xb0000800 /* SPI master controller registers */ +#define MPI_BASE 0xb0001000 /* MPI control registers */ +#define MEMC_BASE 0xb0001200 /* Memory control registers */ +#define DDR_BASE 0xb0001280 /* DDR IO Buf Control registers */ +#define USB_CTL_BASE 0xb0001400 /* USB 2.0 device control registers */ +#define USB_EHCI_BASE 0x10001500 /* USB host registers */ +#define USB_OHCI_BASE 0x10001600 /* USB host registers */ +#define USBH_CFG_BASE 0xb0001700 +#define SAR_BASE 0xb0001800 /* ATM SAR control registers */ +#define SAR_CMF_BASE 0xb0002000 /* ATM SAR CMF control registers */ +#define PCM_BASE 0xb0004000 /* PCM control registers */ +#define IPSEC_BASE 0xb0004100 +#define USB_DMA_BASE 0xb0004800 /* USB 2.0 device DMA regiseters */ +#define SAR_DMA_BASE 0xb0005000 /* ATM SAR DMA control registers */ +#define PCM_DMA_BASE 0xb0005800 /* PCM UIDMA register base */ +#define IPSEC_DMA_BASE 0xb0006000 +#define SWITCH_DMA_BASE 0xb0006800 +#define SWITCH_BASE 0xb0f00000 +#define SWITCH_CMF_BASE 0xb0f0a000 /* Switch CMF register base */ + +#define ADSL_PHY_BASE 0xb0f40000 +#define ADSL_ENUM_BASE 0xb0f56000 +#define ADSL_LMEM_BASE 0xb0f80000 + +/* +##################################################################### +# System PLL Control Register +##################################################################### +*/ + + +/* +##################################################################### +# GPIO Control Registers +##################################################################### +*/ + + +/* +##################################################################### +# Memory Control Registers +##################################################################### +*/ +#define MEMC_CONTROL 0x0 +#define MEMC_CONFIG 0x4 +#define MEMC_REF_PD_CONTROL 0x8 +#define MEMC_BIST_STATUS 0xc +#define MEMC_M_EM_BUF 0x10 +#define MEMC_BANK_CLS_TIM 0x14 +#define MEMC_PRIOR_INV_TIM 0x18 +#define MEMC_DRAM_TIM 0x1c +#define MEMC_INT_STATUS 0x20 +#define MEMC_INT_MASK 0x24 +#define MEMC_INT_INFO 0x28 +#define MEMC_BARRIER 0x50 +#define MEMC_CORE_ID 0x54 + +#define DDR_REV_ID 0x0 +#define DDR_PAD_SSTL_MODE 0x4 +#define DDR_CMD_PAD_CNTL 0x8 +#define DDR_DQ_PAD_CNTL 0xc +#define DDR_DQS_PAD_CNTL 0x10 +#define DDR_CLK_PAD_CNTL 0x14 +#define DDR_PLL_CNTL0 0x18 +#define DDR_PLL_CNTL1 0x1c +#define DDR_MIPSDDR_PLL_CONFIG 0x20 +#define DDR_MIPSDDR_PLL_MDIV 0x24 +#define DDR_DSL_PHY_PHASE_CNTL 0x28 +#define DDR_DSL_CPU_PHASE_CNTL 0x2c +#define DDR_MIPS_PHASE_CNTL 0x30 +#define DDR_DDR1_2_PHASE_CNTL 0x34 +#define DDR_DDR3_4_PHASE_CNTL 0x38 +#define DDR_VCDL_PHASE_CNTL0 0x3c +#define DDR_VCDL_PHASE_CNTL1 0x40 +#define DDR_BSLICE_CNTL 0x44 +#define DDR_DESKEW_DLL_CNTL 0x48 +#define DDR_DESKEW_DLL_RESET 0x4c +#define DDR_DESKEW_DLL_PHASE 0x50 +#define DDR_ANALOG_TEST_CNTL 0x54 +#define DDR_RD_DQS_GATE_CNTL 0x58 +#define DDR_MISC 0x5c +#define DDR_SPARE0 0x60 +#define DDR_SPARE1 0x64 +#define DDR_SPARE2 0x68 +#define DDR_CLBIST 0x6c +#define DDR_LBIST_CRC 0x70 +#define DDR_UBUS_PHASE_CNTR 0x74 +#define DDR_UBUS_PI_DSK0 0x78 +#define DDR_UBUS_PI_DSK1 0x7c + +// Some bit/field definitions for the MEMC_CONFIG register. +#define MEMC_EARLY_HDR_CNT_SHFT 25 +#define MEMC_EARLY_HDR_CNT_MASK (0x7<