From 1a2238d1bddc823df06f67312d96ccf9de2893cc Mon Sep 17 00:00:00 2001 From: root Date: Sat, 19 Dec 2015 13:13:57 +0000 Subject: CFE from danitool [without hostTools dir]: https://mega.nz/#!mwZyFK7a!CPT3BKC8dEw29kubtdYxhB91G9vIIismTkgzQ3iUy3k --- shared/opensource/include/bcm963xx/6328_cpu.h | 150 ++ shared/opensource/include/bcm963xx/6328_intr.h | 120 ++ shared/opensource/include/bcm963xx/6328_map_part.h | 1325 +++++++++++++++++ shared/opensource/include/bcm963xx/6362_cpu.h | 150 ++ shared/opensource/include/bcm963xx/6362_intr.h | 123 ++ shared/opensource/include/bcm963xx/6362_map_part.h | 1478 +++++++++++++++++++ shared/opensource/include/bcm963xx/6368_cpu.h | 150 ++ shared/opensource/include/bcm963xx/6368_intr.h | 123 ++ shared/opensource/include/bcm963xx/6368_map_part.h | 1035 ++++++++++++++ shared/opensource/include/bcm963xx/6816_cpu.h | 150 ++ shared/opensource/include/bcm963xx/6816_intr.h | 116 ++ shared/opensource/include/bcm963xx/6816_map_part.h | 1487 ++++++++++++++++++++ shared/opensource/include/bcm963xx/bcmSpi.h | 55 + shared/opensource/include/bcm963xx/bcmSpiRes.h | 101 ++ shared/opensource/include/bcm963xx/bcmTag.h | 175 +++ shared/opensource/include/bcm963xx/bcm_hwdefs.h | 193 +++ shared/opensource/include/bcm963xx/bcmnetlink.h | 47 + shared/opensource/include/bcm963xx/boardparms.h | 453 ++++++ .../opensource/include/bcm963xx/boardparms_voice.h | 392 ++++++ shared/opensource/include/bcm963xx/fap_mod_size.h | 2 + shared/opensource/include/bcm963xx/flash_api.h | 90 ++ shared/opensource/include/bcm963xx/flash_common.h | 103 ++ shared/opensource/include/bcm963xx/gpio_drv.h | 40 + shared/opensource/include/bcm963xx/wan_det.h | 245 ++++ shared/opensource/include/bcm963xx/wps_led.h | 28 + 25 files changed, 8331 insertions(+) create mode 100755 shared/opensource/include/bcm963xx/6328_cpu.h create mode 100755 shared/opensource/include/bcm963xx/6328_intr.h create mode 100755 shared/opensource/include/bcm963xx/6328_map_part.h create mode 100755 shared/opensource/include/bcm963xx/6362_cpu.h create mode 100755 shared/opensource/include/bcm963xx/6362_intr.h create mode 100755 shared/opensource/include/bcm963xx/6362_map_part.h create mode 100755 shared/opensource/include/bcm963xx/6368_cpu.h create mode 100755 shared/opensource/include/bcm963xx/6368_intr.h create mode 100755 shared/opensource/include/bcm963xx/6368_map_part.h create mode 100755 shared/opensource/include/bcm963xx/6816_cpu.h create mode 100755 shared/opensource/include/bcm963xx/6816_intr.h create mode 100755 shared/opensource/include/bcm963xx/6816_map_part.h create mode 100755 shared/opensource/include/bcm963xx/bcmSpi.h create mode 100755 shared/opensource/include/bcm963xx/bcmSpiRes.h create mode 100755 shared/opensource/include/bcm963xx/bcmTag.h create mode 100755 shared/opensource/include/bcm963xx/bcm_hwdefs.h create mode 100755 shared/opensource/include/bcm963xx/bcmnetlink.h create mode 100755 shared/opensource/include/bcm963xx/boardparms.h create mode 100755 shared/opensource/include/bcm963xx/boardparms_voice.h create mode 100644 shared/opensource/include/bcm963xx/fap_mod_size.h create mode 100755 shared/opensource/include/bcm963xx/flash_api.h create mode 100755 shared/opensource/include/bcm963xx/flash_common.h create mode 100755 shared/opensource/include/bcm963xx/gpio_drv.h create mode 100755 shared/opensource/include/bcm963xx/wan_det.h create mode 100755 shared/opensource/include/bcm963xx/wps_led.h (limited to 'shared/opensource/include/bcm963xx') diff --git a/shared/opensource/include/bcm963xx/6328_cpu.h b/shared/opensource/include/bcm963xx/6328_cpu.h new file mode 100755 index 0000000..8dfef4c --- /dev/null +++ b/shared/opensource/include/bcm963xx/6328_cpu.h @@ -0,0 +1,150 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +#ifndef __BCM6328_CPU_H +#define __BCM6328_CPU_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* +#************************************************************************ +#* Coprocessor 0 Register Names +#************************************************************************ +*/ +#define C0_BCM_CONFIG $22 + +/* +# Select 1 +# Bit 31: unused +# Bits 30:25 MMU Size (Num TLB entries-1) +# Bits 24:22 ICache sets/way (2^n * 64) +# Bits 21:19 ICache Line size (2^(n+1) bytes) 0=No Icache +# Bits 18:16 ICache Associativity (n+1) way +# Bits 15:13 DCache sets/way (2^n * 64) +# Bits 12:10 DCache Line size (2^(n+1) bytes) 0=No Dcache +# Bits 9:7 DCache Associativity (n+1) way +# Bits 6:4 unused +# Bit 3: 1=At least 1 watch register +# Bit 2: 1=MIPS16 code compression implemented +# Bit 1: 1=EJTAG implemented +# Bit 0: 1=FPU implemented +*/ +#define CP0_CFG_ISMSK (0x7 << 22) +#define CP0_CFG_ISSHF 22 +#define CP0_CFG_ILMSK (0x7 << 19) +#define CP0_CFG_ILSHF 19 +#define CP0_CFG_IAMSK (0x7 << 16) +#define CP0_CFG_IASHF 16 +#define CP0_CFG_DSMSK (0x7 << 13) +#define CP0_CFG_DSSHF 13 +#define CP0_CFG_DLMSK (0x7 << 10) +#define CP0_CFG_DLSHF 10 +#define CP0_CFG_DAMSK (0x7 << 7) +#define CP0_CFG_DASHF 7 + +/* +#************************************************************************ +#* Coprocessor 0 Broadcom Config Register Bits +#************************************************************************ +*/ +#define CP0_BCM_CFG_ICSHEN (0x1 << 31) +#define CP0_BCM_CFG_DCSHEN (0x1 << 30) +#define CP0_BCM_CFG_BTHD (0x1 << 21) +#define CP0_BCM_CFG_CLF (0x1 << 20) +#define CP0_BCM_CFG_NBK (0x1 << 17) + +/* +#************************************************************************ +#* Coprocessor 0 CMT Interrupt Register +#************************************************************************ +*/ +#define CP0_CMT_XIR_4 (0x1 << 31) +#define CP0_CMT_XIR_3 (0x1 << 30) +#define CP0_CMT_XIR_2 (0x1 << 29) +#define CP0_CMT_XIR_1 (0x1 << 28) +#define CP0_CMT_XIR_0 (0x1 << 27) +#define CP0_CMT_SIR_1 (0x1 << 16) +#define CP0_CMT_SIR_0 (0x1 << 15) +#define CP0_CMT_NMIR_TP1 (0x1 << 1) +#define CP0_CMT_NMIR_TP0 (0x1 << 0) + +/* +#************************************************************************ +#* Coprocessor 0 CMT Control Register +#************************************************************************ +*/ +#define CP0_CMT_DSU_TP1 (0x1 << 30) +#define CP0_CMT_TPS_SHFT 16 +#define CP0_CMT_TPS_MASK (0xF << CP0_CMT_TPS_SHFT) +#define CP0_CMT_PRIO_TP1 (0x1 << 5) +#define CP0_CMT_PRIO_TP0 (0x1 << 4) +#define CP0_CMT_RSTSE (0x1 << 0) + +/* +#************************************************************************ +#* Coprocessor 0 CMT Local Register +#************************************************************************ +*/ +#define CP0_CMT_TPID (0x1 << 31) + +/* +#************************************************************************ +#* MIPS Registers +#************************************************************************ +*/ + +#define MIPS_BASE_BOOT 0xbfa00000 +#define MIPS_BASE 0xff400000 + +#define MIPS_RAC_CR0 0x00 // RAC Configuration Register +#define MIPS_RAC_CR1 0x08 // RAC Configuration Register 1 +#define RAC_FLH (1 << 8) +#define RAC_DPF (1 << 6) +#define RAC_NCH (1 << 5) +#define RAC_C_INV (1 << 4) +#define RAC_PF_D (1 << 3) +#define RAC_PF_I (1 << 2) +#define RAC_D (1 << 1) +#define RAC_I (1 << 0) + +#define MIPS_RAC_ARR 0x04 // RAC Address Range Register +#define RAC_UPB_SHFT 16 +#define RAC_LWB_SHFT 0 + +#define MIPS_LMB_CR 0x1C // LMB Control Register +#define LMB_EN (1 << 0) + +#define MIPS_SBR 0x20 // System Base Register + +#define MIPS_TP0_ALT_BV 0x30000 +#define MIPS_TP1_ALT_BV 0x38000 +#define ENABLE_ALT_BV (1 << 19) + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/shared/opensource/include/bcm963xx/6328_intr.h b/shared/opensource/include/bcm963xx/6328_intr.h new file mode 100755 index 0000000..e4197d1 --- /dev/null +++ b/shared/opensource/include/bcm963xx/6328_intr.h @@ -0,0 +1,120 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +#ifndef __6328_INTR_H +#define __6328_INTR_H + +#ifdef __cplusplus + extern "C" { +#endif + +#define INTERRUPT_ID_SOFTWARE_0 0 +#define INTERRUPT_ID_SOFTWARE_1 1 + +/*=====================================================================*/ +/* BCM6328 Timer Interrupt Level Assignments */ +/*=====================================================================*/ +#define MIPS_TIMER_INT 7 + +/*=====================================================================*/ +/* Peripheral ISR Table Offset */ +/*=====================================================================*/ +#define INTERNAL_ISR_TABLE_OFFSET 8 +#define INTERNAL_HIGH_ISR_TABLE_OFFSET (INTERNAL_ISR_TABLE_OFFSET + 32) + +/*=====================================================================*/ +/* Logical Peripheral Interrupt IDs */ +/*=====================================================================*/ + +#define INTERRUPT_ID_NAND (INTERNAL_ISR_TABLE_OFFSET + 0) +#define INTERRUPT_ID_PCM (INTERNAL_ISR_TABLE_OFFSET + 1) +#define INTERRUPT_ID_PCM_DMA_0 (INTERNAL_ISR_TABLE_OFFSET + 2) +#define INTERRUPT_ID_PCM_DMA_1 (INTERNAL_ISR_TABLE_OFFSET + 3) +#define INTERRUPT_ID_USBS (INTERNAL_ISR_TABLE_OFFSET + 4) +#define INTERRUPT_ID_USB_CNTL_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 5) +#define INTERRUPT_ID_USB_CNTL_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 6) +#define INTERRUPT_ID_USB_BULK_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 7) +#define INTERRUPT_ID_USB_BULK_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 8) +#define INTERRUPT_ID_USB_ISO_RX_DMA (INTERNAL_ISR_TABLE_OFFSET + 9) +#define INTERRUPT_ID_USB_ISO_TX_DMA (INTERNAL_ISR_TABLE_OFFSET + 10) +#define INTERRUPT_ID_DG (INTERNAL_ISR_TABLE_OFFSET + 11) +#define INTERRUPT_ID_EPHY (INTERNAL_ISR_TABLE_OFFSET + 12) +#define INTERRUPT_ID_EPHY_ENERGY_0_N (INTERNAL_ISR_TABLE_OFFSET + 13) +#define INTERRUPT_ID_EPHY_ENERGY_1_N (INTERNAL_ISR_TABLE_OFFSET + 14) +#define INTERRUPT_ID_EPHY_ENERGY_2_N (INTERNAL_ISR_TABLE_OFFSET + 15) +#define INTERRUPT_ID_EPHY_ENERGY_3_N (INTERNAL_ISR_TABLE_OFFSET + 16) +#define INTERRUPT_ID_EPHY_ENERGY_0 (INTERNAL_ISR_TABLE_OFFSET + 17) +#define INTERRUPT_ID_EPHY_ENERGY_1 (INTERNAL_ISR_TABLE_OFFSET + 18) +#define INTERRUPT_ID_EPHY_ENERGY_2 (INTERNAL_ISR_TABLE_OFFSET + 19) +#define INTERRUPT_ID_EPHY_ENERGY_3 (INTERNAL_ISR_TABLE_OFFSET + 20) +#define INTERRUPT_ID_XDSL (INTERNAL_ISR_TABLE_OFFSET + 21) +#define INTERRUPT_ID_PCIE_EP (INTERNAL_ISR_TABLE_OFFSET + 22) +#define INTERRUPT_ID_PCIE_RC (INTERNAL_ISR_TABLE_OFFSET + 23) +#define INTERRUPT_ID_EXTERNAL_0 (INTERNAL_ISR_TABLE_OFFSET + 24) +#define INTERRUPT_ID_EXTERNAL_1 (INTERNAL_ISR_TABLE_OFFSET + 25) +#define INTERRUPT_ID_EXTERNAL_2 (INTERNAL_ISR_TABLE_OFFSET + 26) +#define INTERRUPT_ID_EXTERNAL_3 (INTERNAL_ISR_TABLE_OFFSET + 27) +#define INTERRUPT_ID_UART (INTERNAL_ISR_TABLE_OFFSET + 28) +#define INTERRUPT_ID_HS_SPIM (INTERNAL_ISR_TABLE_OFFSET + 29) +#define INTERRUPT_ID_WAKE_ON_IRQ (INTERNAL_ISR_TABLE_OFFSET + 30) +#define INTERRUPT_ID_TIMER (INTERNAL_ISR_TABLE_OFFSET + 31) +#define INTERRUPT_ID_ENETSW_RX_DMA_0 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 0) +#define INTERRUPT_ID_ENETSW_RX_DMA_1 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 1) +#define INTERRUPT_ID_ENETSW_RX_DMA_2 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 2) +#define INTERRUPT_ID_ENETSW_RX_DMA_3 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 3) +#define INTERRUPT_ID_UART1 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 7) +#define INTERRUPT_ID_ENETSW_SYS (INTERNAL_HIGH_ISR_TABLE_OFFSET + 8) +#define INTERRUPT_ID_USBH (INTERNAL_HIGH_ISR_TABLE_OFFSET + 9) +#define INTERRUPT_ID_USBH20 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 10) +#define INTERRUPT_ID_ATM_DMA_0 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 11) +#define INTERRUPT_ID_ATM_DMA_1 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 12) +#define INTERRUPT_ID_ATM_DMA_2 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 13) +#define INTERRUPT_ID_ATM_DMA_3 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 14) +#define INTERRUPT_ID_ATM_DMA_4 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 15) +#define INTERRUPT_ID_ATM_DMA_5 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 16) +#define INTERRUPT_ID_ATM_DMA_6 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 17) +#define INTERRUPT_ID_ATM_DMA_7 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 18) +#define INTERRUPT_ID_ATM_DMA_8 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 19) +#define INTERRUPT_ID_ATM_DMA_9 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 20) +#define INTERRUPT_ID_ATM_DMA_10 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 21) +#define INTERRUPT_ID_ATM_DMA_11 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 22) +#define INTERRUPT_ID_ATM_DMA_12 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 23) +#define INTERRUPT_ID_ATM_DMA_13 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 24) +#define INTERRUPT_ID_ATM_DMA_14 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 25) +#define INTERRUPT_ID_ATM_DMA_15 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 26) +#define INTERRUPT_ID_ATM_DMA_16 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 27) +#define INTERRUPT_ID_ATM_DMA_17 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 28) +#define INTERRUPT_ID_ATM_DMA_18 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 29) +#define INTERRUPT_ID_ATM_DMA_19 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 30) +#define INTERRUPT_ID_SAR (INTERNAL_HIGH_ISR_TABLE_OFFSET + 31) + +#define INTERRUPT_ID_LAST INTERRUPT_ID_SAR + +#ifdef __cplusplus + } +#endif + +#endif /* __BCM6328_H */ + + diff --git a/shared/opensource/include/bcm963xx/6328_map_part.h b/shared/opensource/include/bcm963xx/6328_map_part.h new file mode 100755 index 0000000..be199a5 --- /dev/null +++ b/shared/opensource/include/bcm963xx/6328_map_part.h @@ -0,0 +1,1325 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +#ifndef __BCM6328_MAP_H +#define __BCM6328_MAP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" + +#define PERF_BASE 0xb0000000 /* chip control registers */ +#define TIMR_BASE 0xb0000040 /* timer registers */ +#define GPIO_BASE 0xb0000080 /* gpio registers */ +#define UART_BASE 0xb0000100 /* uart registers */ +#define UART1_BASE 0xb0000120 /* uart registers */ +#define NAND_REG_BASE 0xb0000200 /* NAND registers */ +#define NAND_CACHE_BASE 0xb0000400 +#define LED_BASE 0xb0000800 /* LED control registers */ +#define HSSPIM_BASE 0xb0001000 /* High-Speed SPI registers */ +#define MISC_BASE 0xb0001800 /* Miscellaneous Registers */ +#define USB_CTL_BASE 0xb0002400 /* USB 2.0 device control registers */ +#define USB_EHCI_BASE 0x10002500 /* USB host registers */ +#define USB_OHCI_BASE 0x10002600 /* USB host registers */ +#define USBH_CFG_BASE 0xb0002700 +#define DDR_BASE 0xb0003000 /* Memory control registers */ +#define SAR_DMA_BASE 0xb000b800 /* ATM SAR DMA control registers */ +#define PCIE_BASE 0xb0e40000 + +typedef struct DDRPhyControl { + uint32 REVISION; /* 0x00 */ + uint32 CLK_PM_CTRL; /* 0x04 */ + uint32 unused0[2]; /* 0x08-0x10 */ + uint32 PLL_STATUS; /* 0x10 */ + uint32 PLL_CONFIG; /* 0x14 */ + uint32 PLL_PRE_DIVIDER; /* 0x18 */ + uint32 PLL_DIVIDER; /* 0x1c */ + uint32 PLL_CONTROL1; /* 0x20 */ + uint32 PLL_CONTROL2; /* 0x24 */ + uint32 PLL_SS_EN; /* 0x28 */ + uint32 PLL_SS_CFG; /* 0x2c */ + uint32 STATIC_VDL_OVERRIDE; /* 0x30 */ + uint32 DYNAMIC_VDL_OVERRIDE; /* 0x34 */ + uint32 IDLE_PAD_CONTROL; /* 0x38 */ + uint32 ZQ_PVT_COMP_CTL; /* 0x3c */ + uint32 DRIVE_PAD_CTL; /* 0x40 */ + uint32 CLOCK_REG_CONTROL; /* 0x44 */ + uint32 unused1[46]; +} DDRPhyControl; + +typedef struct DDRPhyByteLaneControl { + uint32 REVISION; /* 0x00 */ + uint32 VDL_CALIBRATE; /* 0x04 */ + uint32 VDL_STATUS; /* 0x08 */ + uint32 unused; /* 0x0c */ + uint32 VDL_OVERRIDE_0; /* 0x10 */ + uint32 VDL_OVERRIDE_1; /* 0x14 */ + uint32 VDL_OVERRIDE_2; /* 0x18 */ + uint32 VDL_OVERRIDE_3; /* 0x1c */ + uint32 VDL_OVERRIDE_4; /* 0x20 */ + uint32 VDL_OVERRIDE_5; /* 0x24 */ + uint32 VDL_OVERRIDE_6; /* 0x28 */ + uint32 VDL_OVERRIDE_7; /* 0x2c */ + uint32 READ_CONTROL; /* 0x30 */ + uint32 READ_FIFO_STATUS; /* 0x34 */ + uint32 READ_FIFO_CLEAR; /* 0x38 */ + uint32 IDLE_PAD_CONTROL; /* 0x3c */ + uint32 DRIVE_PAD_CTL; /* 0x40 */ + uint32 CLOCK_PAD_DISABLE; /* 0x44 */ + uint32 WR_PREAMBLE_MODE; /* 0x48 */ + uint32 CLOCK_REG_CONTROL; /* 0x4C */ + uint32 unused0[44]; +} DDRPhyByteLaneControl; + +typedef struct DDRControl { + uint32 CNFG; /* 0x000 */ + uint32 CSST; /* 0x004 */ + uint32 CSEND; /* 0x008 */ + uint32 unused; /* 0x00c */ + uint32 ROW00_0; /* 0x010 */ + uint32 ROW00_1; /* 0x014 */ + uint32 ROW01_0; /* 0x018 */ + uint32 ROW01_1; /* 0x01c */ + uint32 unused0[4]; + uint32 ROW20_0; /* 0x030 */ + uint32 ROW20_1; /* 0x034 */ + uint32 ROW21_0; /* 0x038 */ + uint32 ROW21_1; /* 0x03c */ + uint32 unused1[4]; + uint32 COL00_0; /* 0x050 */ + uint32 COL00_1; /* 0x054 */ + uint32 COL01_0; /* 0x058 */ + uint32 COL01_1; /* 0x05c */ + uint32 unused2[4]; + uint32 COL20_0; /* 0x070 */ + uint32 COL20_1; /* 0x074 */ + uint32 COL21_0; /* 0x078 */ + uint32 COL21_1; /* 0x07c */ + uint32 unused3[4]; + uint32 BNK10; /* 0x090 */ + uint32 BNK32; /* 0x094 */ + uint32 unused4[26]; + uint32 DCMD; /* 0x100 */ +#define DCMD_CS1 (1 << 5) +#define DCMD_CS0 (1 << 4) +#define DCMD_SET_SREF 4 + uint32 DMODE_0; /* 0x104 */ + uint32 DMODE_1; /* 0x108 */ +#define DMODE_1_DRAMSLEEP (1 << 11) + uint32 CLKS; /* 0x10c */ + uint32 ODT; /* 0x110 */ + uint32 TIM1_0; /* 0x114 */ + uint32 TIM1_1; /* 0x118 */ + uint32 TIM2; /* 0x11c */ + uint32 CTL_CRC; /* 0x120 */ + uint32 DOUT_CRC; /* 0x124 */ + uint32 DIN_CRC; /* 0x128 */ + uint32 unused5[53]; + + DDRPhyControl PhyControl; /* 0x200 */ + DDRPhyByteLaneControl PhyByteLane0Control; /* 0x300 */ + DDRPhyByteLaneControl PhyByteLane1Control; /* 0x400 */ + DDRPhyByteLaneControl PhyByteLane2Control; /* 0x500 */ + DDRPhyByteLaneControl PhyByteLane3Control; /* 0x600 */ + uint32 unused6[64]; + + uint32 GCFG; /* 0x800 */ + uint32 LBIST_CFG; /* 0x804 */ + uint32 LBIST_SEED; /* 0x808 */ + uint32 ARB; /* 0x80c */ + uint32 PI_GCF; /* 0x810 */ + uint32 PI_UBUS_CTL; /* 0x814 */ + uint32 PI_MIPS_CTL; /* 0x818 */ + uint32 PI_DSL_MIPS_CTL; /* 0x81c */ + uint32 PI_DSL_PHY_CTL; /* 0x820 */ + uint32 PI_UBUS_ST; /* 0x824 */ + uint32 PI_MIPS_ST; /* 0x828 */ + uint32 PI_DSL_MIPS_ST; /* 0x82c */ + uint32 PI_DSL_PHY_ST; /* 0x830 */ + uint32 PI_UBUS_SMPL; /* 0x834 */ + uint32 TESTMODE; /* 0x838 */ + uint32 TEST_CFG1; /* 0x83c */ + uint32 TEST_PAT; /* 0x840 */ + uint32 TEST_COUNT; /* 0x844 */ + uint32 TEST_CURR_COUNT; /* 0x848 */ + uint32 TEST_ADDR_UPDT; /* 0x84c */ + uint32 TEST_ADDR; /* 0x850 */ + uint32 TEST_DATA0; /* 0x854 */ + uint32 TEST_DATA1; /* 0x858 */ + uint32 TEST_DATA2; /* 0x85c */ + uint32 TEST_DATA3; /* 0x860 */ +} DDRControl; + +#define DDR ((volatile DDRControl * const) DDR_BASE) + +/* +** Peripheral Controller +*/ + +#define IRQ_BITS 64 +typedef struct { + uint64 IrqMask; + uint64 IrqStatus; +} IrqControl_t; + +typedef struct PerfControl { + uint32 RevID; /* (00) word 0 */ + uint32 blkEnables; /* (04) word 1 */ +#define ROBOSW_CLK_EN (1 << 11) +#define PCIE_CLK_EN (1 << 10) +#define HS_SPI_CLK_EN (1 << 9) +#define USBH_CLK_EN (1 << 8) +#define USBD_CLK_EN (1 << 7) +#define PCM_CLK_EN (1 << 6) +#define SAR_CLK_EN (1 << 5) +#define MIPS_CLK_EN (1 << 4) +#define ADSL_CLK_EN (1 << 3) +#define ADSL_AFE_EN (1 << 2) +#define ADSL_QPROC_EN (1 << 1) +#define PHYMIPS_CLK_EN (1 << 0) + + uint32 unused0; /* (08) word 2 */ + uint32 deviceTimeoutEn; /* (0c) word 3 */ + uint32 softResetB; /* (10) word 4 */ +#define SOFT_RST_PCIE_HARD (1 << 10) +#define SOFT_RST_PCIE_EXT (1 << 9) +#define SOFT_RST_PCIE (1 << 8) +#define SOFT_RST_PCIE_CORE (1 << 7) +#define SOFT_RST_PCM (1 << 6) +#define SOFT_RST_USBH (1 << 5) +#define SOFT_RST_USBD (1 << 4) +#define SOFT_RST_SWITCH (1 << 3) +#define SOFT_RST_SAR (1 << 2) +#define SOFT_RST_EPHY (1 << 1) +#define SOFT_RST_SPI (1 << 0) + + uint32 diagControl; /* (14) word 5 */ + uint32 ExtIrqCfg; /* (18) word 6*/ + uint32 unused1; /* (1c) word 7 */ +#define EI_SENSE_SHFT 0 +#define EI_STATUS_SHFT 4 +#define EI_CLEAR_SHFT 8 +#define EI_MASK_SHFT 12 +#define EI_INSENS_SHFT 16 +#define EI_LEVEL_SHFT 20 + + IrqControl_t IrqControl[2]; +} PerfControl; + +#define PERF ((volatile PerfControl * const) PERF_BASE) + +/* +** Timer +*/ +typedef struct Timer { + uint16 unused0; + byte TimerMask; +#define TIMER0EN 0x01 +#define TIMER1EN 0x02 +#define TIMER2EN 0x04 + byte TimerInts; +#define TIMER0 0x01 +#define TIMER1 0x02 +#define TIMER2 0x04 +#define WATCHDOG 0x08 + uint32 TimerCtl0; + uint32 TimerCtl1; + uint32 TimerCtl2; +#define TIMERENABLE 0x80000000 +#define RSTCNTCLR 0x40000000 + uint32 TimerCnt0; + uint32 TimerCnt1; + uint32 TimerCnt2; + uint32 WatchDogDefCount; + + /* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * Read from this register returns current watch dog count + */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; + + uint32 SoftRst; +#define SOFT_RESET 0x00000001 // 0 +} Timer; + +#define TIMER ((volatile Timer * const) TIMR_BASE) + +/* +** UART +*/ +typedef struct UartChannel { + byte unused0; + byte control; +#define BRGEN 0x80 /* Control register bit defs */ +#define TXEN 0x40 +#define RXEN 0x20 +#define LOOPBK 0x10 +#define TXPARITYEN 0x08 +#define TXPARITYEVEN 0x04 +#define RXPARITYEN 0x02 +#define RXPARITYEVEN 0x01 + + byte config; +#define XMITBREAK 0x40 +#define BITS5SYM 0x00 +#define BITS6SYM 0x10 +#define BITS7SYM 0x20 +#define BITS8SYM 0x30 +#define ONESTOP 0x07 +#define TWOSTOP 0x0f + /* 4-LSBS represent STOP bits/char + * in 1/8 bit-time intervals. Zero + * represents 1/8 stop bit interval. + * Fifteen represents 2 stop bits. + */ + byte fifoctl; +#define RSTTXFIFOS 0x80 +#define RSTRXFIFOS 0x40 + /* 5-bit TimeoutCnt is in low bits of this register. + * This count represents the number of characters + * idle times before setting receive Irq when below threshold + */ + uint32 baudword; + /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate + */ + + byte txf_levl; /* Read-only fifo depth */ + byte rxf_levl; /* Read-only fifo depth */ + byte fifocfg; /* Upper 4-bits are TxThresh, Lower are + * RxThreshold. Irq can be asserted + * when rx fifo> thresh, txfifo thresh, txfifo thresh, txfifo thresh, txfifo +#include +#include +#include +#include +#include + +struct bcmspi +{ + spinlock_t lock; + char * devName; + int irq; + unsigned bus_num; + unsigned num_chipselect; + u8 stopping; + struct list_head queue; + struct platform_device *pdev; + struct spi_transfer *curTrans; +}; +#endif + +#define BCM_SPI_READ 0 +#define BCM_SPI_WRITE 1 +#define BCM_SPI_FULL 2 + +#endif /* __BCM_SPI_H__ */ + diff --git a/shared/opensource/include/bcm963xx/bcmSpiRes.h b/shared/opensource/include/bcm963xx/bcmSpiRes.h new file mode 100755 index 0000000..cb39756 --- /dev/null +++ b/shared/opensource/include/bcm963xx/bcmSpiRes.h @@ -0,0 +1,101 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +#ifndef __BCMSPIRES_H__ +#define __BCMSPIRES_H__ + +#ifndef _CFE_ +#include +#endif + +#define SPI_STATUS_OK (0) +#define SPI_STATUS_INVALID_LEN (-1) +#define SPI_STATUS_ERR (-2) + +/* legacy and HS controllers can coexist - use bus num to differentiate */ +#define LEG_SPI_BUS_NUM 0 +#define HS_SPI_BUS_NUM 1 + +#define LEG_SPI_CLOCK_DEF 2 + +#if defined(_BCM96816_) || defined(CONFIG_BCM96816) || defined(_BCM96362_) || defined(CONFIG_BCM96362) +#define HS_SPI_PLL_FREQ 400000000 +#else +#define HS_SPI_PLL_FREQ 133333333 +#endif +#define HS_SPI_CLOCK_DEF 40000000 +#define HS_SPI_BUFFER_LEN 512 + +/* used to specify ctrlState for the interface BcmSpiReserveSlave2 + SPI_CONTROLLER_STATE_SET is used to differentiate a value of 0 which results in + the controller using default values and the case where CPHA_EXT, GATE_CLK_SSOFF, + CLK_POLARITY, and ASYNC_CLOCK all need to be 0 + + SPI MODE sets the values for CPOL and CPHA + SPI_CONTROLLER_STATE_CPHA_EXT will extend these modes +CPOL = 0 -> base value of clock is 0 +CPHA = 0, CPHA_EXT = 0 -> latch data on rising edge, launch data on falling edge +CPHA = 1, CPHA_EXT = 0 -> latch data on falling edge, launch data on rising edge +CPHA = 0, CPHA_EXT = 1 -> latch data on rising edge, launch data on rising edge +CPHA = 1, CPHA_EXT = 1 -> latch data on falling edge, launch data on falling edge + +CPOL = 1 -> base value of clock is 1 +CPHA = 0, CPHA_EXT = 0 -> latch data on falling edge, launch data on rising edge +CPHA = 1, CPHA_EXT = 0 -> latch data on rising edge, launch data on falling edge +CPHA = 0, CPHA_EXT = 1 -> latch data on falling edge, launch data on falling edge +CPHA = 1, CPHA_EXT = 1 -> latch data on rising edge, launch data on rising edge +*/ +#define SPI_CONTROLLER_STATE_SET (1 << 31) +#define SPI_CONTROLLER_STATE_CPHA_EXT (1 << 30) +#define SPI_CONTROLLER_STATE_GATE_CLK_SSOFF (1 << 29) +#define SPI_CONTROLLER_STATE_CLK_POLARITY (1 << 28) +#define SPI_CONTROLLER_STATE_ASYNC_CLOCK (1 << 27) + +/* set mode and controller state based on CHIP defaults + these values do not matter for the legacy controller */ +#if defined(CONFIG_BCM96816) +#define SPI_MODE_DEFAULT SPI_MODE_1 +#define SPI_CONTROLLER_STATE_DEFAULT (SPI_CONTROLLER_STATE_GATE_CLK_SSOFF | SPI_CONTROLLER_STATE_CPHA_EXT) +#elif (defined(CONFIG_BCM96362) || defined(CONFIG_BCM96328)) +#define SPI_MODE_DEFAULT SPI_MODE_0 +#define SPI_CONTROLLER_STATE_DEFAULT (SPI_CONTROLLER_STATE_GATE_CLK_SSOFF) +#else +#define SPI_MODE_DEFAULT SPI_MODE_3 +#define SPI_CONTROLLER_STATE_DEFAULT (0) +#endif + +#ifndef _CFE_ +int BcmSpiReserveSlave(int busNum, int slaveId, int maxFreq); +int BcmSpiReserveSlave2(int busNum, int slaveId, int maxFreq, int mode, int ctrlState); +int BcmSpiReleaseSlave(int busNum, int slaveId); +int BcmSpiSyncTrans(unsigned char *txBuf, unsigned char *rxBuf, int prependcnt, int nbytes, int busNum, int slaveId); +#endif + +int BcmSpi_SetFlashCtrl( int, int, int, int, int ); +int BcmSpi_GetMaxRWSize( int ); +int BcmSpi_Read(unsigned char *, int, int, int, int, int); +int BcmSpi_Write(unsigned char *, int, int, int, int); + +#endif /* __BCMSPIRES_H__ */ + diff --git a/shared/opensource/include/bcm963xx/bcmTag.h b/shared/opensource/include/bcm963xx/bcmTag.h new file mode 100755 index 0000000..8a1ca24 --- /dev/null +++ b/shared/opensource/include/bcm963xx/bcmTag.h @@ -0,0 +1,175 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +//************************************************************************************** +// File Name : bcmTag.h +// +// Description: add tag with validation system to the firmware image file to be uploaded +// via http +// +// Created : 02/28/2002 seanl +//************************************************************************************** + +#ifndef _BCMTAG_H_ +#define _BCMTAG_H_ + + +#define BCM_SIG_1 "Broadcom Corporation" +#define BCM_SIG_2 "ver. 2.0" // was "firmware version 2.0" now it is split 6 char out for chip id. + +#define BCM_TAG_VER "6" + +// file tag (head) structure all is in clear text except validationTokens (crc, md5, sha1, etc). Total: 128 unsigned chars +#define TAG_LEN 256 +#define TAG_VER_LEN 4 +#define SIG_LEN 20 +#define SIG_LEN_2 14 // Original second SIG = 20 is now devided into 14 for SIG_LEN_2 and 6 for CHIP_ID +#define CHIP_ID_LEN 6 +#define IMAGE_LEN 10 +#define ADDRESS_LEN 12 +#define FLAG_LEN 2 +#define TOKEN_LEN 20 +#define BOARD_ID_LEN 16 +#define RESERVED_LEN (TAG_LEN - TAG_VER_LEN - SIG_LEN - SIG_LEN_2 - CHIP_ID_LEN - BOARD_ID_LEN - \ + (4*IMAGE_LEN) - (3*ADDRESS_LEN) - (3*FLAG_LEN) - (2*TOKEN_LEN)) + + +// TAG for downloadable image (kernel plus file system) +typedef struct _FILE_TAG +{ + char tagVersion[TAG_VER_LEN]; // tag version. Will be 2 here. + char signiture_1[SIG_LEN]; // text line for company info + char signiture_2[SIG_LEN_2]; // additional info (can be version number) + char chipId[CHIP_ID_LEN]; // chip id + char boardId[BOARD_ID_LEN]; // board id + char bigEndian[FLAG_LEN]; // if = 1 - big, = 0 - little endia of the host + char totalImageLen[IMAGE_LEN]; // the sum of all the following length + char cfeAddress[ADDRESS_LEN]; // if non zero, cfe starting address + char cfeLen[IMAGE_LEN]; // if non zero, cfe size in clear ASCII text. + char rootfsAddress[ADDRESS_LEN]; // if non zero, filesystem starting address + char rootfsLen[IMAGE_LEN]; // if non zero, filesystem size in clear ASCII text. + char kernelAddress[ADDRESS_LEN]; // if non zero, kernel starting address + char kernelLen[IMAGE_LEN]; // if non zero, kernel size in clear ASCII text. + char imageSequence[FLAG_LEN * 2]; // incrments everytime an image is flashed + char reserved[RESERVED_LEN]; // reserved for later use + char imageValidationToken[TOKEN_LEN];// image validation token - can be crc, md5, sha; for + // now will be 4 unsigned char crc + char tagValidationToken[TOKEN_LEN]; // validation token for tag(from signiture_1 to end of // mageValidationToken) +} FILE_TAG, *PFILE_TAG; + +/* Whole flash image TAG definitions. */ +#define WFI_VERSION 0x00005731 +#define WFI_ANY_VERS_MASK 0x0000ff00 +#define WFI_ANY_VERS 0x00005700 +#define WFI_NOR_FLASH 1 +#define WFI_NAND16_FLASH 2 +#define WFI_NAND128_FLASH 3 + +/* TAG at end of whole flash ".w" image. Size must be TOKEN_LEN. */ +typedef struct _WFI_TAG +{ + unsigned long wfiCrc; + unsigned long wfiVersion; + unsigned long wfiChipId; + unsigned long wfiFlashType; + unsigned long wfiReserved; +} WFI_TAG, *PWFI_TAG; + +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */ +#define CRC_LEN 4 + +// only included if for bcmTag.exe program +#ifdef BCMTAG_EXE_USE + +static unsigned long Crc32_table[256] = { + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, + 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3, + 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988, + 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91, + 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE, + 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7, + 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC, + 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5, + 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172, + 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B, + 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940, + 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59, + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, + 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F, + 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924, + 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D, + 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A, + 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433, + 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, + 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01, + 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E, + 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457, + 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C, + 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65, + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, + 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB, + 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0, + 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9, + 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086, + 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F, + 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, + 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD, + 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A, + 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683, + 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8, + 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1, + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, + 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7, + 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC, + 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5, + 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252, + 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B, + 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60, + 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79, + 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236, + 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F, + 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04, + 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D, + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A, + 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713, + 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38, + 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21, + 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E, + 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777, + 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C, + 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45, + 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2, + 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB, + 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0, + 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9, + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6, + 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF, + 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94, + 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D +}; +#endif // BCMTAG_USE + + +#endif // _BCMTAG_H_ + diff --git a/shared/opensource/include/bcm963xx/bcm_hwdefs.h b/shared/opensource/include/bcm963xx/bcm_hwdefs.h new file mode 100755 index 0000000..07ecc29 --- /dev/null +++ b/shared/opensource/include/bcm963xx/bcm_hwdefs.h @@ -0,0 +1,193 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL?, available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +/***********************************************************************/ +/* */ +/* MODULE: bcm_hwdefs.h */ +/* PURPOSE: Define all base device addresses and HW specific macros. */ +/* */ +/***********************************************************************/ +#ifndef _BCM_HWDEFS_H +#define _BCM_HWDEFS_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define DYING_GASP_API + +/*****************************************************************************/ +/* Physical Memory Map */ +/*****************************************************************************/ + +#define PHYS_DRAM_BASE 0x00000000 /* Dynamic RAM Base */ +#if defined(CONFIG_BRCM_IKOS) +#define PHYS_FLASH_BASE 0x18000000 /* Flash Memory */ +#else +#define PHYS_FLASH_BASE 0x1FC00000 /* Flash Memory */ +#endif + +/*****************************************************************************/ +/* Note that the addresses above are physical addresses and that programs */ +/* have to use converted addresses defined below: */ +/*****************************************************************************/ +#define DRAM_BASE (0x80000000 | PHYS_DRAM_BASE) /* cached DRAM */ +#define DRAM_BASE_NOCACHE (0xA0000000 | PHYS_DRAM_BASE) /* uncached DRAM */ + +/* Binary images are always built for a standard MIPS boot address */ +#define IMAGE_BASE (0xA0000000 | PHYS_FLASH_BASE) + +/* Some chips don't support alternative boot vector */ +#if defined(CONFIG_BRCM_IKOS) +#define FLASH_BASE (0xA0000000 | PHYS_FLASH_BASE) /* uncached Flash */ +#define BOOT_OFFSET 0 +#else +#if defined(_BCM96328_) || defined(CONFIG_BCM96328) || defined(_BCM96362_) || defined(CONFIG_BCM96362) +#define FLASH_BASE 0xB8000000 +#else +#define FLASH_BASE (0xA0000000 | (MPI->cs[0].base & 0xFFFFFF00)) +#endif +#define BOOT_OFFSET (FLASH_BASE - IMAGE_BASE) +#endif + +/*****************************************************************************/ +/* Select the PLL value to get the desired CPU clock frequency. */ +/*****************************************************************************/ +#define FPERIPH 50000000 + +/*****************************************************************************/ +/* Board memory type offset */ +/*****************************************************************************/ +#define ONEK 1024 +#define FLASH_LENGTH_BOOT_ROM (64*ONEK) + +#define PROJECT_ID_LEN 7 /* Foxconn added by zacker, 02/29/2008, strlen("U12H094") */ +#ifdef _CFE_ +#define FLASH_SIZE 32 * 1024 * 1024 +#endif +#define BOARD_DATA_ADDR (FLASH_BASE + FLASH_SIZE - 0x20000) +#define BOARD_FOXNVRAM_ADDR (FLASH_BASE + FLASH_SIZE - 0x10000) +#define FOX_BOARD_ID_MAX_LEN 64 +#define BOARD_ID "U12L161" +/*****************************************************************************/ +/* NVRAM Offset and definition */ +/*****************************************************************************/ +#define NVRAM_SECTOR 0 +#define NVRAM_DATA_OFFSET 0x0580 +#define NVRAM_DATA_ID 0x0f1e2d3c // This is only for backwards compatability + +#define NVRAM_LENGTH ONEK // 1k nvram +#define NVRAM_VERSION_NUMBER 6 +#define NVRAM_FULL_LEN_VERSION_NUMBER 5 /* version in which the checksum was + placed at the end of the NVRAM + structure */ + +#define NVRAM_BOOTLINE_LEN 256 +#define NVRAM_BOARD_ID_STRING_LEN 16 +#define NVRAM_MAC_ADDRESS_LEN 6 + +#define NVRAM_GPON_SERIAL_NUMBER_LEN 13 +#define NVRAM_GPON_PASSWORD_LEN 11 + +#define NVRAM_WLAN_PARAMS_LEN 256 +#define NVRAM_WPS_DEVICE_PIN_LEN 8 + +#define THREAD_NUM_ADDRESS_OFFSET (NVRAM_DATA_OFFSET + 4 + NVRAM_BOOTLINE_LEN + NVRAM_BOARD_ID_STRING_LEN) +#define THREAD_NUM_ADDRESS (0x80000000 + THREAD_NUM_ADDRESS_OFFSET) + +#define DEFAULT_BOOTLINE "e=192.168.1.1:ffffff00 h=192.168.1.100 g= r=f f=vmlinux i=bcm963xx_fs_kernel d=1 p=0 " +#define DEFAULT_BOARD_IP "192.168.1.1" +#define DEFAULT_MAC_NUM 10 +#define DEFAULT_BOARD_MAC "00:10:18:00:00:00" +#define DEFAULT_TP_NUM 0 +#define DEFAULT_PSI_SIZE 24 +#define DEFAULT_GPON_SN "BRCM12345678" +#define DEFAULT_GPON_PW " " + +#define DEFAULT_WPS_DEVICE_PIN "12345670" + +#define DEFAULT_VOICE_BOARD_ID "NONE" + +#define NVRAM_MAC_COUNT_MAX 32 +#define NVRAM_MAX_PSI_SIZE 64 +#define NVRAM_MAX_SYSLOG_SIZE 256 + +#define NP_BOOT 0 +#define NP_ROOTFS_1 1 +#define NP_ROOTFS_2 2 +#define NP_DATA 3 +#define NP_BBT 4 +#define NP_TOTAL 5 + +#define NAND_DATA_SIZE_KB 1024 +#define NAND_BBT_THRESHOLD_KB (512 * 1024) +#define NAND_BBT_SMALL_SIZE_KB 1024 +#define NAND_BBT_BIG_SIZE_KB 4096 + +#define NAND_CFE_RAM_NAME "cferam.000" + +#ifndef _LANGUAGE_ASSEMBLY +typedef struct +{ + unsigned long ulVersion; + char szBootline[NVRAM_BOOTLINE_LEN]; + char szBoardId[NVRAM_BOARD_ID_STRING_LEN]; + unsigned long ulMainTpNum; + unsigned long ulPsiSize; + unsigned long ulNumMacAddrs; + unsigned char ucaBaseMacAddr[NVRAM_MAC_ADDRESS_LEN]; + char pad; + char backupPsi; /**< if 0x01, allocate space for a backup PSI */ + unsigned long ulCheckSumV4; + char gponSerialNumber[NVRAM_GPON_SERIAL_NUMBER_LEN]; + char gponPassword[NVRAM_GPON_PASSWORD_LEN]; + char wpsDevicePin[NVRAM_WPS_DEVICE_PIN_LEN]; + char wlanParams[NVRAM_WLAN_PARAMS_LEN]; + unsigned long ulSyslogSize; /**< number of KB to allocate for persistent syslog */ + unsigned long ulNandPartOfsKb[NP_TOTAL]; + unsigned long ulNandPartSizeKb[NP_TOTAL]; + char szVoiceBoardId[NVRAM_BOARD_ID_STRING_LEN]; + unsigned long afeId[2]; + char szFirmwareUpgradeBoardId[32]; /* foxconn added Bob, 07/12/2010, for TFTP firmware upgrade */ + char chUnused[332]; /* reduce array size from 364 to 332, total size of NVRAM_DATA is unchanged, Bob, 07/12/2010 */ + unsigned long ulCheckSum; +} NVRAM_DATA, *PNVRAM_DATA; +#endif + +#define BOOT_LATEST_IMAGE '0' +#define BOOT_PREVIOUS_IMAGE '1' + +/*****************************************************************************/ +/* Misc Offsets */ +/*****************************************************************************/ +#define CFE_VERSION_OFFSET 0x0570 +#define CFE_VERSION_MARK_SIZE 5 +#define CFE_VERSION_SIZE 5 + +#ifdef __cplusplus +} +#endif + +#endif /* _BCM_HWDEFS_H */ + diff --git a/shared/opensource/include/bcm963xx/bcmnetlink.h b/shared/opensource/include/bcm963xx/bcmnetlink.h new file mode 100755 index 0000000..e5fc77f --- /dev/null +++ b/shared/opensource/include/bcm963xx/bcmnetlink.h @@ -0,0 +1,47 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +/************************************************************************** + * File Name : bcmnetlink.h + * + * Description: This file defines broadcom specific netlink message types + ***************************************************************************/ +#ifndef _BCMNETLINK_H +#define _BCMNETLINK_H + +#include + +#ifndef NETLINK_BRCM_MONITOR +#define NETLINK_BRCM_MONITOR 25 +#endif + +/* message types exchanged using NETLINK_BRCM_MONITOR */ +#define MSG_NETLINK_BRCM_WAKEUP_MONITOR_TASK 0X1000 + +#define MSG_NETLINK_BRCM_LINK_STATUS_CHANGED 0X2000 + + +extern void kerSysSendtoMonitorTask(int msgType, char *msgData, int msgDataLen); + +#endif /*_BCMNETLINK_H */ diff --git a/shared/opensource/include/bcm963xx/boardparms.h b/shared/opensource/include/bcm963xx/boardparms.h new file mode 100755 index 0000000..7fec91c --- /dev/null +++ b/shared/opensource/include/bcm963xx/boardparms.h @@ -0,0 +1,453 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +/************************************************************************** + * File Name : boardparms.h + * + * Description: This file contains definitions and function prototypes for + * the BCM63xx board parameter access functions. + * + * Updates : 07/14/2003 Created. + ***************************************************************************/ + +#if !defined(_BOARDPARMS_H) +#define _BOARDPARMS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Return codes. */ +#define BP_SUCCESS 0 +#define BP_BOARD_ID_NOT_FOUND 1 +#define BP_VALUE_NOT_DEFINED 2 +#define BP_BOARD_ID_NOT_SET 3 + +/* Values for EthernetMacInfo PhyType. */ +#define BP_ENET_NO_PHY 0 +#define BP_ENET_INTERNAL_PHY 1 +#define BP_ENET_EXTERNAL_SWITCH 2 +#define BP_ENET_SWITCH_VIA_INTERNAL_PHY 3 /* it is for cpu internal phy connects to port 4 of 5325e */ + +/* Values for EthernetMacInfo Configuration type. */ +#define BP_ENET_CONFIG_MDIO 0 /* Internal PHY, External PHY, Switch+(no GPIO, no SPI, no MDIO Pseudo phy */ +#define BP_ENET_CONFIG_MDIO_PSEUDO_PHY 1 +#define BP_ENET_CONFIG_SPI_SSB_0 2 +#define BP_ENET_CONFIG_SPI_SSB_1 3 +#define BP_ENET_CONFIG_SPI_SSB_2 4 +#define BP_ENET_CONFIG_SPI_SSB_3 5 +#define BP_ENET_CONFIG_MMAP 6 +#define BP_ENET_CONFIG_GPIO_MDIO 7 /* use GPIO to simulate MDC/MDIO */ + +/* Values for VoIPDSPInfo DSPType. */ +#define BP_VOIP_NO_DSP 0 +#define BP_VOIP_DSP 1 +#define BP_VOIP_MIPS 2 + +/* Values for GPIO pin assignments (AH = Active High, AL = Active Low). */ +#define BP_GPIO_NUM_MASK 0x00FF +#define BP_ACTIVE_MASK 0x8000 +#define BP_ACTIVE_HIGH 0x0000 +#define BP_ACTIVE_LOW 0x8000 +#define BP_GPIO_SERIAL 0x4000 + +#define BP_GPIO_0_AH (0) +#define BP_GPIO_0_AL (0 | BP_ACTIVE_LOW) +#define BP_GPIO_1_AH (1) +#define BP_GPIO_1_AL (1 | BP_ACTIVE_LOW) +#define BP_GPIO_2_AH (2) +#define BP_GPIO_2_AL (2 | BP_ACTIVE_LOW) +#define BP_GPIO_3_AH (3) +#define BP_GPIO_3_AL (3 | BP_ACTIVE_LOW) +#define BP_GPIO_4_AH (4) +#define BP_GPIO_4_AL (4 | BP_ACTIVE_LOW) +#define BP_GPIO_5_AH (5) +#define BP_GPIO_5_AL (5 | BP_ACTIVE_LOW) +#define BP_GPIO_6_AH (6) +#define BP_GPIO_6_AL (6 | BP_ACTIVE_LOW) +#define BP_GPIO_7_AH (7) +#define BP_GPIO_7_AL (7 | BP_ACTIVE_LOW) +#define BP_GPIO_8_AH (8) +#define BP_GPIO_8_AL (8 | BP_ACTIVE_LOW) +#define BP_GPIO_9_AH (9) +#define BP_GPIO_9_AL (9 | BP_ACTIVE_LOW) +#define BP_GPIO_10_AH (10) +#define BP_GPIO_10_AL (10 | BP_ACTIVE_LOW) +#define BP_GPIO_11_AH (11) +#define BP_GPIO_11_AL (11 | BP_ACTIVE_LOW) +#define BP_GPIO_12_AH (12) +#define BP_GPIO_12_AL (12 | BP_ACTIVE_LOW) +#define BP_GPIO_13_AH (13) +#define BP_GPIO_13_AL (13 | BP_ACTIVE_LOW) +#define BP_GPIO_14_AH (14) +#define BP_GPIO_14_AL (14 | BP_ACTIVE_LOW) +#define BP_GPIO_15_AH (15) +#define BP_GPIO_15_AL (15 | BP_ACTIVE_LOW) +#define BP_GPIO_16_AH (16) +#define BP_GPIO_16_AL (16 | BP_ACTIVE_LOW) +#define BP_GPIO_17_AH (17) +#define BP_GPIO_17_AL (17 | BP_ACTIVE_LOW) +#define BP_GPIO_18_AH (18) +#define BP_GPIO_18_AL (18 | BP_ACTIVE_LOW) +#define BP_GPIO_19_AH (19) +#define BP_GPIO_19_AL (19 | BP_ACTIVE_LOW) +#define BP_GPIO_20_AH (20) +#define BP_GPIO_20_AL (20 | BP_ACTIVE_LOW) +#define BP_GPIO_21_AH (21) +#define BP_GPIO_21_AL (21 | BP_ACTIVE_LOW) +#define BP_GPIO_22_AH (22) +#define BP_GPIO_22_AL (22 | BP_ACTIVE_LOW) +#define BP_GPIO_23_AH (23) +#define BP_GPIO_23_AL (23 | BP_ACTIVE_LOW) +#define BP_GPIO_24_AH (24) +#define BP_GPIO_24_AL (24 | BP_ACTIVE_LOW) +#define BP_GPIO_25_AH (25) +#define BP_GPIO_25_AL (25 | BP_ACTIVE_LOW) +#define BP_GPIO_26_AH (26) +#define BP_GPIO_26_AL (26 | BP_ACTIVE_LOW) +#define BP_GPIO_27_AH (27) +#define BP_GPIO_27_AL (27 | BP_ACTIVE_LOW) +#define BP_GPIO_28_AH (28) +#define BP_GPIO_28_AL (28 | BP_ACTIVE_LOW) +#define BP_GPIO_29_AH (29) +#define BP_GPIO_29_AL (29 | BP_ACTIVE_LOW) +#define BP_GPIO_30_AH (30) +#define BP_GPIO_30_AL (30 | BP_ACTIVE_LOW) +#define BP_GPIO_31_AH (31) +#define BP_GPIO_31_AL (31 | BP_ACTIVE_LOW) +#define BP_GPIO_32_AH (32) +#define BP_GPIO_32_AL (32 | BP_ACTIVE_LOW) +#define BP_GPIO_33_AH (33) +#define BP_GPIO_33_AL (33 | BP_ACTIVE_LOW) +#define BP_GPIO_34_AH (34) +#define BP_GPIO_34_AL (34 | BP_ACTIVE_LOW) +#define BP_GPIO_35_AH (35) +#define BP_GPIO_35_AL (35 | BP_ACTIVE_LOW) +#define BP_GPIO_36_AH (36) +#define BP_GPIO_36_AL (36 | BP_ACTIVE_LOW) +#define BP_GPIO_37_AH (37) +#define BP_GPIO_37_AL (37 | BP_ACTIVE_LOW) +#define BP_GPIO_38_AH (38) +#define BP_GPIO_38_AL (38 | BP_ACTIVE_LOW) +#define BP_GPIO_39_AH (39) +#define BP_GPIO_39_AL (39 | BP_ACTIVE_LOW) +#define BP_GPIO_40_AH (40) +#define BP_GPIO_40_AL (40 | BP_ACTIVE_LOW) +#define BP_GPIO_41_AH (41) +#define BP_GPIO_41_AL (41 | BP_ACTIVE_LOW) +#define BP_GPIO_42_AH (42) +#define BP_GPIO_42_AL (42 | BP_ACTIVE_LOW) +#define BP_GPIO_43_AH (43) +#define BP_GPIO_43_AL (43 | BP_ACTIVE_LOW) +#define BP_GPIO_44_AH (44) +#define BP_GPIO_44_AL (44 | BP_ACTIVE_LOW) +#define BP_GPIO_45_AH (45) +#define BP_GPIO_45_AL (45 | BP_ACTIVE_LOW) +#define BP_GPIO_46_AH (46) +#define BP_GPIO_46_AL (46 | BP_ACTIVE_LOW) +#define BP_GPIO_47_AH (47) +#define BP_GPIO_47_AL (47 | BP_ACTIVE_LOW) + +#define BP_SERIAL_GPIO_0_AH (0 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_0_AL (0 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_1_AH (1 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_1_AL (1 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_2_AH (2 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_2_AL (2 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_3_AH (3 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_3_AL (3 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_4_AH (4 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_4_AL (4 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_5_AH (5 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_5_AL (5 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_6_AH (6 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_6_AL (6 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_7_AH (7 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_7_AL (7 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_8_AH (8 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_8_AL (8 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_9_AH (9 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_9_AL (9 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_10_AH (10 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_10_AL (10 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_11_AH (11 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_11_AL (11 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_12_AH (12 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_12_AL (12 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_13_AH (13 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_13_AL (13 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_14_AH (14 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_14_AL (14 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_15_AH (15 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_15_AL (15 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_16_AH (16 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_16_AL (16 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_17_AH (17 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_17_AL (17 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_18_AH (18 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_18_AL (18 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_19_AH (19 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_19_AL (19 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_20_AH (20 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_20_AL (20 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_21_AH (21 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_21_AL (21 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_22_AH (22 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_22_AL (22 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) +#define BP_SERIAL_GPIO_23_AH (23 | BP_GPIO_SERIAL) +#define BP_SERIAL_GPIO_23_AL (23 | BP_GPIO_SERIAL | BP_ACTIVE_LOW) + +/* Values for external interrupt assignments. */ +#define BP_EXT_INTR_0 0 +#define BP_EXT_INTR_1 1 +#define BP_EXT_INTR_2 2 +#define BP_EXT_INTR_3 3 +#define BP_EXT_INTR_4 4 +#define BP_EXT_INTR_5 5 + +/* Values for chip select assignments. */ +#define BP_CS_0 0 +#define BP_CS_1 1 +#define BP_CS_2 2 +#define BP_CS_3 3 + +#define BP_OVERLAY_GPON_TX_EN_L (1<<0) +#define BP_OVERLAY_PCI (1<<0) +#define BP_OVERLAY_CB (1<<1) +#define BP_OVERLAY_SPI_EXT_CS (1<<2) +#define BP_OVERLAY_UART1 (1<<3) +#define BP_OVERLAY_PHY (1<<4) +#define BP_OVERLAY_SERIAL_LEDS (1<<5) +#define BP_OVERLAY_EPHY_LED_0 (1<<6) +#define BP_OVERLAY_EPHY_LED_1 (1<<7) +#define BP_OVERLAY_GPHY_LED_0 (1<<6) +#define BP_OVERLAY_GPHY_LED_1 (1<<7) +#define BP_OVERLAY_EPHY_LED_2 (1<<8) +#define BP_OVERLAY_EPHY_LED_3 (1<<9) +#define BP_OVERLAY_INET_LED (1<<10) +#define BP_OVERLAY_MOCA_LED (1<<11) +#define BP_OVERLAY_USB_LED (1<<12) +#define BP_OVERLAY_USB_DEVICE (1<<13) + +/* Value for GPIO and external interrupt fields that are not used. */ +#define BP_NOT_DEFINED 0xffff + +/* Maximum size of the board id string. */ +#define BP_BOARD_ID_LEN 16 + +/* Maximum number of Ethernet MACs. */ +#define BP_MAX_ENET_MACS 2 +#define BP_MAX_SWITCH_PORTS 8 +/* Maximum number of VoIP DSPs. */ +#define BP_MAX_VOIP_DSP 2 + +/* Wireless Antenna Settings. */ +#define BP_WLAN_ANT_MAIN 0 +#define BP_WLAN_ANT_AUX 1 +#define BP_WLAN_ANT_BOTH 3 + +/* Wireless FLAGS */ +#define BP_WLAN_MAC_ADDR_OVERRIDE 0x0001 /* use kerSysGetMacAddress for mac address */ +#define BP_WLAN_EXCLUDE_ONBOARD 0x0002 /* exclude onboard wireless */ +#define BP_WLAN_EXCLUDE_ONBOARD_FORCE 0x0004 /* force exclude onboard wireless even without addon card*/ +#define BP_WLAN_USE_OTP 0x0008 /* don't use sw srom map, may fall to OTP or uninitialzed */ + +#define BP_WLAN_NVRAM_NAME_LEN 16 +#define BP_WLAN_MAX_PATCH_ENTRY 32 + +/* AFE IDs */ +#define BP_AFE_DEFAULT 0 + +#define BP_AFE_CHIP_INT (1 << 28) +#define BP_AFE_CHIP_6505 (2 << 28) +#define BP_AFE_CHIP_6306 (3 << 28) + +#define BP_AFE_LD_ISIL1556 (1 << 21) +#define BP_AFE_LD_6301 (2 << 21) +#define BP_AFE_LD_6302 (3 << 21) + +#define BP_AFE_FE_ANNEXA (1 << 15) +#define BP_AFE_FE_ANNEXB (2 << 15) +#define BP_AFE_FE_ANNEXJ (3 << 15) + +#define BP_AFE_FE_AVMODE_COMBO (0 << 13) +#define BP_AFE_FE_AVMODE_ADSL (1 << 13) +#define BP_AFE_FE_AVMODE_VDSL (2 << 13) + +/* VDSL only */ +#define BP_AFE_FE_REV_ISIL_REV1 (1 << 8) +/* Combo */ +#define BP_AFE_FE_REV_6302_REV1 (1 << 8) +#define BP_AFE_FE_REV_6302_REV_7_12 (1 << 8) +#define BP_AFE_FE_REV_6302_REV_7_4 (2 << 8) + +#define BP_AFE_FE_REV_6302_REV_7_2_1 (3 << 8) +#define BP_AFE_FE_REV_6302_REV_7_2 (4 << 8) +#define BP_AFE_FE_REV_6302_REV_7_2_UR2 (5 << 8) +#define BP_AFE_FE_REV_6302_REV_7_2_2 (6 << 8) +/* ADSL only*/ +#define BP_AFE_FE_REV_6302_REV_5_2_1 (1 << 8) +#define BP_AFE_FE_REV_6302_REV_5_2_2 (2 << 8) +#define BP_AFE_FE_REV_6301_REV_5_1_1 (1 << 8) + +#define BP_GET_EXT_AFE_DEFINED + +#if !defined(__ASSEMBLER__) + +/* Information about Ethernet switch */ +typedef struct { + int port_map; + int phy_id[BP_MAX_SWITCH_PORTS]; +} ETHERNET_SW_INFO; + +/* WAN port flag in the phy_id of ETHERNET_SW_INFO */ +#define BCM_WAN_PORT 0x40 +#define IsWanPort(id) (((id) & BCM_WAN_PORT) && ((id) != 0xFF)) + +#define c0(n) (((n) & 0x55555555) + (((n) >> 1) & 0x55555555)) +#define c1(n) (((n) & 0x33333333) + (((n) >> 2) & 0x33333333)) +#define c2(n) (((n) & 0x0f0f0f0f) + (((n) >> 4) & 0x0f0f0f0f)) +#define bitcount(r, n) {r = n; r = c0(r); r = c1(r); r = c2(r); r %= 255;} + +/* Information about an Ethernet MAC. If ucPhyType is BP_ENET_NO_PHY, + * then the other fields are not valid. + */ +typedef struct EthernetMacInfo +{ + unsigned char ucPhyType; /* BP_ENET_xxx */ + unsigned char ucPhyAddress; /* 0 to 31 */ + unsigned short usGpioLedPhyLinkSpeed; /* GPIO pin or not defined */ + unsigned short usConfigType; /* Configuration type */ + ETHERNET_SW_INFO sw; /* switch information */ + unsigned short usGpioMDC; /* GPIO pin to simulate MDC */ + unsigned short usGpioMDIO; /* GPIO pin to simulate MDIO */ +} ETHERNET_MAC_INFO, *PETHERNET_MAC_INFO; + +typedef struct WlanSromEntry { + char name[BP_WLAN_NVRAM_NAME_LEN]; + unsigned short wordOffset; + unsigned short value; +} WLAN_SROM_ENTRY; + +typedef struct WlanSromPatchInfo { + char szboardId[BP_BOARD_ID_LEN]; + unsigned short usWirelessChipId; + unsigned short usNeededSize; + WLAN_SROM_ENTRY entries[BP_WLAN_MAX_PATCH_ENTRY]; +} WLAN_SROM_PATCH_INFO, *PWLAN_SROM_PATCH_INFO; + +typedef struct WlanPciEntry { + char name[BP_WLAN_NVRAM_NAME_LEN]; + unsigned int dwordOffset; + unsigned int value; +} WLAN_PCI_ENTRY; + +typedef struct WlanPciPatchInfo { + char szboardId[BP_BOARD_ID_LEN]; + unsigned int usWirelessPciId; + int usNeededSize; + WLAN_PCI_ENTRY entries[BP_WLAN_MAX_PATCH_ENTRY]; +} WLAN_PCI_PATCH_INFO, *PWLAN_PCI_PATCH_INFO; + +/* Information about VoIP DSPs. If ucDspType is BP_VOIP_NO_DSP, + * then the other fields are not valid. + */ +typedef struct VoIPDspInfo +{ + unsigned char ucDspType; + unsigned char ucDspAddress; + unsigned short usGpioLedVoip; + unsigned short usGpioVoip1Led; + unsigned short usGpioVoip1LedFail; + unsigned short usGpioVoip2Led; + unsigned short usGpioVoip2LedFail; + unsigned short usGpioPotsLed; + unsigned short usGpioDectLed; + +} VOIP_DSP_INFO; + +int BpSetBoardId( char *pszBoardId ); +int BpGetBoardId( char *pszBoardId); +int BpGetBoardIds( char *pszBoardIds, int nBoardIdsSize ); + +int BpGetGPIOverlays( unsigned short *pusValue ); + +int BpGetRj11InnerOuterPairGpios( unsigned short *pusInner, unsigned short *pusOuter ); +int BpGetRtsCtsUartGpios( unsigned short *pusRts, unsigned short *pusCts ); + +int BpGetAdslLedGpio( unsigned short *pusValue ); +int BpGetAdslFailLedGpio( unsigned short *pusValue ); +int BpGetSecAdslLedGpio( unsigned short *pusValue ); +int BpGetSecAdslFailLedGpio( unsigned short *pusValue ); +int BpGetWirelessSesLedGpio( unsigned short *pusValue ); +int BpGetHpnaLedGpio( unsigned short *pusValue ); +int BpGetWanDataLedGpio( unsigned short *pusValue ); +int BpGetWanErrorLedGpio( unsigned short *pusValue ); +int BpGetBootloaderPowerOnLedGpio( unsigned short *pusValue ); +int BpGetBootloaderStopLedGpio( unsigned short *pusValue ); +int BpGetFpgaResetGpio( unsigned short *pusValue ); +int BpGetGponLedGpio( unsigned short *pusValue ); +int BpGetGponFailLedGpio( unsigned short *pusValue ); +int BpGetMoCALedGpio( unsigned short *pusValue ); +int BpGetMoCAFailLedGpio( unsigned short *pusValue ); + +int BpGetResetToDefaultExtIntr( unsigned short *pusValue ); +int BpGetWirelessSesExtIntr( unsigned short *pusValue ); +int BpGetHpnaExtIntr( unsigned long *pulValue ); + +int BpGetHpnaChipSelect( unsigned long *pulValue ); + +int BpGetWirelessAntInUse( unsigned short *pusValue ); +int BpGetWirelessFlags( unsigned short *pusValue ); +int BpGetWirelessPowerDownGpio( unsigned short *pusValue ); +int BpUpdateWirelessSromMap(unsigned short chipID, unsigned short* pBase, int sizeInWords); +int BpUpdateWirelessPciConfig (unsigned long pciID, unsigned long* pBase, int sizeInDWords); + +int BpGetEthernetMacInfo( PETHERNET_MAC_INFO pEnetInfos, int nNumEnetInfos ); +int BpGet6829PortInfo( unsigned char *portInfo6829 ); +int BpGetDslPhyAfeIds( unsigned long *pulValues ); +int BpGetExtAFEResetGpio( unsigned short *pulValues ); +int BpGetExtAFELDPwrGpio( unsigned short *pulValues ); +int BpGetExtAFELDModeGpio( unsigned short *pulValues ); + +VOIP_DSP_INFO *BpGetVoipDspConfig( unsigned char dspNum ); +int BpGetVoipLedGpio( unsigned short *pusValue ); +int BpGetVoip1LedGpio( unsigned short *pusValue ); +int BpGetVoip1FailLedGpio( unsigned short *pusValue ); +int BpGetVoip2LedGpio( unsigned short *pusValue ); +int BpGetVoip2FailLedGpio( unsigned short *pusValue ); +int BpGetPotsLedGpio( unsigned short *pusValue ); +int BpGetDectLedGpio( unsigned short *pusValue ); + +int bpstrcmp(const char *dest,const char *src); + + +#endif /* __ASSEMBLER__ */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BOARDPARMS_H */ + diff --git a/shared/opensource/include/bcm963xx/boardparms_voice.h b/shared/opensource/include/bcm963xx/boardparms_voice.h new file mode 100755 index 0000000..5d3c7e5 --- /dev/null +++ b/shared/opensource/include/bcm963xx/boardparms_voice.h @@ -0,0 +1,392 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +/************************************************************************** + * File Name : boardparms_voice.h + * + * Description: This file contains definitions and function prototypes for + * the BCM63xx voice board parameter access functions. + * + ***************************************************************************/ + +#if !defined(_BOARDPARMS_VOICE_H) +#define _BOARDPARMS_VOICE_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#define SI32261ENABLE /* Temporary #def until fully supported */ +#define SI32267ENABLE /* Temporary #def until fully supported */ + +/* Board string defines */ + +#define VOICECFG_NOSLIC_STR "NOSLIC" +#define VOICECFG_LE88276_STR "LE88276" +#define VOICECFG_LE88506_STR "LE88506" +#define VOICECFG_LE9530_STR "LE9530" +#define VOICECFG_VE890_STR "VE890" +#define VOICECFG_SI32178_STR "SI32178" +#define VOICECFG_SI3217X_STR "SI3217X" +#define VOICECFG_SI3226_STR "SI3226" +#define VOICECFG_6328AVNG_LE88276_NTR_STR "LE88276-NTR" +#define VOICECFG_6328AVNG_SI32267_STR "AVNG_SI32267" +#define VOICECFG_6328AVNG_VE890HV_PARTIAL_STR "AVNG_VE890HVP" +#define VOICECFG_6328AVNG_VE890HV_STR "AVNG_VE890HV" + +#define VOICECFG_6328AVNGR_SI32176_STR "AVNGR_SI32176" +#define VOICECFG_6328AVNGR_LE89116_STR "AVNGR_LE89116" +#define VOICECFG_6328AVNGR_SI3217X_STR "AVNGR_SI3217X" + +#define VOICECFG_6368MVWG_STR "MVWG" +#define VOICECFG_6368MBG_LE88276_STR "MBG_LE88276" +#define VOICECFG_6368MBG_LE88506_STR "MBG_LE88506" +#define VOICECFG_6368MBG_VE890_STR "MBG_VE890" +#define VOICECFG_6368MBG_LE89116_STR "MBG_LE89116" +#define VOICECFG_6368MBG_LE89316_STR "MBG_LE89316" +#define VOICECFG_6368MBG_SI3217X_STR "MBG_SI3217X" +#define VOICECFG_6368MBG_SI32176_STR "MBG_SI32176" +#define VOICECFG_6368MBG_SI32178_STR "MBG_SI32178" +#define VOICECFG_6368MBG_SI3226_STR "MBG_SI3226" + +#define VOICECFG_6362ADVNGP5_NOSLIC_STR "ADVNGP5_NOSLIC" +#define VOICECFG_6362ADVNGP5_SI3217X_STR "ADVNGP5_SI3217X" +#define VOICECFG_6362ADVNGP5_SI32176_STR "ADVNGP5_SI32176" +#define VOICECFG_6362ADVNGP5_SI32178_STR "ADVNGP5_SI32178" +#define VOICECFG_6362ADVNGP5_VE890_STR "ADVNGP5_VE890" +#define VOICECFG_6362ADVNGP5_LE89116_STR "ADVNGP5_LE89116" +#define VOICECFG_6362ADVNGP5_LE89316_STR "ADVNGP5_LE89316" +#define VOICECFG_6362ADVNGP5_LE88506_STR "ADVNGP5_LE88506" +#define VOICECFG_6362ADVNGP5_LE88276_STR "ADVNGP5_LE88276" +#define VOICECFG_6362ADVNGP5_SI3226_STR "ADVNGP5_SI3226" + +#define VOICECFG_6362ADVNGR_SI3217X_STR "ADVNGR_SI3217X" +#define VOICECFG_6362ADVNGR_SI32176_STR "ADVNGR_SI32176" +#define VOICECFG_6362ADVNGR_SI32178_STR "ADVNGR_SI32178" +#define VOICECFG_6362ADVNGR_SI3217X_NOFXO_STR "ADVNGR_SI3217XN" +#define VOICECFG_6362ADVNGR_VE890_STR "ADVNGR_VE890" +#define VOICECFG_6362ADVNGR_LE89116_STR "ADVNGR_LE89116" +#define VOICECFG_6362ADVNGR_LE89316_STR "ADVNGR_LE89316" +#define VOICECFG_6362ADVNGR_LE88506_STR "ADVNGR_LE88506" +#define VOICECFG_6362ADVNGR_LE88276_STR "ADVNGR_LE88276" +#define VOICECFG_6362ADVNGR_SI3226_STR "ADVNGR_SI3226" +#define VOICECFG_6362ADVNGR_SI32261_STR "ADVNGR_SI32261" +#define VOICECFG_6362ADVNGR_SI32267_STR "ADVNGR_SI32267" +#define VOICECFG_6362ADVNGR_VE890HV_PARTIAL_STR "ADVNGR_VE890HVP" +#define VOICECFG_6362ADVNGR_VE890HV_STR "ADVNGR_VE890HV" + +#define VOICECFG_6362ADVNGR2_SI3217X_STR "ADVNGR2_SI3217X" +#define VOICECFG_6362ADVNGR2_VE890_STR "ADVNGR2_VE890" +#define VOICECFG_6362ADVNGR2_LE88506_STR "ADVNGR2_LE88506" +#define VOICECFG_6362ADVNGR2_LE88276_STR "ADVNGR2_LE88276" +#define VOICECFG_6362ADVNGR2_SI3226_STR "ADVNGR2_SI3226" + +#define VOICECFG_6368MVNGR_SI3217X_STR "MVNGR_SI3217X" +#define VOICECFG_6368MVNGR_SI32176_STR "MVNGR_SI32176" +#define VOICECFG_6368MVNGR_SI32178_STR "MVNGR_SI32178" +#define VOICECFG_6368MVNGR_SI3217X_NOFXO_STR "MVNGR_SI3217XN" +#define VOICECFG_6368MVNGR_VE890_STR "MVNGR_VE890" +#define VOICECFG_6368MVNGR_LE89116_STR "MVNGR_LE89116" +#define VOICECFG_6368MVNGR_LE89316_STR "MVNGR_LE89316" +#define VOICECFG_6368MVNGR_LE88506_STR "MVNGR_LE88506" +#define VOICECFG_6368MVNGR_LE88276_STR "MVNGR_LE88276" +#define VOICECFG_6368MVNGR_SI3226_STR "MVNGR_SI3226" +#define VOICECFG_6368MVNGR_VE890HV_PARTIAL_STR "MVNGR_VE890HVP" +#define VOICECFG_6368MVNGR_VE890HV_STR "MVNGR_VE890HV" + + +/* Maximum number of devices in the system (on the board). +** Devices can refer to DECT, SLAC/SLIC, or SLAC/DAA combo. */ +#define BP_MAX_VOICE_DEVICES 5 + +/* Maximum numbers of channels per SLAC. */ +#define BP_MAX_CHANNELS_PER_DEVICE 2 + +/* Maximum number of voice channels in the system. +** This represents the sum of all channels available on the devices in the system */ +#define BP_MAX_VOICE_CHAN (BP_MAX_VOICE_DEVICES * BP_MAX_CHANNELS_PER_DEVICE) + +/* Max number of GPIO pins used for controling PSTN failover relays +** Note: the number of PSTN failover relays can be larger if multiple +** relays are controlled by single GPIO */ +#define BP_MAX_RELAY_PINS 2 + +#define BP_TIMESLOT_INVALID 0xFF + +/* General-purpose flag definitions (rename as appropriate) */ +#define BP_FLAG_DSP_APMHAL_ENABLE (1 << 0) +#define BP_FLAG_ISI_SUPPORT (1 << 1) +#define BP_FLAG_MODNAME_TESTNAME2 (1 << 2) +#define BP_FLAG_MODNAME_TESTNAME3 (1 << 3) +#define BP_FLAG_MODNAME_TESTNAME4 (1 << 4) +#define BP_FLAG_MODNAME_TESTNAME5 (1 << 5) +#define BP_FLAG_MODNAME_TESTNAME6 (1 << 6) +#define BP_FLAG_MODNAME_TESTNAME7 (1 << 7) +#define BP_FLAG_MODNAME_TESTNAME8 (1 << 8) + +/* +** Device-specific definitions +*/ +typedef enum +{ + BP_VD_NONE = -1, + BP_VD_IDECT1, /* Do not move this around, otherwise rebuild dect_driver.bin */ + BP_VD_EDECT1, + BP_VD_SILABS_3050, + BP_VD_SILABS_3215, + BP_VD_SILABS_3216, + BP_VD_SILABS_3217, + BP_VD_SILABS_32176, + BP_VD_SILABS_32178, + BP_VD_SILABS_3226, + BP_VD_SILABS_32261, + BP_VD_SILABS_32267, + BP_VD_ZARLINK_88010, + BP_VD_ZARLINK_88221, + BP_VD_ZARLINK_88276, + BP_VD_ZARLINK_88506, + BP_VD_ZARLINK_89010, + BP_VD_ZARLINK_89116, + BP_VD_ZARLINK_89316, + BP_VD_ZARLINK_9530, + BP_VD_ZARLINK_89136, + BP_VD_ZARLINK_89336, + BP_VD_MAX, +} BP_VOICE_DEVICE_TYPE; + + +/* +** Channel-specific definitions +*/ + +typedef enum +{ + BP_VOICE_CHANNEL_ACTIVE, + BP_VOICE_CHANNEL_INACTIVE, +} BP_VOICE_CHANNEL_STATUS; + +typedef enum +{ + BP_VCTYPE_NONE = -1, + BP_VCTYPE_SLIC, + BP_VCTYPE_DAA, + BP_VCTYPE_DECT +} BP_VOICE_CHANNEL_TYPE; + +typedef enum +{ + BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS, + BP_VOICE_CHANNEL_SAMPLE_SIZE_8BITS, +} BP_VOICE_CHANNEL_SAMPLE_SIZE; + +typedef enum +{ + BP_VOICE_CHANNEL_NARROWBAND, + BP_VOICE_CHANNEL_WIDEBAND, +} BP_VOICE_CHANNEL_FREQRANGE; + + +typedef enum +{ + BP_VOICE_CHANNEL_ENDIAN_BIG, + BP_VOICE_CHANNEL_ENDIAN_LITTLE, +} BP_VOICE_CHANNEL_ENDIAN_MODE; + +typedef enum +{ + BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW, + BP_VOICE_CHANNEL_PCMCOMP_MODE_ULAW, +} BP_VOICE_CHANNEL_PCMCOMP_MODE; + + +typedef struct +{ + unsigned int status; /* active/inactive */ + unsigned int type; /* SLIC/DAA/DECT */ + unsigned int pcmCompMode; /* u-law/a-law (applicable for 8-bit samples) */ + unsigned int freqRange; /* narrowband/wideband */ + unsigned int sampleSize; /* 8-bit / 16-bit */ + unsigned int endianMode; /* big/little */ + unsigned int rxTimeslot; /* Receive timeslot for the channel */ + unsigned int txTimeslot; /* Sending timeslot for the channel */ + +} BP_VOICE_CHANNEL; + +/* TODO: This structure could possibly be turned into union if needed */ +typedef struct +{ + int spiDevId; /* SPI device id */ + unsigned short spiGpio; /* SPI GPIO (if used for SPI control) */ +} BP_VOICE_SPI_CONTROL; + +typedef struct +{ + unsigned short relayGpio[BP_MAX_RELAY_PINS]; +} BP_PSTN_RELAY_CONTROL; + +typedef struct +{ + unsigned short dectUartGpioTx; + unsigned short dectUartGpioRx; +} BP_DECT_UART_CONTROL; + +typedef struct +{ + unsigned int voiceDeviceType; /* Specific type of device (Le88276, Si32176, etc.) */ + BP_VOICE_SPI_CONTROL spiCtrl; /* SPI control through dedicated SPI pin or GPIO */ + int requiresReset; /* Does the device requires reset (through GPIO) */ + unsigned short resetGpio; /* Reset GPIO */ + BP_VOICE_CHANNEL channel[BP_MAX_CHANNELS_PER_DEVICE]; /* Device channels */ + +} BP_VOICE_DEVICE; + + +/* +** Main structure for defining the board parameters and used by boardHal +** for proper initialization of the DSP and devices (SLACs, DECT, etc.) +*/ +typedef struct VOICE_BOARD_PARMS +{ + char szBoardId[BP_BOARD_ID_LEN]; /* board id string */ + unsigned int numFxsLines; /* Number of FXS lines in the system */ + unsigned int numFxoLines; /* Number of FXO lines in the system */ + unsigned int numDectLines; /* Number of DECT lines in the system */ + unsigned int numFailoverRelayPins; /* Number of GPIO pins controling PSTN failover relays */ + BP_VOICE_DEVICE voiceDevice[BP_MAX_VOICE_DEVICES]; /* Voice devices in the system */ + BP_PSTN_RELAY_CONTROL pstnRelayCtrl; /* Control for PSTN failover relays */ + BP_DECT_UART_CONTROL dectUartControl; /* Control for external DECT UART */ + unsigned int flags; /* General-purpose flags */ +} VOICE_BOARD_PARMS, *PVOICE_BOARD_PARMS; + +/* --- End of voice-specific structures and enums --- */ + +int BpGetVoiceParms( char* pszBoardId, VOICE_BOARD_PARMS* voiceParms ); +int BpSetVoiceBoardId( char *pszBoardId ); +int BpGetVoiceBoardId( char *pszBoardId ); +int BpGetVoiceBoardIds( char *pszBoardIds, int nBoardIdsSize ); + +/* Variable externs */ + +#if defined(_BCM96328_) || defined(CONFIG_BCM96328) + +extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_LE88276; +extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_SI3226; +extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_VE890; +extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_SI3217X; +extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_LE88506; +extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_SI32267; +extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_LE88276_NTR; +extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_VE890HV_Partial; +extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_VE890HV; + +extern VOICE_BOARD_PARMS voiceBoard_96328AVNGR_SI32176; +extern VOICE_BOARD_PARMS voiceBoard_96328AVNGR_LE89116; +extern VOICE_BOARD_PARMS voiceBoard_96328AVNGR_SI3217X; + +#endif + +#if defined(_BCM96362_) || defined(CONFIG_BCM96362) + +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_NOSLIC; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_VE890; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_LE89116; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_LE89316; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_SI3217X; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_SI32176; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_SI32178; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_LE88276; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_SI3226; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_LE88506; + +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI3217X; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI32176; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI32178; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI3217X_NOFXO; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_VE890; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_LE89116; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_LE89316; + +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_LE88506; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_LE88276; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI3226; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI32261; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI32267; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_VE890HVP; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_VE890HV; + +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGR2_SI3217X; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGR2_VE890; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGR2_LE88506; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGR2_LE88276; +extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGR2_SI3226; + +#endif + +#if defined(_BCM96368_) || defined(CONFIG_BCM96368) + +extern VOICE_BOARD_PARMS voiceBoard_96368MVWG; +extern VOICE_BOARD_PARMS voiceBoard_96368MBG_LE88276; +extern VOICE_BOARD_PARMS voiceBoard_96368MBG_LE88506; +extern VOICE_BOARD_PARMS voiceBoard_96368MBG_VE890; +extern VOICE_BOARD_PARMS voiceBoard_96368MBG_LE89116; +extern VOICE_BOARD_PARMS voiceBoard_96368MBG_LE89316; +extern VOICE_BOARD_PARMS voiceBoard_96368MBG_SI3217X; +extern VOICE_BOARD_PARMS voiceBoard_96368MBG_SI32176; +extern VOICE_BOARD_PARMS voiceBoard_96368MBG_SI32178; +extern VOICE_BOARD_PARMS voiceBoard_96368MBG_SI3226; + +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_SI3217X; +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_SI32176; +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_SI32178; +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_SI3217X_NOFXO; +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_VE890; +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_LE89116; +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_LE89316; +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_LE88506; +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_LE88276; +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_SI3226; +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_VE890HV_Partial; +extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_VE890HV; + +#endif + + +#if defined(_BCM96816_) || defined(CONFIG_BCM96816) + +extern VOICE_BOARD_PARMS voiceBoard_96816PVWM_LE88276; +extern VOICE_BOARD_PARMS voiceBoard_96816PVWM_SI3226; +extern VOICE_BOARD_PARMS voiceBoard_96816PVWM_LE88506; +extern VOICE_BOARD_PARMS voiceBoard_96816PVWM_LE9530; + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _BOARDPARMS_VOICE_H */ + diff --git a/shared/opensource/include/bcm963xx/fap_mod_size.h b/shared/opensource/include/bcm963xx/fap_mod_size.h new file mode 100644 index 0000000..03bb799 --- /dev/null +++ b/shared/opensource/include/bcm963xx/fap_mod_size.h @@ -0,0 +1,2 @@ +#define FAP_CORE_SIZE 0 +#define FAP_INIT_SIZE 0 diff --git a/shared/opensource/include/bcm963xx/flash_api.h b/shared/opensource/include/bcm963xx/flash_api.h new file mode 100755 index 0000000..7ac8022 --- /dev/null +++ b/shared/opensource/include/bcm963xx/flash_api.h @@ -0,0 +1,90 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL?, available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +/*************************************************************************** + * File Name : flash_api.h + * + * Description: This file contains definitions and prototypes for a public + * flash device interface and an internal flash device interface. + ***************************************************************************/ + +#if !defined(_FLASH_API_H) +#define _FLASH_API_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Flash definitions. */ +#define FLASH_API_OK 1 +#define FLASH_API_ERROR -1 + +#define FLASH_IFC_UNKNOWN 0 +#define FLASH_IFC_PARALLEL 1 +#define FLASH_IFC_SPI 2 +#define FLASH_IFC_HS_SPI 3 +#define FLASH_IFC_NAND 4 + +#define NAND_REINIT_FLASH 0xffff + +/* Public Interface Prototypes. */ +int flash_init(void); +int flash_sector_erase_int(unsigned short sector); +int flash_read_buf(unsigned short sector, int offset, unsigned char *buffer, + int numbytes); +int flash_write_buf(unsigned short sector, int offset, unsigned char *buffer, + int numbytes); +int flash_get_numsectors(void); +int flash_get_sector_size(unsigned short sector); +unsigned char *flash_get_memptr(unsigned short sector); +int flash_get_blk(int addr); +int flash_get_total_size(void); +int flash_get_flash_type(void); +void flash_change_flash_type(int type); + +/* Internal Flash Device Driver Information. */ +typedef struct flash_device_info_s +{ + unsigned short flash_device_id; + unsigned short flash_type; + char flash_device_name[30]; + + int (*fn_flash_sector_erase_int) (unsigned short sector); + int (*fn_flash_read_buf) (unsigned short sector, int offset, + unsigned char *buffer, int numbytes); + int (*fn_flash_write_buf) (unsigned short sector, int offset, + unsigned char *buffer, int numbytes); + int (*fn_flash_get_numsectors) (void); + int (*fn_flash_get_sector_size) (unsigned short sector); + unsigned char * (*fn_flash_get_memptr) (unsigned short sector); + int (*fn_flash_get_blk) (int addr); + int (*fn_flash_get_total_size) (void); +} flash_device_info_t; + +#ifdef __cplusplus +} +#endif + +#endif /* _FLASH_API_H */ + diff --git a/shared/opensource/include/bcm963xx/flash_common.h b/shared/opensource/include/bcm963xx/flash_common.h new file mode 100755 index 0000000..4fcceca --- /dev/null +++ b/shared/opensource/include/bcm963xx/flash_common.h @@ -0,0 +1,103 @@ +/* + Copyright 2000-2010 Broadcom Corporation + + Unless you and Broadcom execute a separate written software license + agreement governing use of this software, this software is licensed + to you under the terms of the GNU General Public License version 2 + (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php, + with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and to + copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + + Notwithstanding the above, under no circumstances may you combine this + software in any way with any other Broadcom software provided under a + license other than the GPL, without Broadcom's express prior written + consent. +*/ + +/*!\file flash_common.h + * \brief This file contains definitions and prototypes used by both + * CFE and kernel. + * + */ + +#if !defined(_FLASH_COMMON_H) +#define _FLASH_COMMON_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** default scratch pad length */ +#define SP_MAX_LEN (8 * 1024) + + +/** Flash storage address information that is determined by the flash driver. + * + * This structure is used by CFE and kernel. + */ +typedef struct flashaddrinfo +{ + int flash_persistent_start_blk; /**< primary psi, for config file */ + int flash_persistent_number_blk; + int flash_persistent_length; /**< in bytes */ + unsigned long flash_persistent_blk_offset; + int flash_scratch_pad_start_blk; /**< start of scratch pad */ + int flash_scratch_pad_number_blk; + int flash_scratch_pad_length; /**< in bytes */ + unsigned long flash_scratch_pad_blk_offset; + unsigned long flash_rootfs_start_offset; /**< offset from start of flash to fs+kernel image */ + int flash_backup_psi_start_blk; /**< starting block of backup psi. Length is + the same as primary psi. + Start at begining of sector, so offset is always 0. + No sharing sectors with anybody else. */ + int flash_backup_psi_number_blk; /**< The number of sectors for primary and backup + * psi may be different due to the irregular + * sector sizes at the end of the flash. */ + int flash_syslog_start_blk; /**< starting block of persistent syslog. */ + int flash_syslog_number_blk; /**< number of blocks */ + int flash_syslog_length; /**< in bytes, set from CFE, note busybox syslogd uses 16KB buffer. + Like backup_psi, always start at beginning of sector, + so offset is 0, and no sharing of sectors. */ + int flash_meta_start_blk; /**< The first block which is used for meta info such + as the psi, scratch pad, syslog, backup psi. + The kernel can use everything above this sector. */ +} FLASH_ADDR_INFO, *PFLASH_ADDR_INFO; + + +/** Fill in the fInfo structure with primary PSI, scratch pad, syslog, secondary PSI info. + * + * @param nvRam (IN) nvram info. + * @param fInfo (OUT) flash addr info that will be filled out by this function. + */ +void flash_init_info(const NVRAM_DATA *nvRam, FLASH_ADDR_INFO *fInfo); + + +/** Get the total number of bytes at the bottom of the flash used for PSI, scratch pad, etc. + * + * Even though this function is returning the number of bytes, it it guaranteed to + * return the number of bytes of whole sectors at the end which are in use. + * If customer enables backup PSI and persistent syslog, the number of bytes + * may go above 64KB. This function replaces the old FLASH_RESERVED_AT_END define. + * + * @param fInfo (IN) Pointer to flash_addr_info struct. + * + * @return number of bytes reserved at the end. + */ +unsigned int flash_get_reserved_bytes_at_end(const FLASH_ADDR_INFO *fInfo); + + +#ifdef __cplusplus +} +#endif + +#endif /* _FLASH_COMMON_H */ + diff --git a/shared/opensource/include/bcm963xx/gpio_drv.h b/shared/opensource/include/bcm963xx/gpio_drv.h new file mode 100755 index 0000000..8131153 --- /dev/null +++ b/shared/opensource/include/bcm963xx/gpio_drv.h @@ -0,0 +1,40 @@ +/*************************************************************************** +*** +*** Copyright 2008 Hon Hai Precision Ind. Co. Ltd. +*** All Rights Reserved. +*** No portions of this material shall be reproduced in any form without the +*** written permission of Hon Hai Precision Ind. Co. Ltd. +*** +*** All information contained in this document is Hon Hai Precision Ind. +*** Co. Ltd. company private, proprietary, and trade secret property and +*** are protected by international intellectual property laws and treaties. +*** +****************************************************************************/ + +#ifndef __GPIO_DRV_H__ +#define __GPIO_DRV_H__ + +#define DEV_GPIO_DRV "gpio_drv" + +#define GPIO_IOCTL_NUM 'W' + +#define IOCTL_LAN_LED_STATE _IOWR(GPIO_IOCTL_NUM, 0, int *) +#define IOCTL_USB_LED_STATE _IOWR(GPIO_IOCTL_NUM, 1, int *) +#define IOCTL_WPS_LED_STATE _IOWR(GPIO_IOCTL_NUM, 2, int *) +#define IOCTL_VOIP_LED_OFF _IOWR(GPIO_IOCTL_NUM, 3, int *) +#define IOCTL_VOIP_LED_ON _IOWR(GPIO_IOCTL_NUM, 4, int *) +#define IOCTL_VOIP_LED_BS _IOWR(GPIO_IOCTL_NUM, 5, int *) +#define IOCTL_VOIP_LED_BF _IOWR(GPIO_IOCTL_NUM, 6, int *) +#define IOCTL_VOIP_LED_BN _IOWR(GPIO_IOCTL_NUM, 7, int *) +#define IOCTL_WAN_LED_STATE _IOWR(GPIO_IOCTL_NUM, 8, int *) +#define IOCTL_LAN_VLAN_ID _IOWR(GPIO_IOCTL_NUM, 9, int *) +#define IOCTL_WAN_VLAN_ID _IOWR(GPIO_IOCTL_NUM, 10, int *) +#define IOCTL_3G_LED_STATE _IOWR(GPIO_IOCTL_NUM, 11, int *) //Foxconn added, Neil Chen, 2009/11/2 +/* Foxconn added start Bob, 01/28/2010, for wan detection */ +#define IOCTL_PVC_DET_START _IOWR(GPIO_IOCTL_NUM, 12, int *) +#define IOCTL_PVC_DET_STOP _IOWR(GPIO_IOCTL_NUM, 13, int *) +#define IOCTL_PVC_DET_RESULT _IOWR(GPIO_IOCTL_NUM, 14, int *) +/* Foxconn added end Bob, 01/28/2010, for wan detection */ +#define IOCTL_LAN_UNTAGGED_VLAN_ID _IOWR(GPIO_IOCTL_NUM, 15, int *) /* Foxconn added Bob, 10/25/2010, for tag based vlan */ + +#endif /* __GPIO_DRV_H__ */ diff --git a/shared/opensource/include/bcm963xx/wan_det.h b/shared/opensource/include/bcm963xx/wan_det.h new file mode 100755 index 0000000..d8a5645 --- /dev/null +++ b/shared/opensource/include/bcm963xx/wan_det.h @@ -0,0 +1,245 @@ +/*************************************************************************** +*** +*** Copyright 2008 Hon Hai Precision Ind. Co. Ltd. +*** All Rights Reserved. +*** No portions of this material shall be reproduced in any form without the +*** written permission of Hon Hai Precision Ind. Co. Ltd. +*** +*** All information contained in this document is Hon Hai Precision Ind. +*** Co. Ltd. company private, proprietary, and trade secret property and +*** are protected by international intellectual property laws and treaties. +*** +****************************************************************************/ + +#ifndef __WAN_DET_H__ +#define __WAN_DET_H__ + +/* Foxconn added start Bob, 01/22/2010 */ + +#define MAX_SCAN_SERVICE 8 + +typedef struct _vpivcitable +{ + int portId; + int vpi; + int vci; +}_VpiVciTable; + + +typedef struct scanResult +{ + _VpiVciTable service[MAX_SCAN_SERVICE]; + _VpiVciTable oam; + _VpiVciTable BPDU; +}SCAN_RESULT; +/* Foxconn added end Bob, 01/22/2010 */ + +typedef unsigned short U16; +typedef unsigned int U32; +typedef unsigned char U8; + +#define PATTERN_ROUTED 0 +#define PATTERN_BRIDGED 1 + +#define ETHER_TYPE_OFFSET 12 +#define ETHERTYPE_IP 0x0800 +#define ETHERTYPE_ARP 0x0806 +#define ETHERTYPE_PPPOE_DISCOVERY 0x8863 +#define ETHERHEADER_LEN 14 + +typedef struct _PacketContent +{ + U32 length; + U8 *data; +}PacketContent; + +typedef struct _Pattern +{ + const char *name; + const PacketContent *payload; + int protoType; + U16 ethertype; + const PacketContent *header; + const PacketContent *expected_payload; + +}Pattern; + + +static U8 dhcp_request_bytes[] = { + + // IP header + 0x45, 0x00, 0x01, 0x48, // version, IHL, TOS, Total Length + 0x00, 0x04, 0x00, 0x00, // ident, flags, frag off + 0x9b, 0x11, 0x1e, 0xa2, // TTL, proto, hdr checksum + 0x00, 0x00, 0x00, 0x00, // source addr + 0xff, 0xff, 0xff, 0xff, // destination addr + + // UDP header + 0x00, 0x44, 0x00, 0x43, 0x01, 0x34, 0xe6, 0x9a, 0x01, 0x01, 0x06, 0x00, + 0xb3, 0x05, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x2b, 0x00, 0x74, 0xb1, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x63, 0x82, 0x53, 0x63, 0x35, 0x01, 0x01, 0x33, + 0x04, 0x00, 0x00, 0x1c, 0x20, 0x37, 0x07, 0x01, 0x1c, 0x02, 0x03, 0x0f, 0x06, 0x0c, 0xff, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + +}; + +static PacketContent dhcp_request = { sizeof(dhcp_request_bytes), dhcp_request_bytes +}; + +static U8 pppoe_padi_bytes[] = { + 0x11, 0x09, 0x00, 0x00, 0x00, 0x04, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; +static PacketContent pppoe_padi = { sizeof(pppoe_padi_bytes), pppoe_padi_bytes }; + +/** Sequence of bytes for a PPP LCP Configure-Request (RFC1661). */ +static U8 ppp_lcp_confreq_bytes[] = { + 0xc0, 0x21, // LCP + 0x01, // Configure Request + 0x99, // randomish identifier + 0x00, 0x04, // length +}; +static PacketContent ppp_lcp_confreq = { sizeof(ppp_lcp_confreq_bytes), ppp_lcp_confreq_bytes }; + +/** Expected response from NULL (aka VcMux) encapsulated PPP/LCP */ +static U8 ppp_lcp_response_bytes[] = { 0xc0, 0x21 }; +static PacketContent ppp_lcp_response = { sizeof(ppp_lcp_response_bytes), ppp_lcp_response_bytes }; + +/** SNAP/LLC routed */ +static U8 snap_llc_routed_bytes[] = { 0xaa, 0xaa, 3, 0, 0, 0, 8, 0 }; +static PacketContent snap_llc_routed = { sizeof(snap_llc_routed_bytes), snap_llc_routed_bytes }; + +/** SNAP/LLC bridged, no fcs */ +static U8 snap_llc_bridged_bytes[] = { + 0xaa, 0xaa, 0x3, // LLC + 0x0, 0x80, 0xc2, // OUI + 0x00, 0x07, // PID + 0x00, 0x00 // PAD + }; +static PacketContent snap_llc_bridged = { sizeof(snap_llc_bridged_bytes), snap_llc_bridged_bytes }; + +/* foxconn added start Bob, 12/07/2009, ignore BPDU frame */ +/** SNAP/LLC bridged BPDU */ +static U8 snap_llc_bridged_BPDU_bytes[] = { + 0xaa, 0xaa, 0x3, // LLC + 0x0, 0x80, 0xc2, // OUI + 0x00, 0x0e, // PID + }; + /* foxconn added end Bob, 12/07/2009, ignore BPDU frame */ + +/** LLC for PPPoA. See RFC2364 section 6. */ +static U8 llc_pppoa_bytes[] = { 0xfe, 0xfe, 0x03, 0xcf }; +static PacketContent llc_pppoa = { + sizeof(llc_pppoa_bytes), llc_pppoa_bytes +}; + +static U8 vcmux_bridged_bytes[] = { 0, 0 }; +static PacketContent vcmux_bridged = { sizeof(vcmux_bridged_bytes), vcmux_bridged_bytes }; + +/** +Patterns to be sent to CO side +1. PPPoE LLC Bridged +2. VcMux encapsulated PPPoA +3. LLC encapsulated PPPoA +4. RFC1483 SNAP/LLC Routed +5. RFC1483 VcMux Bridged +6. PPPoE VCMux Bridged +7. RFC1483 SNAP/LLC Bridged +8. RFC1483 VcMux Routed +*/ +static Pattern patterns[] = +{ + { + "PPPoE LLC Bridged", + &pppoe_padi, + PATTERN_BRIDGED, + ETHERTYPE_PPPOE_DISCOVERY, + &snap_llc_bridged, + NULL + }, + { + "VcMux encapsulated PPPoA", + &ppp_lcp_confreq, + PATTERN_ROUTED, + 0, // no need for etherheader! + NULL, + &ppp_lcp_response + }, + + { + "LLC encapsulated PPPoA", + &ppp_lcp_confreq, + PATTERN_ROUTED, + 0, // no need for etherheader! + &llc_pppoa, // encapsulated with PPPoA LLC header + NULL + }, + + /* RFC1483 SNAP/LLC routed */ + { + "RFC1483 SNAP/LLC Routed", + &dhcp_request, + PATTERN_ROUTED, + 0, + &snap_llc_routed, + NULL + }, + + /* RFC1483 VC mux bridged */ + { + "RFC1483 VcMux Bridged", + &dhcp_request, + PATTERN_BRIDGED, + ETHERTYPE_IP, + &vcmux_bridged, + NULL + }, + + /* PPPOE VCMux Bridged*/ + { + "PPPoE VCMux Bridged", + &pppoe_padi, + PATTERN_BRIDGED, + ETHERTYPE_PPPOE_DISCOVERY, + &vcmux_bridged, + NULL + }, + + /* RFC1483 SNAP/LLC bridged */ + { + "RFC1483 SNAP/LLC Bridged", + &dhcp_request, + PATTERN_BRIDGED, + ETHERTYPE_IP, + &snap_llc_bridged, + NULL + }, + + /* RFC1483 VC mux routed */ + { + "RFC1483 VcMux Routed", + &dhcp_request, + PATTERN_ROUTED, + 0, + NULL, + NULL + }, +}; + +#endif /* __WAN_DET_H__ */ diff --git a/shared/opensource/include/bcm963xx/wps_led.h b/shared/opensource/include/bcm963xx/wps_led.h new file mode 100755 index 0000000..69f8682 --- /dev/null +++ b/shared/opensource/include/bcm963xx/wps_led.h @@ -0,0 +1,28 @@ +/*************************************************************************** +*** +*** Copyright 2007 Hon Hai Precision Ind. Co. Ltd. +*** All Rights Reserved. +*** No portions of this material shall be reproduced in any form without the +*** written permission of Hon Hai Precision Ind. Co. Ltd. +*** +*** All information contained in this document is Hon Hai Precision Ind. +*** Co. Ltd. company private, proprietary, and trade secret property and +*** are protected by international intellectual property laws and treaties. +*** +****************************************************************************/ + +#ifndef __WPS_LED_H__ +#define __WPS_LED_H__ + +#define DEV_GPIO_DRV "wps_led" + +#define WPS_LED_IOCTL_NUM 'W' + +#define WPS_LED_BLINK_NORMAL _IOWR(WPS_LED_IOCTL_NUM, 0, int *) +#define WPS_LED_BLINK_QUICK _IOWR(WPS_LED_IOCTL_NUM, 1, int *) +#define WPS_LED_BLINK_OFF _IOWR(WPS_LED_IOCTL_NUM, 2, int *) +#define WPS_LED_CHANGE_GREEN _IOWR(WPS_LED_IOCTL_NUM, 3, int *) +#define WPS_LED_CHANGE_AMBER _IOWR(WPS_LED_IOCTL_NUM, 4, int *) +#define WPS_LED_BLINK_QUICK2 _IOWR(WPS_LED_IOCTL_NUM, 5, int *) + +#endif -- cgit v1.2.3