/* * QEMU MC146818 RTC emulation * * Copyright (c) 2003-2004 Fabrice Bellard * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. */ #include "vl.h" //#define DEBUG_CMOS #define RTC_SECONDS 0 #define RTC_SECONDS_ALARM 1 #define RTC_MINUTES 2 #define RTC_MINUTES_ALARM 3 #define RTC_HOURS 4 #define RTC_HOURS_ALARM 5 #define RTC_ALARM_DONT_CARE 0xC0 #define RTC_DAY_OF_WEEK 6 #define RTC_DAY_OF_MONTH 7 #define RTC_MONTH 8 #define RTC_YEAR 9 #define RTC_REG_A 10 #define RTC_REG_B 11 #define RTC_REG_C 12 #define RTC_REG_D 13 #define REG_A_UIP 0x80 #define REG_B_SET 0x80 #define REG_B_PIE 0x40 #define REG_B_AIE 0x20 #define REG_B_UIE 0x10 struct RTCState { uint8_t cmos_data[128]; uint8_t cmos_index; struct tm current_tm; int irq; /* periodic timer */ QEMUTimer *periodic_timer; int64_t next_periodic_time; /* second update */ int64_t next_second_time; QEMUTimer *second_timer; QEMUTimer *second_timer2; }; static void rtc_set_time(RTCState *s); static void rtc_copy_date(RTCState *s); static void rtc_timer_update(RTCState *s, int64_t current_time) { int period_code, period; int64_t cur_clock, next_irq_clock; period_code = s->cmos_data[RTC_REG_A] & 0x0f; if (period_code != 0 && (s->cmos_data[RTC_REG_B] & REG_B_PIE)) { if (period_code <= 2) period_code += 7; /* period in 32 Khz cycles */ period = 1 << (period_code - 1); /* compute 32 khz clock */ cur_clock = muldiv64(current_time, 32768, ticks_per_sec); next_irq_clock = (cur_clock & ~(period - 1)) + period; s->next_periodic_time = muldiv64(next_irq_clock, ticks_per_sec, 32768) + 1; qemu_mod_timer(s->periodic_timer, s->next_periodic_time); } else { qemu_del_timer(s->periodic_timer); } } static void rtc_periodic_timer(void *opaque) { RTCState *s = opaque; rtc_timer_update(s, s->next_periodic_time); s->cmos_data[RTC_REG_C] |= 0xc0; pic_set_irq(s->irq, 1); } static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data) { RTCState *s = opaque; if ((addr & 1) == 0) { s->cmos_index = data & 0x7f; } else { #ifdef DEBUG_CMOS printf("cmos: write index=0x%02x val=0x%02x\n", s->cmos_index, data); #endif switch(s->cmos_index) { case RTC_SECONDS_ALARM: case RTC_MINUTES_ALARM: case RTC_HOURS_ALARM: /* XXX: not supported */ s->cmos_data[s->cmos_index] = data; break; case RTC_SECONDS: case RTC_MINUTES: case RTC_HOURS: case RTC_DAY_OF_WEEK: case RTC_DAY_OF_MONTH: case RTC_MONTH: case RTC_YEAR: s->cmos_data[s->cmos_index] = data; /* if in set mode, do not update the time */ if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { rtc_set_time(s); } break; case RTC_REG_A: /* UIP bit is read only */ s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | (s->cmos_data[RTC_REG_A] & REG_A_UIP); rtc_timer_update(s, qemu_get_clock(vm_clock)); break; case RTC_REG_B: if (data & REG_B_SET) { /* set mode: reset UIP mode
From 34e2b403040a2f9d3ba071d95a7f42457e2950f9 Mon Sep 17 00:00:00 2001
From: Gabor Juhos <juhosg@openwrt.org>
Date: Tue, 7 Apr 2015 18:35:15 +0200
Subject: [PATCH] mtd: spi-nor: add support for the ISSI SI25CD512 SPI flash

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
---
 drivers/mtd/spi-nor/spi-nor.c |    3 +++
 1 file changed, 3 insertions(+)

--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -566,6 +566,9 @@ static const struct flash_info spi_nor_i
 	/* ISSI */
 	{ "is25cd512", INFO(0x7f9d20, 0, 32 * 1024,   2, SECT_4K) },
 
+	/* ISSI */
+	{ "is25cd512", INFO(0x7f9d20, 0, 32 * 1024,   2, SECT_4K) },
+
 	/* Macronix */
 	{ "mx25l512e",   INFO(0xc22010, 0, 64 * 1024,   1, SECT_4K) },
 	{ "mx25l2005a",  INFO(0xc22012, 0, 64 * 1024,   4, SECT_4K) },
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-29 03:57:18 +0000
t = s->cmos_data[s->cmos_index]; break; } #ifdef DEBUG_CMOS printf("cmos: read index=0x%02x val=0x%02x\n", s->cmos_index, ret); #endif return ret; } } void rtc_set_memory(RTCState *s, int addr, int val) { if (addr >= 0 && addr <= 127) s->cmos_data[addr] = val; } void rtc_set_date(RTCState *s, const struct tm *tm) { s->current_tm = *tm; rtc_copy_date(s); } static void rtc_save(QEMUFile *f, void *opaque) { RTCState *s = opaque; qemu_put_buffer(f, s->cmos_data, 128); qemu_put_8s(f, &s->cmos_index); qemu_put_be32s(f, &s->current_tm.tm_sec); qemu_put_be32s(f, &s->current_tm.tm_min); qemu_put_be32s(f, &s->current_tm.tm_hour); qemu_put_be32s(f, &s->current_tm.tm_wday); qemu_put_be32s(f, &s->current_tm.tm_mday); qemu_put_be32s(f, &s->current_tm.tm_mon); qemu_put_be32s(f, &s->current_tm.tm_year); qemu_put_timer(f, s->periodic_timer); qemu_put_be64s(f, &s->next_periodic_time); qemu_put_be64s(f, &s->next_second_time); qemu_put_timer(f, s->second_timer); qemu_put_timer(f, s->second_timer2); } static int rtc_load(QEMUFile *f, void *opaque, int version_id) { RTCState *s = opaque; if (version_id != 1) return -EINVAL; qemu_get_buffer(f, s->cmos_data, 128); qemu_get_8s(f, &s->cmos_index); qemu_get_be32s(f, &s->current_tm.tm_sec); qemu_get_be32s(f, &s->current_tm.tm_min); qemu_get_be32s(f, &s->current_tm.tm_hour); qemu_get_be32s(f, &s->current_tm.tm_wday); qemu_get_be32s(f, &s->current_tm.tm_mday); qemu_get_be32s(f, &s->current_tm.tm_mon); qemu_get_be32s(f, &s->current_tm.tm_year); qemu_get_timer(f, s->periodic_timer); qemu_get_be64s(f, &s->next_periodic_time); qemu_get_be64s(f, &s->next_second_time); qemu_get_timer(f, s->second_timer); qemu_get_timer(f, s->second_timer2); return 0; } RTCState *rtc_init(int base, int irq) { RTCState *s; s = qemu_mallocz(sizeof(RTCState)); if (!s) return NULL; s->irq = irq; s->cmos_data[RTC_REG_A] = 0x26; s->cmos_data[RTC_REG_B] = 0x02; s->cmos_data[RTC_REG_C] = 0x00; s->cmos_data[RTC_REG_D] = 0x80; s->periodic_timer = qemu_new_timer(vm_clock, rtc_periodic_timer, s); s->second_timer = qemu_new_timer(vm_clock, rtc_update_second, s); s->second_timer2 = qemu_new_timer(vm_clock, rtc_update_second2, s); s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100; qemu_mod_timer(s->second_timer2, s->next_second_time); register_ioport_write(base, 2, 1, cmos_ioport_write, s); register_ioport_read(base, 2, 1, cmos_ioport_read, s); register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s); return s; }