* update patches to 3.0

* add basic vr9 support
* backport 3.1 fixes
* backport 3.2 queue (falcon)

SVN-Revision: 28405

100 files changed, 8778 insertions, 6148 deletions

diff --git a/target/linux/lantiq/Makefile b/target/linux/lantiq/Makefile
index e355c15730..8d845b95a7 100644
--- a/target/linux/lantiq/Makefile
+++ b/target/linux/lantiq/Makefile
@@ -12,7 +12,7 @@ BOARDNAME:=Lantiq GPON/XWAY
 FEATURES:=squashfs jffs2
 DEFAULT_SUBTARGET:=danube
 
-LINUX_VERSION:=2.6.39.4
+LINUX_VERSION:=3.0.3
 
 CFLAGS=-Os -pipe -mips32r2 -mtune=mips32r2 -fno-caller-saves
 
diff --git a/target/linux/lantiq/ar9/config-3.0 b/target/linux/lantiq/ar9/config-3.0
deleted file mode 100644
index f596114d76..0000000000
--- a/target/linux/lantiq/ar9/config-3.0
+++ /dev/null
@@ -1,51 +0,0 @@
-CONFIG_ADM6996_PHY=y
-CONFIG_AR8216_PHY=y
-# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
-# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
-# CONFIG_ATH79 is not set
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IRQ_WORK=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_INPUT=y
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_GPIO_BUTTONS is not set
-CONFIG_INPUT_POLLDEV=y
-# CONFIG_ISDN is not set
-CONFIG_LANTIQ_ETOP=y
-# CONFIG_LANTIQ_MACH_ARV45XX is not set
-# CONFIG_LANTIQ_MACH_EASY50712 is not set
-CONFIG_LANTIQ_MACH_NETGEAR=y
-# CONFIG_LANTIQ_MACH_GIGASX76X is not set
-CONFIG_MACH_NO_WESTBRIDGE=y
-# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_QUOTACTL is not set
-CONFIG_RTL8306_PHY=y
-# CONFIG_SOC_AMAZON_SE is not set
-# CONFIG_SOC_FALCON is not set
-CONFIG_SOC_TYPE_XWAY=y
-CONFIG_SOC_XWAY=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-# CONFIG_SPI_GPIO is not set
-CONFIG_SPI_LANTIQ=y
-CONFIG_SPI_MASTER=y
-CONFIG_USB_SUPPORT=y
-CONFIG_XZ_DEC=y
diff --git a/target/linux/lantiq/ar9/config-default b/target/linux/lantiq/ar9/config-default
index fb69899594..34192d03fc 100644
--- a/target/linux/lantiq/ar9/config-default
+++ b/target/linux/lantiq/ar9/config-default
@@ -27,8 +27,8 @@ CONFIG_LANTIQ_ETOP=y
 # CONFIG_LANTIQ_MACH_ARV45XX is not set
 # CONFIG_LANTIQ_MACH_EASY50712 is not set
 CONFIG_LANTIQ_MACH_NETGEAR=y
-# CONFIG_LANTIQ_MACH_GIGASX76X is not set
 CONFIG_LANTIQ_MACH_WBMR=y
+# CONFIG_LANTIQ_MACH_GIGASX76X is not set
 CONFIG_MACH_NO_WESTBRIDGE=y
 # CONFIG_MINIX_FS_NATIVE_ENDIAN is not set
 CONFIG_NEED_DMA_MAP_STATE=y
@@ -40,6 +40,7 @@ CONFIG_PERF_USE_VMALLOC=y
 # CONFIG_QUOTACTL is not set
 CONFIG_RTL8306_PHY=y
 # CONFIG_SOC_AMAZON_SE is not set
+# CONFIG_SOC_VR9 is not set
 # CONFIG_SOC_FALCON is not set
 CONFIG_SOC_TYPE_XWAY=y
 CONFIG_SOC_XWAY=y
@@ -50,3 +51,4 @@ CONFIG_SPI_LANTIQ=y
 CONFIG_SPI_MASTER=y
 CONFIG_USB_SUPPORT=y
 CONFIG_XZ_DEC=y
+CONFIG_SPI_XWAY=y
diff --git a/target/linux/lantiq/ar9/profiles/003-buffalo.mk b/target/linux/lantiq/ar9/profiles/003-buffalo.mk
index bdf838d6e8..df2829ef3e 100644
--- a/target/linux/lantiq/ar9/profiles/003-buffalo.mk
+++ b/target/linux/lantiq/ar9/profiles/003-buffalo.mk
@@ -1,7 +1,7 @@
 define Profile/WBMR
   NAME:=WBMR - Buffalo WBMR-HP-G300H
   PACKAGES:= kmod-usb-core kmod-usb-dwc-otg kmod-leds-gpio \
-	 kmod-ltq-dsl-firmware-b kmod-ledtrig-usbdev 
+	 kmod-ltq-dsl-firmware-b-ar9 kmod-ledtrig-usbdev
 endef
 
 define Profile/WBMR/Description
diff --git a/target/linux/lantiq/ar9/target.mk b/target/linux/lantiq/ar9/target.mk
index a04384efeb..89a1586d58 100644
--- a/target/linux/lantiq/ar9/target.mk
+++ b/target/linux/lantiq/ar9/target.mk
@@ -3,7 +3,7 @@ SUBTARGET:=ar9
 BOARDNAME:=AR9
 FEATURES:=squashfs jffs2 atm
 
-DEFAULT_PACKAGES+=kmod-pppoa ppp-mod-pppoa linux-atm atm-tools br2684ctl kmod-ltq-dsl ltq-dsl-app swconfig
+DEFAULT_PACKAGES+=kmod-pppoa ppp-mod-pppoa linux-atm atm-tools br2684ctl kmod-ltq-dsl-ar9 ltq-dsl-app swconfig
 
 define Target/Description
 	Lantiq XWAY (danube/twinpass/ar9)
diff --git a/target/linux/lantiq/ase/config-3.0 b/target/linux/lantiq/ase/config-3.0
deleted file mode 100644
index b39ed5e501..0000000000
--- a/target/linux/lantiq/ase/config-3.0
+++ /dev/null
@@ -1,37 +0,0 @@
-# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
-# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
-# CONFIG_ATH79 is not set
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IRQ_WORK=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_INPUT=y
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_GPIO_BUTTONS is not set
-CONFIG_INPUT_POLLDEV=y
-# CONFIG_ISDN is not set
-CONFIG_LANTIQ_ETOP=y
-CONFIG_LANTIQ_MACH_EASY50601=y
-CONFIG_MACH_NO_WESTBRIDGE=y
-# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set
-# CONFIG_MTD_LATCH_ADDR is not set
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_PERF_USE_VMALLOC=y
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_QUOTACTL is not set
-CONFIG_SOC_AMAZON_SE=y
-# CONFIG_SOC_FALCON is not set
-CONFIG_SOC_TYPE_XWAY=y
-# CONFIG_SOC_XWAY is not set
-CONFIG_XZ_DEC=y
diff --git a/target/linux/lantiq/ase/config-default b/target/linux/lantiq/ase/config-default
index b39ed5e501..a6c8a3d00f 100644
--- a/target/linux/lantiq/ase/config-default
+++ b/target/linux/lantiq/ase/config-default
@@ -31,7 +31,9 @@ CONFIG_PERF_USE_VMALLOC=y
 # CONFIG_PREEMPT_RCU is not set
 # CONFIG_QUOTACTL is not set
 CONFIG_SOC_AMAZON_SE=y
+# CONFIG_SOC_VR9 is not set
 # CONFIG_SOC_FALCON is not set
 CONFIG_SOC_TYPE_XWAY=y
 # CONFIG_SOC_XWAY is not set
 CONFIG_XZ_DEC=y
+CONFIG_SPI_XWAY=y
diff --git a/target/linux/lantiq/ase/target.mk b/target/linux/lantiq/ase/target.mk
index 343edf98ef..98374634c2 100644
--- a/target/linux/lantiq/ase/target.mk
+++ b/target/linux/lantiq/ase/target.mk
@@ -3,7 +3,7 @@ SUBTARGET:=ase
 BOARDNAME:=Amazon-SE
 FEATURES:=squashfs jffs2 atm
 
-DEFAULT_PACKAGES+=kmod-pppoa ppp-mod-pppoa linux-atm atm-tools br2684ctl kmod-ltq-dsl ltq-dsl-app
+DEFAULT_PACKAGES+=kmod-pppoa ppp-mod-pppoa linux-atm atm-tools br2684ctl kmod-ltq-dsl-ase ltq-dsl-app
 
 define Target/Description
 	Lantiq ASE
diff --git a/target/linux/lantiq/config-3.0 b/target/linux/lantiq/config-3.0
deleted file mode 100644
index d57cf35cf2..0000000000
--- a/target/linux/lantiq/config-3.0
+++ /dev/null
@@ -1,112 +0,0 @@
-# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
-CONFIG_ARCH_POPULATES_NODE_MAP=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-CONFIG_ARCH_SUPPORTS_OPROFILE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_ATH79 is not set
-CONFIG_BCMA_POSSIBLE=y
-# CONFIG_BRCMUTIL is not set
-CONFIG_CEVT_R4K=y
-CONFIG_CEVT_R4K_LIB=y
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_R4K=y
-CONFIG_CSRC_R4K_LIB=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_EARLY_PRINTK=y
-# CONFIG_FSNOTIFY is not set
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_IRQ_WORK=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ=250
-# CONFIG_HZ_100 is not set
-CONFIG_HZ_250=y
-CONFIG_IFX_UDP_REDIRECT=y
-CONFIG_IMAGE_CMDLINE_HACK=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQ_CPU=y
-CONFIG_LANTIQ=y
-CONFIG_LANTIQ_MACH_95C3AM1=y
-CONFIG_LANTIQ_MACH_EASY98000=y
-CONFIG_LANTIQ_MACH_EASY98020=y
-CONFIG_LANTIQ_WDT=y
-CONFIG_LEDS_GPIO=y
-CONFIG_MACH_NO_WESTBRIDGE=y
-# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set
-CONFIG_MIPS=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-CONFIG_MIPS_MACHINE=y
-CONFIG_MIPS_MT_DISABLED=y
-# CONFIG_MIPS_MT_SMP is not set
-# CONFIG_MIPS_MT_SMTC is not set
-# CONFIG_MIPS_VPE_LOADER is not set
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_LANTIQ=y
-CONFIG_MTD_UIMAGE_SPLIT=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NLS=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_QUOTACTL is not set
-# CONFIG_RTC_CLASS is not set
-CONFIG_RTL8366RB_PHY=y
-CONFIG_RTL8366_SMI=y
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SERIAL_8250 is not set
-CONFIG_SERIAL_LANTIQ=y
-CONFIG_SWAP_IO_SPACE=y
-CONFIG_SWCONFIG=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MULTITHREADING=y
-CONFIG_XZ_DEC=y
-CONFIG_ZONE_DMA_FLAG=0
diff --git a/target/linux/lantiq/config-default b/target/linux/lantiq/config-default
index d799d24993..d4e90c9b9a 100644
--- a/target/linux/lantiq/config-default
+++ b/target/linux/lantiq/config-default
@@ -1,70 +1,62 @@
-# CONFIG_64BIT is not set
+# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
 # CONFIG_ARCH_HAS_ILOG2_U32 is not set
 # CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
 CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_ARCH_REQUIRE_GPIOLIB=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
 CONFIG_ARCH_SUPPORTS_OPROFILE=y
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_ATH79 is not set
+CONFIG_BCMA_POSSIBLE=y
+# CONFIG_BRCMUTIL is not set
 CONFIG_CEVT_R4K=y
 CONFIG_CEVT_R4K_LIB=y
-CONFIG_CFG80211_DEFAULT_PS_VALUE=0
 CONFIG_CPU_BIG_ENDIAN=y
-# CONFIG_CPU_CAVIUM_OCTEON is not set
 CONFIG_CPU_HAS_PREFETCH=y
 CONFIG_CPU_HAS_SYNC=y
-# CONFIG_CPU_LITTLE_ENDIAN is not set
-# CONFIG_CPU_LOONGSON2E is not set
 CONFIG_CPU_MIPS32=y
 # CONFIG_CPU_MIPS32_R1 is not set
 CONFIG_CPU_MIPS32_R2=y
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
 CONFIG_CPU_MIPSR2=y
-# CONFIG_CPU_NEVADA is not set
-# CONFIG_CPU_R10000 is not set
-# CONFIG_CPU_R3000 is not set
-# CONFIG_CPU_R4300 is not set
-# CONFIG_CPU_R4X00 is not set
-# CONFIG_CPU_R5000 is not set
-# CONFIG_CPU_R5432 is not set
-# CONFIG_CPU_R5500 is not set
-# CONFIG_CPU_R6000 is not set
-# CONFIG_CPU_R8000 is not set
-# CONFIG_CPU_RM7000 is not set
-# CONFIG_CPU_RM9000 is not set
-# CONFIG_CPU_SB1 is not set
 CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
 CONFIG_CPU_SUPPORTS_HIGHMEM=y
-# CONFIG_CPU_TX39XX is not set
-# CONFIG_CPU_TX49XX is not set
-# CONFIG_CPU_VR41XX is not set
 CONFIG_CSRC_R4K=y
 CONFIG_CSRC_R4K_LIB=y
 CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DMA_NEED_PCI_MAP_STATE=y
 CONFIG_DMA_NONCOHERENT=y
 CONFIG_EARLY_PRINTK=y
 # CONFIG_FSNOTIFY is not set
+CONFIG_GENERIC_ATOMIC64=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_FIND_LAST_BIT=y
-CONFIG_GENERIC_FIND_NEXT_BIT=y
 CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_GENERIC_IRQ_SHOW=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_HARDWARE_WATCHPOINTS=y
 CONFIG_HAS_DMA=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
 CONFIG_HAVE_ARCH_KGDB=y
 CONFIG_HAVE_CLK=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_GENERIC_HARDIRQS=y
 CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IRQ_WORK=y
 CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_PERF_EVENTS=y
 CONFIG_HW_RANDOM=y
 CONFIG_HZ=250
 # CONFIG_HZ_100 is not set
@@ -74,9 +66,13 @@ CONFIG_IMAGE_CMDLINE_HACK=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_IRQ_CPU=y
 CONFIG_LANTIQ=y
+CONFIG_LANTIQ_MACH_95C3AM1=y
+CONFIG_LANTIQ_MACH_EASY98000=y
+CONFIG_LANTIQ_MACH_EASY98020=y
 CONFIG_LANTIQ_WDT=y
 CONFIG_LEDS_GPIO=y
-# CONFIG_MACH_ALCHEMY is not set
+CONFIG_MACH_NO_WESTBRIDGE=y
+# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set
 CONFIG_MIPS=y
 CONFIG_MIPS_L1_CACHE_SHIFT=5
 CONFIG_MIPS_MACHINE=y
@@ -89,9 +85,15 @@ CONFIG_MTD_CFI_GEOMETRY=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_LANTIQ=y
 CONFIG_MTD_UIMAGE_SPLIT=y
-CONFIG_NLS=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
 CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_PERF_USE_VMALLOC=y
 CONFIG_PHYLIB=y
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_QUOTACTL is not set
+CONFIG_RTL8366RB_PHY=y
+CONFIG_RTL8366_SMI=y
 # CONFIG_SCSI_DMA is not set
 # CONFIG_SERIAL_8250 is not set
 CONFIG_SERIAL_LANTIQ=y
@@ -104,5 +106,5 @@ CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
 CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
 CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
 CONFIG_SYS_SUPPORTS_MULTITHREADING=y
-CONFIG_TREE_RCU=y
+CONFIG_XZ_DEC=y
 CONFIG_ZONE_DMA_FLAG=0
diff --git a/target/linux/lantiq/danube/config-default b/target/linux/lantiq/danube/config-default
index 00ae07fc0c..508706d812 100644
--- a/target/linux/lantiq/danube/config-default
+++ b/target/linux/lantiq/danube/config-default
@@ -27,8 +27,8 @@ CONFIG_LANTIQ_ETOP=y
 CONFIG_LANTIQ_MACH_ARV45XX=y
 CONFIG_LANTIQ_MACH_EASY50712=y
 # CONFIG_LANTIQ_MACH_NETGEAR is not set
-CONFIG_LANTIQ_MACH_GIGASX76X=y
 # CONFIG_LANTIQ_MACH_WBMR is not set
+CONFIG_LANTIQ_MACH_GIGASX76X=y
 CONFIG_MACH_NO_WESTBRIDGE=y
 # CONFIG_MINIX_FS_NATIVE_ENDIAN is not set
 CONFIG_NEED_DMA_MAP_STATE=y
@@ -41,6 +41,7 @@ CONFIG_PERF_USE_VMALLOC=y
 CONFIG_RTL8306_PHY=y
 # CONFIG_SOC_AMAZON_SE is not set
 # CONFIG_SOC_FALCON is not set
+# CONFIG_SOC_VR9 is not set
 CONFIG_SOC_TYPE_XWAY=y
 CONFIG_SOC_XWAY=y
 CONFIG_SPI=y
@@ -50,3 +51,4 @@ CONFIG_SPI_LANTIQ=y
 CONFIG_SPI_MASTER=y
 CONFIG_USB_SUPPORT=y
 CONFIG_XZ_DEC=y
+CONFIG_SPI_XWAY=y
diff --git a/target/linux/lantiq/danube/profiles/002-arcadyan.mk b/target/linux/lantiq/danube/profiles/002-arcadyan.mk
index 509fe07c9c..00cd00b67a 100644
--- a/target/linux/lantiq/danube/profiles/002-arcadyan.mk
+++ b/target/linux/lantiq/danube/profiles/002-arcadyan.mk
@@ -1,6 +1,6 @@
 define Profile/ARV3527P
   NAME:=ARV3527P - Arcor Easybox 401
-  PACKAGES:=kmod-ledtrig-netdev kmod-leds-gpio kmod-button-hotplug kmod-ltq-dsl-firmware-b
+  PACKAGES:=kmod-ledtrig-netdev kmod-leds-gpio kmod-button-hotplug kmod-ltq-dsl-firmware-b-danube
 endef
 
 define Profile/ARV3527P/Description
@@ -13,7 +13,7 @@ define Profile/ARV4510PW
   NAME:=ARV4510PW - Wippies Homebox
   PACKAGES:= kmod-usb-core \
   	kmod-ledtrig-netdev kmod-ledtrig-usbdev kmod-leds-gpio kmod-button-hotplug \
-	kmod-rt61-pci wpad-mini kmod-ltq-dsl-firmware-a
+	kmod-rt61-pci wpad-mini kmod-ltq-dsl-firmware-a-danube
 endef
 
 define Profile/ARV4510PW/Description
@@ -26,7 +26,7 @@ define Profile/ARV4518PW
   NAME:=ARV4518PW - SMC7908A
   PACKAGES:= kmod-usb-core kmod-usb-dwc-otg \
   	kmod-ledtrig-netdev kmod-ledtrig-usbdev kmod-leds-gpio kmod-button-hotplug \
-	kmod-madwifi wpad-mini kmod-ltq-dsl-firmware-a
+	kmod-madwifi wpad-mini kmod-ltq-dsl-firmware-a-danube
 endef
 
 define Profile/ARV4518PW/Description
@@ -39,7 +39,7 @@ define Profile/ARV4520PW
   NAME:=ARV4520PW - Arcor Easybox 800
   PACKAGES:= kmod-usb-core kmod-usb-dwc-otg \
   	kmod-ledtrig-netdev kmod-ledtrig-usbdev kmod-leds-gpio kmod-button-hotplug \
-	kmod-rt61-pci wpad-mini kmod-ltq-dsl-firmware-b 
+	kmod-rt61-pci wpad-mini kmod-ltq-dsl-firmware-b-danube 
 endef
 
 define Profile/ARV4520PW/Description
@@ -52,7 +52,7 @@ define Profile/ARV4525PW
   NAME:=ARV4525PW - Speedport W502V
   PACKAGES:= kmod-usb-core kmod-usb-dwc-otg \
   	kmod-ledtrig-netdev kmod-ledtrig-usbdev kmod-leds-gpio kmod-button-hotplug \
-	kmod-madwifi wpad-mini kmod-ltq-dsl-firmware-b
+	kmod-madwifi wpad-mini kmod-ltq-dsl-firmware-b-danube
 endef
 
 define Profile/ARV4525PW/Description
@@ -65,7 +65,7 @@ define Profile/ARV7525PW
   NAME:=ARV7525PW - Speedport W303V Typ A
   PACKAGES:= kmod-usb-core kmod-usb-dwc-otg \
   	kmod-ledtrig-netdev kmod-ledtrig-usbdev kmod-leds-gpio kmod-button-hotplug \
-	kmod-rt2800-pci wpad-mini kmod-ltq-dsl-firmware-b
+	kmod-rt2800-pci wpad-mini kmod-ltq-dsl-firmware-b-danube
 endef
 
 define Profile/ARV4525PW/Description
@@ -78,7 +78,7 @@ define Profile/ARV452CPW
   NAME:=ARV452CPW - Arcor Easybox 801
   PACKAGES:= kmod-usb-core kmod-usb-dwc-otg \
   	kmod-ledtrig-netdev kmod-ledtrig-usbdev kmod-leds-gpio kmod-button-hotplug \
-	kmod-madwifi wpad-mini kmod-ltq-dsl-firmware-b
+	kmod-madwifi wpad-mini kmod-ltq-dsl-firmware-b-danube
 endef
 
 define Profile/ARV452CPW/Description
@@ -91,7 +91,7 @@ define Profile/ARV752DPW
   NAME:=ARV752DPW - Arcor Easybox 802
   PACKAGES:= kmod-usb-core kmod-usb-dwc-otg \
   	kmod-ledtrig-netdev kmod-ledtrig-usbdev kmod-leds-gpio kmod-button-hotplug \
-	kmod-rt2800-pci kmod-ltq-dsl-firmware-b
+	kmod-rt2800-pci kmod-ltq-dsl-firmware-b-danube
 endef
 
 define Profile/ARV752DPW/Description
@@ -104,7 +104,7 @@ define Profile/ARV752DPW22
   NAME:=ARV752DPW22 - Arcor Easybox 803
   PACKAGES:= kmod-usb-core kmod-usb2 kmod-usb-uhci kmod-usb-dwc-otg \
   	kmod-ledtrig-netdev kmod-ledtrig-usbdev kmod-leds-gpio kmod-button-hotplug \
-	kmod-ltq-dsl-firmware-b
+	kmod-ltq-dsl-firmware-b-danube
 endef
 
 define Profile/ARV752DPW22/Description
diff --git a/target/linux/lantiq/danube/profiles/003-gigaset.mk b/target/linux/lantiq/danube/profiles/003-gigaset.mk
index 844b411890..ee4605a58c 100644
--- a/target/linux/lantiq/danube/profiles/003-gigaset.mk
+++ b/target/linux/lantiq/danube/profiles/003-gigaset.mk
@@ -1,7 +1,7 @@
 define Profile/GIGASX76X
   NAME:=GIGASX76X - Gigaset SX761,SX762,SX763
   PACKAGES:= kmod-usb-core kmod-usb-dwc-otg kmod-leds-gpio \
-	 kmod-ltq-dsl-firmware-b kmod-ledtrig-usbdev 
+	 kmod-ltq-dsl-firmware-b-danube kmod-ledtrig-usbdev 
 endef
 
 define Profile/GIGASX76X/Description
diff --git a/target/linux/lantiq/danube/target.mk b/target/linux/lantiq/danube/target.mk
index 2fa1261848..03fc186754 100644
--- a/target/linux/lantiq/danube/target.mk
+++ b/target/linux/lantiq/danube/target.mk
@@ -3,7 +3,7 @@ SUBTARGET:=danube
 BOARDNAME:=Danube
 FEATURES:=squashfs jffs2 atm
 
-DEFAULT_PACKAGES+=kmod-pppoa ppp-mod-pppoa linux-atm atm-tools br2684ctl kmod-ltq-dsl ltq-dsl-app swconfig
+DEFAULT_PACKAGES+=kmod-pppoa ppp-mod-pppoa linux-atm atm-tools br2684ctl kmod-ltq-dsl-danube ltq-dsl-app swconfig
 
 define Target/Description
 	Lantiq Danube/Twinpass
diff --git a/target/linux/lantiq/falcon/config-3.0 b/target/linux/lantiq/falcon/config-3.0
deleted file mode 100644
index 05049289f1..0000000000
--- a/target/linux/lantiq/falcon/config-3.0
+++ /dev/null
@@ -1,27 +0,0 @@
-CONFIG_CPU_MIPSR2_IRQ_EI=y
-CONFIG_CPU_MIPSR2_IRQ_VI=y
-CONFIG_IFX_VPE_CACHE_SPLIT=y
-CONFIG_IFX_VPE_EXT=y
-CONFIG_M25PXX_USE_FAST_READ=y
-CONFIG_MIPS_MT=y
-# CONFIG_MIPS_VPE_APSP_API is not set
-CONFIG_MIPS_VPE_LOADER=y
-CONFIG_MIPS_VPE_LOADER_TOM=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_NAND_PLATFORM=y
-# CONFIG_MTD_SM_COMMON is not set
-CONFIG_MTSCHED=y
-# CONFIG_PERFCTRS is not set
-# CONFIG_SOC_AMAZON_SE is not set
-CONFIG_SOC_FALCON=y
-# CONFIG_SOC_TYPE_XWAY is not set
-# CONFIG_SOC_XWAY is not set
-CONFIG_SPI=y
-# CONFIG_SPI_BITBANG is not set
-CONFIG_SPI_FALCON=y
-# CONFIG_SPI_GPIO is not set
-CONFIG_SPI_MASTER=y
-# CONFIG_I2C_DESIGNWARE is not set
-
diff --git a/target/linux/lantiq/falcon/config-default b/target/linux/lantiq/falcon/config-default
index 5f864f4ae6..f1d6e482e2 100644
--- a/target/linux/lantiq/falcon/config-default
+++ b/target/linux/lantiq/falcon/config-default
@@ -1,31 +1,8 @@
-# CONFIG_ARCH_DMA_ADDR_T_64BIT is not set
-# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
-# CONFIG_ATH79 is not set
 CONFIG_CPU_MIPSR2_IRQ_EI=y
 CONFIG_CPU_MIPSR2_IRQ_VI=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IRQ_WORK=y
-CONFIG_HAVE_PERF_EVENTS=y
 CONFIG_IFX_VPE_CACHE_SPLIT=y
 CONFIG_IFX_VPE_EXT=y
-CONFIG_LANTIQ_MACH_95C3AM1=y
-CONFIG_LANTIQ_MACH_EASY98000=y
-CONFIG_LANTIQ_MACH_EASY98020=y
 CONFIG_M25PXX_USE_FAST_READ=y
-CONFIG_MACH_NO_WESTBRIDGE=y
-# CONFIG_MFD_MAX8997 is not set
-# CONFIG_MINIX_FS_NATIVE_ENDIAN is not set
 CONFIG_MIPS_MT=y
 # CONFIG_MIPS_VPE_APSP_API is not set
 CONFIG_MIPS_VPE_LOADER=y
@@ -33,24 +10,19 @@ CONFIG_MIPS_VPE_LOADER_TOM=y
 CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ECC=y
-# CONFIG_MTD_NAND_ECC_BCH is not set
 CONFIG_MTD_NAND_PLATFORM=y
 # CONFIG_MTD_SM_COMMON is not set
 CONFIG_MTSCHED=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
 # CONFIG_PERFCTRS is not set
-CONFIG_PERF_USE_VMALLOC=y
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_QUOTACTL is not set
 # CONFIG_SOC_AMAZON_SE is not set
 CONFIG_SOC_FALCON=y
 # CONFIG_SOC_TYPE_XWAY is not set
 # CONFIG_SOC_XWAY is not set
+# CONFIG_SOC_VR9 is not set
 CONFIG_SPI=y
 # CONFIG_SPI_BITBANG is not set
 CONFIG_SPI_FALCON=y
 # CONFIG_SPI_GPIO is not set
 CONFIG_SPI_MASTER=y
-CONFIG_XZ_DEC=y
 # CONFIG_I2C_DESIGNWARE is not set
+
diff --git a/target/linux/lantiq/files-3.0/arch/mips/include/asm/mach-lantiq/dev-leds-gpio.h b/target/linux/lantiq/files-3.0/arch/mips/include/asm/mach-lantiq/dev-leds-gpio.h
new file mode 100644
index 0000000000..099119949a
--- /dev/null
+++ b/target/linux/lantiq/files-3.0/arch/mips/include/asm/mach-lantiq/dev-leds-gpio.h
@@ -0,0 +1,21 @@
+/*
+ *  Lantiq GPIO LED device support
+ *
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef _LANTIQ_DEV_LEDS_GPIO_H
+#define _LANTIQ_DEV_LEDS_GPIO_H
+
+#include <linux/leds.h>
+
+void ltq_add_device_leds_gpio(int id,
+				 unsigned num_leds,
+				 struct gpio_led *leds) __init;
+
+#endif /* _LANTIQ_DEV_LEDS_GPIO_H */
diff --git a/target/linux/lantiq/files-3.0/arch/mips/lantiq/dev-gpio-buttons.c b/target/linux/lantiq/files-3.0/arch/mips/lantiq/dev-gpio-buttons.c
new file mode 100644
index 0000000000..bcc4f58dac
--- /dev/null
+++ b/target/linux/lantiq/files-3.0/arch/mips/lantiq/dev-gpio-buttons.c
@@ -0,0 +1,58 @@
+/*
+ *  Lantiq GPIO button support
+ *
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include "linux/init.h"
+#include "linux/slab.h"
+#include <linux/platform_device.h>
+
+#include "dev-gpio-buttons.h"
+
+void __init ltq_register_gpio_keys_polled(int id,
+					     unsigned poll_interval,
+					     unsigned nbuttons,
+					     struct gpio_keys_button *buttons)
+{
+	struct platform_device *pdev;
+	struct gpio_keys_platform_data pdata;
+	struct gpio_keys_button *p;
+	int err;
+
+	p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL);
+	if (!p)
+		return;
+
+	memcpy(p, buttons, nbuttons * sizeof(*p));
+
+	pdev = platform_device_alloc("gpio-keys-polled", id);
+	if (!pdev)
+		goto err_free_buttons;
+
+	memset(&pdata, 0, sizeof(pdata));
+	pdata.poll_interval = poll_interval;
+	pdata.nbuttons = nbuttons;
+	pdata.buttons = p;
+
+	err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
+	if (err)
+		goto err_put_pdev;
+
+	err = platform_device_add(pdev);
+	if (err)
+		goto err_put_pdev;
+
+	return;
+
+err_put_pdev:
+	platform_device_put(pdev);
+
+err_free_buttons:
+	kfree(p);
+}
diff --git a/target/linux/lantiq/files-3.0/arch/mips/lantiq/dev-gpio-buttons.h b/target/linux/lantiq/files-3.0/arch/mips/lantiq/dev-gpio-buttons.h
new file mode 100644
index 0000000000..adb531c39b
--- /dev/null
+++ b/target/linux/lantiq/files-3.0/arch/mips/lantiq/dev-gpio-buttons.h
@@ -0,0 +1,26 @@
+/*
+ *  Lantiq GPIO button support
+ *
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef _LANTIQ_DEV_GPIO_BUTTONS_H
+#define _LANTIQ_DEV_GPIO_BUTTONS_H
+
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+
+#define LTQ_KEYS_POLL_INTERVAL		20 /* msecs */
+#define LTQ_KEYS_DEBOUNCE_INTERVAL	(3 * LTQ_KEYS_POLL_INTERVAL)
+
+void ltq_register_gpio_keys_polled(int id,
+				      unsigned poll_interval,
+				      unsigned nbuttons,
+				      struct gpio_keys_button *buttons);
+
+#endif /* _LANTIQ_DEV_GPIO_BUTTONS_H */
diff --git a/target/linux/lantiq/files-3.0/arch/mips/lantiq/dev-leds-gpio.c b/target/linux/lantiq/files-3.0/arch/mips/lantiq/dev-leds-gpio.c
new file mode 100644
index 0000000000..8ebd0543fc
--- /dev/null
+++ b/target/linux/lantiq/files-3.0/arch/mips/lantiq/dev-leds-gpio.c
@@ -0,0 +1,57 @@
+/*
+ *  Lantiq GPIO LED device support
+ *
+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  Parts of this file are based on Atheros' 2.6.15 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+
+#include "dev-leds-gpio.h"
+
+void __init ltq_add_device_leds_gpio(int id, unsigned num_leds,
+					struct gpio_led *leds)
+{
+	struct platform_device *pdev;
+	struct gpio_led_platform_data pdata;
+	struct gpio_led *p;
+	int err;
+
+	p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL);
+	if (!p)
+		return;
+
+	memcpy(p, leds, num_leds * sizeof(*p));
+
+	pdev = platform_device_alloc("leds-gpio", id);
+	if (!pdev)
+		goto err_free_leds;
+
+	memset(&pdata, 0, sizeof(pdata));
+	pdata.num_leds = num_leds;
+	pdata.leds = p;
+
+	err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
+	if (err)
+		goto err_put_pdev;
+
+	err = platform_device_add(pdev);
+	if (err)
+		goto err_put_pdev;
+
+	return;
+
+err_put_pdev:
+	platform_device_put(pdev);
+
+err_free_leds:
+	kfree(p);
+}
diff --git a/target/linux/lantiq/files-3.0/arch/mips/lantiq/falcon/addon-easy98000.c b/target/linux/lantiq/files-3.0/arch/mips/lantiq/falcon/addon-easy98000.c
new file mode 100644
index 0000000000..2085a1c77d
--- /dev/null
+++ b/target/linux/lantiq/files-3.0/arch/mips/lantiq/falcon/addon-easy98000.c
@@ -0,0 +1,212 @@
+/*
+ *  EASY98000 CPLD Addon driver
+ *
+ *  Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2  as published
+ *  by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
+
+struct easy98000_reg_cpld {
+	u16 cmdreg1;		/* 0x1 */
+	u16 cmdreg0;		/* 0x0 */
+	u16 idreg0;		/* 0x3 */
+	u16 resreg;		/* 0x2 */
+	u16 intreg;		/* 0x5 */
+	u16 idreg1;		/* 0x4 */
+	u16 ledreg;		/* 0x7 */
+	u16 pcmconconfig;	/* 0x6 */
+	u16 res0;		/* 0x9 */
+	u16 ethledreg;		/* 0x8 */
+	u16 res1[4];		/* 0xa-0xd */
+	u16 cpld1v;		/* 0xf */
+	u16 cpld2v;		/* 0xe */
+};
+static struct easy98000_reg_cpld * const cpld =
+	(struct easy98000_reg_cpld *)(KSEG1 | 0x17c00000);
+#define cpld_r8(reg) (__raw_readw(&cpld->reg) & 0xFF)
+#define cpld_w8(val, reg) __raw_writew((val) & 0xFF, &cpld->reg)
+
+int easy98000_addon_has_dm9000(void)
+{
+	if ((cpld_r8(idreg0) & 0xF) == 1)
+		return 1;
+	return 0;
+}
+
+#if defined(CONFIG_PROC_FS)
+typedef void (*cpld_dump) (struct seq_file *s);
+struct proc_entry {
+	char *name;
+	void *callback;
+};
+
+static int cpld_proc_show ( struct seq_file *s, void *p )
+{
+	cpld_dump dump = s->private;
+
+	if ( dump != NULL )
+		dump(s);
+
+	return 0;
+}
+
+static int cpld_proc_open ( struct inode *inode, struct file *file )
+{
+	return single_open ( file, cpld_proc_show, PDE(inode)->data );
+}
+
+static void cpld_versions_get ( struct seq_file *s )
+{
+	seq_printf(s, "CPLD1: V%d\n", cpld_r8(cpld1v));
+	seq_printf(s, "CPLD2: V%d\n", cpld_r8(cpld2v));
+}
+
+static void cpld_ebu_module_get ( struct seq_file *s )
+{
+	u8 addon_id;
+
+	addon_id = cpld_r8(idreg0) & 0xF;
+	switch (addon_id) {
+	case 0xF: /* nothing connected */
+		break;
+	case 1:
+		seq_printf(s, "Ethernet Controller module (dm9000)\n");
+		break;
+	default:
+		seq_printf(s, "Unknown EBU module (EBU_ID=0x%02X)\n", addon_id);
+		break;
+	}
+}
+
+static void cpld_xmii_module_get ( struct seq_file *s )
+{
+	u8 addon_id;
+	char *mod = NULL;
+
+	addon_id = cpld_r8(idreg1) & 0xF;
+	switch (addon_id) {
+	case 0xF:
+		mod = "no module";
+		break;
+	case 0x1:
+		mod = "RGMII module";
+		break;
+	case 0x4:
+		mod = "GMII MAC Mode (XWAY TANTOS-3G)";
+		break;
+	case 0x6:
+		mod = "TMII MAC Mode (XWAY TANTOS-3G)";
+		break;
+	case 0x8:
+		mod = "GMII PHY module";
+		break;
+	case 0x9:
+		mod = "MII PHY module";
+		break;
+	case 0xA:
+		mod = "RMII PHY module";
+		break;
+	default:
+		break;
+	}
+	if (mod)
+		seq_printf(s, "%s\n", mod);
+	else
+		seq_printf(s, "unknown xMII module (xMII_ID=0x%02X)\n", addon_id);
+}
+
+static struct proc_entry proc_entries[] = {
+	{"versions",	cpld_versions_get},
+	{"ebu",		cpld_ebu_module_get},
+	{"xmii",	cpld_xmii_module_get},
+};
+
+static struct file_operations ops = {
+	.owner   = THIS_MODULE,
+	.open    = cpld_proc_open,
+	.read    = seq_read,
+	.llseek  = seq_lseek,
+	.release = single_release,
+};
+
+static void cpld_proc_entry_create(struct proc_dir_entry *parent_node,
+				   struct proc_entry *proc_entry)
+{
+	proc_create_data ( proc_entry->name, (S_IFREG | S_IRUGO), parent_node,
+			   &ops, proc_entry->callback);
+}
+
+static int cpld_proc_install(void)
+{
+	struct proc_dir_entry *driver_proc_node;
+
+	driver_proc_node = proc_mkdir("cpld", NULL);
+	if (driver_proc_node != NULL) {
+		int i;
+		for (i = 0; i < ARRAY_SIZE(proc_entries); i++)
+			cpld_proc_entry_create(driver_proc_node,
+					      &proc_entries[i]);
+	} else {
+		printk("cannot create proc entry");
+		return -1;
+	}
+	return 0;
+}
+#else
+static inline int cpld_proc_install(void) {}
+#endif
+
+static int easy98000_addon_probe(struct platform_device *pdev)
+{
+	return cpld_proc_install();
+}
+
+static int easy98000_addon_remove(struct platform_device *pdev)
+{
+#if defined(CONFIG_PROC_FS)
+	char buf[64];
+	int i;
+
+	for (i = 0; i < sizeof(proc_entries) / sizeof(proc_entries[0]); i++) {
+		sprintf(buf, "cpld/%s", proc_entries[i].name);
+		remove_proc_entry(buf, 0);
+	}
+	remove_proc_entry("cpld", 0);
+#endif
+	return 0;
+}
+
+static struct platform_driver easy98000_addon_driver = {
+	.probe = easy98000_addon_probe,
+	.remove = __devexit_p(easy98000_addon_remove),
+	.driver = {
+		.name = "easy98000_addon",
+		.owner = THIS_MODULE,
+	},
+};
+
+int __init easy98000_addon_init(void)
+{
+	return platform_driver_register(&easy98000_addon_driver);
+}
+
+void __exit easy98000_addon_exit(void)
+{
+	platform_driver_unregister(&easy98000_addon_driver);
+}
+
+module_init(easy98000_addon_init);
+module_exit(easy98000_addon_exit);
diff --git a/target/linux/lantiq/files-3.0/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.c b/target/linux/lantiq/files-3.0/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.c
new file mode 100644
index 0000000000..d02d2617e0
--- /dev/null
+++ b/target/linux/lantiq/files-3.0/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.c
@@ -0,0 +1,160 @@
+/*
+ *  EASY98000 CPLD LED driver
+ *
+ *  Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2  as published
+ *  by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/errno.h>
+#include <linux/leds.h>
+#include <linux/slab.h>
+
+#include "dev-leds-easy98000-cpld.h"
+
+const char *led_name[8] = {
+	"ge0_act",
+	"ge0_link",
+	"ge1_act",
+	"ge1_link",
+	"fe2_act",
+	"fe2_link",
+	"fe3_act",
+	"fe3_link"
+};
+
+#define cpld_base7			((u16 *)(KSEG1 | 0x17c0000c))
+#define cpld_base8			((u16 *)(KSEG1 | 0x17c00012))
+
+#define ltq_r16(reg)			__raw_readw(reg)
+#define ltq_w16(val, reg)		__raw_writew(val, reg)
+
+struct cpld_led_dev {
+	struct led_classdev	cdev;
+	u8			mask;
+	u16			*base;
+};
+
+struct cpld_led_drvdata {
+	struct cpld_led_dev	*led_devs;
+	int			num_leds;
+};
+
+void led_set(u8 mask, u16 *base)
+{
+	ltq_w16(ltq_r16(base) | mask, base);
+}
+
+void led_clear(u8 mask, u16 *base)
+{
+	ltq_w16(ltq_r16(base) & (~mask), base);
+}
+
+void led_blink_clear(u8 mask, u16 *base)
+{
+	led_clear(mask, base);
+}
+
+static void led_brightness(struct led_classdev *led_cdev,
+			       enum led_brightness value)
+{
+	struct cpld_led_dev *led_dev =
+	    container_of(led_cdev, struct cpld_led_dev, cdev);
+
+	if (value)
+		led_set(led_dev->mask, led_dev->base);
+	else
+		led_clear(led_dev->mask, led_dev->base);
+}
+
+static int led_probe(struct platform_device *pdev)
+{
+	int i;
+	char name[32];
+	struct cpld_led_drvdata *drvdata;
+	int ret = 0;
+
+	drvdata = kzalloc(sizeof(struct cpld_led_drvdata) +
+			  sizeof(struct cpld_led_dev) * MAX_LED,
+			  GFP_KERNEL);
+	if (!drvdata)
+		return -ENOMEM;
+
+	drvdata->led_devs = (struct cpld_led_dev *) &drvdata[1];
+
+	for (i = 0; i < MAX_LED; i++) {
+		struct cpld_led_dev *led_dev = &drvdata->led_devs[i];
+		led_dev->cdev.brightness_set = led_brightness;
+		led_dev->cdev.default_trigger = NULL;
+		led_dev->mask = 1 << (i % 8);
+		if(i < 8) {
+			sprintf(name, "easy98000-cpld:%s", led_name[i]);
+			led_dev->base = cpld_base8;
+		} else {
+			sprintf(name, "easy98000-cpld:red:%d", i-8);
+			led_dev->base = cpld_base7;
+		}
+		led_dev->cdev.name = name;
+		ret = led_classdev_register(&pdev->dev, &led_dev->cdev);
+		if (ret)
+			goto err;
+	}
+	platform_set_drvdata(pdev, drvdata);
+	return 0;
+
+err:
+	printk("led_probe: 3\n");
+	for (i = i - 1; i >= 0; i--)
+		led_classdev_unregister(&drvdata->led_devs[i].cdev);
+
+	kfree(drvdata);
+	return ret;
+}
+
+static int led_remove(struct platform_device *pdev)
+{
+	int i;
+	struct cpld_led_drvdata *drvdata = platform_get_drvdata(pdev);
+	for (i = 0; i < MAX_LED; i++)
+		led_classdev_unregister(&drvdata->led_devs[i].cdev);
+	kfree(drvdata);
+	return 0;
+}
+
+static struct platform_driver led_driver = {
+	.probe = led_probe,
+	.remove = __devexit_p(led_remove),
+	.driver = {
+		   .name = LED_NAME,
+		   .owner = THIS_MODULE,
+		   },
+};
+
+int __init easy98000_cpld_led_init(void)
+{
+	pr_info(LED_DESC ", Version " LED_VERSION
+		" (c) Copyright 2011, Lantiq Deutschland GmbH\n");
+	return platform_driver_register(&led_driver);
+}
+
+void __exit easy98000_cpld_led_exit(void)
+{
+	platform_driver_unregister(&led_driver);
+}
+
+module_init(easy98000_cpld_led_init);
+module_exit(easy98000_cpld_led_exit);
+
+MODULE_DESCRIPTION(LED_NAME);
+MODULE_DESCRIPTION(LED_DESC);
+MODULE_AUTHOR("Ralph Hempel <ralph.hempel@lantiq.com>");
+MODULE_LICENSE("GPL v2");
+
diff --git a/target/linux/lantiq/files-3.0/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.h b/target/linux/lantiq/files-3.0/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.h
new file mode 100644
index 0000000000..3160189fe9
--- /dev/null
+++ b/target/linux/lantiq/files-3.0/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.h
@@ -0,0 +1,20 @@
+/*
+ *  EASY98000 CPLD LED driver
+ *
+ *  Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2  as published
+ *  by the Free Software Foundation.
+ *
+ */
+#ifndef _INCLUDE_EASY98000_CPLD_LED_H_
+#define _INCLUDE_EASY98000_CPLD_LED_H_
+
+#define LED_NAME	"easy98000_cpld_led"
+#define LED_DESC	"EASY98000 LED driver"
+#define LED_VERSION	"1.0.0"
+
+#define MAX_LED		16
+
+#endif	/* _INCLUDE_EASY98000_CPLD_LED_H_ */
diff --git a/target/linux/lantiq/files-3.0/arch/mips/lantiq/falcon/mach-95C3AM1.c b/target/linux/lantiq/files-3.0/arch/mips/lantiq/falcon/mach-95C3AM1.c
new file mode 100644
index 0000000000..f2e91c1a5f
--- /dev/null
+++ b/target/linux/lantiq/files-3.0/arch/mips/lantiq/falcon/mach-95C3AM1.c
@@ -0,0 +1,95 @@
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/i2c-gpio.h>
+#include "../machtypes.h"
+
+#include "devices.h"
+#include "dev-leds-gpio.h"
+
+#define BOARD_95C3AM1_GPIO_LED_0 10
+#define BOARD_95C3AM1_GPIO_LED_1 11
+#define BOARD_95C3AM1_GPIO_LED_2 12
+#define BOARD_95C3AM1_GPIO_LED_3 13
+
+extern unsigned char ltq_ethaddr[6];
+
+static struct mtd_partition board_95C3AM1_partitions[] =
+{
+	{
+		.name	= "uboot",
+		.offset	= 0x0,
+		.size	= 0x40000,
+	},
+	{
+		.name	= "uboot_env",
+		.offset	= 0x40000,
+		.size	= 0x40000,	/* 2 sectors for redundant env. */
+	},
+	{
+		.name	= "linux",
+		.offset	= 0x80000,
+		.size	= 0xF80000,	/* map only 16 MiB */
+	},
+};
+
+static struct flash_platform_data board_95C3AM1_flash_platform_data = {
+	.name = "sflash",
+	.parts = board_95C3AM1_partitions,
+	.nr_parts = ARRAY_SIZE(board_95C3AM1_partitions)
+};
+
+static struct spi_board_info board_95C3AM1_flash_data __initdata = {
+	.modalias		= "m25p80",
+	.bus_num		= 0,
+	.chip_select		= 0,
+	.max_speed_hz		= 10 * 1000 * 1000,
+	.mode			= SPI_MODE_3,
+	.platform_data		= &board_95C3AM1_flash_platform_data
+};
+
+static struct gpio_led board_95C3AM1_leds_gpio[] __initdata = {
+	{
+		.name		= "power",
+		.gpio		= BOARD_95C3AM1_GPIO_LED_0,
+		.active_low	= 0,
+	}, {
+		.name		= "optical",
+		.gpio		= BOARD_95C3AM1_GPIO_LED_1,
+		.active_low	= 0,
+	}, {
+		.name		= "lan",
+		.gpio		= BOARD_95C3AM1_GPIO_LED_2,
+		.active_low	= 0,
+	}, {
+		.name		= "update",
+		.gpio		= BOARD_95C3AM1_GPIO_LED_3,
+		.active_low	= 0,
+	}
+};
+
+static struct i2c_gpio_platform_data board_95C3AM1_i2c_gpio_data = {
+	.sda_pin	= 107,
+	.scl_pin	= 108,
+};
+
+static struct platform_device board_95C3AM1_i2c_gpio_device = {
+	.name		= "i2c-gpio",
+	.id		= 0,
+	.dev = {
+		.platform_data	= &board_95C3AM1_i2c_gpio_data,
+	}
+};
+
+static void __init board_95C3AM1_init(void)
+{
+	falcon_register_i2c();
+	falcon_register_spi_flash(&board_95C3AM1_flash_data);
+	platform_device_register(&board_95C3AM1_i2c_gpio_device);
+	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(board_95C3AM1_leds_gpio),
+						board_95C3AM1_leds_gpio);
+}
+
+MIPS_MACHINE(LANTIQ_MACH_95C3AM1,
+			"95C3AM1",
+			"95C3AM1 Board",
+			board_95C3AM1_init);
diff --git a/target/linux/lantiq/files-3.0/arch/mips/lantiq/falcon/mach-easy98020.c b/target/linux/lantiq/files-3.0/arch/mips/lantiq/falcon/mach-easy98020.c
new file mode 100644
index 0000000000..30e24dea94
--- /dev/null
+++ b/target/linux/lantiq/files-3.0/arch/mips/lantiq/falcon/mach-easy98020.c
@@ -0,0 +1,119 @@
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/gpio_buttons.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+
+#include "../machtypes.h"
+#include "devices.h"
+#include "dev-leds-gpio.h"
+
+#define EASY98020_GPIO_LED_0 9
+#define EASY98020_GPIO_LED_1 10
+#define EASY98020_GPIO_LED_2 11
+#define EASY98020_GPIO_LED_3 12
+#define EASY98020_GPIO_LED_GE0_ACT 110
+#define EASY98020_GPIO_LED_GE0_LINK 109
+#define EASY98020_GPIO_LED_GE1_ACT 106
+#define EASY98020_GPIO_LED_GE1_LINK 105
+
+extern unsigned char ltq_ethaddr[6];
+
+static struct mtd_partition easy98020_spi_partitions[] =
+{
+	{
+		.name	= "uboot",
+		.offset	= 0x0,
+		.size	= 0x40000,
+	},
+	{
+		.name	= "uboot_env",
+		.offset	= 0x40000,
+		.size	= 0x40000,	/* 2 sectors for redundant env. */
+	},
+	{
+		.name	= "linux",
+		.offset	= 0x80000,
+		.size	= 0xF80000,	/* map only 16 MiB */
+	},
+};
+
+static struct flash_platform_data easy98020_spi_flash_platform_data = {
+	.name = "sflash",
+	.parts = easy98020_spi_partitions,
+	.nr_parts = ARRAY_SIZE(easy98020_spi_partitions)
+};
+
+static struct spi_board_info easy98020_spi_flash_data __initdata = {
+	.modalias		= "m25p80",
+	.bus_num		= 0,
+	.chip_select		= 0,
+	.max_speed_hz		= 10 * 1000 * 1000,
+	.mode			= SPI_MODE_3,
+	.platform_data		= &easy98020_spi_flash_platform_data
+};
+
+static struct gpio_led easy98020_leds_gpio[] __initdata = {
+	{
+		.name		= "easy98020:green:0",
+		.gpio		= EASY98020_GPIO_LED_0,
+		.active_low	= 0,
+	}, {
+		.name		= "easy98020:green:1",
+		.gpio		= EASY98020_GPIO_LED_1,
+		.active_low	= 0,
+	}, {
+		.name		= "easy98020:green:2",
+		.gpio		= EASY98020_GPIO_LED_2,
+		.active_low	= 0,
+	}, {
+		.name		= "easy98020:green:3",
+		.gpio		= EASY98020_GPIO_LED_3,
+		.active_low	= 0,
+	}, {
+		.name		= "easy98020:ge0_act",
+		.gpio		= EASY98020_GPIO_LED_GE0_ACT,
+		.active_low	= 0,
+	}, {
+		.name		= "easy98020:ge0_link",
+		.gpio		= EASY98020_GPIO_LED_GE0_LINK,
+		.active_low	= 0,
+	}, {
+		.name		= "easy98020:ge1_act",
+		.gpio		= EASY98020_GPIO_LED_GE1_ACT,
+		.active_low	= 0,
+	}, {
+		.name		= "easy98020:ge1_link",
+		.gpio		= EASY98020_GPIO_LED_GE1_LINK,
+		.active_low	= 0,
+	}
+};
+
+static void __init easy98020_init(void)
+{
+	falcon_register_i2c();
+	falcon_register_spi_flash(&easy98020_spi_flash_data);
+	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(easy98020_leds_gpio),
+					easy98020_leds_gpio);
+}
+
+MIPS_MACHINE(LANTIQ_MACH_EASY98020,
+			"EASY98020",
+			"EASY98020 Eval Board",
+			easy98020_init);
+
+MIPS_MACHINE(LANTIQ_MACH_EASY98020_1LAN,
+			"EASY98020_1LAN",
+			"EASY98020 Eval Board (1 LAN port)",
+			easy98020_init);
+
+MIPS_MACHINE(LANTIQ_MACH_EASY98020_2LAN,
+			"EASY98020_2LAN",
+			"EASY98020 Eval Board (2 LAN ports)",
+			easy98020_init);
diff --git a/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/dev-dwc_otg.c b/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/dev-dwc_otg.c
new file mode 100644
index 0000000000..90b63fc72d
--- /dev/null
+++ b/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/dev-dwc_otg.c
@@ -0,0 +1,70 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/mtd/physmap.h>
+#include <linux/kernel.h>
+#include <linux/reboot.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/etherdevice.h>
+#include <linux/reboot.h>
+#include <linux/time.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+
+#include <lantiq_soc.h>
+#include <lantiq_irq.h>
+#include <lantiq_platform.h>
+
+#define LTQ_USB_IOMEM_BASE 0x1e101000
+#define LTQ_USB_IOMEM_SIZE 0x00001000
+
+static struct resource resources[] =
+{
+	[0] = {
+		.name    = "dwc_otg_membase",
+		.start   = LTQ_USB_IOMEM_BASE,
+		.end	 = LTQ_USB_IOMEM_BASE + LTQ_USB_IOMEM_SIZE - 1,
+		.flags	 = IORESOURCE_MEM,
+	},
+	[1] = {
+		.name    = "dwc_otg_irq",
+		.start   = LTQ_USB_INT,
+		.flags   = IORESOURCE_IRQ,
+	},
+};
+
+static u64 dwc_dmamask = (u32)0x1fffffff;
+
+static struct platform_device platform_dev = {
+	.name = "dwc_otg",
+	.dev = {
+		.dma_mask      = &dwc_dmamask,
+	},
+	.resource		= resources,
+	.num_resources		= ARRAY_SIZE(resources),
+};
+
+int __init
+xway_register_dwc(int pin)
+{
+	struct irq_data d;
+	d.irq = resources[1].start;
+	ltq_enable_irq(&d);
+	platform_dev.dev.platform_data = (void*) pin;
+	return platform_device_register(&platform_dev);
+}
diff --git a/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/dev-dwc_otg.h b/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/dev-dwc_otg.h
new file mode 100644
index 0000000000..521fad05ef
--- /dev/null
+++ b/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/dev-dwc_otg.h
@@ -0,0 +1,17 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef _LTQ_DEV_DWC_H__
+#define _LTQ_DEV_DWC_H__
+
+#include <lantiq_platform.h>
+
+extern void __init xway_register_dwc(int pin);
+
+#endif
diff --git a/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/mach-arv45xx.c b/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/mach-arv45xx.c
new file mode 100644
index 0000000000..7cd2bd81f8
--- /dev/null
+++ b/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/mach-arv45xx.c
@@ -0,0 +1,495 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/gpio_buttons.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/input.h>
+#include <linux/etherdevice.h>
+#include <linux/ath5k_platform.h>
+#include <linux/pci.h>
+
+#include <lantiq_soc.h>
+#include <lantiq_platform.h>
+
+#include "../machtypes.h"
+#include "../dev-leds-gpio.h"
+#include "devices.h"
+#include "dev-dwc_otg.h"
+
+static struct mtd_partition arv4510_partitions[] =
+{
+	{
+		.name	= "uboot",
+		.offset	= 0x0,
+		.size	= 0x20000,
+	},
+	{
+		.name	= "uboot_env",
+		.offset	= 0x20000,
+		.size	= 0x120000,
+	},
+	{
+		.name	= "linux",
+		.offset	= 0x40000,
+		.size	= 0xfa0000,
+	},
+	{
+		.name	= "board_config",
+		.offset	= 0xfe0000,
+		.size	= 0x20000,
+	},
+};
+
+static struct mtd_partition arv45xx_partitions[] =
+{
+	{
+		.name	= "uboot",
+		.offset	= 0x0,
+		.size	= 0x20000,
+	},
+	{
+		.name	= "uboot_env",
+		.offset	= 0x20000,
+		.size	= 0x10000,
+	},
+	{
+		.name	= "linux",
+		.offset	= 0x30000,
+		.size	= 0x3c0000,
+	},
+	{
+		.name	= "board_config",
+		.offset	= 0x3f0000,
+		.size	= 0x10000,
+	},
+};
+
+static struct mtd_partition arv75xx_partitions[] =
+{
+	{
+		.name	= "uboot",
+		.offset	= 0x0,
+		.size	= 0x10000,
+	},
+	{
+		.name	= "uboot_env",
+		.offset	= 0x10000,
+		.size	= 0x10000,
+	},
+	{
+		.name	= "linux",
+		.offset	= 0x20000,
+		.size	= 0x7d0000,
+	},
+	{
+		.name	= "board_config",
+		.offset	= 0x7f0000,
+		.size	= 0x10000,
+	},
+};
+
+static struct physmap_flash_data arv4510_flash_data = {
+	.nr_parts	= ARRAY_SIZE(arv4510_partitions),
+	.parts		= arv4510_partitions,
+};
+
+static struct physmap_flash_data arv45xx_flash_data = {
+	.nr_parts	= ARRAY_SIZE(arv45xx_partitions),
+	.parts		= arv45xx_partitions,
+};
+
+static struct physmap_flash_data arv75xx_flash_data = {
+	.nr_parts	= ARRAY_SIZE(arv75xx_partitions),
+	.parts		= arv75xx_partitions,
+};
+
+static struct ltq_pci_data ltq_pci_data = {
+	.clock  = PCI_CLOCK_EXT,
+	.gpio   = PCI_GNT1 | PCI_REQ1,
+	.irq    = {
+		[14] = INT_NUM_IM0_IRL0 + 22,
+	},
+};
+
+static struct ltq_eth_data ltq_eth_data = {
+	.mii_mode	= PHY_INTERFACE_MODE_RMII,
+};
+
+static struct gpio_led
+arv4510pw_leds_gpio[] __initdata = {
+	{ .name = "soc:green:foo", .gpio = 4, .active_low = 1, },
+};
+
+static struct gpio_led
+arv4518pw_leds_gpio[] __initdata = {
+	{ .name = "soc:green:power", .gpio = 3, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:green:adsl", .gpio = 4, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:green:internet", .gpio = 5, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:green:wlan", .gpio = 6, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:yellow:wps", .gpio = 7, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:red:fail", .gpio = 8, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:green:usb", .gpio = 19, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:green:voip", .gpio = 100, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:green:fxs1", .gpio = 101, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:green:fxs2", .gpio = 102, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:green:fxo", .gpio = 103, .active_low = 1, .default_trigger = "default-on" },
+};
+
+static struct gpio_button
+arv4518pw_gpio_buttons[] __initdata = {
+	{ .desc = "wlan", .type = EV_KEY, .code = BTN_0, .threshold = 3, .gpio = 28, .active_low = 1, },
+	{ .desc = "wps", .type = EV_KEY, .code = BTN_1, .threshold = 3, .gpio = 29, .active_low = 1, },
+	{ .desc = "reset", .type = EV_KEY, .code = BTN_2, .threshold = 3, .gpio = 30, .active_low = 1, },
+};
+
+static struct gpio_led
+arv4520pw_leds_gpio[] __initdata = {
+	{ .name = "soc:blue:power", .gpio = 3, .active_low = 1, },
+	{ .name = "soc:blue:adsl", .gpio = 4, .active_low = 1, },
+	{ .name = "soc:blue:internet", .gpio = 5, .active_low = 1, },
+	{ .name = "soc:red:power", .gpio = 6, .active_low = 1, },
+	{ .name = "soc:yellow:wps", .gpio = 7, .active_low = 1, },
+	{ .name = "soc:red:wps", .gpio = 9, .active_low = 1, },
+	{ .name = "soc:blue:voip", .gpio = 100, .active_low = 1, },
+	{ .name = "soc:blue:fxs1", .gpio = 101, .active_low = 1, },
+	{ .name = "soc:blue:fxs2", .gpio = 102, .active_low = 1, },
+	{ .name = "soc:blue:fxo", .gpio = 103, .active_low = 1, },
+	{ .name = "soc:blue:voice", .gpio = 104, .active_low = 1, },
+	{ .name = "soc:blue:usb", .gpio = 105, .active_low = 1, },
+	{ .name = "soc:blue:wlan", .gpio = 106, .active_low = 1, },
+};
+
+static struct gpio_led
+arv452cpw_leds_gpio[] __initdata = {
+	{ .name = "soc:blue:power", .gpio = 3, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:blue:adsl", .gpio = 4, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:blue:isdn", .gpio = 5, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:red:power", .gpio = 6, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:yellow:wps", .gpio = 7, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:red:wps", .gpio = 9, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:blue:fxs1", .gpio = 100, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:blue:fxs2", .gpio = 101, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:blue:wps", .gpio = 102, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:blue:fxo", .gpio = 103, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:blue:voice", .gpio = 104, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:blue:usb", .gpio = 105, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:blue:wlan", .gpio = 106, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:blue:internet", .gpio = 108, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:red:internet", .gpio = 109, .active_low = 1, .default_trigger = "default-on" },
+};
+
+static struct gpio_led
+arv4525pw_leds_gpio[] __initdata = {
+	{ .name = "soc:green:festnetz", .gpio = 4, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:green:internet", .gpio = 5, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:green:dsl", .gpio = 6, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:green:wlan", .gpio = 8, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:green:online", .gpio = 9, .active_low = 1, .default_trigger = "default-on" },
+};
+
+static struct gpio_led
+arv752dpw22_leds_gpio[] __initdata = {
+	{ .name = "soc:blue:power", .gpio = 3, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:red:internet", .gpio = 5, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:red:power", .gpio = 6, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:red:wps", .gpio = 8, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:red:fxo", .gpio = 103, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:red:voice", .gpio = 104, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:green:usb", .gpio = 105, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:green:wlan", .gpio = 106, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:green:wlan1", .gpio = 107, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:blue:wlan", .gpio = 108, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:blue:wlan1", .gpio = 109, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:green:eth1", .gpio = 111, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:green:eth2", .gpio = 112, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:green:eth3", .gpio = 113, .active_low = 1, .default_trigger = "default-on" },
+	{ .name = "soc:green:eth4", .gpio = 114, .active_low = 1, .default_trigger = "default-on", },
+};
+
+static struct gpio_button
+arv752dpw22_gpio_buttons[] __initdata = {
+	{ .desc = "btn0", .type = EV_KEY, .code = BTN_0, .threshold = 3, .gpio = 12, .active_low = 1, },
+	{ .desc = "btn1", .type = EV_KEY, .code = BTN_1, .threshold = 3, .gpio = 13, .active_low = 1, },
+	{ .desc = "btn2", .type = EV_KEY, .code = BTN_2, .threshold = 3, .gpio = 28, .active_low = 1, },
+};
+
+static struct gpio_led
+arv7518pw_leds_gpio[] __initdata = {
+	{ .name = "soc:green:power", .gpio = 2, .active_low = 1, },
+	{ .name = "soc:green:adsl", .gpio = 4, .active_low = 1, },
+	{ .name = "soc:green:internet", .gpio = 5, .active_low = 1, },
+	{ .name = "soc:green:wlan", .gpio = 6, .active_low = 1, },
+	{ .name = "soc:red:internet", .gpio = 8, .active_low = 1, },
+	{ .name = "soc:green:usb", .gpio = 19, .active_low = 1, },
+};
+
+static struct gpio_button
+arv7518pw_gpio_buttons[] __initdata = {
+	{ .desc = "reset", .type = EV_KEY, .code = BTN_0, .threshold = 3, .gpio = 23, .active_low = 1, },
+	{ .desc = "wlan", .type = EV_KEY, .code = BTN_1, .threshold = 3, .gpio = 25, .active_low = 1, },
+};
+
+static void
+arv45xx_register_ethernet(void)
+{
+#define ARV45XX_BRN_MAC			0x3f0016
+	memcpy_fromio(&ltq_eth_data.mac.sa_data,
+		(void *)KSEG1ADDR(LTQ_FLASH_START + ARV45XX_BRN_MAC), 6);
+	ltq_register_etop(&ltq_eth_data);
+}
+
+static void
+arv75xx_register_ethernet(void)
+{
+#define ARV75XX_BRN_MAC			0x7f0016
+	memcpy_fromio(&ltq_eth_data.mac.sa_data,
+		(void *)KSEG1ADDR(LTQ_FLASH_START + ARV75XX_BRN_MAC), 6);
+	ltq_register_etop(&ltq_eth_data);
+}
+
+static void
+bewan_register_ethernet(void)
+{
+#define BEWAN_BRN_MAC			0x3f0014
+	memcpy_fromio(&ltq_eth_data.mac.sa_data,
+		(void *)KSEG1ADDR(LTQ_FLASH_START + BEWAN_BRN_MAC), 6);
+	ltq_register_etop(&ltq_eth_data);
+}
+
+static u16 arv45xx_ath5k_eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS];
+static struct ath5k_platform_data arv45xx_ath5k_platform_data;
+
+/*static int arv45xx_pci_plat_dev_init(struct pci_dev *dev)
+{
+	dev->dev.platform_data = &arv45xx_ath5k_platform_data;
+	return 0;
+}
+*/
+void __init
+arv45xx_register_ath5k(void)
+{
+#define ARV45XX_BRN_ATH		0x3f0478
+	int i;
+	unsigned char eeprom_mac[6];
+	static u16 eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS];
+	u32 *p = (u32*)arv45xx_ath5k_eeprom_data;
+
+	memcpy_fromio(eeprom_mac,
+		(void *)KSEG1ADDR(LTQ_FLASH_START + ARV45XX_BRN_MAC), 6);
+	eeprom_mac[5]++;
+	memcpy_fromio(arv45xx_ath5k_eeprom_data,
+		(void *)KSEG1ADDR(LTQ_FLASH_START + ARV45XX_BRN_ATH), ATH5K_PLAT_EEP_MAX_WORDS);
+	// swap eeprom bytes
+	for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS>>1; i++){
+		//arv4518_ath5k_eeprom_data[i] = ((eeprom_data[i]&0xff)<<8)|((eeprom_data[i]&0xff00)>>8);
+		p[i] = ((eeprom_data[(i<<1)+1]&0xff)<<24)|((eeprom_data[(i<<1)+1]&0xff00)<<8)|((eeprom_data[i<<1]&0xff)<<8)|((eeprom_data[i<<1]&0xff00)>>8);
+		if (i == 0xbf>>1){
+			// printk ("regdomain: 0x%x --> 0x%x\n", p[i], (p[i] & 0xffff0000)|0x67);
+			/* regdomain is invalid?? how did original fw convert 
+			* value to 0x82d4 ??
+			* for now, force to 0x67 */
+			p[i] &= 0xffff0000;
+			p[i] |= 0x67;
+		}
+	}
+	arv45xx_ath5k_platform_data.eeprom_data = arv45xx_ath5k_eeprom_data;
+	arv45xx_ath5k_platform_data.macaddr = eeprom_mac;
+	//lqpci_plat_dev_init = arv45xx_pci_plat_dev_init;
+}
+
+static void __init
+arv3527p_init(void)
+{
+	ltq_register_gpio_stp();
+	//ltq_add_device_leds_gpio(arv3527p_leds_gpio, ARRAY_SIZE(arv3527p_leds_gpio));
+	ltq_register_nor(&arv45xx_flash_data);
+	arv45xx_register_ethernet();
+}
+
+MIPS_MACHINE(LANTIQ_MACH_ARV3527P,
+			"ARV3527P",
+			"ARV3527P - Arcor Easybox 401",
+			arv3527p_init);
+
+static void __init
+arv4510pw_init(void)
+{
+	ltq_register_gpio_stp();
+	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(arv4510pw_leds_gpio), arv4510pw_leds_gpio);
+	ltq_register_nor(&arv4510_flash_data);
+	ltq_pci_data.irq[12] = (INT_NUM_IM2_IRL0 + 31);
+	ltq_pci_data.irq[15] = (INT_NUM_IM0_IRL0 + 26);
+	ltq_pci_data.gpio |= PCI_EXIN2 | PCI_REQ2;
+	ltq_register_pci(&ltq_pci_data);
+	bewan_register_ethernet();
+}
+
+MIPS_MACHINE(LANTIQ_MACH_ARV4510PW,
+			"ARV4510PW",
+			"ARV4510PW - Wippies Homebox",
+			arv4510pw_init);
+
+static void __init
+arv4518pw_init(void)
+{
+#define ARV4518PW_EBU			0
+#define ARV4518PW_USB			14
+#define ARV4518PW_SWITCH_RESET		13
+
+	ltq_register_gpio_ebu(ARV4518PW_EBU);
+	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(arv4518pw_leds_gpio), arv4518pw_leds_gpio);
+	ltq_register_gpio_buttons(arv4518pw_gpio_buttons, ARRAY_SIZE(arv4518pw_gpio_buttons));
+	ltq_register_nor(&arv45xx_flash_data);
+	ltq_pci_data.gpio = PCI_GNT2 | PCI_REQ2;
+	ltq_register_pci(&ltq_pci_data);
+	ltq_register_madwifi_eep();
+	xway_register_dwc(ARV4518PW_USB);
+	arv45xx_register_ethernet();
+	arv45xx_register_ath5k();
+
+	gpio_request(ARV4518PW_SWITCH_RESET, "switch");
+	gpio_direction_output(ARV4518PW_SWITCH_RESET, 1);
+	gpio_export(ARV4518PW_SWITCH_RESET, 0);
+}
+
+MIPS_MACHINE(LANTIQ_MACH_ARV4518PW,
+			"ARV4518PW",
+			"ARV4518PW - SMC7908A-ISP, Airties WAV-221",
+			arv4518pw_init);
+
+static void __init
+arv4520pw_init(void)
+{
+#define ARV4520PW_EBU			0x400
+#define ARV4520PW_USB			28
+#define ARV4520PW_SWITCH_RESET		110
+
+	ltq_register_gpio_ebu(ARV4520PW_EBU);
+	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(arv4520pw_leds_gpio), arv4520pw_leds_gpio);
+	ltq_register_nor(&arv45xx_flash_data);
+	ltq_register_pci(&ltq_pci_data);
+	ltq_register_tapi();
+	arv45xx_register_ethernet();
+	xway_register_dwc(ARV4520PW_USB);
+
+	gpio_request(ARV4520PW_SWITCH_RESET, "switch");
+	gpio_set_value(ARV4520PW_SWITCH_RESET, 1);
+}
+
+MIPS_MACHINE(LANTIQ_MACH_ARV4520PW,
+			"ARV4520PW",
+			"ARV4520PW - Airties WAV-281, Arcor A800",
+			arv4520pw_init);
+
+static void __init
+arv452Cpw_init(void)
+{
+#define ARV452CPW_EBU			0x77f
+#define ARV452CPW_USB			28
+#define ARV452CPW_RELAY1		31
+#define ARV452CPW_RELAY2		107
+#define ARV452CPW_SWITCH_RESET		110
+
+	ltq_register_gpio_ebu(ARV452CPW_EBU);
+	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(arv452cpw_leds_gpio), arv452cpw_leds_gpio);
+	ltq_register_nor(&arv45xx_flash_data);
+	ltq_register_pci(&ltq_pci_data);
+	ltq_register_madwifi_eep();
+	xway_register_dwc(ARV452CPW_USB);
+	arv45xx_register_ethernet();
+	arv45xx_register_ath5k();
+
+	gpio_request(ARV452CPW_SWITCH_RESET, "switch");
+	gpio_set_value(ARV452CPW_SWITCH_RESET, 1);
+	gpio_export(ARV452CPW_SWITCH_RESET, 0);
+
+	gpio_request(ARV452CPW_RELAY1, "relay1");
+	gpio_direction_output(ARV452CPW_RELAY1, 1);
+	gpio_export(ARV452CPW_RELAY1, 0);
+
+	gpio_request(ARV452CPW_RELAY2, "relay2");
+	gpio_set_value(ARV452CPW_RELAY2, 1);
+	gpio_export(ARV452CPW_RELAY2, 0);
+}
+
+MIPS_MACHINE(LANTIQ_MACH_ARV452CPW,
+			"ARV452CPW",
+			"ARV452CPW - Arcor A801",
+			arv452Cpw_init);
+
+static void __init
+arv4525pw_init(void)
+{
+	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(arv4525pw_leds_gpio), arv4525pw_leds_gpio);
+	ltq_register_nor(&arv45xx_flash_data);
+	ltq_pci_data.clock = PCI_CLOCK_INT;
+	ltq_register_pci(&ltq_pci_data);
+	ltq_register_madwifi_eep();
+	ltq_eth_data.mii_mode = PHY_INTERFACE_MODE_MII;
+	arv45xx_register_ethernet();
+}
+
+MIPS_MACHINE(LANTIQ_MACH_ARV4525PW,
+			"ARV4525PW",
+			"ARV4525PW - Speedport W502V",
+			arv4525pw_init);
+
+static void __init
+arv7518pw_init(void)
+{
+#define ARV7518PW_EBU			0x2
+#define ARV7518PW_USB			14
+
+	ltq_register_gpio_ebu(ARV7518PW_EBU);
+	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(arv7518pw_leds_gpio), arv7518pw_leds_gpio);
+	ltq_register_gpio_buttons(arv7518pw_gpio_buttons, ARRAY_SIZE(arv7518pw_gpio_buttons));
+	ltq_register_nor(&arv75xx_flash_data);
+	ltq_register_pci(&ltq_pci_data);
+	ltq_register_tapi();
+	xway_register_dwc(ARV7518PW_USB);
+	arv75xx_register_ethernet();
+	//arv7518_register_ath9k(mac);
+}
+
+MIPS_MACHINE(LANTIQ_MACH_ARV7518PW,
+			"ARV7518PW",
+			"ARV7518PW - ASTORIA",
+			arv7518pw_init);
+
+static void __init
+arv752dpw22_init(void)
+{
+#define ARV752DPW22_EBU			0x2
+#define ARV752DPW22_USB			100
+#define ARV752DPW22_RELAY		101
+
+	ltq_register_gpio_ebu(ARV752DPW22_EBU);
+	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(arv752dpw22_leds_gpio), arv752dpw22_leds_gpio);
+	ltq_register_gpio_buttons(arv752dpw22_gpio_buttons, ARRAY_SIZE(arv752dpw22_gpio_buttons));
+	ltq_register_nor(&arv75xx_flash_data);
+	ltq_pci_data.irq[15] = (INT_NUM_IM3_IRL0 + 31);
+	ltq_pci_data.gpio |= PCI_EXIN1 | PCI_REQ2;
+	ltq_register_pci(&ltq_pci_data);
+	xway_register_dwc(ARV752DPW22_USB);
+	arv75xx_register_ethernet();
+
+	gpio_request(ARV752DPW22_RELAY, "relay");
+	gpio_set_value(ARV752DPW22_RELAY, 1);
+	gpio_export(ARV752DPW22_RELAY, 0);
+}
+
+MIPS_MACHINE(LANTIQ_MACH_ARV752DPW22,
+			"ARV752DPW22",
+			"ARV752DPW22 - Arcor A803",
+			arv752dpw22_init);
diff --git a/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/mach-easy50601.c b/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/mach-easy50601.c
new file mode 100644
index 0000000000..a5a01057a3
--- /dev/null
+++ b/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/mach-easy50601.c
@@ -0,0 +1,57 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/input.h>
+
+#include <lantiq.h>
+
+#include "../machtypes.h"
+#include "devices.h"
+
+static struct mtd_partition easy50601_partitions[] = {
+	{
+		.name	= "uboot",
+		.offset	= 0x0,
+		.size	= 0x10000,
+	},
+	{
+		.name	= "uboot_env",
+		.offset	= 0x10000,
+		.size	= 0x10000,
+	},
+	{
+		.name	= "linux",
+		.offset	= 0x20000,
+		.size	= 0x3d0000,
+	},
+};
+
+static struct physmap_flash_data easy50601_flash_data = {
+	.nr_parts	= ARRAY_SIZE(easy50601_partitions),
+	.parts		= easy50601_partitions,
+};
+
+static struct ltq_eth_data ltq_eth_data = {
+	.mii_mode = -1, /* use EPHY */
+};
+
+static void __init easy50601_init(void)
+{
+	ltq_register_nor(&easy50601_flash_data);
+	ltq_register_etop(&ltq_eth_data);
+}
+
+MIPS_MACHINE(LTQ_MACH_EASY50601,
+			"EASY50601",
+			"EASY50601 Eval Board",
+			easy50601_init);
diff --git a/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/mach-easy50712.c b/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/mach-easy50712.c
new file mode 100644
index 0000000000..2fddfca6db
--- /dev/null
+++ b/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/mach-easy50712.c
@@ -0,0 +1,70 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/input.h>
+#include <linux/phy.h>
+
+#include <lantiq_soc.h>
+#include <irq.h>
+
+#include "../machtypes.h"
+#include "devices.h"
+
+static struct mtd_partition easy50712_partitions[] = {
+	{
+		.name	= "uboot",
+		.offset	= 0x0,
+		.size	= 0x10000,
+	},
+	{
+		.name	= "uboot_env",
+		.offset	= 0x10000,
+		.size	= 0x10000,
+	},
+	{
+		.name	= "linux",
+		.offset	= 0x20000,
+		.size	= 0x3d0000,
+	},
+};
+
+static struct physmap_flash_data easy50712_flash_data = {
+	.nr_parts	= ARRAY_SIZE(easy50712_partitions),
+	.parts		= easy50712_partitions,
+};
+
+static struct ltq_pci_data ltq_pci_data = {
+	.clock	= PCI_CLOCK_INT,
+	.gpio	= PCI_GNT1 | PCI_REQ1,
+	.irq	= {
+		[14] = INT_NUM_IM0_IRL0 + 22,
+	},
+};
+
+static struct ltq_eth_data ltq_eth_data = {
+	.mii_mode = PHY_INTERFACE_MODE_MII,
+};
+
+static void __init easy50712_init(void)
+{
+	ltq_register_gpio_stp();
+	ltq_register_nor(&easy50712_flash_data);
+	ltq_register_pci(&ltq_pci_data);
+	ltq_register_etop(&ltq_eth_data);
+	ltq_register_tapi();
+}
+
+MIPS_MACHINE(LTQ_MACH_EASY50712,
+	     "EASY50712",
+	     "EASY50712 Eval Board",
+	      easy50712_init);
diff --git a/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/mach-fritz.c b/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/mach-fritz.c
new file mode 100644
index 0000000000..9b542425c8
--- /dev/null
+++ b/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/mach-fritz.c
@@ -0,0 +1,77 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/input.h>
+#include <linux/phy.h>
+
+#include <lantiq_soc.h>
+#include <irq.h>
+
+#include "../machtypes.h"
+#include "devices.h"
+
+/*static struct mtd_partition fritz3370_partitions[] = {
+	{
+		.name	= "uboot",
+		.offset	= 0x0,
+		.size	= 0x10000,
+	},
+	{
+		.name	= "uboot_env",
+		.offset	= 0x10000,
+		.size	= 0x10000,
+	},
+	{
+		.name	= "linux",
+		.offset	= 0x20000,
+		.size	= 0xe0000,
+	},
+	{
+		.name	= "rootfs",
+		.offset	= 0x100000,
+		.size	= 0x300000,
+	},
+};
+
+static struct physmap_flash_data fritz3370_flash_data = {
+	.nr_parts	= ARRAY_SIZE(fritz3370_partitions),
+	.parts		= fritz3370_partitions,
+};
+
+static struct ltq_pci_data ltq_pci_data = {
+	.clock	= PCI_CLOCK_INT,
+	.gpio	= PCI_GNT1 | PCI_REQ1,
+	.irq	= {
+		[14] = INT_NUM_IM0_IRL0 + 22,
+	},
+};
+*/
+static struct ltq_eth_data ltq_eth_data = {
+	.mii_mode = PHY_INTERFACE_MODE_MII,
+};
+
+extern void xway_register_nand(void);
+
+static void __init fritz3370_init(void)
+{
+//	ltq_register_gpio_stp();
+//	ltq_register_nor(&fritz3370_flash_data);
+//	ltq_register_pci(&ltq_pci_data);
+	ltq_register_etop(&ltq_eth_data);
+	xway_register_nand();
+}
+
+MIPS_MACHINE(LANTIQ_MACH_FRITZ3370,
+	     "FRITZ3370",
+	     "FRITZ!BOX 3370",
+	      fritz3370_init);
diff --git a/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/mach-gigasx76x.c b/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/mach-gigasx76x.c
new file mode 100644
index 0000000000..ab2b08c7ef
--- /dev/null
+++ b/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/mach-gigasx76x.c
@@ -0,0 +1,109 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2011 Andrej Vlašić
+ *  Copyright (C) 2011 Luka Perkov
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/gpio_buttons.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/input.h>
+#include <linux/ath5k_platform.h>
+#include <linux/pci.h>
+#include <linux/phy.h>
+
+#include <irq.h>
+
+#include <lantiq_soc.h>
+#include <lantiq_platform.h>
+
+#include "../machtypes.h"
+#include "../dev-leds-gpio.h"
+#include "devices.h"
+#include "dev-dwc_otg.h"
+
+static struct mtd_partition gigasx76x_partitions[] =
+{
+	{
+		.name	= "secondary_env",
+		.offset	= 0xe000,
+		.size	= 0x2000,
+	},
+	{
+		.name	= "secondary_boot",
+		.offset	= 0x10000,
+		.size	= 0x10000,
+	},
+	{
+		.name	= "uboot",
+		.offset	= 0x20000,
+		.size	= 0x30000,
+	},
+	{
+		.name	= "linux",
+		.offset	= 0x50000,
+		.size	= 0x7a0000,
+	},
+	{
+		.name	= "board_config",
+		.offset	= 0x7f0000,
+		.size	= 0x10000,
+	},
+};
+
+static struct gpio_led
+gigasx76x_leds_gpio[] __initdata = {
+	{ .name = "soc:green:usb", .gpio = 202, },
+	{ .name = "soc:green:wlan", .gpio = 203, },
+	{ .name = "soc:green:phone2", .gpio = 204, },
+	{ .name = "soc:green:phone1", .gpio = 205, },
+	{ .name = "soc:green:line", .gpio = 206, },
+	{ .name = "soc:green:online", .gpio = 207, },
+};
+
+
+static struct physmap_flash_data gigasx76x_flash_data = {
+	.nr_parts	= ARRAY_SIZE(gigasx76x_partitions),
+	.parts		= gigasx76x_partitions,
+};
+
+static struct ltq_pci_data ltq_pci_data = {
+	.clock      = PCI_CLOCK_INT,
+	.gpio   = PCI_GNT1 | PCI_REQ1,
+	.irq    = {
+		[14] = INT_NUM_IM0_IRL0 + 22,
+	},
+};
+
+static struct ltq_eth_data ltq_eth_data = {
+  .mii_mode = PHY_INTERFACE_MODE_MII,
+};
+
+static void __init
+gigasx76x_init(void)
+{
+#define GIGASX76X_USB			29
+
+	ltq_register_gpio_stp();
+	ltq_register_nor(&gigasx76x_flash_data);
+	ltq_register_pci(&ltq_pci_data);
+	ltq_register_etop(&ltq_eth_data);
+	xway_register_dwc(GIGASX76X_USB);
+	ltq_register_tapi();
+	ltq_register_madwifi_eep();
+	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(gigasx76x_leds_gpio), gigasx76x_leds_gpio);
+}
+
+MIPS_MACHINE(LANTIQ_MACH_GIGASX76X,
+			"GIGASX76X",
+			"GIGASX76X - Gigaset SX761,SX762,SX763",
+			gigasx76x_init);
diff --git a/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/mach-netgear.c b/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/mach-netgear.c
new file mode 100644
index 0000000000..826bfe2bcd
--- /dev/null
+++ b/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/mach-netgear.c
@@ -0,0 +1,57 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/input.h>
+#include <linux/phy.h>
+#include <linux/spi/spi.h>
+
+#include <lantiq_soc.h>
+#include <irq.h>
+
+#include "../machtypes.h"
+#include "devices.h"
+
+static struct ltq_pci_data ltq_pci_data = {
+	.clock	= PCI_CLOCK_INT,
+	.gpio	= PCI_GNT1 | PCI_REQ1,
+	.irq	= {
+		[14] = INT_NUM_IM0_IRL0 + 22,
+	},
+};
+
+static struct ltq_eth_data ltq_eth_data = {
+	.mii_mode = PHY_INTERFACE_MODE_MII,
+};
+
+struct spi_board_info spi_info = {
+	.bus_num        = 0,
+	.chip_select    = 3,
+	.max_speed_hz   = 25000000,
+	.modalias       = "mx25l12805d",
+};
+
+struct ltq_spi_platform_data ltq_spi_data = {
+	.num_chipselect = 4,
+};
+
+static void __init dgn3500_init(void)
+{
+	ltq_register_pci(&ltq_pci_data);
+	ltq_register_etop(&ltq_eth_data);
+	ltq_register_spi(&ltq_spi_data, &spi_info, 1);
+}
+
+MIPS_MACHINE(LANTIQ_MACH_DGN3500B,
+	     "DGN3500B",
+	     "Netgear DGN3500B",
+	      dgn3500_init);
diff --git a/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/mach-wbmr.c b/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/mach-wbmr.c
new file mode 100644
index 0000000000..141a5b7c47
--- /dev/null
+++ b/target/linux/lantiq/files-3.0/arch/mips/lantiq/xway/mach-wbmr.c
@@ -0,0 +1,120 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/gpio_buttons.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/input.h>
+
+#include <lantiq_soc.h>
+#include <irq.h>
+
+#include "../machtypes.h"
+#include "../dev-leds-gpio.h"
+#include "../dev-gpio-buttons.h"
+#include "devices.h"
+#include "dev-dwc_otg.h"
+
+static struct mtd_partition wbmr_partitions[] =
+{
+	{
+		.name	= "uboot",
+		.offset	= 0x0,
+		.size	= 0x40000,
+	},
+	{
+		.name	= "uboot-env",
+		.offset	= 0x40000,
+		.size	= 0x20000,
+	},
+	{
+		.name	= "linux",
+		.offset	= 0x60000,
+		.size	= 0x1f20000,
+	},
+	{
+		.name	= "calibration",
+		.offset	= 0x1fe0000,
+		.size	= 0x20000,
+	},
+};
+
+static struct physmap_flash_data wbmr_flash_data = {
+	.nr_parts	= ARRAY_SIZE(wbmr_partitions),
+	.parts		= wbmr_partitions,
+};
+
+static struct gpio_led
+wbmr_leds_gpio[] __initdata = {
+	{ .name = "soc:blue:movie", .gpio = 20, .active_low = 1, },
+	{ .name = "soc:red:internet", .gpio = 18, .active_low = 1, },
+	{ .name = "soc:green:internet", .gpio = 17, .active_low = 1, },
+	{ .name = "soc:green:adsl", .gpio = 16, .active_low = 1, },
+	{ .name = "soc:green:wlan", .gpio = 15, .active_low = 1, },
+	{ .name = "soc:red:security", .gpio = 14, .active_low = 1, },
+	{ .name = "soc:green:power", .gpio = 1, .active_low = 1, },
+	{ .name = "soc:red:power", .gpio = 5, .active_low = 1, },
+	{ .name = "soc:green:usb", .gpio = 28, .active_low = 1, },
+};
+
+static struct gpio_keys_button
+wbmr_gpio_keys[] __initdata = {
+	{
+		.desc = "aoss",
+		.type = EV_KEY,
+		.code = BTN_0,
+		.debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL,
+		.gpio = 0,
+		.active_low = 1,
+	},
+	{
+		.desc = "reset",
+		.type = EV_KEY,
+		.code = BTN_1,
+		.debounce_interval = LTQ_KEYS_DEBOUNCE_INTERVAL,
+		.gpio = 37,
+		.active_low = 1,
+	},
+};
+
+static struct ltq_pci_data ltq_pci_data = {
+	.clock      = PCI_CLOCK_INT,
+	.gpio   = PCI_GNT1 | PCI_REQ1,
+	.irq    = {
+		[14] = INT_NUM_IM0_IRL0 + 22,
+	},
+};
+
+static struct ltq_eth_data ltq_eth_data = {
+	.mii_mode = PHY_INTERFACE_MODE_RGMII,
+};
+
+static void __init
+wbmr_init(void)
+{
+#define WMBR_BRN_MAC			0x1fd0024
+
+	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(wbmr_leds_gpio), wbmr_leds_gpio);
+	ltq_register_gpio_keys_polled(-1, LTQ_KEYS_POLL_INTERVAL, ARRAY_SIZE(wbmr_gpio_keys), wbmr_gpio_keys);
+	ltq_register_nor(&wbmr_flash_data);
+	ltq_register_pci(&ltq_pci_data);
+	memcpy_fromio(&ltq_eth_data.mac.sa_data,
+		(void *)KSEG1ADDR(LTQ_FLASH_START + WMBR_BRN_MAC), 6);
+	ltq_register_etop(&ltq_eth_data);
+	xway_register_dwc(36);
+}
+
+MIPS_MACHINE(LANTIQ_MACH_WBMR,
+			"WBMR",
+			"WBMR",
+			wbmr_init);
diff --git a/target/linux/lantiq/modules.mk b/target/linux/lantiq/modules.mk
index 0d4ad2da1c..b0db10e2c7 100644
--- a/target/linux/lantiq/modules.mk
+++ b/target/linux/lantiq/modules.mk
@@ -29,7 +29,7 @@ USB_MENU:=USB Support
 define KernelPackage/usb-dwc-otg
   TITLE:=Synopsis DWC_OTG support
   SUBMENU:=$(USB_MENU)
-  DEPENDS+=@TARGET_lantiq_danube +kmod-usb-core
+  DEPENDS+=@(TARGET_lantiq_danube||TARGET_lantiq_ar9||TARGET_lantiq_vr9) +kmod-usb-core
   KCONFIG:=CONFIG_DWC_OTG \
   	CONFIG_DWC_OTG_DEBUG=n \
 	CONFIG_DWC_OTG_LANTIQ=y \
@@ -51,7 +51,7 @@ I2C_FALCON_MODULES:= \
 define KernelPackage/i2c-falcon-lantiq
   TITLE:=Falcon I2C controller
   $(call i2c_defaults,$(I2C_FALCON_MODULES),52)
-  DEPENDS:=kmod-i2c-core @TARGET_lantiq
+  DEPENDS:=kmod-i2c-core @(TARGET_lantiq_falcon||TARGET_lantiq_falcon_stable)
 endef
 
 define KernelPackage/i2c-falcon-lantiq/description
diff --git a/target/linux/lantiq/patches-3.0/000-gpio_fix.patch b/target/linux/lantiq/patches-3.0/000-gpio_fix.patch
deleted file mode 100644
index 6295f78990..0000000000
--- a/target/linux/lantiq/patches-3.0/000-gpio_fix.patch
+++ /dev/null
@@ -1,20 +0,0 @@
---- a/arch/mips/lantiq/xway/gpio_ebu.c
-+++ b/arch/mips/lantiq/xway/gpio_ebu.c
-@@ -63,7 +63,6 @@ static struct gpio_chip ltq_ebu_chip = {
- 	.set = ltq_ebu_set,
- 	.base = 72,
- 	.ngpio = 16,
--	.can_sleep = 1,
- 	.owner = THIS_MODULE,
- };
- 
---- a/arch/mips/lantiq/xway/gpio_stp.c
-+++ b/arch/mips/lantiq/xway/gpio_stp.c
-@@ -72,7 +72,6 @@ static struct gpio_chip ltq_stp_chip = {
- 	.set = ltq_stp_set,
- 	.base = 48,
- 	.ngpio = 24,
--	.can_sleep = 1,
- 	.owner = THIS_MODULE,
- };
- 
diff --git a/target/linux/lantiq/patches-3.0/0001-MIPS-lantiq-fix-early-printk.patch b/target/linux/lantiq/patches-3.0/0001-MIPS-lantiq-fix-early-printk.patch
new file mode 100644
index 0000000000..2671360f93
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/0001-MIPS-lantiq-fix-early-printk.patch
@@ -0,0 +1,67 @@
+From 91f8d0c8fbb9ea70bf78a291e312157177be8ee3 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sat, 20 Aug 2011 18:55:13 +0200
+Subject: [PATCH 01/24] MIPS: lantiq: fix early printk
+
+The code was using a 32bit write operation in the early_printk code. This
+resulted in 3 zero bytes also being written to the serial port. Change the
+memory access to 8bit.
+
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Cc: linux-mips@linux-mips.org
+---
+ .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |    4 ++++
+ arch/mips/lantiq/early_printk.c                    |   14 ++++++++------
+ 2 files changed, 12 insertions(+), 6 deletions(-)
+
+diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+index 8a3c6be..e6d1ca0 100644
+--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+@@ -34,6 +34,10 @@
+ #define LTQ_ASC1_BASE_ADDR	0x1E100C00
+ #define LTQ_ASC_SIZE		0x400
+ 
++/* during early_printk no ioremap is possible
++   lets use KSEG1 instead  */
++#define LTQ_EARLY_ASC		KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
++
+ /* RCU - reset control unit */
+ #define LTQ_RCU_BASE_ADDR	0x1F203000
+ #define LTQ_RCU_SIZE		0x1000
+diff --git a/arch/mips/lantiq/early_printk.c b/arch/mips/lantiq/early_printk.c
+index 972e05f..5089075 100644
+--- a/arch/mips/lantiq/early_printk.c
++++ b/arch/mips/lantiq/early_printk.c
+@@ -12,11 +12,13 @@
+ #include <lantiq.h>
+ #include <lantiq_soc.h>
+ 
+-/* no ioremap possible at this early stage, lets use KSEG1 instead  */
+-#define LTQ_ASC_BASE	KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
+ #define ASC_BUF		1024
+-#define LTQ_ASC_FSTAT	((u32 *)(LTQ_ASC_BASE + 0x0048))
+-#define LTQ_ASC_TBUF	((u32 *)(LTQ_ASC_BASE + 0x0020))
++#define LTQ_ASC_FSTAT	((u32 *)(LTQ_EARLY_ASC + 0x0048))
++#ifdef __BIG_ENDIAN
++#define LTQ_ASC_TBUF	((u32 *)(LTQ_EARLY_ASC + 0x0020 + 3))
++#else
++#define LTQ_ASC_TBUF	((u32 *)(LTQ_EARLY_ASC + 0x0020))
++#endif
+ #define TXMASK		0x3F00
+ #define TXOFFSET	8
+ 
+@@ -27,7 +29,7 @@ void prom_putchar(char c)
+ 	local_irq_save(flags);
+ 	do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET);
+ 	if (c == '\n')
+-		ltq_w32('\r', LTQ_ASC_TBUF);
+-	ltq_w32(c, LTQ_ASC_TBUF);
++		ltq_w8('\r', LTQ_ASC_TBUF);
++	ltq_w8(c, LTQ_ASC_TBUF);
+ 	local_irq_restore(flags);
+ }
+-- 
+1.7.5.4
+
diff --git a/target/linux/lantiq/patches-3.0/0002-MIPS-lantiq-fix-cmdline-parsing.patch b/target/linux/lantiq/patches-3.0/0002-MIPS-lantiq-fix-cmdline-parsing.patch
new file mode 100644
index 0000000000..680a8dcd38
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/0002-MIPS-lantiq-fix-cmdline-parsing.patch
@@ -0,0 +1,37 @@
+From b85d5204f2fe8c3b5e6172f7cc1741ad6e849334 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 12 Aug 2011 16:27:38 +0200
+Subject: [PATCH 02/24] MIPS: lantiq: fix cmdline parsing
+
+The code tested if the KSEG1 mapped address of argv was != 0. We need to use
+CPHYSADDR instead to make the conditional actually work.
+
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Cc: linux-mips@linux-mips.org
+---
+ arch/mips/lantiq/prom.c |    6 ++++--
+ 1 files changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
+index 56ba007..5035c10 100644
+--- a/arch/mips/lantiq/prom.c
++++ b/arch/mips/lantiq/prom.c
+@@ -45,10 +45,12 @@ static void __init prom_init_cmdline(void)
+ 	char **argv = (char **) KSEG1ADDR(fw_arg1);
+ 	int i;
+ 
++	arcs_cmdline[0] = '\0';
++
+ 	for (i = 0; i < argc; i++) {
+-		char *p = (char *)  KSEG1ADDR(argv[i]);
++		char *p = (char *) KSEG1ADDR(argv[i]);
+ 
+-		if (p && *p) {
++		if (CPHYSADDR(p) && *p) {
+ 			strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
+ 			strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
+ 		}
+-- 
+1.7.5.4
+
diff --git a/target/linux/lantiq/patches-3.0/991-fix-wdt-timeout.patch b/target/linux/lantiq/patches-3.0/0003-MIPS-lantiq-fix-watchdogs-timeout-handling.patch
index 32e82cfb5f..5d0061acaa 100644
--- a/target/linux/lantiq/patches-3.0/991-fix-wdt-timeout.patch
+++ b/target/linux/lantiq/patches-3.0/0003-MIPS-lantiq-fix-watchdogs-timeout-handling.patch
@@ -1,7 +1,7 @@
 From 14ea48a5f5702ddc97425cbe520600e187e14e4a Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Thu, 11 Aug 2011 13:58:39 +0200
-Subject: [PATCH 03/16] MIPS: lantiq: fix watchdogs timeout handling
+Subject: [PATCH 03/24] MIPS: lantiq: fix watchdogs timeout handling
 
 The enable function was using the global timeout variable for local operations.
 This resulted in the value of the global variable being corrupted, thus
@@ -15,6 +15,8 @@ Cc: linux-mips@linux-mips.org
  drivers/watchdog/lantiq_wdt.c |    8 ++++----
  1 files changed, 4 insertions(+), 4 deletions(-)
 
+diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c
+index 7d82ada..102aed0 100644
 --- a/drivers/watchdog/lantiq_wdt.c
 +++ b/drivers/watchdog/lantiq_wdt.c
 @@ -51,16 +51,16 @@ static int ltq_wdt_ok_to_close;
@@ -38,3 +40,6 @@ Cc: linux-mips@linux-mips.org
  }
  
  static void
+-- 
+1.7.5.4
+
diff --git a/target/linux/lantiq/patches-3.0/0004-MIPS-lantiq-reorganize-xway-code.patch b/target/linux/lantiq/patches-3.0/0004-MIPS-lantiq-reorganize-xway-code.patch
new file mode 100644
index 0000000000..a847bee218
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/0004-MIPS-lantiq-reorganize-xway-code.patch
@@ -0,0 +1,883 @@
+From d90739a8962b541969b4c5f7ef1df8fec9c7f153 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 10 Aug 2011 14:57:04 +0200
+Subject: [PATCH 04/24] MIPS: lantiq: reorganize xway code
+
+Inside the folder arch/mips/lantiq/xway, there were alot of small files with
+lots of duplicated code. This patch adds a wrapper function for inserting and
+requesting resources and unifies the small files into one bigger file.
+
+This patch makes the xway code consistent with the falcon support added later
+in this series.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Cc: linux-mips@linux-mips.org
+---
+ arch/mips/include/asm/mach-lantiq/lantiq.h         |   14 +---
+ .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |   14 ++++
+ arch/mips/lantiq/clk.c                             |   25 +------
+ arch/mips/lantiq/devices.c                         |   30 ++------
+ arch/mips/lantiq/devices.h                         |    4 +
+ arch/mips/lantiq/prom.c                            |   50 +++++++++++--
+ arch/mips/lantiq/prom.h                            |    4 +
+ arch/mips/lantiq/xway/Makefile                     |    6 +-
+ arch/mips/lantiq/xway/devices.c                    |   42 ++---------
+ arch/mips/lantiq/xway/dma.c                        |   21 ++----
+ arch/mips/lantiq/xway/ebu.c                        |   53 --------------
+ arch/mips/lantiq/xway/pmu.c                        |   70 ------------------
+ arch/mips/lantiq/xway/prom-ase.c                   |    9 +++
+ arch/mips/lantiq/xway/prom-xway.c                  |   10 +++
+ arch/mips/lantiq/xway/reset.c                      |   21 ++----
+ arch/mips/lantiq/xway/setup-ase.c                  |   19 -----
+ arch/mips/lantiq/xway/setup-xway.c                 |   20 -----
+ arch/mips/lantiq/xway/sysctrl.c                    |   77 ++++++++++++++++++++
+ drivers/watchdog/lantiq_wdt.c                      |    2 +-
+ 19 files changed, 197 insertions(+), 294 deletions(-)
+ delete mode 100644 arch/mips/lantiq/xway/ebu.c
+ delete mode 100644 arch/mips/lantiq/xway/pmu.c
+ delete mode 100644 arch/mips/lantiq/xway/setup-ase.c
+ delete mode 100644 arch/mips/lantiq/xway/setup-xway.c
+ create mode 100644 arch/mips/lantiq/xway/sysctrl.c
+
+diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
+index ce2f029..66d7300 100644
+--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
++++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
+@@ -9,6 +9,7 @@
+ #define _LANTIQ_H__
+ 
+ #include <linux/irq.h>
++#include <linux/ioport.h>
+ 
+ /* generic reg access functions */
+ #define ltq_r32(reg)		__raw_readl(reg)
+@@ -18,15 +19,6 @@
+ #define ltq_r8(reg)		__raw_readb(reg)
+ #define ltq_w8(val, reg)	__raw_writeb(val, reg)
+ 
+-/* register access macros for EBU and CGU */
+-#define ltq_ebu_w32(x, y)	ltq_w32((x), ltq_ebu_membase + (y))
+-#define ltq_ebu_r32(x)		ltq_r32(ltq_ebu_membase + (x))
+-#define ltq_cgu_w32(x, y)	ltq_w32((x), ltq_cgu_membase + (y))
+-#define ltq_cgu_r32(x)		ltq_r32(ltq_cgu_membase + (x))
+-
+-extern __iomem void *ltq_ebu_membase;
+-extern __iomem void *ltq_cgu_membase;
+-
+ extern unsigned int ltq_get_cpu_ver(void);
+ extern unsigned int ltq_get_soc_type(void);
+ 
+@@ -51,7 +43,9 @@ extern void ltq_enable_irq(struct irq_data *data);
+ 
+ /* find out what caused the last cpu reset */
+ extern int ltq_reset_cause(void);
+-#define LTQ_RST_CAUSE_WDTRST	0x20
++
++/* helper for requesting and remapping resources */
++extern void __iomem *ltq_remap_resource(struct resource *res);
+ 
+ #define IOPORT_RESOURCE_START	0x10000000
+ #define IOPORT_RESOURCE_END	0xffffffff
+diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+index e6d1ca0..da8ff95 100644
+--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+@@ -65,6 +65,8 @@
+ #define LTQ_CGU_BASE_ADDR	0x1F103000
+ #define LTQ_CGU_SIZE		0x1000
+ 
++#define CGU_EPHY		0x10
++
+ /* ICU - interrupt control unit */
+ #define LTQ_ICU_BASE_ADDR	0x1F880200
+ #define LTQ_ICU_SIZE		0x100
+@@ -101,6 +103,8 @@
+ #define LTQ_WDT_BASE_ADDR	0x1F8803F0
+ #define LTQ_WDT_SIZE		0x10
+ 
++#define LTQ_RST_CAUSE_WDTRST	0x20
++
+ /* STP - serial to parallel conversion unit */
+ #define LTQ_STP_BASE_ADDR	0x1E100BB0
+ #define LTQ_STP_SIZE		0x40
+@@ -125,11 +129,21 @@
+ #define LTQ_MPS_BASE_ADDR	(KSEG1 + 0x1F107000)
+ #define LTQ_MPS_CHIPID		((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
+ 
++/* register access macros for EBU and CGU */
++#define ltq_ebu_w32(x, y)	ltq_w32((x), ltq_ebu_membase + (y))
++#define ltq_ebu_r32(x)		ltq_r32(ltq_ebu_membase + (x))
++#define ltq_cgu_w32(x, y)	ltq_w32((x), ltq_cgu_membase + (y))
++#define ltq_cgu_r32(x)		ltq_r32(ltq_cgu_membase + (x))
++
++extern __iomem void *ltq_ebu_membase;
++extern __iomem void *ltq_cgu_membase;
++
+ /* request a non-gpio and set the PIO config */
+ extern int  ltq_gpio_request(unsigned int pin, unsigned int alt0,
+ 	unsigned int alt1, unsigned int dir, const char *name);
+ extern void ltq_pmu_enable(unsigned int module);
+ extern void ltq_pmu_disable(unsigned int module);
++extern void ltq_cgu_enable(unsigned int clk);
+ 
+ static inline int ltq_is_ar9(void)
+ {
+diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c
+index 7e9c0ff..4254f08 100644
+--- a/arch/mips/lantiq/clk.c
++++ b/arch/mips/lantiq/clk.c
+@@ -22,6 +22,7 @@
+ #include <lantiq_soc.h>
+ 
+ #include "clk.h"
++#include "prom.h"
+ 
+ struct clk {
+ 	const char *name;
+@@ -46,16 +47,6 @@ static struct clk cpu_clk_generic[] = {
+ 	},
+ };
+ 
+-static struct resource ltq_cgu_resource = {
+-	.name	= "cgu",
+-	.start	= LTQ_CGU_BASE_ADDR,
+-	.end	= LTQ_CGU_BASE_ADDR + LTQ_CGU_SIZE - 1,
+-	.flags	= IORESOURCE_MEM,
+-};
+-
+-/* remapped clock register range */
+-void __iomem *ltq_cgu_membase;
+-
+ void clk_init(void)
+ {
+ 	cpu_clk = cpu_clk_generic;
+@@ -133,21 +124,11 @@ void __init plat_time_init(void)
+ {
+ 	struct clk *clk;
+ 
+-	if (insert_resource(&iomem_resource, &ltq_cgu_resource) < 0)
+-		panic("Failed to insert cgu memory\n");
+-
+-	if (request_mem_region(ltq_cgu_resource.start,
+-			resource_size(&ltq_cgu_resource), "cgu") < 0)
+-		panic("Failed to request cgu memory\n");
++	ltq_soc_init();
+ 
+-	ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start,
+-				resource_size(&ltq_cgu_resource));
+-	if (!ltq_cgu_membase) {
+-		pr_err("Failed to remap cgu memory\n");
+-		unreachable();
+-	}
+ 	clk = clk_get(0, "cpu");
+ 	mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution();
+ 	write_c0_compare(read_c0_count());
++	pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
+ 	clk_put(clk);
+ }
+diff --git a/arch/mips/lantiq/devices.c b/arch/mips/lantiq/devices.c
+index 44a3677..81c7aab 100644
+--- a/arch/mips/lantiq/devices.c
++++ b/arch/mips/lantiq/devices.c
+@@ -27,12 +27,8 @@
+ #include "devices.h"
+ 
+ /* nor flash */
+-static struct resource ltq_nor_resource = {
+-	.name	= "nor",
+-	.start	= LTQ_FLASH_START,
+-	.end	= LTQ_FLASH_START + LTQ_FLASH_MAX - 1,
+-	.flags  = IORESOURCE_MEM,
+-};
++static struct resource ltq_nor_resource =
++	MEM_RES("nor", LTQ_FLASH_START, LTQ_FLASH_MAX);
+ 
+ static struct platform_device ltq_nor = {
+ 	.name		= "ltq_nor",
+@@ -47,12 +43,8 @@ void __init ltq_register_nor(struct physmap_flash_data *data)
+ }
+ 
+ /* watchdog */
+-static struct resource ltq_wdt_resource = {
+-	.name	= "watchdog",
+-	.start  = LTQ_WDT_BASE_ADDR,
+-	.end    = LTQ_WDT_BASE_ADDR + LTQ_WDT_SIZE - 1,
+-	.flags  = IORESOURCE_MEM,
+-};
++static struct resource ltq_wdt_resource =
++	MEM_RES("watchdog", LTQ_WDT_BASE_ADDR, LTQ_WDT_SIZE);
+ 
+ void __init ltq_register_wdt(void)
+ {
+@@ -61,24 +53,14 @@ void __init ltq_register_wdt(void)
+ 
+ /* asc ports */
+ static struct resource ltq_asc0_resources[] = {
+-	{
+-		.name	= "asc0",
+-		.start  = LTQ_ASC0_BASE_ADDR,
+-		.end    = LTQ_ASC0_BASE_ADDR + LTQ_ASC_SIZE - 1,
+-		.flags  = IORESOURCE_MEM,
+-	},
++	MEM_RES("asc0", LTQ_ASC0_BASE_ADDR, LTQ_ASC_SIZE),
+ 	IRQ_RES(tx, LTQ_ASC_TIR(0)),
+ 	IRQ_RES(rx, LTQ_ASC_RIR(0)),
+ 	IRQ_RES(err, LTQ_ASC_EIR(0)),
+ };
+ 
+ static struct resource ltq_asc1_resources[] = {
+-	{
+-		.name	= "asc1",
+-		.start  = LTQ_ASC1_BASE_ADDR,
+-		.end    = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1,
+-		.flags  = IORESOURCE_MEM,
+-	},
++	MEM_RES("asc1", LTQ_ASC1_BASE_ADDR, LTQ_ASC_SIZE),
+ 	IRQ_RES(tx, LTQ_ASC_TIR(1)),
+ 	IRQ_RES(rx, LTQ_ASC_RIR(1)),
+ 	IRQ_RES(err, LTQ_ASC_EIR(1)),
+diff --git a/arch/mips/lantiq/devices.h b/arch/mips/lantiq/devices.h
+index 2947bb1..a03c23f 100644
+--- a/arch/mips/lantiq/devices.h
++++ b/arch/mips/lantiq/devices.h
+@@ -14,6 +14,10 @@
+ 
+ #define IRQ_RES(resname, irq) \
+ 	{.name = #resname, .start = (irq), .flags = IORESOURCE_IRQ}
++#define MEM_RES(resname, adr_start, adr_size) \
++	{ .name = resname, .flags = IORESOURCE_MEM, \
++	  .start = ((adr_start) & ~KSEG1), \
++	  .end = ((adr_start + adr_size - 1) & ~KSEG1) }
+ 
+ extern void ltq_register_nor(struct physmap_flash_data *data);
+ extern void ltq_register_wdt(void);
+diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
+index 5035c10..fead2cc 100644
+--- a/arch/mips/lantiq/prom.c
++++ b/arch/mips/lantiq/prom.c
+@@ -16,6 +16,10 @@
+ #include "prom.h"
+ #include "clk.h"
+ 
++/* access to the ebu needs to be locked between different drivers */
++DEFINE_SPINLOCK(ebu_lock);
++EXPORT_SYMBOL_GPL(ebu_lock);
++
+ static struct ltq_soc_info soc_info;
+ 
+ unsigned int ltq_get_cpu_ver(void)
+@@ -57,16 +61,50 @@ static void __init prom_init_cmdline(void)
+ 	}
+ }
+ 
+-void __init prom_init(void)
++void __iomem *ltq_remap_resource(struct resource *res)
+ {
+-	struct clk *clk;
++	__iomem void *ret = NULL;
++	struct resource *lookup = lookup_resource(&iomem_resource, res->start);
++
++	if (lookup && strcmp(lookup->name, res->name)) {
++		panic("conflicting memory range %s\n", res->name);
++		return NULL;
++	}
++	if (!lookup) {
++		if (insert_resource(&iomem_resource, res) < 0) {
++			panic("Failed to insert %s memory\n", res->name);
++			return NULL;
++		}
++	}
++	if (request_mem_region(res->start,
++			resource_size(res), res->name) < 0) {
++		panic("Failed to request %s memory\n", res->name);
++		goto err_res;
++	}
+ 
++	ret = ioremap_nocache(res->start, resource_size(res));
++	if (!ret)
++		goto err_mem;
++
++	pr_debug("remap: 0x%08X-0x%08X : \"%s\"\n",
++		res->start, res->end, res->name);
++	return ret;
++
++err_mem:
++	panic("Failed to remap %s memory\n", res->name);
++	release_mem_region(res->start, resource_size(res));
++
++err_res:
++	release_resource(res);
++	return NULL;
++}
++
++void __init prom_init(void)
++{
+ 	ltq_soc_detect(&soc_info);
+ 	clk_init();
+-	clk = clk_get(0, "cpu");
+-	snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev1.%d",
+-		soc_info.name, soc_info.rev);
+-	clk_put(clk);
++	snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s",
++		soc_info.name, soc_info.rev_type);
+ 	soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
+ 	pr_info("SoC: %s\n", soc_info.sys_type);
+ 	prom_init_cmdline();
+diff --git a/arch/mips/lantiq/prom.h b/arch/mips/lantiq/prom.h
+index b4229d9..51dba1b 100644
+--- a/arch/mips/lantiq/prom.h
++++ b/arch/mips/lantiq/prom.h
+@@ -9,17 +9,21 @@
+ #ifndef _LTQ_PROM_H__
+ #define _LTQ_PROM_H__
+ 
++#define LTQ_SYS_REV_LEN		0x10
+ #define LTQ_SYS_TYPE_LEN	0x100
+ 
+ struct ltq_soc_info {
+ 	unsigned char *name;
+ 	unsigned int rev;
++	unsigned char rev_type[LTQ_SYS_REV_LEN];
++	unsigned int srev;
+ 	unsigned int partnum;
+ 	unsigned int type;
+ 	unsigned char sys_type[LTQ_SYS_TYPE_LEN];
+ };
+ 
+ extern void ltq_soc_detect(struct ltq_soc_info *i);
++extern void ltq_soc_init(void);
+ extern void ltq_soc_setup(void);
+ 
+ #endif
+diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
+index c517f2e..6678402 100644
+--- a/arch/mips/lantiq/xway/Makefile
++++ b/arch/mips/lantiq/xway/Makefile
+@@ -1,7 +1,7 @@
+-obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
++obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
+ 
+-obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o
+-obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o
++obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o
++obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o
+ 
+ obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
+ obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
+diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c
+index d0e32ab..9bacaa8 100644
+--- a/arch/mips/lantiq/xway/devices.c
++++ b/arch/mips/lantiq/xway/devices.c
+@@ -31,22 +31,9 @@
+ 
+ /* gpio */
+ static struct resource ltq_gpio_resource[] = {
+-	{
+-		.name	= "gpio0",
+-		.start  = LTQ_GPIO0_BASE_ADDR,
+-		.end    = LTQ_GPIO0_BASE_ADDR + LTQ_GPIO_SIZE - 1,
+-		.flags  = IORESOURCE_MEM,
+-	}, {
+-		.name	= "gpio1",
+-		.start  = LTQ_GPIO1_BASE_ADDR,
+-		.end    = LTQ_GPIO1_BASE_ADDR + LTQ_GPIO_SIZE - 1,
+-		.flags  = IORESOURCE_MEM,
+-	}, {
+-		.name	= "gpio2",
+-		.start  = LTQ_GPIO2_BASE_ADDR,
+-		.end    = LTQ_GPIO2_BASE_ADDR + LTQ_GPIO_SIZE - 1,
+-		.flags  = IORESOURCE_MEM,
+-	}
++	MEM_RES("gpio0", LTQ_GPIO0_BASE_ADDR, LTQ_GPIO_SIZE),
++	MEM_RES("gpio1", LTQ_GPIO1_BASE_ADDR, LTQ_GPIO_SIZE),
++	MEM_RES("gpio2", LTQ_GPIO2_BASE_ADDR, LTQ_GPIO_SIZE),
+ };
+ 
+ void __init ltq_register_gpio(void)
+@@ -64,12 +51,8 @@ void __init ltq_register_gpio(void)
+ }
+ 
+ /* serial to parallel conversion */
+-static struct resource ltq_stp_resource = {
+-	.name   = "stp",
+-	.start  = LTQ_STP_BASE_ADDR,
+-	.end    = LTQ_STP_BASE_ADDR + LTQ_STP_SIZE - 1,
+-	.flags  = IORESOURCE_MEM,
+-};
++static struct resource ltq_stp_resource =
++	MEM_RES("stp", LTQ_STP_BASE_ADDR, LTQ_STP_SIZE);
+ 
+ void __init ltq_register_gpio_stp(void)
+ {
+@@ -78,12 +61,7 @@ void __init ltq_register_gpio_stp(void)
+ 
+ /* asc ports - amazon se has its own serial mapping */
+ static struct resource ltq_ase_asc_resources[] = {
+-	{
+-		.name	= "asc0",
+-		.start  = LTQ_ASC1_BASE_ADDR,
+-		.end    = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1,
+-		.flags  = IORESOURCE_MEM,
+-	},
++	MEM_RES("asc0", LTQ_ASC1_BASE_ADDR, LTQ_ASC_SIZE),
+ 	IRQ_RES(tx, LTQ_ASC_ASE_TIR),
+ 	IRQ_RES(rx, LTQ_ASC_ASE_RIR),
+ 	IRQ_RES(err, LTQ_ASC_ASE_EIR),
+@@ -96,12 +74,8 @@ void __init ltq_register_ase_asc(void)
+ }
+ 
+ /* ethernet */
+-static struct resource ltq_etop_resources = {
+-	.name	= "etop",
+-	.start	= LTQ_ETOP_BASE_ADDR,
+-	.end	= LTQ_ETOP_BASE_ADDR + LTQ_ETOP_SIZE - 1,
+-	.flags	= IORESOURCE_MEM,
+-};
++static struct resource ltq_etop_resources =
++	MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE);
+ 
+ static struct platform_device ltq_etop = {
+ 	.name		= "ltq_etop",
+diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
+index 4278a45..af35e62 100644
+--- a/arch/mips/lantiq/xway/dma.c
++++ b/arch/mips/lantiq/xway/dma.c
+@@ -23,6 +23,8 @@
+ #include <lantiq_soc.h>
+ #include <xway_dma.h>
+ 
++#include "../devices.h"
++
+ #define LTQ_DMA_CTRL		0x10
+ #define LTQ_DMA_CPOLL		0x14
+ #define LTQ_DMA_CS		0x18
+@@ -54,12 +56,8 @@
+ #define ltq_dma_w32_mask(x, y, z)	ltq_w32_mask(x, y, \
+ 						ltq_dma_membase + (z))
+ 
+-static struct resource ltq_dma_resource = {
+-	.name	= "dma",
+-	.start	= LTQ_DMA_BASE_ADDR,
+-	.end	= LTQ_DMA_BASE_ADDR + LTQ_DMA_SIZE - 1,
+-	.flags  = IORESOURCE_MEM,
+-};
++static struct resource ltq_dma_resource =
++	MEM_RES("dma", LTQ_DMA_BASE_ADDR, LTQ_DMA_SIZE);
+ 
+ static void __iomem *ltq_dma_membase;
+ 
+@@ -219,17 +217,8 @@ ltq_dma_init(void)
+ {
+ 	int i;
+ 
+-	/* insert and request the memory region */
+-	if (insert_resource(&iomem_resource, &ltq_dma_resource) < 0)
+-		panic("Failed to insert dma memory\n");
+-
+-	if (request_mem_region(ltq_dma_resource.start,
+-			resource_size(&ltq_dma_resource), "dma") < 0)
+-		panic("Failed to request dma memory\n");
+-
+ 	/* remap dma register range */
+-	ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start,
+-				resource_size(&ltq_dma_resource));
++	ltq_dma_membase = ltq_remap_resource(&ltq_dma_resource);
+ 	if (!ltq_dma_membase)
+ 		panic("Failed to remap dma memory\n");
+ 
+diff --git a/arch/mips/lantiq/xway/ebu.c b/arch/mips/lantiq/xway/ebu.c
+deleted file mode 100644
+index 66eb52f..0000000
+--- a/arch/mips/lantiq/xway/ebu.c
++++ /dev/null
+@@ -1,53 +0,0 @@
+-/*
+- *  This program is free software; you can redistribute it and/or modify it
+- *  under the terms of the GNU General Public License version 2 as published
+- *  by the Free Software Foundation.
+- *
+- *  EBU - the external bus unit attaches PCI, NOR and NAND
+- *
+- *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+- */
+-
+-#include <linux/kernel.h>
+-#include <linux/module.h>
+-#include <linux/version.h>
+-#include <linux/ioport.h>
+-
+-#include <lantiq_soc.h>
+-
+-/* all access to the ebu must be locked */
+-DEFINE_SPINLOCK(ebu_lock);
+-EXPORT_SYMBOL_GPL(ebu_lock);
+-
+-static struct resource ltq_ebu_resource = {
+-	.name	= "ebu",
+-	.start	= LTQ_EBU_BASE_ADDR,
+-	.end	= LTQ_EBU_BASE_ADDR + LTQ_EBU_SIZE - 1,
+-	.flags	= IORESOURCE_MEM,
+-};
+-
+-/* remapped base addr of the clock unit and external bus unit */
+-void __iomem *ltq_ebu_membase;
+-
+-static int __init lantiq_ebu_init(void)
+-{
+-	/* insert and request the memory region */
+-	if (insert_resource(&iomem_resource, &ltq_ebu_resource) < 0)
+-		panic("Failed to insert ebu memory\n");
+-
+-	if (request_mem_region(ltq_ebu_resource.start,
+-			resource_size(&ltq_ebu_resource), "ebu") < 0)
+-		panic("Failed to request ebu memory\n");
+-
+-	/* remap ebu register range */
+-	ltq_ebu_membase = ioremap_nocache(ltq_ebu_resource.start,
+-				resource_size(&ltq_ebu_resource));
+-	if (!ltq_ebu_membase)
+-		panic("Failed to remap ebu memory\n");
+-
+-	/* make sure to unprotect the memory region where flash is located */
+-	ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
+-	return 0;
+-}
+-
+-postcore_initcall(lantiq_ebu_init);
+diff --git a/arch/mips/lantiq/xway/pmu.c b/arch/mips/lantiq/xway/pmu.c
+deleted file mode 100644
+index 9d69f01e..0000000
+--- a/arch/mips/lantiq/xway/pmu.c
++++ /dev/null
+@@ -1,70 +0,0 @@
+-/*
+- *  This program is free software; you can redistribute it and/or modify it
+- *  under the terms of the GNU General Public License version 2 as published
+- *  by the Free Software Foundation.
+- *
+- *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+- */
+-
+-#include <linux/kernel.h>
+-#include <linux/module.h>
+-#include <linux/version.h>
+-#include <linux/ioport.h>
+-
+-#include <lantiq_soc.h>
+-
+-/* PMU - the power management unit allows us to turn part of the core
+- * on and off
+- */
+-
+-/* the enable / disable registers */
+-#define LTQ_PMU_PWDCR	0x1C
+-#define LTQ_PMU_PWDSR	0x20
+-
+-#define ltq_pmu_w32(x, y)	ltq_w32((x), ltq_pmu_membase + (y))
+-#define ltq_pmu_r32(x)		ltq_r32(ltq_pmu_membase + (x))
+-
+-static struct resource ltq_pmu_resource = {
+-	.name	= "pmu",
+-	.start	= LTQ_PMU_BASE_ADDR,
+-	.end	= LTQ_PMU_BASE_ADDR + LTQ_PMU_SIZE - 1,
+-	.flags	= IORESOURCE_MEM,
+-};
+-
+-static void __iomem *ltq_pmu_membase;
+-
+-void ltq_pmu_enable(unsigned int module)
+-{
+-	int err = 1000000;
+-
+-	ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR);
+-	do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module));
+-
+-	if (!err)
+-		panic("activating PMU module failed!\n");
+-}
+-EXPORT_SYMBOL(ltq_pmu_enable);
+-
+-void ltq_pmu_disable(unsigned int module)
+-{
+-	ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR);
+-}
+-EXPORT_SYMBOL(ltq_pmu_disable);
+-
+-int __init ltq_pmu_init(void)
+-{
+-	if (insert_resource(&iomem_resource, &ltq_pmu_resource) < 0)
+-		panic("Failed to insert pmu memory\n");
+-
+-	if (request_mem_region(ltq_pmu_resource.start,
+-			resource_size(&ltq_pmu_resource), "pmu") < 0)
+-		panic("Failed to request pmu memory\n");
+-
+-	ltq_pmu_membase = ioremap_nocache(ltq_pmu_resource.start,
+-				resource_size(&ltq_pmu_resource));
+-	if (!ltq_pmu_membase)
+-		panic("Failed to remap pmu memory\n");
+-	return 0;
+-}
+-
+-core_initcall(ltq_pmu_init);
+diff --git a/arch/mips/lantiq/xway/prom-ase.c b/arch/mips/lantiq/xway/prom-ase.c
+index abe49f4..aaccdcb 100644
+--- a/arch/mips/lantiq/xway/prom-ase.c
++++ b/arch/mips/lantiq/xway/prom-ase.c
+@@ -13,6 +13,7 @@
+ 
+ #include <lantiq_soc.h>
+ 
++#include "devices.h"
+ #include "../prom.h"
+ 
+ #define SOC_AMAZON_SE	"Amazon_SE"
+@@ -26,6 +27,7 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
+ {
+ 	i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
+ 	i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
++	sprintf(i->rev_type, "1.%d", i->rev);
+ 	switch (i->partnum) {
+ 	case SOC_ID_AMAZON_SE:
+ 		i->name = SOC_AMAZON_SE;
+@@ -37,3 +39,10 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
+ 		break;
+ 	}
+ }
++
++void __init ltq_soc_setup(void)
++{
++	ltq_register_ase_asc();
++	ltq_register_gpio();
++	ltq_register_wdt();
++}
+diff --git a/arch/mips/lantiq/xway/prom-xway.c b/arch/mips/lantiq/xway/prom-xway.c
+index 1686692a..f3d1228 100644
+--- a/arch/mips/lantiq/xway/prom-xway.c
++++ b/arch/mips/lantiq/xway/prom-xway.c
+@@ -13,6 +13,7 @@
+ 
+ #include <lantiq_soc.h>
+ 
++#include "devices.h"
+ #include "../prom.h"
+ 
+ #define SOC_DANUBE	"Danube"
+@@ -28,6 +29,7 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
+ {
+ 	i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
+ 	i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
++	sprintf(i->rev_type, "1.%d", i->rev);
+ 	switch (i->partnum) {
+ 	case SOC_ID_DANUBE1:
+ 	case SOC_ID_DANUBE2:
+@@ -52,3 +54,11 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
+ 		break;
+ 	}
+ }
++
++void __init ltq_soc_setup(void)
++{
++	ltq_register_asc(0);
++	ltq_register_asc(1);
++	ltq_register_gpio();
++	ltq_register_wdt();
++}
+diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
+index a1be36d..e701a48 100644
+--- a/arch/mips/lantiq/xway/reset.c
++++ b/arch/mips/lantiq/xway/reset.c
+@@ -15,6 +15,8 @@
+ 
+ #include <lantiq_soc.h>
+ 
++#include "../devices.h"
++
+ #define ltq_rcu_w32(x, y)	ltq_w32((x), ltq_rcu_membase + (y))
+ #define ltq_rcu_r32(x)		ltq_r32(ltq_rcu_membase + (x))
+ 
+@@ -25,12 +27,8 @@
+ #define LTQ_RCU_RST_STAT	0x0014
+ #define LTQ_RCU_STAT_SHIFT	26
+ 
+-static struct resource ltq_rcu_resource = {
+-	.name   = "rcu",
+-	.start  = LTQ_RCU_BASE_ADDR,
+-	.end    = LTQ_RCU_BASE_ADDR + LTQ_RCU_SIZE - 1,
+-	.flags  = IORESOURCE_MEM,
+-};
++static struct resource ltq_rcu_resource =
++	MEM_RES("rcu", LTQ_RCU_BASE_ADDR, LTQ_RCU_SIZE);
+ 
+ /* remapped base addr of the reset control unit */
+ static void __iomem *ltq_rcu_membase;
+@@ -67,17 +65,8 @@ static void ltq_machine_power_off(void)
+ 
+ static int __init mips_reboot_setup(void)
+ {
+-	/* insert and request the memory region */
+-	if (insert_resource(&iomem_resource, &ltq_rcu_resource) < 0)
+-		panic("Failed to insert rcu memory\n");
+-
+-	if (request_mem_region(ltq_rcu_resource.start,
+-			resource_size(&ltq_rcu_resource), "rcu") < 0)
+-		panic("Failed to request rcu memory\n");
+-
+ 	/* remap rcu register range */
+-	ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start,
+-				resource_size(&ltq_rcu_resource));
++	ltq_rcu_membase = ltq_remap_resource(&ltq_rcu_resource);
+ 	if (!ltq_rcu_membase)
+ 		panic("Failed to remap rcu memory\n");
+ 
+diff --git a/arch/mips/lantiq/xway/setup-ase.c b/arch/mips/lantiq/xway/setup-ase.c
+deleted file mode 100644
+index f6f3267..0000000
+--- a/arch/mips/lantiq/xway/setup-ase.c
++++ /dev/null
+@@ -1,19 +0,0 @@
+-/*
+- *  This program is free software; you can redistribute it and/or modify it
+- *  under the terms of the GNU General Public License version 2 as published
+- *  by the Free Software Foundation.
+- *
+- *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+- */
+-
+-#include <lantiq_soc.h>
+-
+-#include "../prom.h"
+-#include "devices.h"
+-
+-void __init ltq_soc_setup(void)
+-{
+-	ltq_register_ase_asc();
+-	ltq_register_gpio();
+-	ltq_register_wdt();
+-}
+diff --git a/arch/mips/lantiq/xway/setup-xway.c b/arch/mips/lantiq/xway/setup-xway.c
+deleted file mode 100644
+index c292f64..0000000
+--- a/arch/mips/lantiq/xway/setup-xway.c
++++ /dev/null
+@@ -1,20 +0,0 @@
+-/*
+- *  This program is free software; you can redistribute it and/or modify it
+- *  under the terms of the GNU General Public License version 2 as published
+- *  by the Free Software Foundation.
+- *
+- *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+- */
+-
+-#include <lantiq_soc.h>
+-
+-#include "../prom.h"
+-#include "devices.h"
+-
+-void __init ltq_soc_setup(void)
+-{
+-	ltq_register_asc(0);
+-	ltq_register_asc(1);
+-	ltq_register_gpio();
+-	ltq_register_wdt();
+-}
+diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
+new file mode 100644
+index 0000000..a29944f
+--- /dev/null
++++ b/arch/mips/lantiq/xway/sysctrl.c
+@@ -0,0 +1,77 @@
++/*
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ *
++ *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/ioport.h>
++
++#include <lantiq_soc.h>
++
++#include "../devices.h"
++
++/* clock control register */
++#define LTQ_CGU_IFCCR	0x0018
++
++/* the enable / disable registers */
++#define LTQ_PMU_PWDCR	0x1C
++#define LTQ_PMU_PWDSR	0x20
++
++#define ltq_pmu_w32(x, y)	ltq_w32((x), ltq_pmu_membase + (y))
++#define ltq_pmu_r32(x)		ltq_r32(ltq_pmu_membase + (x))
++
++static struct resource ltq_cgu_resource =
++	MEM_RES("cgu", LTQ_CGU_BASE_ADDR, LTQ_CGU_SIZE);
++
++static struct resource ltq_pmu_resource =
++	MEM_RES("pmu", LTQ_PMU_BASE_ADDR, LTQ_PMU_SIZE);
++
++static struct resource ltq_ebu_resource =
++	MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE);
++
++void __iomem *ltq_cgu_membase;
++void __iomem *ltq_ebu_membase;
++static void __iomem *ltq_pmu_membase;
++
++void ltq_cgu_enable(unsigned int clk)
++{
++	ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk, LTQ_CGU_IFCCR);
++}
++
++void ltq_pmu_enable(unsigned int module)
++{
++	int err = 1000000;
++
++	ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR);
++	do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module));
++
++	if (!err)
++		panic("activating PMU module failed!\n");
++}
++EXPORT_SYMBOL(ltq_pmu_enable);
++
++void ltq_pmu_disable(unsigned int module)
++{
++	ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR);
++}
++EXPORT_SYMBOL(ltq_pmu_disable);
++
++void __init ltq_soc_init(void)
++{
++	ltq_pmu_membase = ltq_remap_resource(&ltq_pmu_resource);
++	if (!ltq_pmu_membase)
++		panic("Failed to remap pmu memory\n");
++
++	ltq_cgu_membase = ltq_remap_resource(&ltq_cgu_resource);
++	if (!ltq_cgu_membase)
++		panic("Failed to remap cgu memory\n");
++
++	ltq_ebu_membase = ltq_remap_resource(&ltq_ebu_resource);
++	if (!ltq_ebu_membase)
++		panic("Failed to remap ebu memory\n");
++
++	/* make sure to unprotect the memory region where flash is located */
++	ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
++}
+diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c
+index 102aed0..179bf98 100644
+--- a/drivers/watchdog/lantiq_wdt.c
++++ b/drivers/watchdog/lantiq_wdt.c
+@@ -16,7 +16,7 @@
+ #include <linux/clk.h>
+ #include <linux/io.h>
+ 
+-#include <lantiq.h>
++#include <lantiq_soc.h>
+ 
+ /* Section 3.4 of the datasheet
+  * The password sequence protects the WDT control register from unintended
+-- 
+1.7.5.4
+
diff --git a/target/linux/lantiq/patches-3.0/0005-MIPS-lantiq-make-irq.c-support-the-FALC-ON.patch b/target/linux/lantiq/patches-3.0/0005-MIPS-lantiq-make-irq.c-support-the-FALC-ON.patch
new file mode 100644
index 0000000000..7caea708e4
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/0005-MIPS-lantiq-make-irq.c-support-the-FALC-ON.patch
@@ -0,0 +1,74 @@
+From d9355bb07878f9aa40856cc437c43cedc87662fc Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 11 Aug 2011 12:25:55 +0200
+Subject: [PATCH 05/24] MIPS: lantiq: make irq.c support the FALC-ON
+
+There are minor differences in how irqs work on xway and falcon socs.
+Xway needs 2 quirks that we need to disable for falcon to also work with
+this code.
+
+* EBU irq does not need to send a special ack to the EBU
+* The EIU does not exist
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Cc: linux-mips@linux-mips.org
+---
+ arch/mips/lantiq/irq.c |   24 +++++++++++++-----------
+ 1 files changed, 13 insertions(+), 11 deletions(-)
+
+diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
+index f9737bb..17c057f 100644
+--- a/arch/mips/lantiq/irq.c
++++ b/arch/mips/lantiq/irq.c
+@@ -195,7 +195,7 @@ static void ltq_hw_irqdispatch(int module)
+ 	do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
+ 
+ 	/* if this is a EBU irq, we need to ack it or get a deadlock */
+-	if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0))
++	if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
+ 		ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
+ 			LTQ_EBU_PCC_ISTAT);
+ }
+@@ -260,17 +260,19 @@ void __init arch_init_irq(void)
+ 	if (!ltq_icu_membase)
+ 		panic("Failed to remap icu memory\n");
+ 
+-	if (insert_resource(&iomem_resource, &ltq_eiu_resource) < 0)
+-		panic("Failed to insert eiu memory\n");
++	if (LTQ_EIU_BASE_ADDR) {
++		if (insert_resource(&iomem_resource, &ltq_eiu_resource) < 0)
++			panic("Failed to insert eiu memory\n");
+ 
+-	if (request_mem_region(ltq_eiu_resource.start,
+-			resource_size(&ltq_eiu_resource), "eiu") < 0)
+-		panic("Failed to request eiu memory\n");
++		if (request_mem_region(ltq_eiu_resource.start,
++				resource_size(&ltq_eiu_resource), "eiu") < 0)
++			panic("Failed to request eiu memory\n");
+ 
+-	ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start,
++		ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start,
+ 				resource_size(&ltq_eiu_resource));
+-	if (!ltq_eiu_membase)
+-		panic("Failed to remap eiu memory\n");
++		if (!ltq_eiu_membase)
++			panic("Failed to remap eiu memory\n");
++	}
+ 
+ 	/* make sure all irqs are turned off by default */
+ 	for (i = 0; i < 5; i++)
+@@ -296,8 +298,8 @@ void __init arch_init_irq(void)
+ 
+ 	for (i = INT_NUM_IRQ0;
+ 		i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
+-		if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) ||
+-			(i == LTQ_EIU_IR2))
++		if (((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) ||
++			(i == LTQ_EIU_IR2)) && LTQ_EIU_BASE_ADDR)
+ 			irq_set_chip_and_handler(i, &ltq_eiu_type,
+ 				handle_level_irq);
+ 		/* EIU3-5 only exist on ar9 and vr9 */
+-- 
+1.7.5.4
+
diff --git a/target/linux/lantiq/patches-3.0/0006-MIPS-lantiq-add-basic-support-for-FALC-ON.patch b/target/linux/lantiq/patches-3.0/0006-MIPS-lantiq-add-basic-support-for-FALC-ON.patch
new file mode 100644
index 0000000000..e4a0b9fccd
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/0006-MIPS-lantiq-add-basic-support-for-FALC-ON.patch
@@ -0,0 +1,1064 @@
+From ff57bc17a9964d24708759c6d78a51e337563d5f Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 11 Aug 2011 14:33:04 +0200
+Subject: [PATCH 06/24] MIPS: lantiq: add basic support for FALC-ON
+
+Adds support for the FALC-ON SoC. This SoC is from the fiber to the home GPON
+series.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Cc: linux-mips@linux-mips.org
+---
+ .../include/asm/mach-lantiq/falcon/falcon_irq.h    |  268 ++++++++++++++++++++
+ arch/mips/include/asm/mach-lantiq/falcon/irq.h     |   18 ++
+ .../include/asm/mach-lantiq/falcon/lantiq_soc.h    |  140 ++++++++++
+ arch/mips/include/asm/mach-lantiq/lantiq.h         |    1 +
+ arch/mips/lantiq/Kconfig                           |    4 +
+ arch/mips/lantiq/Makefile                          |    1 +
+ arch/mips/lantiq/Platform                          |    1 +
+ arch/mips/lantiq/falcon/Makefile                   |    1 +
+ arch/mips/lantiq/falcon/clk.c                      |   44 ++++
+ arch/mips/lantiq/falcon/devices.c                  |   87 +++++++
+ arch/mips/lantiq/falcon/devices.h                  |   18 ++
+ arch/mips/lantiq/falcon/prom.c                     |   72 ++++++
+ arch/mips/lantiq/falcon/reset.c                    |   87 +++++++
+ arch/mips/lantiq/falcon/sysctrl.c                  |  181 +++++++++++++
+ 14 files changed, 923 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
+ create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/irq.h
+ create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
+ create mode 100644 arch/mips/lantiq/falcon/Makefile
+ create mode 100644 arch/mips/lantiq/falcon/clk.c
+ create mode 100644 arch/mips/lantiq/falcon/devices.c
+ create mode 100644 arch/mips/lantiq/falcon/devices.h
+ create mode 100644 arch/mips/lantiq/falcon/prom.c
+ create mode 100644 arch/mips/lantiq/falcon/reset.c
+ create mode 100644 arch/mips/lantiq/falcon/sysctrl.c
+
+diff --git a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
+new file mode 100644
+index 0000000..4dc6466
+--- /dev/null
++++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
+@@ -0,0 +1,268 @@
++/*
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ *
++ *  Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
++ */
++
++#ifndef _FALCON_IRQ__
++#define _FALCON_IRQ__
++
++#define INT_NUM_IRQ0			8
++#define INT_NUM_IM0_IRL0		(INT_NUM_IRQ0 + 0)
++#define INT_NUM_IM1_IRL0		(INT_NUM_IM0_IRL0 + 32)
++#define INT_NUM_IM2_IRL0		(INT_NUM_IM1_IRL0 + 32)
++#define INT_NUM_IM3_IRL0		(INT_NUM_IM2_IRL0 + 32)
++#define INT_NUM_IM4_IRL0		(INT_NUM_IM3_IRL0 + 32)
++#define INT_NUM_EXTRA_START		(INT_NUM_IM4_IRL0 + 32)
++#define INT_NUM_IM_OFFSET		(INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
++
++#define MIPS_CPU_TIMER_IRQ			7
++
++/* HOST IF Event Interrupt */
++#define FALCON_IRQ_HOST				(INT_NUM_IM0_IRL0 + 0)
++/* HOST IF Mailbox0 Receive Interrupt */
++#define FALCON_IRQ_HOST_MB0_RX			(INT_NUM_IM0_IRL0 + 1)
++/* HOST IF Mailbox0 Transmit Interrupt */
++#define FALCON_IRQ_HOST_MB0_TX			(INT_NUM_IM0_IRL0 + 2)
++/* HOST IF Mailbox1 Receive Interrupt */
++#define FALCON_IRQ_HOST_MB1_RX			(INT_NUM_IM0_IRL0 + 3)
++/* HOST IF Mailbox1 Transmit Interrupt */
++#define FALCON_IRQ_HOST_MB1_TX			(INT_NUM_IM0_IRL0 + 4)
++/* I2C Last Single Data Transfer Request */
++#define FALCON_IRQ_I2C_LSREQ			(INT_NUM_IM0_IRL0 + 8)
++/* I2C Single Data Transfer Request */
++#define FALCON_IRQ_I2C_SREQ			(INT_NUM_IM0_IRL0 + 9)
++/* I2C Last Burst Data Transfer Request */
++#define FALCON_IRQ_I2C_LBREQ			(INT_NUM_IM0_IRL0 + 10)
++/* I2C Burst Data Transfer Request */
++#define FALCON_IRQ_I2C_BREQ			(INT_NUM_IM0_IRL0 + 11)
++/* I2C Error Interrupt */
++#define FALCON_IRQ_I2C_I2C_ERR			(INT_NUM_IM0_IRL0 + 12)
++/* I2C Protocol Interrupt */
++#define FALCON_IRQ_I2C_I2C_P			(INT_NUM_IM0_IRL0 + 13)
++/* SSC Transmit Interrupt */
++#define FALCON_IRQ_SSC_T			(INT_NUM_IM0_IRL0 + 14)
++/* SSC Receive Interrupt */
++#define FALCON_IRQ_SSC_R			(INT_NUM_IM0_IRL0 + 15)
++/* SSC Error Interrupt */
++#define FALCON_IRQ_SSC_E			(INT_NUM_IM0_IRL0 + 16)
++/* SSC Frame Interrupt */
++#define FALCON_IRQ_SSC_F			(INT_NUM_IM0_IRL0 + 17)
++/* Advanced Encryption Standard Interrupt */
++#define FALCON_IRQ_AES_AES			(INT_NUM_IM0_IRL0 + 27)
++/* Secure Hash Algorithm Interrupt */
++#define FALCON_IRQ_SHA_HASH			(INT_NUM_IM0_IRL0 + 28)
++/* PCM Receive Interrupt */
++#define FALCON_IRQ_PCM_RX			(INT_NUM_IM0_IRL0 + 29)
++/* PCM Transmit Interrupt */
++#define FALCON_IRQ_PCM_TX			(INT_NUM_IM0_IRL0 + 30)
++/* PCM Transmit Crash Interrupt */
++#define FALCON_IRQ_PCM_HW2_CRASH		(INT_NUM_IM0_IRL0 + 31)
++
++/* EBU Serial Flash Command Error */
++#define FALCON_IRQ_EBU_SF_CMDERR		(INT_NUM_IM1_IRL0 + 0)
++/* EBU Serial Flash Command Overwrite Error */
++#define FALCON_IRQ_EBU_SF_COVERR		(INT_NUM_IM1_IRL0 + 1)
++/* EBU Serial Flash Busy */
++#define FALCON_IRQ_EBU_SF_BUSY			(INT_NUM_IM1_IRL0 + 2)
++/* External Interrupt from GPIO P0 */
++#define FALCON_IRQ_GPIO_P0			(INT_NUM_IM1_IRL0 + 4)
++/* External Interrupt from GPIO P1 */
++#define FALCON_IRQ_GPIO_P1			(INT_NUM_IM1_IRL0 + 5)
++/* External Interrupt from GPIO P2 */
++#define FALCON_IRQ_GPIO_P2			(INT_NUM_IM1_IRL0 + 6)
++/* External Interrupt from GPIO P3 */
++#define FALCON_IRQ_GPIO_P3			(INT_NUM_IM1_IRL0 + 7)
++/* External Interrupt from GPIO P4 */
++#define FALCON_IRQ_GPIO_P4			(INT_NUM_IM1_IRL0 + 8)
++/* 8kHz backup interrupt derived from core-PLL */
++#define FALCON_IRQ_FSC_BKP			(INT_NUM_IM1_IRL0 + 10)
++/* FSC Timer Interrupt 0 */
++#define FALCON_IRQ_FSCT_CMP0			(INT_NUM_IM1_IRL0 + 11)
++/* FSC Timer Interrupt 1 */
++#define FALCON_IRQ_FSCT_CMP1			(INT_NUM_IM1_IRL0 + 12)
++/* 8kHz root interrupt derived from GPON interface */
++#define FALCON_IRQ_FSC_ROOT			(INT_NUM_IM1_IRL0 + 13)
++/* Time of Day */
++#define FALCON_IRQ_TOD				(INT_NUM_IM1_IRL0 + 14)
++/* PMA Interrupt from IntNode of the 200MHz Domain */
++#define FALCON_IRQ_PMA_200M			(INT_NUM_IM1_IRL0 + 15)
++/* PMA Interrupt from IntNode of the TX Clk Domain */
++#define FALCON_IRQ_PMA_TX			(INT_NUM_IM1_IRL0 + 16)
++/* PMA Interrupt from IntNode of the RX Clk Domain */
++#define FALCON_IRQ_PMA_RX			(INT_NUM_IM1_IRL0 + 17)
++/* SYS1 Interrupt */
++#define FALCON_IRQ_SYS1				(INT_NUM_IM1_IRL0 + 20)
++/* SYS GPE Interrupt */
++#define FALCON_IRQ_SYS_GPE			(INT_NUM_IM1_IRL0 + 21)
++/* Watchdog Access Error Interrupt */
++#define FALCON_IRQ_WDT_AEIR			(INT_NUM_IM1_IRL0 + 24)
++/* Watchdog Prewarning Interrupt */
++#define FALCON_IRQ_WDT_PIR			(INT_NUM_IM1_IRL0 + 25)
++/* SBIU interrupt */
++#define FALCON_IRQ_SBIU0			(INT_NUM_IM1_IRL0 + 27)
++/* FPI Bus Control Unit Interrupt */
++#define FALCON_IRQ_BCU0				(INT_NUM_IM1_IRL0 + 29)
++/* DDR Controller Interrupt */
++#define FALCON_IRQ_DDR				(INT_NUM_IM1_IRL0 + 30)
++/* Crossbar Error Interrupt */
++#define FALCON_IRQ_XBAR_ERROR			(INT_NUM_IM1_IRL0 + 31)
++
++/* ICTRLL 0 Interrupt */
++#define FALCON_IRQ_ICTRLL0			(INT_NUM_IM2_IRL0 + 0)
++/* ICTRLL 1 Interrupt */
++#define FALCON_IRQ_ICTRLL1			(INT_NUM_IM2_IRL0 + 1)
++/* ICTRLL 2 Interrupt */
++#define FALCON_IRQ_ICTRLL2			(INT_NUM_IM2_IRL0 + 2)
++/* ICTRLL 3 Interrupt */
++#define FALCON_IRQ_ICTRLL3			(INT_NUM_IM2_IRL0 + 3)
++/* OCTRLL 0 Interrupt */
++#define FALCON_IRQ_OCTRLL0			(INT_NUM_IM2_IRL0 + 4)
++/* OCTRLL 1 Interrupt */
++#define FALCON_IRQ_OCTRLL1			(INT_NUM_IM2_IRL0 + 5)
++/* OCTRLL 2 Interrupt */
++#define FALCON_IRQ_OCTRLL2			(INT_NUM_IM2_IRL0 + 6)
++/* OCTRLL 3 Interrupt */
++#define FALCON_IRQ_OCTRLL3			(INT_NUM_IM2_IRL0 + 7)
++/* OCTRLG Interrupt */
++#define FALCON_IRQ_OCTRLG			(INT_NUM_IM2_IRL0 + 9)
++/* IQM Interrupt */
++#define FALCON_IRQ_IQM				(INT_NUM_IM2_IRL0 + 10)
++/* FSQM Interrupt */
++#define FALCON_IRQ_FSQM				(INT_NUM_IM2_IRL0 + 11)
++/* TMU Interrupt */
++#define FALCON_IRQ_TMU				(INT_NUM_IM2_IRL0 + 12)
++/* LINK1 Interrupt */
++#define FALCON_IRQ_LINK1			(INT_NUM_IM2_IRL0 + 14)
++/* ICTRLC 0 Interrupt */
++#define FALCON_IRQ_ICTRLC0			(INT_NUM_IM2_IRL0 + 16)
++/* ICTRLC 1 Interrupt */
++#define FALCON_IRQ_ICTRLC1			(INT_NUM_IM2_IRL0 + 17)
++/* OCTRLC Interrupt */
++#define FALCON_IRQ_OCTRLC			(INT_NUM_IM2_IRL0 + 18)
++/* CONFIG Break Interrupt */
++#define FALCON_IRQ_CONFIG_BREAK			(INT_NUM_IM2_IRL0 + 19)
++/* CONFIG Interrupt */
++#define FALCON_IRQ_CONFIG			(INT_NUM_IM2_IRL0 + 20)
++/* Dispatcher Interrupt */
++#define FALCON_IRQ_DISP				(INT_NUM_IM2_IRL0 + 21)
++/* TBM Interrupt */
++#define FALCON_IRQ_TBM				(INT_NUM_IM2_IRL0 + 22)
++/* GTC Downstream Interrupt */
++#define FALCON_IRQ_GTC_DS			(INT_NUM_IM2_IRL0 + 29)
++/* GTC Upstream Interrupt */
++#define FALCON_IRQ_GTC_US			(INT_NUM_IM2_IRL0 + 30)
++/* EIM Interrupt */
++#define FALCON_IRQ_EIM				(INT_NUM_IM2_IRL0 + 31)
++
++/* ASC0 Transmit Interrupt */
++#define FALCON_IRQ_ASC0_T			(INT_NUM_IM3_IRL0 + 0)
++/* ASC0 Receive Interrupt */
++#define FALCON_IRQ_ASC0_R			(INT_NUM_IM3_IRL0 + 1)
++/* ASC0 Error Interrupt */
++#define FALCON_IRQ_ASC0_E			(INT_NUM_IM3_IRL0 + 2)
++/* ASC0 Transmit Buffer Interrupt */
++#define FALCON_IRQ_ASC0_TB			(INT_NUM_IM3_IRL0 + 3)
++/* ASC0 Autobaud Start Interrupt */
++#define FALCON_IRQ_ASC0_ABST			(INT_NUM_IM3_IRL0 + 4)
++/* ASC0 Autobaud Detection Interrupt */
++#define FALCON_IRQ_ASC0_ABDET			(INT_NUM_IM3_IRL0 + 5)
++/* ASC1 Modem Status Interrupt */
++#define FALCON_IRQ_ASC0_MS			(INT_NUM_IM3_IRL0 + 6)
++/* ASC0 Soft Flow Control Interrupt */
++#define FALCON_IRQ_ASC0_SFC			(INT_NUM_IM3_IRL0 + 7)
++/* ASC1 Transmit Interrupt */
++#define FALCON_IRQ_ASC1_T			(INT_NUM_IM3_IRL0 + 8)
++/* ASC1 Receive Interrupt */
++#define FALCON_IRQ_ASC1_R			(INT_NUM_IM3_IRL0 + 9)
++/* ASC1 Error Interrupt */
++#define FALCON_IRQ_ASC1_E			(INT_NUM_IM3_IRL0 + 10)
++/* ASC1 Transmit Buffer Interrupt */
++#define FALCON_IRQ_ASC1_TB			(INT_NUM_IM3_IRL0 + 11)
++/* ASC1 Autobaud Start Interrupt */
++#define FALCON_IRQ_ASC1_ABST			(INT_NUM_IM3_IRL0 + 12)
++/* ASC1 Autobaud Detection Interrupt */
++#define FALCON_IRQ_ASC1_ABDET			(INT_NUM_IM3_IRL0 + 13)
++/* ASC1 Modem Status Interrupt */
++#define FALCON_IRQ_ASC1_MS			(INT_NUM_IM3_IRL0 + 14)
++/* ASC1 Soft Flow Control Interrupt */
++#define FALCON_IRQ_ASC1_SFC			(INT_NUM_IM3_IRL0 + 15)
++/* GPTC Timer/Counter 1A Interrupt */
++#define FALCON_IRQ_GPTC_TC1A			(INT_NUM_IM3_IRL0 + 16)
++/* GPTC Timer/Counter 1B Interrupt */
++#define FALCON_IRQ_GPTC_TC1B			(INT_NUM_IM3_IRL0 + 17)
++/* GPTC Timer/Counter 2A Interrupt */
++#define FALCON_IRQ_GPTC_TC2A			(INT_NUM_IM3_IRL0 + 18)
++/* GPTC Timer/Counter 2B Interrupt */
++#define FALCON_IRQ_GPTC_TC2B			(INT_NUM_IM3_IRL0 + 19)
++/* GPTC Timer/Counter 3A Interrupt */
++#define FALCON_IRQ_GPTC_TC3A			(INT_NUM_IM3_IRL0 + 20)
++/* GPTC Timer/Counter 3B Interrupt */
++#define FALCON_IRQ_GPTC_TC3B			(INT_NUM_IM3_IRL0 + 21)
++/* DFEV0, Channel 1 Transmit Interrupt */
++#define FALCON_IRQ_DFEV0_2TX			(INT_NUM_IM3_IRL0 + 26)
++/* DFEV0, Channel 1 Receive Interrupt */
++#define FALCON_IRQ_DFEV0_2RX			(INT_NUM_IM3_IRL0 + 27)
++/* DFEV0, Channel 1 General Purpose Interrupt */
++#define FALCON_IRQ_DFEV0_2GP			(INT_NUM_IM3_IRL0 + 28)
++/* DFEV0, Channel 0 Transmit Interrupt */
++#define FALCON_IRQ_DFEV0_1TX			(INT_NUM_IM3_IRL0 + 29)
++/* DFEV0, Channel 0 Receive Interrupt */
++#define FALCON_IRQ_DFEV0_1RX			(INT_NUM_IM3_IRL0 + 30)
++/* DFEV0, Channel 0 General Purpose Interrupt */
++#define FALCON_IRQ_DFEV0_1GP			(INT_NUM_IM3_IRL0 + 31)
++
++/* ICTRLL 0 Error */
++#define FALCON_IRQ_ICTRLL0_ERR			(INT_NUM_IM4_IRL0 + 0)
++/* ICTRLL 1 Error */
++#define FALCON_IRQ_ICTRLL1_ERR			(INT_NUM_IM4_IRL0 + 1)
++/* ICTRLL 2 Error */
++#define FALCON_IRQ_ICTRLL2_ERR			(INT_NUM_IM4_IRL0 + 2)
++/* ICTRLL 3 Error */
++#define FALCON_IRQ_ICTRLL3_ERR			(INT_NUM_IM4_IRL0 + 3)
++/* OCTRLL 0 Error */
++#define FALCON_IRQ_OCTRLL0_ERR			(INT_NUM_IM4_IRL0 + 4)
++/* OCTRLL 1 Error */
++#define FALCON_IRQ_OCTRLL1_ERR			(INT_NUM_IM4_IRL0 + 5)
++/* OCTRLL 2 Error */
++#define FALCON_IRQ_OCTRLL2_ERR			(INT_NUM_IM4_IRL0 + 6)
++/* OCTRLL 3 Error */
++#define FALCON_IRQ_OCTRLL3_ERR			(INT_NUM_IM4_IRL0 + 7)
++/* ICTRLG Error */
++#define FALCON_IRQ_ICTRLG_ERR			(INT_NUM_IM4_IRL0 + 8)
++/* OCTRLG Error */
++#define FALCON_IRQ_OCTRLG_ERR			(INT_NUM_IM4_IRL0 + 9)
++/* IQM Error */
++#define FALCON_IRQ_IQM_ERR			(INT_NUM_IM4_IRL0 + 10)
++/* FSQM Error */
++#define FALCON_IRQ_FSQM_ERR			(INT_NUM_IM4_IRL0 + 11)
++/* TMU Error */
++#define FALCON_IRQ_TMU_ERR			(INT_NUM_IM4_IRL0 + 12)
++/* MPS Status Interrupt #0 (VPE1 to VPE0) */
++#define FALCON_IRQ_MPS_IR0			(INT_NUM_IM4_IRL0 + 14)
++/* MPS Status Interrupt #1 (VPE1 to VPE0) */
++#define FALCON_IRQ_MPS_IR1			(INT_NUM_IM4_IRL0 + 15)
++/* MPS Status Interrupt #2 (VPE1 to VPE0) */
++#define FALCON_IRQ_MPS_IR2			(INT_NUM_IM4_IRL0 + 16)
++/* MPS Status Interrupt #3 (VPE1 to VPE0) */
++#define FALCON_IRQ_MPS_IR3			(INT_NUM_IM4_IRL0 + 17)
++/* MPS Status Interrupt #4 (VPE1 to VPE0) */
++#define FALCON_IRQ_MPS_IR4			(INT_NUM_IM4_IRL0 + 18)
++/* MPS Status Interrupt #5 (VPE1 to VPE0) */
++#define FALCON_IRQ_MPS_IR5			(INT_NUM_IM4_IRL0 + 19)
++/* MPS Status Interrupt #6 (VPE1 to VPE0) */
++#define FALCON_IRQ_MPS_IR6			(INT_NUM_IM4_IRL0 + 20)
++/* MPS Status Interrupt #7 (VPE1 to VPE0) */
++#define FALCON_IRQ_MPS_IR7			(INT_NUM_IM4_IRL0 + 21)
++/* MPS Status Interrupt #8 (VPE1 to VPE0) */
++#define FALCON_IRQ_MPS_IR8			(INT_NUM_IM4_IRL0 + 22)
++/* VPE0 Exception Level Flag Interrupt */
++#define FALCON_IRQ_VPE0_EXL			(INT_NUM_IM4_IRL0 + 29)
++/* VPE0 Error Level Flag Interrupt */
++#define FALCON_IRQ_VPE0_ERL			(INT_NUM_IM4_IRL0 + 30)
++/* VPE0 Performance Monitoring Counter Interrupt */
++#define FALCON_IRQ_VPE0_PMCIR			(INT_NUM_IM4_IRL0 + 31)
++
++#endif /* _FALCON_IRQ__ */
+diff --git a/arch/mips/include/asm/mach-lantiq/falcon/irq.h b/arch/mips/include/asm/mach-lantiq/falcon/irq.h
+new file mode 100644
+index 0000000..2caccd9
+--- /dev/null
++++ b/arch/mips/include/asm/mach-lantiq/falcon/irq.h
+@@ -0,0 +1,18 @@
++/*
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ *
++ *  Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
++ */
++
++#ifndef __FALCON_IRQ_H
++#define __FALCON_IRQ_H
++
++#include <falcon_irq.h>
++
++#define NR_IRQS 328
++
++#include_next <irq.h>
++
++#endif
+diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
+new file mode 100644
+index 0000000..c092531
+--- /dev/null
++++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
+@@ -0,0 +1,140 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
++ */
++
++#ifndef _LTQ_FALCON_H__
++#define _LTQ_FALCON_H__
++
++#ifdef CONFIG_SOC_FALCON
++
++#include <lantiq.h>
++
++/* Chip IDs */
++#define SOC_ID_FALCON		0x01B8
++
++/* SoC Types */
++#define SOC_TYPE_FALCON		0x01
++
++/* ASC0/1 - serial port */
++#define LTQ_ASC0_BASE_ADDR	0x1E100C00
++#define LTQ_ASC1_BASE_ADDR	0x1E100B00
++#define LTQ_ASC_SIZE		0x100
++
++#define LTQ_ASC_TIR(x)          (INT_NUM_IM3_IRL0 + (x * 8))
++#define LTQ_ASC_RIR(x)          (INT_NUM_IM3_IRL0 + (x * 8) + 1)
++#define LTQ_ASC_EIR(x)          (INT_NUM_IM3_IRL0 + (x * 8) + 2)
++
++/* during early_printk no ioremap possible at this early stage
++   lets use KSEG1 instead  */
++#define LTQ_EARLY_ASC		KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
++
++/* ICU - interrupt control unit */
++#define LTQ_ICU_BASE_ADDR	0x1F880200
++#define LTQ_ICU_SIZE		0x100
++
++/* WDT */
++#define LTQ_WDT_BASE_ADDR	0x1F8803F0
++#define LTQ_WDT_SIZE		0x10
++
++#define LTQ_RST_CAUSE_WDTRST	0x0002
++
++/* EBU - external bus unit */
++#define LTQ_EBU_BASE_ADDR       0x18000000
++#define LTQ_EBU_SIZE            0x0100
++
++#define LTQ_EBU_MODCON  0x000C
++
++/* GPIO */
++#define LTQ_GPIO0_BASE_ADDR     0x1D810000
++#define LTQ_GPIO0_SIZE          0x0080
++#define LTQ_GPIO1_BASE_ADDR     0x1E800100
++#define LTQ_GPIO1_SIZE          0x0080
++#define LTQ_GPIO2_BASE_ADDR     0x1D810100
++#define LTQ_GPIO2_SIZE          0x0080
++#define LTQ_GPIO3_BASE_ADDR     0x1E800200
++#define LTQ_GPIO3_SIZE          0x0080
++#define LTQ_GPIO4_BASE_ADDR     0x1E800300
++#define LTQ_GPIO4_SIZE          0x0080
++#define LTQ_PADCTRL0_BASE_ADDR  0x1DB01000
++#define LTQ_PADCTRL0_SIZE       0x0100
++#define LTQ_PADCTRL1_BASE_ADDR  0x1E800400
++#define LTQ_PADCTRL1_SIZE       0x0100
++#define LTQ_PADCTRL2_BASE_ADDR  0x1DB02000
++#define LTQ_PADCTRL2_SIZE       0x0100
++#define LTQ_PADCTRL3_BASE_ADDR  0x1E800500
++#define LTQ_PADCTRL3_SIZE       0x0100
++#define LTQ_PADCTRL4_BASE_ADDR  0x1E800600
++#define LTQ_PADCTRL4_SIZE       0x0100
++
++/* CHIP ID */
++#define LTQ_STATUS_BASE_ADDR	0x1E802000
++
++#define LTQ_FALCON_CHIPID	((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c))
++#define LTQ_FALCON_CHIPCONF	((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40))
++
++/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */
++#define LTQ_SYS1_BASE_ADDR      0x1EF00000
++#define LTQ_SYS1_SIZE           0x0100
++#define LTQ_STATUS_BASE_ADDR	0x1E802000
++#define LTQ_STATUS_SIZE		0x0080
++#define LTQ_SYS_ETH_BASE_ADDR	0x1DB00000
++#define LTQ_SYS_ETH_SIZE	0x0100
++#define LTQ_SYS_GPE_BASE_ADDR	0x1D700000
++#define LTQ_SYS_GPE_SIZE	0x0100
++
++#define SYSCTL_SYS1		0
++#define SYSCTL_SYSETH		1
++#define SYSCTL_SYSGPE		2
++
++/* Activation Status Register */
++#define ACTS_ASC1_ACT	0x00000800
++#define ACTS_P0		0x00010000
++#define ACTS_P1		0x00010000
++#define ACTS_P2		0x00020000
++#define ACTS_P3		0x00020000
++#define ACTS_P4		0x00040000
++#define ACTS_PADCTRL0	0x00100000
++#define ACTS_PADCTRL1	0x00100000
++#define ACTS_PADCTRL2	0x00200000
++#define ACTS_PADCTRL3	0x00200000
++#define ACTS_PADCTRL4	0x00400000
++
++extern void ltq_sysctl_activate(int module, unsigned int mask);
++extern void ltq_sysctl_deactivate(int module, unsigned int mask);
++extern void ltq_sysctl_clken(int module, unsigned int mask);
++extern void ltq_sysctl_clkdis(int module, unsigned int mask);
++extern void ltq_sysctl_reboot(int module, unsigned int mask);
++extern int ltq_gpe_is_activated(unsigned int mask);
++
++/* global register ranges */
++extern __iomem void *ltq_ebu_membase;
++extern __iomem void *ltq_sys1_membase;
++#define ltq_ebu_w32(x, y)	ltq_w32((x), ltq_ebu_membase + (y))
++#define ltq_ebu_r32(x)		ltq_r32(ltq_ebu_membase + (x))
++#define ltq_ebu_w32_mask(clear, set, reg)   \
++	ltq_ebu_w32((ltq_ebu_r32(reg) & ~(clear)) | (set), reg)
++
++#define ltq_sys1_w32(x, y)	ltq_w32((x), ltq_sys1_membase + (y))
++#define ltq_sys1_r32(x)		ltq_r32(ltq_sys1_membase + (x))
++#define ltq_sys1_w32_mask(clear, set, reg)   \
++	ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
++
++/* gpio_request wrapper to help configure the pin */
++extern int ltq_gpio_request(unsigned int pin, unsigned int val,
++				unsigned int dir, const char *name);
++extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux);
++
++/* to keep the irq code generic we need to define these to 0 as falcon
++   has no EIU/EBU */
++#define LTQ_EIU_BASE_ADDR	0
++#define LTQ_EBU_PCC_ISTAT	0
++
++#define ltq_is_ar9()	0
++#define ltq_is_vr9()	0
++
++#endif /* CONFIG_SOC_FALCON */
++#endif /* _LTQ_XWAY_H__ */
+diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h
+index 66d7300..188de0f 100644
+--- a/arch/mips/include/asm/mach-lantiq/lantiq.h
++++ b/arch/mips/include/asm/mach-lantiq/lantiq.h
+@@ -25,6 +25,7 @@ extern unsigned int ltq_get_soc_type(void);
+ /* clock speeds */
+ #define CLOCK_60M	60000000
+ #define CLOCK_83M	83333333
++#define CLOCK_100M	100000000
+ #define CLOCK_111M	111111111
+ #define CLOCK_133M	133333333
+ #define CLOCK_167M	166666667
+diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
+index 3fccf21..cb6b39f 100644
+--- a/arch/mips/lantiq/Kconfig
++++ b/arch/mips/lantiq/Kconfig
+@@ -16,8 +16,12 @@ config SOC_XWAY
+ 	bool "XWAY"
+ 	select SOC_TYPE_XWAY
+ 	select HW_HAS_PCI
++
++config SOC_FALCON
++	bool "FALCON"
+ endchoice
+ 
+ source "arch/mips/lantiq/xway/Kconfig"
++source "arch/mips/lantiq/falcon/Kconfig"
+ 
+ endif
+diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile
+index e5dae0e..7e9c69e 100644
+--- a/arch/mips/lantiq/Makefile
++++ b/arch/mips/lantiq/Makefile
+@@ -9,3 +9,4 @@ obj-y := irq.o setup.o clk.o prom.o devices.o
+ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+ 
+ obj-$(CONFIG_SOC_TYPE_XWAY) += xway/
++obj-$(CONFIG_SOC_FALCON) += falcon/
+diff --git a/arch/mips/lantiq/Platform b/arch/mips/lantiq/Platform
+index f3dff05..b3ec498 100644
+--- a/arch/mips/lantiq/Platform
++++ b/arch/mips/lantiq/Platform
+@@ -6,3 +6,4 @@ platform-$(CONFIG_LANTIQ)	+= lantiq/
+ cflags-$(CONFIG_LANTIQ)		+= -I$(srctree)/arch/mips/include/asm/mach-lantiq
+ load-$(CONFIG_LANTIQ)		= 0xffffffff80002000
+ cflags-$(CONFIG_SOC_TYPE_XWAY)	+= -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
++cflags-$(CONFIG_SOC_FALCON)	+= -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon
+diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile
+new file mode 100644
+index 0000000..e9c7455
+--- /dev/null
++++ b/arch/mips/lantiq/falcon/Makefile
+@@ -0,0 +1 @@
++obj-y := clk.o prom.o reset.o sysctrl.o devices.o
+diff --git a/arch/mips/lantiq/falcon/clk.c b/arch/mips/lantiq/falcon/clk.c
+new file mode 100644
+index 0000000..1a550ea
+--- /dev/null
++++ b/arch/mips/lantiq/falcon/clk.c
+@@ -0,0 +1,44 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
++ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/ioport.h>
++#include <linux/module.h>
++
++#include <lantiq_soc.h>
++
++#include "devices.h"
++
++/* CPU0 Clock Control Register */
++#define LTQ_SYS1_CPU0CC		0x0040
++/* clock divider bit */
++#define LTQ_CPU0CC_CPUDIV	0x0001
++
++unsigned int
++ltq_get_io_region_clock(void)
++{
++	return CLOCK_200M;
++}
++EXPORT_SYMBOL(ltq_get_io_region_clock);
++
++unsigned int
++ltq_get_cpu_hz(void)
++{
++	if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV)
++		return CLOCK_200M;
++	else
++		return CLOCK_400M;
++}
++EXPORT_SYMBOL(ltq_get_cpu_hz);
++
++unsigned int
++ltq_get_fpi_hz(void)
++{
++	return CLOCK_100M;
++}
++EXPORT_SYMBOL(ltq_get_fpi_hz);
+diff --git a/arch/mips/lantiq/falcon/devices.c b/arch/mips/lantiq/falcon/devices.c
+new file mode 100644
+index 0000000..c4606f2
+--- /dev/null
++++ b/arch/mips/lantiq/falcon/devices.c
+@@ -0,0 +1,87 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
++ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/platform_device.h>
++#include <linux/mtd/nand.h>
++
++#include <lantiq_soc.h>
++
++#include "devices.h"
++
++/* nand flash */
++/* address lines used for NAND control signals */
++#define NAND_ADDR_ALE		0x10000
++#define NAND_ADDR_CLE		0x20000
++/* Ready/Busy Status */
++#define MODCON_STS		0x0002
++/* Ready/Busy Status Edge */
++#define MODCON_STSEDGE		0x0004
++
++static const char *part_probes[] = { "cmdlinepart", NULL };
++
++static int
++falcon_nand_ready(struct mtd_info *mtd)
++{
++	u32 modcon = ltq_ebu_r32(LTQ_EBU_MODCON);
++
++	return (((modcon & (MODCON_STS | MODCON_STSEDGE)) ==
++						(MODCON_STS | MODCON_STSEDGE)));
++}
++
++static void
++falcon_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
++{
++	struct nand_chip *this = mtd->priv;
++	unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
++
++	if (ctrl & NAND_CTRL_CHANGE) {
++		nandaddr &= ~(NAND_ADDR_ALE | NAND_ADDR_CLE);
++
++		if (ctrl & NAND_CLE)
++			nandaddr |= NAND_ADDR_CLE;
++		if (ctrl & NAND_ALE)
++			nandaddr |= NAND_ADDR_ALE;
++
++		this->IO_ADDR_W = (void __iomem *) nandaddr;
++	}
++
++	if (cmd != NAND_CMD_NONE)
++		writeb(cmd, this->IO_ADDR_W);
++}
++
++static struct platform_nand_data falcon_flash_nand_data = {
++	.chip = {
++		.nr_chips		= 1,
++		.chip_delay		= 25,
++		.part_probe_types	= part_probes,
++	},
++	.ctrl = {
++		.cmd_ctrl		= falcon_hwcontrol,
++		.dev_ready		= falcon_nand_ready,
++	}
++};
++
++static struct resource ltq_nand_res =
++	MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_MAX);
++
++static struct platform_device ltq_flash_nand = {
++	.name		= "gen_nand",
++	.id		= -1,
++	.num_resources	= 1,
++	.resource	= &ltq_nand_res,
++	.dev		= {
++		.platform_data = &falcon_flash_nand_data,
++	},
++};
++
++void __init
++falcon_register_nand(void)
++{
++	platform_device_register(&ltq_flash_nand);
++}
+diff --git a/arch/mips/lantiq/falcon/devices.h b/arch/mips/lantiq/falcon/devices.h
+new file mode 100644
+index 0000000..e802a7c
+--- /dev/null
++++ b/arch/mips/lantiq/falcon/devices.h
+@@ -0,0 +1,18 @@
++/*
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
++ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
++ */
++
++#ifndef _FALCON_DEVICES_H__
++#define _FALCON_DEVICES_H__
++
++#include "../devices.h"
++
++extern void falcon_register_nand(void);
++
++#endif
+diff --git a/arch/mips/lantiq/falcon/prom.c b/arch/mips/lantiq/falcon/prom.c
+new file mode 100644
+index 0000000..89367c4
+--- /dev/null
++++ b/arch/mips/lantiq/falcon/prom.c
+@@ -0,0 +1,72 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
++ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
++ */
++
++#include <lantiq_soc.h>
++
++#include "devices.h"
++
++#include "../prom.h"
++
++#define SOC_FALCON		"Falcon"
++
++#define PART_SHIFT	12
++#define PART_MASK	0x0FFFF000
++#define REV_SHIFT	28
++#define REV_MASK	0xF0000000
++#define SREV_SHIFT	22
++#define SREV_MASK	0x03C00000
++
++#define MUXC_SIF_RX_PIN		112
++#define MUXC_SIF_TX_PIN		113
++
++/* this parameter allows us enable/disable asc1 via commandline */
++static int register_asc1;
++static int __init
++ltq_parse_asc1(char *p)
++{
++	register_asc1 = 1;
++	return 0;
++}
++__setup("use_asc1", ltq_parse_asc1);
++
++void __init
++ltq_soc_setup(void)
++{
++	ltq_register_asc(0);
++	ltq_register_wdt();
++	falcon_register_gpio();
++	if (register_asc1) {
++		ltq_register_asc(1);
++		if (ltq_gpio_request(MUXC_SIF_RX_PIN, 3, 0, "asc1-rx"))
++			pr_err("failed to request asc1-rx");
++		if (ltq_gpio_request(MUXC_SIF_TX_PIN, 3, 1, "asc1-tx"))
++			pr_err("failed to request asc1-tx");
++		ltq_sysctl_activate(SYSCTL_SYS1, ACTS_ASC1_ACT);
++	}
++}
++
++void __init
++ltq_soc_detect(struct ltq_soc_info *i)
++{
++	i->partnum = (ltq_r32(LTQ_FALCON_CHIPID) & PART_MASK) >> PART_SHIFT;
++	i->rev = (ltq_r32(LTQ_FALCON_CHIPID) & REV_MASK) >> REV_SHIFT;
++	i->srev = (ltq_r32(LTQ_FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT;
++	sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'),
++		i->rev & 0x7, i->srev & 0x3);
++	switch (i->partnum) {
++	case SOC_ID_FALCON:
++		i->name = SOC_FALCON;
++		i->type = SOC_TYPE_FALCON;
++		break;
++
++	default:
++		unreachable();
++		break;
++	}
++}
+diff --git a/arch/mips/lantiq/falcon/reset.c b/arch/mips/lantiq/falcon/reset.c
+new file mode 100644
+index 0000000..d3289ca
+--- /dev/null
++++ b/arch/mips/lantiq/falcon/reset.c
+@@ -0,0 +1,87 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
++ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/init.h>
++#include <linux/io.h>
++#include <linux/pm.h>
++#include <asm/reboot.h>
++#include <linux/module.h>
++
++#include <lantiq_soc.h>
++
++/* CPU0 Reset Source Register */
++#define LTQ_SYS1_CPU0RS		0x0040
++/* reset cause mask */
++#define LTQ_CPU0RS_MASK		0x0003
++
++int
++ltq_reset_cause(void)
++{
++	return ltq_sys1_r32(LTQ_SYS1_CPU0RS) & LTQ_CPU0RS_MASK;
++}
++EXPORT_SYMBOL_GPL(ltq_reset_cause);
++
++#define BOOT_REG_BASE	(KSEG1 | 0x1F200000)
++#define BOOT_PW1_REG	(BOOT_REG_BASE | 0x20)
++#define BOOT_PW2_REG	(BOOT_REG_BASE | 0x24)
++#define BOOT_PW1	0x4C545100
++#define BOOT_PW2	0x0051544C
++
++#define WDT_REG_BASE	(KSEG1 | 0x1F8803F0)
++#define WDT_PW1		0x00BE0000
++#define WDT_PW2		0x00DC0000
++
++static void
++ltq_machine_restart(char *command)
++{
++	pr_notice("System restart\n");
++	local_irq_disable();
++
++	/* reboot magic */
++	ltq_w32(BOOT_PW1, (void *)BOOT_PW1_REG); /* 'LTQ\0' */
++	ltq_w32(BOOT_PW2, (void *)BOOT_PW2_REG); /* '\0QTL' */
++	ltq_w32(0, (void *)BOOT_REG_BASE); /* reset Bootreg RVEC */
++
++	/* watchdog magic */
++	ltq_w32(WDT_PW1, (void *)WDT_REG_BASE);
++	ltq_w32(WDT_PW2 |
++		(0x3 << 26) | /* PWL */
++		(0x2 << 24) | /* CLKDIV */
++		(0x1 << 31) | /* enable */
++		(1), /* reload */
++		(void *)WDT_REG_BASE);
++	unreachable();
++}
++
++static void
++ltq_machine_halt(void)
++{
++	pr_notice("System halted.\n");
++	local_irq_disable();
++	unreachable();
++}
++
++static void
++ltq_machine_power_off(void)
++{
++	pr_notice("Please turn off the power now.\n");
++	local_irq_disable();
++	unreachable();
++}
++
++static int __init
++mips_reboot_setup(void)
++{
++	_machine_restart = ltq_machine_restart;
++	_machine_halt = ltq_machine_halt;
++	pm_power_off = ltq_machine_power_off;
++	return 0;
++}
++
++arch_initcall(mips_reboot_setup);
+diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
+new file mode 100644
+index 0000000..d20b46b
+--- /dev/null
++++ b/arch/mips/lantiq/falcon/sysctrl.c
+@@ -0,0 +1,181 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
++ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/ioport.h>
++#include <asm/delay.h>
++
++#include <lantiq_soc.h>
++
++#include "devices.h"
++
++/* infrastructure control register */
++#define SYS1_INFRAC		0x00bc
++/* Configuration fuses for drivers and pll */
++#define STATUS_CONFIG		0x0040
++
++/* GPE frequency selection */
++#define GPPC_OFFSET		24
++#define GPEFREQ_MASK		0x00000C0
++#define GPEFREQ_OFFSET		10
++/* Clock status register */
++#define LTQ_SYSCTL_CLKS		0x0000
++/* Clock enable register */
++#define LTQ_SYSCTL_CLKEN	0x0004
++/* Clock clear register */
++#define LTQ_SYSCTL_CLKCLR	0x0008
++/* Activation Status Register */
++#define LTQ_SYSCTL_ACTS		0x0020
++/* Activation Register */
++#define LTQ_SYSCTL_ACT		0x0024
++/* Deactivation Register */
++#define LTQ_SYSCTL_DEACT	0x0028
++/* reboot Register */
++#define LTQ_SYSCTL_RBT		0x002c
++
++static struct resource ltq_sysctl_res[] = {
++	MEM_RES("sys1", LTQ_SYS1_BASE_ADDR, LTQ_SYS1_SIZE),
++	MEM_RES("syseth", LTQ_SYS_ETH_BASE_ADDR, LTQ_SYS_ETH_SIZE),
++	MEM_RES("sysgpe", LTQ_SYS_GPE_BASE_ADDR, LTQ_SYS_GPE_SIZE),
++};
++
++static struct resource ltq_status_res =
++	MEM_RES("status", LTQ_STATUS_BASE_ADDR, LTQ_STATUS_SIZE);
++static struct resource ltq_ebu_res =
++	MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE);
++
++static void __iomem *ltq_sysctl[3];
++static void __iomem *ltq_status_membase;
++void __iomem *ltq_sys1_membase;
++void __iomem *ltq_ebu_membase;
++
++#define ltq_reg_w32(m, x, y)	ltq_w32((x), ltq_sysctl[m] + (y))
++#define ltq_reg_r32(m, x)	ltq_r32(ltq_sysctl[m] + (x))
++#define ltq_reg_w32_mask(m, clear, set, reg)	\
++		ltq_reg_w32(m, (ltq_reg_r32(m, reg) & ~(clear)) | (set), reg)
++
++#define ltq_status_w32(x, y)	ltq_w32((x), ltq_status_membase + (y))
++#define ltq_status_r32(x)	ltq_r32(ltq_status_membase + (x))
++
++static inline void
++ltq_sysctl_wait(int module, unsigned int mask, unsigned int test)
++{
++	int err = 1000000;
++
++	do {} while (--err && ((ltq_reg_r32(module, LTQ_SYSCTL_ACTS)
++					& mask) != test));
++	if (!err)
++		pr_err("module de/activation failed %d %08X %08X\n",
++							module, mask, test);
++}
++
++void
++ltq_sysctl_activate(int module, unsigned int mask)
++{
++	if (module > SYSCTL_SYSGPE)
++		return;
++
++	ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN);
++	ltq_reg_w32(module, mask, LTQ_SYSCTL_ACT);
++	ltq_sysctl_wait(module, mask, mask);
++}
++EXPORT_SYMBOL(ltq_sysctl_activate);
++
++void
++ltq_sysctl_deactivate(int module, unsigned int mask)
++{
++	if (module > SYSCTL_SYSGPE)
++		return;
++
++	ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR);
++	ltq_reg_w32(module, mask, LTQ_SYSCTL_DEACT);
++	ltq_sysctl_wait(module, mask, 0);
++}
++EXPORT_SYMBOL(ltq_sysctl_deactivate);
++
++void
++ltq_sysctl_clken(int module, unsigned int mask)
++{
++	if (module > SYSCTL_SYSGPE)
++		return;
++
++	ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN);
++	ltq_sysctl_wait(module, mask, mask);
++}
++EXPORT_SYMBOL(ltq_sysctl_clken);
++
++void
++ltq_sysctl_clkdis(int module, unsigned int mask)
++{
++	if (module > SYSCTL_SYSGPE)
++		return;
++
++	ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR);
++	ltq_sysctl_wait(module, mask, 0);
++}
++EXPORT_SYMBOL(ltq_sysctl_clkdis);
++
++void
++ltq_sysctl_reboot(int module, unsigned int mask)
++{
++	unsigned int act;
++
++	if (module > SYSCTL_SYSGPE)
++		return;
++
++	act = ltq_reg_r32(module, LTQ_SYSCTL_ACT);
++	if ((~act & mask) != 0)
++		ltq_sysctl_activate(module, ~act & mask);
++	ltq_reg_w32(module, act & mask, LTQ_SYSCTL_RBT);
++	ltq_sysctl_wait(module, mask, mask);
++}
++EXPORT_SYMBOL(ltq_sysctl_reboot);
++
++/* enable the ONU core */
++static void
++ltq_gpe_enable(void)
++{
++	unsigned int freq;
++	unsigned int status;
++
++	/* if if the clock is already enabled */
++	status = ltq_reg_r32(SYSCTL_SYS1, SYS1_INFRAC);
++	if (status & (1 << (GPPC_OFFSET + 1)))
++		return;
++
++	if (ltq_status_r32(STATUS_CONFIG) == 0)
++		freq = 1; /* use 625MHz on unfused chip */
++	else
++		freq = (ltq_status_r32(STATUS_CONFIG) &
++			GPEFREQ_MASK) >>
++			GPEFREQ_OFFSET;
++
++	/* apply new frequency */
++	ltq_reg_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1),
++		freq << (GPPC_OFFSET + 2) , SYS1_INFRAC);
++	udelay(1);
++
++	/* enable new frequency */
++	ltq_reg_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC);
++	udelay(1);
++}
++
++void __init
++ltq_soc_init(void)
++{
++	int i;
++
++	for (i = 0; i < 3; i++)
++		ltq_sysctl[i] = ltq_remap_resource(&ltq_sysctl_res[i]);
++
++	ltq_sys1_membase = ltq_sysctl[0];
++	ltq_status_membase = ltq_remap_resource(&ltq_status_res);
++	ltq_ebu_membase = ltq_remap_resource(&ltq_ebu_res);
++
++	ltq_gpe_enable();
++}
+-- 
+1.7.5.4
+
diff --git a/target/linux/lantiq/patches-3.0/0007-MIPS-lantiq-add-support-for-FALC-ON-GPIOs.patch b/target/linux/lantiq/patches-3.0/0007-MIPS-lantiq-add-support-for-FALC-ON-GPIOs.patch
new file mode 100644
index 0000000000..0d8b92d1b8
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/0007-MIPS-lantiq-add-support-for-FALC-ON-GPIOs.patch
@@ -0,0 +1,501 @@
+From 02d9df56be1ba23c7bec51c94e5d2ac0d13d2d78 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 11 Aug 2011 14:35:02 +0200
+Subject: [PATCH 07/24] MIPS: lantiq: add support for FALC-ON GPIOs
+
+FALC-ON uses a different GPIO core than the other Lantiq SoCs. This patch adds
+the new driver.
+
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Cc: linux-mips@linux-mips.org
+---
+ arch/mips/lantiq/falcon/Makefile  |    2 +-
+ arch/mips/lantiq/falcon/devices.c |   41 ++++
+ arch/mips/lantiq/falcon/devices.h |    2 +
+ arch/mips/lantiq/falcon/gpio.c    |  398 +++++++++++++++++++++++++++++++++++++
+ 4 files changed, 442 insertions(+), 1 deletions(-)
+ create mode 100644 arch/mips/lantiq/falcon/gpio.c
+
+diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile
+index e9c7455..de72209 100644
+--- a/arch/mips/lantiq/falcon/Makefile
++++ b/arch/mips/lantiq/falcon/Makefile
+@@ -1 +1 @@
+-obj-y := clk.o prom.o reset.o sysctrl.o devices.o
++obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o
+diff --git a/arch/mips/lantiq/falcon/devices.c b/arch/mips/lantiq/falcon/devices.c
+index c4606f2..4f47b44 100644
+--- a/arch/mips/lantiq/falcon/devices.c
++++ b/arch/mips/lantiq/falcon/devices.c
+@@ -9,6 +9,7 @@
+ 
+ #include <linux/platform_device.h>
+ #include <linux/mtd/nand.h>
++#include <linux/gpio.h>
+ 
+ #include <lantiq_soc.h>
+ 
+@@ -85,3 +86,43 @@ falcon_register_nand(void)
+ {
+ 	platform_device_register(&ltq_flash_nand);
+ }
++
++/* gpio */
++#define DECLARE_GPIO_RES(port) \
++static struct resource falcon_gpio ## port ## _res[] = { \
++	MEM_RES("gpio"#port, LTQ_GPIO ## port ## _BASE_ADDR, \
++		LTQ_GPIO ## port ## _SIZE), \
++	MEM_RES("padctrl"#port, LTQ_PADCTRL ## port ## _BASE_ADDR, \
++		LTQ_PADCTRL ## port ## _SIZE), \
++	IRQ_RES("gpio_mux"#port, FALCON_IRQ_GPIO_P ## port) \
++}
++DECLARE_GPIO_RES(0);
++DECLARE_GPIO_RES(1);
++DECLARE_GPIO_RES(2);
++DECLARE_GPIO_RES(3);
++DECLARE_GPIO_RES(4);
++
++void __init
++falcon_register_gpio(void)
++{
++	platform_device_register_simple("falcon_gpio", 0,
++		falcon_gpio0_res, ARRAY_SIZE(falcon_gpio0_res));
++	platform_device_register_simple("falcon_gpio", 1,
++		falcon_gpio1_res, ARRAY_SIZE(falcon_gpio1_res));
++	platform_device_register_simple("falcon_gpio", 2,
++		falcon_gpio2_res, ARRAY_SIZE(falcon_gpio2_res));
++	ltq_sysctl_activate(SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1);
++	ltq_sysctl_activate(SYSCTL_SYSETH, ACTS_PADCTRL0 |
++		ACTS_PADCTRL2 | ACTS_P0 | ACTS_P2);
++}
++
++void __init
++falcon_register_gpio_extra(void)
++{
++	platform_device_register_simple("falcon_gpio", 3,
++		falcon_gpio3_res, ARRAY_SIZE(falcon_gpio3_res));
++	platform_device_register_simple("falcon_gpio", 4,
++		falcon_gpio4_res, ARRAY_SIZE(falcon_gpio4_res));
++	ltq_sysctl_activate(SYSCTL_SYS1,
++		ACTS_PADCTRL3 | ACTS_PADCTRL4 | ACTS_P3 | ACTS_P4);
++}
+diff --git a/arch/mips/lantiq/falcon/devices.h b/arch/mips/lantiq/falcon/devices.h
+index e802a7c..18be8b6 100644
+--- a/arch/mips/lantiq/falcon/devices.h
++++ b/arch/mips/lantiq/falcon/devices.h
+@@ -14,5 +14,7 @@
+ #include "../devices.h"
+ 
+ extern void falcon_register_nand(void);
++extern void falcon_register_gpio(void);
++extern void falcon_register_gpio_extra(void);
+ 
+ #endif
+diff --git a/arch/mips/lantiq/falcon/gpio.c b/arch/mips/lantiq/falcon/gpio.c
+new file mode 100644
+index 0000000..b87582d
+--- /dev/null
++++ b/arch/mips/lantiq/falcon/gpio.c
+@@ -0,0 +1,398 @@
++/*
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ *
++ *  Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
++ *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/gpio.h>
++#include <linux/interrupt.h>
++#include <linux/slab.h>
++#include <linux/platform_device.h>
++
++#include <lantiq_soc.h>
++
++/* Multiplexer Control Register */
++#define LTQ_PADC_MUX(x)         (x * 0x4)
++/* Pad Control Availability Register */
++#define LTQ_PADC_AVAIL          0x000000F0
++
++/* Data Output Register */
++#define LTQ_GPIO_OUT            0x00000000
++/* Data Input Register */
++#define LTQ_GPIO_IN             0x00000004
++/* Direction Register */
++#define LTQ_GPIO_DIR            0x00000008
++/* External Interrupt Control Register 0 */
++#define LTQ_GPIO_EXINTCR0       0x00000018
++/* External Interrupt Control Register 1 */
++#define LTQ_GPIO_EXINTCR1       0x0000001C
++/* IRN Capture Register */
++#define LTQ_GPIO_IRNCR          0x00000020
++/* IRN Interrupt Configuration Register */
++#define LTQ_GPIO_IRNCFG		0x0000002C
++/* IRN Interrupt Enable Set Register */
++#define LTQ_GPIO_IRNRNSET       0x00000030
++/* IRN Interrupt Enable Clear Register */
++#define LTQ_GPIO_IRNENCLR       0x00000034
++/* Output Set Register */
++#define LTQ_GPIO_OUTSET         0x00000040
++/* Output Cler Register */
++#define LTQ_GPIO_OUTCLR         0x00000044
++/* Direction Clear Register */
++#define LTQ_GPIO_DIRSET         0x00000048
++/* Direction Set Register */
++#define LTQ_GPIO_DIRCLR         0x0000004C
++
++/* turn a gpio_chip into a falcon_gpio_port */
++#define ctop(c)		container_of(c, struct falcon_gpio_port, gpio_chip)
++/* turn a irq_data into a falcon_gpio_port */
++#define itop(i)		((struct falcon_gpio_port *) irq_get_chip_data(i->irq))
++
++#define ltq_pad_r32(p, reg)		ltq_r32(p->pad + reg)
++#define ltq_pad_w32(p, val, reg)	ltq_w32(val, p->pad + reg)
++#define ltq_pad_w32_mask(c, clear, set, reg) \
++		ltq_pad_w32(c, (ltq_pad_r32(c, reg) & ~(clear)) | (set), reg)
++
++#define ltq_port_r32(p, reg)		ltq_r32(p->port + reg)
++#define ltq_port_w32(p, val, reg)	ltq_w32(val, p->port + reg)
++#define ltq_port_w32_mask(p, clear, set, reg) \
++		ltq_port_w32(p, (ltq_port_r32(p, reg) & ~(clear)) | (set), reg)
++
++#define MAX_PORTS		5
++#define PINS_PER_PORT		32
++
++struct falcon_gpio_port {
++	struct gpio_chip gpio_chip;
++	void __iomem *pad;
++	void __iomem *port;
++	unsigned int irq_base;
++	unsigned int chained_irq;
++};
++
++static struct falcon_gpio_port ltq_gpio_port[MAX_PORTS];
++
++int gpio_to_irq(unsigned int gpio)
++{
++	return __gpio_to_irq(gpio);
++}
++EXPORT_SYMBOL(gpio_to_irq);
++
++int ltq_gpio_mux_set(unsigned int pin, unsigned int mux)
++{
++	int port = pin / 100;
++	int offset = pin % 100;
++	struct falcon_gpio_port *gpio_port;
++
++	if ((offset >= PINS_PER_PORT) || (port >= MAX_PORTS))
++		return -EINVAL;
++
++	gpio_port = &ltq_gpio_port[port];
++	ltq_pad_w32(gpio_port, mux & 0x3, LTQ_PADC_MUX(offset));
++
++	return 0;
++}
++EXPORT_SYMBOL(ltq_gpio_mux_set);
++
++int ltq_gpio_request(unsigned int pin, unsigned int val,
++		unsigned int dir, const char *name)
++{
++	int port = pin / 100;
++	int offset = pin % 100;
++
++	if (offset >= PINS_PER_PORT || port >= MAX_PORTS)
++		return -EINVAL;
++
++	if (gpio_request(pin, name)) {
++		pr_err("failed to setup lantiq gpio: %s\n", name);
++		return -EBUSY;
++	}
++
++	if (dir)
++		gpio_direction_output(pin, 1);
++	else
++		gpio_direction_input(pin);
++
++	return ltq_gpio_mux_set(pin, val);
++}
++EXPORT_SYMBOL(ltq_gpio_request);
++
++static int
++falcon_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
++{
++	ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRCLR);
++
++	return 0;
++}
++
++static void
++falcon_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
++{
++	if (value)
++		ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTSET);
++	else
++		ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTCLR);
++}
++
++static int
++falcon_gpio_direction_output(struct gpio_chip *chip,
++			unsigned int offset, int value)
++{
++	falcon_gpio_set(chip, offset, value);
++	ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRSET);
++
++	return 0;
++}
++
++static int
++falcon_gpio_get(struct gpio_chip *chip, unsigned int offset)
++{
++	if ((ltq_port_r32(ctop(chip), LTQ_GPIO_DIR) >> offset) & 1)
++		return (ltq_port_r32(ctop(chip), LTQ_GPIO_OUT) >> offset) & 1;
++	else
++		return (ltq_port_r32(ctop(chip), LTQ_GPIO_IN) >> offset) & 1;
++}
++
++static int
++falcon_gpio_request(struct gpio_chip *chip, unsigned offset)
++{
++	if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) {
++		if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1)
++			return -EBUSY;
++		/* switch on gpio function */
++		ltq_pad_w32(ctop(chip), 1, LTQ_PADC_MUX(offset));
++		return 0;
++	}
++
++	return -ENODEV;
++}
++
++static void
++falcon_gpio_free(struct gpio_chip *chip, unsigned offset)
++{
++	if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) {
++		if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1)
++			return;
++		/* switch off gpio function */
++		ltq_pad_w32(ctop(chip), 0, LTQ_PADC_MUX(offset));
++	}
++}
++
++static int
++falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
++{
++	return ctop(chip)->irq_base + offset;
++}
++
++static void
++falcon_gpio_disable_irq(struct irq_data *d)
++{
++	unsigned int offset = d->irq - itop(d)->irq_base;
++
++	ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR);
++}
++
++static void
++falcon_gpio_enable_irq(struct irq_data *d)
++{
++	unsigned int offset = d->irq - itop(d)->irq_base;
++
++	if (!ltq_pad_r32(itop(d), LTQ_PADC_MUX(offset)) < 1)
++		/* switch on gpio function */
++		ltq_pad_w32(itop(d), 1, LTQ_PADC_MUX(offset));
++
++	ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNRNSET);
++}
++
++static void
++falcon_gpio_ack_irq(struct irq_data *d)
++{
++	unsigned int offset = d->irq - itop(d)->irq_base;
++
++	ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR);
++}
++
++static void
++falcon_gpio_mask_and_ack_irq(struct irq_data *d)
++{
++	unsigned int offset = d->irq - itop(d)->irq_base;
++
++	ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR);
++	ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR);
++}
++
++static struct irq_chip falcon_gpio_irq_chip;
++static int
++falcon_gpio_irq_type(struct irq_data *d, unsigned int type)
++{
++	unsigned int offset = d->irq - itop(d)->irq_base;
++	unsigned int mask = 1 << offset;
++
++	if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
++		return 0;
++
++	if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) {
++		/* level triggered */
++		ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_IRNCFG);
++		irq_set_chip_and_handler_name(d->irq,
++				&falcon_gpio_irq_chip, handle_level_irq, "mux");
++	} else {
++		/* edge triggered */
++		ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_IRNCFG);
++		irq_set_chip_and_handler_name(d->irq,
++			&falcon_gpio_irq_chip, handle_simple_irq, "mux");
++	}
++
++	if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
++		ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0);
++		ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR1);
++	} else {
++		if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) != 0)
++			/* positive logic: rising edge, high level */
++			ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0);
++		else
++			/* negative logic: falling edge, low level */
++			ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR0);
++		ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR1);
++	}
++
++	return gpio_direction_input(itop(d)->gpio_chip.base + offset);
++}
++
++static void
++falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
++{
++	struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc);
++	unsigned long irncr;
++	int offset;
++
++	/* acknowledge interrupt */
++	irncr = ltq_port_r32(gpio_port, LTQ_GPIO_IRNCR);
++	ltq_port_w32(gpio_port, irncr, LTQ_GPIO_IRNCR);
++
++	desc->irq_data.chip->irq_ack(&desc->irq_data);
++
++	for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio)
++		generic_handle_irq(gpio_port->irq_base + offset);
++}
++
++static struct irq_chip falcon_gpio_irq_chip = {
++	.name = "gpio_irq_mux",
++	.irq_mask = falcon_gpio_disable_irq,
++	.irq_unmask = falcon_gpio_enable_irq,
++	.irq_ack = falcon_gpio_ack_irq,
++	.irq_mask_ack = falcon_gpio_mask_and_ack_irq,
++	.irq_set_type = falcon_gpio_irq_type,
++};
++
++static struct irqaction gpio_cascade = {
++	.handler = no_action,
++	.flags = IRQF_DISABLED,
++	.name = "gpio_cascade",
++};
++
++static int
++falcon_gpio_probe(struct platform_device *pdev)
++{
++	struct falcon_gpio_port *gpio_port;
++	int ret, i;
++	struct resource *gpiores, *padres;
++	int irq;
++
++	if (pdev->id >= MAX_PORTS)
++		return -ENODEV;
++
++	gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	padres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++	irq = platform_get_irq(pdev, 0);
++	if (!gpiores || !padres)
++		return -ENODEV;
++
++	gpio_port = &ltq_gpio_port[pdev->id];
++	gpio_port->gpio_chip.label = "falcon-gpio";
++	gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input;
++	gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output;
++	gpio_port->gpio_chip.get = falcon_gpio_get;
++	gpio_port->gpio_chip.set = falcon_gpio_set;
++	gpio_port->gpio_chip.request = falcon_gpio_request;
++	gpio_port->gpio_chip.free = falcon_gpio_free;
++	gpio_port->gpio_chip.base = 100 * pdev->id;
++	gpio_port->gpio_chip.ngpio = 32;
++	gpio_port->gpio_chip.dev = &pdev->dev;
++
++	gpio_port->port = ltq_remap_resource(gpiores);
++	gpio_port->pad = ltq_remap_resource(padres);
++
++	if (!gpio_port->port || !gpio_port->pad) {
++		dev_err(&pdev->dev, "Could not map io ranges\n");
++		ret = -ENOMEM;
++		goto err;
++	}
++
++	if (irq > 0) {
++		/* irq_chip support */
++		gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq;
++		gpio_port->irq_base = INT_NUM_EXTRA_START + (32 * pdev->id);
++
++		for (i = 0; i < 32; i++) {
++			irq_set_chip_and_handler_name(gpio_port->irq_base + i,
++				&falcon_gpio_irq_chip, handle_simple_irq,
++				"mux");
++			irq_set_chip_data(gpio_port->irq_base + i, gpio_port);
++			/* set to negative logic (falling edge, low level) */
++			ltq_port_w32_mask(gpio_port, 0, 1 << i,
++				LTQ_GPIO_EXINTCR0);
++		}
++
++		gpio_port->chained_irq = irq;
++		setup_irq(irq, &gpio_cascade);
++		irq_set_handler_data(irq, gpio_port);
++		irq_set_chained_handler(irq, falcon_gpio_irq_handler);
++	}
++
++	ret = gpiochip_add(&gpio_port->gpio_chip);
++	if (ret < 0) {
++		dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n",
++			pdev->id, ret);
++		goto err;
++	}
++	platform_set_drvdata(pdev, gpio_port);
++	return ret;
++
++err:
++	dev_err(&pdev->dev, "Error in gpio_probe %d, %d\n", pdev->id, ret);
++	if (gpiores)
++		release_resource(gpiores);
++	if (padres)
++		release_resource(padres);
++
++	if (gpio_port->port)
++		iounmap(gpio_port->port);
++	if (gpio_port->pad)
++		iounmap(gpio_port->pad);
++	return ret;
++}
++
++static struct platform_driver falcon_gpio_driver = {
++	.probe = falcon_gpio_probe,
++	.driver = {
++		.name = "falcon_gpio",
++		.owner = THIS_MODULE,
++	},
++};
++
++int __init
++falcon_gpio_init(void)
++{
++	int ret;
++
++	pr_info("FALC(tm) ON GPIO Driver, (C) 2011 Lantiq Deutschland Gmbh\n");
++	ret = platform_driver_register(&falcon_gpio_driver);
++	if (ret)
++		pr_err("falcon_gpio: Error registering platform driver!");
++	return ret;
++}
++
++postcore_initcall(falcon_gpio_init);
+-- 
+1.7.5.4
+
diff --git a/target/linux/lantiq/patches-3.0/0008-MIPS-lantiq-add-support-for-the-EASY98000-evaluation.patch b/target/linux/lantiq/patches-3.0/0008-MIPS-lantiq-add-support-for-the-EASY98000-evaluation.patch
new file mode 100644
index 0000000000..2383584ecf
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/0008-MIPS-lantiq-add-support-for-the-EASY98000-evaluation.patch
@@ -0,0 +1,179 @@
+From ec6ba0f79c010a878d679c057fb6306b50a201b0 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 11 Aug 2011 14:09:35 +0200
+Subject: [PATCH 08/24] MIPS: lantiq: add support for the EASY98000 evaluation
+ board
+
+This patch adds the machine code for the EASY9800 evaluation board.
+
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Cc: linux-mips@linux-mips.org
+---
+ arch/mips/lantiq/falcon/Kconfig          |   11 +++
+ arch/mips/lantiq/falcon/Makefile         |    1 +
+ arch/mips/lantiq/falcon/mach-easy98000.c |  110 ++++++++++++++++++++++++++++++
+ arch/mips/lantiq/machtypes.h             |    5 ++
+ 4 files changed, 127 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/lantiq/falcon/Kconfig
+ create mode 100644 arch/mips/lantiq/falcon/mach-easy98000.c
+
+diff --git a/arch/mips/lantiq/falcon/Kconfig b/arch/mips/lantiq/falcon/Kconfig
+new file mode 100644
+index 0000000..03e999d
+--- /dev/null
++++ b/arch/mips/lantiq/falcon/Kconfig
+@@ -0,0 +1,11 @@
++if SOC_FALCON
++
++menu "MIPS Machine"
++
++config LANTIQ_MACH_EASY98000
++	bool "Easy98000"
++	default y
++
++endmenu
++
++endif
+diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile
+index de72209..56b22eb 100644
+--- a/arch/mips/lantiq/falcon/Makefile
++++ b/arch/mips/lantiq/falcon/Makefile
+@@ -1 +1,2 @@
+ obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o
++obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o
+diff --git a/arch/mips/lantiq/falcon/mach-easy98000.c b/arch/mips/lantiq/falcon/mach-easy98000.c
+new file mode 100644
+index 0000000..361b8f0
+--- /dev/null
++++ b/arch/mips/lantiq/falcon/mach-easy98000.c
+@@ -0,0 +1,110 @@
++/*
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ *
++ *  Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
++ *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/platform_device.h>
++#include <linux/mtd/partitions.h>
++#include <linux/spi/spi.h>
++#include <linux/spi/spi_gpio.h>
++#include <linux/spi/eeprom.h>
++
++#include "../machtypes.h"
++
++#include "devices.h"
++
++static struct mtd_partition easy98000_nor_partitions[] = {
++	{
++		.name	= "uboot",
++		.offset	= 0x0,
++		.size	= 0x40000,
++	},
++	{
++		.name	= "uboot_env",
++		.offset	= 0x40000,
++		.size	= 0x40000,	/* 2 sectors for redundant env. */
++	},
++	{
++		.name	= "linux",
++		.offset	= 0x80000,
++		.size	= 0xF80000,	/* map only 16 MiB */
++	},
++};
++
++struct physmap_flash_data easy98000_nor_flash_data = {
++	.nr_parts	= ARRAY_SIZE(easy98000_nor_partitions),
++	.parts		= easy98000_nor_partitions,
++};
++
++/* setup gpio based spi bus/device for access to the eeprom on the board */
++#define SPI_GPIO_MRST		102
++#define SPI_GPIO_MTSR		103
++#define SPI_GPIO_CLK		104
++#define SPI_GPIO_CS0		105
++#define SPI_GPIO_CS1		106
++#define SPI_GPIO_BUS_NUM	1
++
++static struct spi_gpio_platform_data easy98000_spi_gpio_data = {
++	.sck		= SPI_GPIO_CLK,
++	.mosi		= SPI_GPIO_MTSR,
++	.miso		= SPI_GPIO_MRST,
++	.num_chipselect	= 2,
++};
++
++static struct platform_device easy98000_spi_gpio_device = {
++	.name			= "spi_gpio",
++	.id			= SPI_GPIO_BUS_NUM,
++	.dev.platform_data	= &easy98000_spi_gpio_data,
++};
++
++static struct spi_eeprom at25160n = {
++	.byte_len	= 16 * 1024 / 8,
++	.name		= "at25160n",
++	.page_size	= 32,
++	.flags		= EE_ADDR2,
++};
++
++static struct spi_board_info easy98000_spi_gpio_devices __initdata = {
++	.modalias		= "at25",
++	.bus_num		= SPI_GPIO_BUS_NUM,
++	.max_speed_hz		= 1000 * 1000,
++	.mode			= SPI_MODE_3,
++	.chip_select		= 1,
++	.controller_data	= (void *) SPI_GPIO_CS1,
++	.platform_data		= &at25160n,
++};
++
++static void __init
++easy98000_init_common(void)
++{
++	spi_register_board_info(&easy98000_spi_gpio_devices, 1);
++	platform_device_register(&easy98000_spi_gpio_device);
++}
++
++static void __init
++easy98000_init(void)
++{
++	easy98000_init_common();
++	ltq_register_nor(&easy98000_nor_flash_data);
++}
++
++static void __init
++easy98000nand_init(void)
++{
++	easy98000_init_common();
++	falcon_register_nand();
++}
++
++MIPS_MACHINE(LANTIQ_MACH_EASY98000,
++			"EASY98000",
++			"EASY98000 Eval Board",
++			easy98000_init);
++
++MIPS_MACHINE(LANTIQ_MACH_EASY98000NAND,
++			"EASY98000NAND",
++			"EASY98000 Eval Board (NAND Flash)",
++			easy98000nand_init);
+diff --git a/arch/mips/lantiq/machtypes.h b/arch/mips/lantiq/machtypes.h
+index 7e01b8c..dfc6af7 100644
+--- a/arch/mips/lantiq/machtypes.h
++++ b/arch/mips/lantiq/machtypes.h
+@@ -15,6 +15,11 @@ enum lantiq_mach_type {
+ 	LTQ_MACH_GENERIC = 0,
+ 	LTQ_MACH_EASY50712,	/* Danube evaluation board */
+ 	LTQ_MACH_EASY50601,	/* Amazon SE evaluation board */
++
++	/* FALCON */
++	LANTIQ_MACH_EASY98000,		/* Falcon Eval Board, NOR Flash */
++	LANTIQ_MACH_EASY98000SF,	/* Falcon Eval Board, Serial Flash */
++	LANTIQ_MACH_EASY98000NAND,	/* Falcon Eval Board, NAND Flash */
+ };
+ 
+ #endif
+-- 
+1.7.5.4
+
diff --git a/target/linux/lantiq/patches-3.0/0009-MIPS-make-oprofile-use-cp0_perfcount_irq-if-it-is-se.patch b/target/linux/lantiq/patches-3.0/0009-MIPS-make-oprofile-use-cp0_perfcount_irq-if-it-is-se.patch
new file mode 100644
index 0000000000..ed35805046
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/0009-MIPS-make-oprofile-use-cp0_perfcount_irq-if-it-is-se.patch
@@ -0,0 +1,56 @@
+From 88bb1794592e3fe9c8d65ce73ee851e11dbbd26b Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 24 Aug 2011 13:24:11 +0200
+Subject: [PATCH 09/24] MIPS: make oprofile use cp0_perfcount_irq if it is set
+
+The patch makes the oprofile code use the performance counters irq.
+
+This patch is written by Felix Fietkau.
+
+Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Cc: linux-mips@linux-mips.org
+---
+ arch/mips/oprofile/op_model_mipsxx.c |   12 ++++++++++++
+ 1 files changed, 12 insertions(+), 0 deletions(-)
+
+diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
+index 54759f1..86cf234 100644
+--- a/arch/mips/oprofile/op_model_mipsxx.c
++++ b/arch/mips/oprofile/op_model_mipsxx.c
+@@ -298,6 +298,11 @@ static void reset_counters(void *arg)
+ 	}
+ }
+ 
++static irqreturn_t mipsxx_perfcount_int(int irq, void *dev_id)
++{
++	return mipsxx_perfcount_handler();
++}
++
+ static int __init mipsxx_init(void)
+ {
+ 	int counters;
+@@ -374,6 +379,10 @@ static int __init mipsxx_init(void)
+ 	save_perf_irq = perf_irq;
+ 	perf_irq = mipsxx_perfcount_handler;
+ 
++	if (cp0_perfcount_irq >= 0)
++		return request_irq(cp0_perfcount_irq, mipsxx_perfcount_int,
++			IRQF_SHARED, "Perfcounter", save_perf_irq);
++
+ 	return 0;
+ }
+ 
+@@ -381,6 +390,9 @@ static void mipsxx_exit(void)
+ {
+ 	int counters = op_model_mipsxx_ops.num_counters;
+ 
++	if (cp0_perfcount_irq >= 0)
++		free_irq(cp0_perfcount_irq, save_perf_irq);
++
+ 	counters = counters_per_cpu_to_total(counters);
+ 	on_each_cpu(reset_counters, (void *)(long)counters, 1);
+ 
+-- 
+1.7.5.4
+
diff --git a/target/linux/lantiq/patches-3.0/0010-MIPS-enable-oprofile-support-on-lantiq-targets.patch b/target/linux/lantiq/patches-3.0/0010-MIPS-enable-oprofile-support-on-lantiq-targets.patch
new file mode 100644
index 0000000000..2f6d1a13bb
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/0010-MIPS-enable-oprofile-support-on-lantiq-targets.patch
@@ -0,0 +1,52 @@
+From cc4b9cdff8665a414ae51101d3a0ca6ed7444a27 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 24 Aug 2011 13:28:55 +0200
+Subject: [PATCH 10/24] MIPS: enable oprofile support on lantiq targets
+
+This patch sets the performance counters irq and HAVE_OPROFILE flag.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Cc: linux-mips@linux-mips.org
+---
+ arch/mips/Kconfig      |    1 +
+ arch/mips/lantiq/irq.c |    5 +++++
+ 2 files changed, 6 insertions(+), 0 deletions(-)
+
+diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
+index b122adc..0cf5bbd 100644
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -230,6 +230,7 @@ config LANTIQ
+ 	select SWAP_IO_SPACE
+ 	select BOOT_RAW
+ 	select HAVE_CLK
++	select HAVE_OPROFILE
+ 	select MIPS_MACHINE
+ 
+ config LASAT
+diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
+index 17c057f..0b2ed87 100644
+--- a/arch/mips/lantiq/irq.c
++++ b/arch/mips/lantiq/irq.c
+@@ -40,6 +40,9 @@
+ 
+ #define MAX_EIU			6
+ 
++/* the performance counter */
++#define LTQ_PERF_IRQ		(INT_NUM_IM4_IRL0 + 31)
++
+ /* irqs generated by device attached to the EBU need to be acked in
+  * a special manner
+  */
+@@ -318,6 +321,8 @@ void __init arch_init_irq(void)
+ 	set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
+ 		IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
+ #endif
++
++	cp0_perfcount_irq = LTQ_PERF_IRQ;
+ }
+ 
+ unsigned int __cpuinit get_c0_compare_int(void)
+-- 
+1.7.5.4
+
diff --git a/target/linux/lantiq/patches-3.0/120-falcon-i2c.patch b/target/linux/lantiq/patches-3.0/0011-MIPS-lantiq-adds-falcon-I2C.patch
index 2def0a802a..84af96fae4 100644
--- a/target/linux/lantiq/patches-3.0/120-falcon-i2c.patch
+++ b/target/linux/lantiq/patches-3.0/0011-MIPS-lantiq-adds-falcon-I2C.patch
@@ -1,12 +1,59 @@
---- a/drivers/i2c/busses/Makefile
-+++ b/drivers/i2c/busses/Makefile
-@@ -82,5 +82,6 @@ obj-$(CONFIG_I2C_SIBYTE)	+= i2c-sibyte.o
- obj-$(CONFIG_I2C_STUB)		+= i2c-stub.o
- obj-$(CONFIG_SCx200_ACB)	+= scx200_acb.o
- obj-$(CONFIG_SCx200_I2C)	+= scx200_i2c.o
-+obj-$(CONFIG_I2C_FALCON)	+= i2c-falcon.o
+From 6437f41dfdf9475178e22ab0dd886af033f90cc2 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 29 Sep 2011 21:10:16 +0200
+Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C
+
+---
+ arch/mips/lantiq/falcon/devices.c |   21 +
+ arch/mips/lantiq/falcon/devices.h |    1 +
+ drivers/i2c/busses/Kconfig        |    4 +
+ drivers/i2c/busses/Makefile       |    1 +
+ drivers/i2c/busses/i2c-falcon.c   |  815 +++++++++++++++++++++++++++++++++++++
+ 5 files changed, 842 insertions(+), 0 deletions(-)
+ create mode 100644 drivers/i2c/busses/i2c-falcon.c
+
+diff --git a/arch/mips/lantiq/falcon/devices.c b/arch/mips/lantiq/falcon/devices.c
+index 4f47b44..a998b6b 100644
+--- a/arch/mips/lantiq/falcon/devices.c
++++ b/arch/mips/lantiq/falcon/devices.c
+@@ -126,3 +126,24 @@ falcon_register_gpio_extra(void)
+ 	ltq_sysctl_activate(SYSCTL_SYS1,
+ 		ACTS_PADCTRL3 | ACTS_PADCTRL4 | ACTS_P3 | ACTS_P4);
+ }
++
++/* i2c */
++static struct resource falcon_i2c_resources[] = {
++	MEM_RES("i2c", GPON_I2C_BASE,GPON_I2C_END),
++	IRQ_RES("i2c_lb", FALCON_IRQ_I2C_LBREQ),
++	IRQ_RES("i2c_b", FALCON_IRQ_I2C_BREQ),
++	IRQ_RES("i2c_err", FALCON_IRQ_I2C_I2C_ERR),
++	IRQ_RES("i2c_p", FALCON_IRQ_I2C_I2C_P),
++};
++
++void __init falcon_register_i2c(void)
++{
++	platform_device_register_simple("i2c-falcon", 0,
++	falcon_i2c_resources, ARRAY_SIZE(falcon_i2c_resources));
++	sys1_hw_activate(ACTS_I2C_ACT);
++}
++
++void __init falcon_register_crypto(void)
++{
++	platform_device_register_simple("ltq_falcon_deu", 0, NULL, 0);
++}
+diff --git a/arch/mips/lantiq/falcon/devices.h b/arch/mips/lantiq/falcon/devices.h
+index 18be8b6..2fdcb08 100644
+--- a/arch/mips/lantiq/falcon/devices.h
++++ b/arch/mips/lantiq/falcon/devices.h
+@@ -16,5 +16,6 @@
+ extern void falcon_register_nand(void);
+ extern void falcon_register_gpio(void);
+ extern void falcon_register_gpio_extra(void);
++extern void falcon_register_i2c(void);
  
- ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG
+ #endif
+diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
+index 646068e..e6c3ab6 100644
 --- a/drivers/i2c/busses/Kconfig
 +++ b/drivers/i2c/busses/Kconfig
 @@ -284,6 +284,10 @@ config I2C_POWERMAC
@@ -20,6 +67,20 @@
  config I2C_AT91
  	tristate "Atmel AT91 I2C Two-Wire interface (TWI)"
  	depends on ARCH_AT91 && EXPERIMENTAL && BROKEN
+diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
+index e6cf294..83e9250 100644
+--- a/drivers/i2c/busses/Makefile
++++ b/drivers/i2c/busses/Makefile
+@@ -82,5 +82,6 @@ obj-$(CONFIG_I2C_SIBYTE)	+= i2c-sibyte.o
+ obj-$(CONFIG_I2C_STUB)		+= i2c-stub.o
+ obj-$(CONFIG_SCx200_ACB)	+= scx200_acb.o
+ obj-$(CONFIG_SCx200_I2C)	+= scx200_i2c.o
++obj-$(CONFIG_I2C_FALCON)	+= i2c-falcon.o
+ 
+ ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG
+diff --git a/drivers/i2c/busses/i2c-falcon.c b/drivers/i2c/busses/i2c-falcon.c
+new file mode 100644
+index 0000000..7bb1253
 --- /dev/null
 +++ b/drivers/i2c/busses/i2c-falcon.c
 @@ -0,0 +1,815 @@
@@ -838,3 +899,6 @@
 +MODULE_ALIAS("platform:" DRV_NAME);
 +MODULE_LICENSE("GPL");
 +MODULE_VERSION(DRV_VERSION);
+-- 
+1.7.5.4
+
diff --git a/target/linux/lantiq/patches-3.0/0012-MIPS-lantiq-adds-GPIO3-support-on-AR9.patch b/target/linux/lantiq/patches-3.0/0012-MIPS-lantiq-adds-GPIO3-support-on-AR9.patch
new file mode 100644
index 0000000000..e20b66b4e3
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/0012-MIPS-lantiq-adds-GPIO3-support-on-AR9.patch
@@ -0,0 +1,212 @@
+From 6b5e2ee7c8f9722d59213f17d423b3f90d80f822 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sat, 13 Aug 2011 13:59:50 +0200
+Subject: [PATCH 12/24] MIPS: lantiq: adds GPIO3 support on AR9
+
+There are 3 16bit and 1 8bit gpio ports on AR9. The gpio driver needs a hack
+at 2 places to make the different register layout of the GPIO3 work properly
+with the driver. Before only GPIO0-2 were supported. As the GPIO number scheme
+clashes with the new size, we also move the other gpio chips to new offsets.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+---
+ .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |    2 +
+ arch/mips/lantiq/xway/devices.c                    |    3 +
+ arch/mips/lantiq/xway/gpio.c                       |   62 ++++++++++++++++----
+ arch/mips/lantiq/xway/gpio_ebu.c                   |    3 +-
+ arch/mips/lantiq/xway/gpio_stp.c                   |    3 +-
+ 5 files changed, 57 insertions(+), 16 deletions(-)
+
+diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+index da8ff95..421768e 100644
+--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+@@ -113,7 +113,9 @@
+ #define LTQ_GPIO0_BASE_ADDR	0x1E100B10
+ #define LTQ_GPIO1_BASE_ADDR	0x1E100B40
+ #define LTQ_GPIO2_BASE_ADDR	0x1E100B70
++#define LTQ_GPIO3_BASE_ADDR	0x1E100BA0
+ #define LTQ_GPIO_SIZE		0x30
++#define LTQ_GPIO3_SIZE		0x10
+ 
+ /* SSC */
+ #define LTQ_SSC_BASE_ADDR	0x1e100800
+diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c
+index 9bacaa8..b7efac5 100644
+--- a/arch/mips/lantiq/xway/devices.c
++++ b/arch/mips/lantiq/xway/devices.c
+@@ -34,6 +34,7 @@ static struct resource ltq_gpio_resource[] = {
+ 	MEM_RES("gpio0", LTQ_GPIO0_BASE_ADDR, LTQ_GPIO_SIZE),
+ 	MEM_RES("gpio1", LTQ_GPIO1_BASE_ADDR, LTQ_GPIO_SIZE),
+ 	MEM_RES("gpio2", LTQ_GPIO2_BASE_ADDR, LTQ_GPIO_SIZE),
++	MEM_RES("gpio3", LTQ_GPIO3_BASE_ADDR, LTQ_GPIO3_SIZE),
+ };
+ 
+ void __init ltq_register_gpio(void)
+@@ -47,6 +48,8 @@ void __init ltq_register_gpio(void)
+ 	if (ltq_is_ar9() || ltq_is_vr9()) {
+ 		platform_device_register_simple("ltq_gpio", 2,
+ 			&ltq_gpio_resource[2], 1);
++		platform_device_register_simple("ltq_gpio", 3,
++			&ltq_gpio_resource[3], 1);
+ 	}
+ }
+ 
+diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c
+index a321451..2c48c17 100644
+--- a/arch/mips/lantiq/xway/gpio.c
++++ b/arch/mips/lantiq/xway/gpio.c
+@@ -21,9 +21,15 @@
+ #define LTQ_GPIO_ALTSEL0	0x0C
+ #define LTQ_GPIO_ALTSEL1	0x10
+ #define LTQ_GPIO_OD		0x14
++#define LTQ_GPIO3_OD		0x24
++#define LTQ_GPIO3_ALTSEL1	0x24
+ 
++/* PORT3 only has 8 pins and its register layout
++   is slightly different */
+ #define PINS_PER_PORT		16
+-#define MAX_PORTS		3
++#define PINS_PORT3		8
++#define MAX_PORTS		4
++#define MAX_PIN			56
+ 
+ #define ltq_gpio_getbit(m, r, p)	(!!(ltq_r32(m + r) & (1 << p)))
+ #define ltq_gpio_setbit(m, r, p)	ltq_w32_mask(0, (1 << p), m + r)
+@@ -53,7 +59,7 @@ int ltq_gpio_request(unsigned int pin, unsigned int alt0,
+ {
+ 	int id = 0;
+ 
+-	if (pin >= (MAX_PORTS * PINS_PER_PORT))
++	if (pin >= MAX_PIN)
+ 		return -EINVAL;
+ 	if (gpio_request(pin, name)) {
+ 		pr_err("failed to setup lantiq gpio: %s\n", name);
+@@ -73,12 +79,21 @@ int ltq_gpio_request(unsigned int pin, unsigned int alt0,
+ 	else
+ 		ltq_gpio_clearbit(ltq_gpio_port[id].membase,
+ 			LTQ_GPIO_ALTSEL0, pin);
+-	if (alt1)
+-		ltq_gpio_setbit(ltq_gpio_port[id].membase,
+-			LTQ_GPIO_ALTSEL1, pin);
+-	else
+-		ltq_gpio_clearbit(ltq_gpio_port[id].membase,
+-			LTQ_GPIO_ALTSEL1, pin);
++	if (id == 3) {
++		if (alt1)
++			ltq_gpio_setbit(ltq_gpio_port[1].membase,
++				LTQ_GPIO3_ALTSEL1, pin);
++		else
++			ltq_gpio_clearbit(ltq_gpio_port[1].membase,
++				LTQ_GPIO3_ALTSEL1, pin);
++	} else {
++		if (alt1)
++			ltq_gpio_setbit(ltq_gpio_port[id].membase,
++				LTQ_GPIO_ALTSEL1, pin);
++		else
++			ltq_gpio_clearbit(ltq_gpio_port[id].membase,
++				LTQ_GPIO_ALTSEL1, pin);
++	}
+ 	return 0;
+ }
+ EXPORT_SYMBOL(ltq_gpio_request);
+@@ -104,7 +119,11 @@ static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
+ {
+ 	struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
+ 
+-	ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
++	if (chip->ngpio == PINS_PORT3)
++		ltq_gpio_clearbit(ltq_gpio_port[0].membase,
++				LTQ_GPIO3_OD, offset);
++	else
++		ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
+ 	ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
+ 
+ 	return 0;
+@@ -115,7 +134,10 @@ static int ltq_gpio_direction_output(struct gpio_chip *chip,
+ {
+ 	struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
+ 
+-	ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
++	if (chip->ngpio == PINS_PORT3)
++		ltq_gpio_setbit(ltq_gpio_port[0].membase, LTQ_GPIO3_OD, offset);
++	else
++		ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
+ 	ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
+ 	ltq_gpio_set(chip, offset, value);
+ 
+@@ -127,7 +149,11 @@ static int ltq_gpio_req(struct gpio_chip *chip, unsigned offset)
+ 	struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
+ 
+ 	ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL0, offset);
+-	ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset);
++	if (chip->ngpio == PINS_PORT3)
++		ltq_gpio_clearbit(ltq_gpio_port[1].membase,
++				LTQ_GPIO3_ALTSEL1, offset);
++	else
++		ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset);
+ 	return 0;
+ }
+ 
+@@ -140,6 +166,15 @@ static int ltq_gpio_probe(struct platform_device *pdev)
+ 			pdev->id);
+ 		return -EINVAL;
+ 	}
++
++	/* dirty hack - The registers of port3 are not mapped linearly.
++	   Port 3 may only load if Port 1/2 are mapped */
++	if ((pdev->id == 3) && (!ltq_gpio_port[1].membase || !ltq_gpio_port[2].membase)) {
++		dev_err(&pdev->dev,
++			"ports 1/2 need to be loaded before port 3 works\n");
++		return -ENOMEM;
++	}
++
+ 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ 	if (!res) {
+ 		dev_err(&pdev->dev, "failed to get memory for gpio port %d\n",
+@@ -169,7 +204,10 @@ static int ltq_gpio_probe(struct platform_device *pdev)
+ 	ltq_gpio_port[pdev->id].chip.set = ltq_gpio_set;
+ 	ltq_gpio_port[pdev->id].chip.request = ltq_gpio_req;
+ 	ltq_gpio_port[pdev->id].chip.base = PINS_PER_PORT * pdev->id;
+-	ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT;
++	if (pdev->id == 3)
++		ltq_gpio_port[pdev->id].chip.ngpio = PINS_PORT3;
++	else
++		ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT;
+ 	platform_set_drvdata(pdev, &ltq_gpio_port[pdev->id]);
+ 	return gpiochip_add(&ltq_gpio_port[pdev->id].chip);
+ }
+diff --git a/arch/mips/lantiq/xway/gpio_ebu.c b/arch/mips/lantiq/xway/gpio_ebu.c
+index a479355..729f8e3 100644
+--- a/arch/mips/lantiq/xway/gpio_ebu.c
++++ b/arch/mips/lantiq/xway/gpio_ebu.c
+@@ -61,9 +61,8 @@ static struct gpio_chip ltq_ebu_chip = {
+ 	.label = "ltq_ebu",
+ 	.direction_output = ltq_ebu_direction_output,
+ 	.set = ltq_ebu_set,
+-	.base = 72,
++	.base = 100,
+ 	.ngpio = 16,
+-	.can_sleep = 1,
+ 	.owner = THIS_MODULE,
+ };
+ 
+diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c
+index 67d59d6..c01294e 100644
+--- a/arch/mips/lantiq/xway/gpio_stp.c
++++ b/arch/mips/lantiq/xway/gpio_stp.c
+@@ -70,9 +70,8 @@ static struct gpio_chip ltq_stp_chip = {
+ 	.label = "ltq_stp",
+ 	.direction_output = ltq_stp_direction_output,
+ 	.set = ltq_stp_set,
+-	.base = 48,
++	.base = 200,
+ 	.ngpio = 24,
+-	.can_sleep = 1,
+ 	.owner = THIS_MODULE,
+ };
+ 
+-- 
+1.7.5.4
+
diff --git a/target/linux/lantiq/patches-3.0/0013-MIPS-lantiq-adds-FALC-ON-spi-driver.patch b/target/linux/lantiq/patches-3.0/0013-MIPS-lantiq-adds-FALC-ON-spi-driver.patch
new file mode 100644
index 0000000000..ddc624f0b8
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/0013-MIPS-lantiq-adds-FALC-ON-spi-driver.patch
@@ -0,0 +1,659 @@
+From 2bd534c30688bcb3f70f1816fbcff813fc746103 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sat, 27 Aug 2011 18:12:26 +0200
+Subject: [PATCH 13/24] MIPS: lantiq: adds FALC-ON spi driver
+
+The external bus unit (EBU) found on the FALC-ON SoC has spi emulation that is
+designed for serial flash access.
+
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/lantiq/falcon/devices.c        |   12 +-
+ arch/mips/lantiq/falcon/devices.h        |    4 +
+ arch/mips/lantiq/falcon/mach-easy98000.c |   27 ++
+ drivers/spi/Kconfig                      |    4 +
+ drivers/spi/Makefile                     |    1 +
+ drivers/spi/spi-falcon.c                 |  477 ++++++++++++++++++++++++++++++
+ 6 files changed, 523 insertions(+), 2 deletions(-)
+ create mode 100644 drivers/spi/spi-falcon.c
+
+Index: linux-3.0.3/arch/mips/lantiq/falcon/devices.c
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/falcon/devices.c	2011-10-05 12:30:34.584838403 +0200
++++ linux-3.0.3/arch/mips/lantiq/falcon/devices.c	2011-10-05 12:42:58.696870214 +0200
+@@ -129,7 +129,7 @@
+ 
+ /* i2c */
+ static struct resource falcon_i2c_resources[] = {
+-	MEM_RES("i2c", GPON_I2C_BASE,GPON_I2C_END),
++	MEM_RES("i2c", LTQ_I2C_BASE_ADDR, LTQ_I2C_SIZE),
+ 	IRQ_RES("i2c_lb", FALCON_IRQ_I2C_LBREQ),
+ 	IRQ_RES("i2c_b", FALCON_IRQ_I2C_BREQ),
+ 	IRQ_RES("i2c_err", FALCON_IRQ_I2C_I2C_ERR),
+@@ -140,10 +140,18 @@
+ {
+ 	platform_device_register_simple("i2c-falcon", 0,
+ 	falcon_i2c_resources, ARRAY_SIZE(falcon_i2c_resources));
+-	sys1_hw_activate(ACTS_I2C_ACT);
++	ltq_sysctl_activate(SYSCTL_SYS1, ACTS_I2C_ACT);
+ }
+ 
+-void __init falcon_register_crypto(void)
++/* spi flash */
++static struct platform_device ltq_spi = {
++	.name			= "falcon_spi",
++	.num_resources		= 0,
++};
++
++void __init
++falcon_register_spi_flash(struct spi_board_info *data)
+ {
+-	platform_device_register_simple("ltq_falcon_deu", 0, NULL, 0);
++	spi_register_board_info(data, 1);
++	platform_device_register(&ltq_spi);
+ }
+Index: linux-3.0.3/arch/mips/lantiq/falcon/devices.h
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/falcon/devices.h	2011-10-05 12:30:34.584838403 +0200
++++ linux-3.0.3/arch/mips/lantiq/falcon/devices.h	2011-10-05 12:30:34.600838405 +0200
+@@ -11,11 +11,15 @@
+ #ifndef _FALCON_DEVICES_H__
+ #define _FALCON_DEVICES_H__
+ 
++#include <linux/spi/spi.h>
++#include <linux/spi/flash.h>
++
+ #include "../devices.h"
+ 
+ extern void falcon_register_nand(void);
+ extern void falcon_register_gpio(void);
+ extern void falcon_register_gpio_extra(void);
+ extern void falcon_register_i2c(void);
++extern void falcon_register_spi_flash(struct spi_board_info *data);
+ 
+ #endif
+Index: linux-3.0.3/arch/mips/lantiq/falcon/mach-easy98000.c
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/falcon/mach-easy98000.c	2011-10-05 12:30:34.552838402 +0200
++++ linux-3.0.3/arch/mips/lantiq/falcon/mach-easy98000.c	2011-10-05 12:30:34.600838405 +0200
+@@ -40,6 +40,21 @@
+ 	.parts		= easy98000_nor_partitions,
+ };
+ 
++static struct flash_platform_data easy98000_spi_flash_platform_data = {
++	.name = "sflash",
++	.parts = easy98000_nor_partitions,
++	.nr_parts = ARRAY_SIZE(easy98000_nor_partitions)
++};
++
++static struct spi_board_info easy98000_spi_flash_data __initdata = {
++	.modalias		= "m25p80",
++	.bus_num		= 0,
++	.chip_select		= 0,
++	.max_speed_hz		= 10 * 1000 * 1000,
++	.mode			= SPI_MODE_3,
++	.platform_data		= &easy98000_spi_flash_platform_data
++};
++
+ /* setup gpio based spi bus/device for access to the eeprom on the board */
+ #define SPI_GPIO_MRST		102
+ #define SPI_GPIO_MTSR		103
+@@ -93,6 +108,13 @@
+ }
+ 
+ static void __init
++easy98000sf_init(void)
++{
++	easy98000_init_common();
++	falcon_register_spi_flash(&easy98000_spi_flash_data);
++}
++
++static void __init
+ easy98000nand_init(void)
+ {
+ 	easy98000_init_common();
+@@ -104,6 +126,11 @@
+ 			"EASY98000 Eval Board",
+ 			easy98000_init);
+ 
++MIPS_MACHINE(LANTIQ_MACH_EASY98000SF,
++			"EASY98000SF",
++			"EASY98000 Eval Board (Serial Flash)",
++			easy98000sf_init);
++
+ MIPS_MACHINE(LANTIQ_MACH_EASY98000NAND,
+ 			"EASY98000NAND",
+ 			"EASY98000 Eval Board (NAND Flash)",
+Index: linux-3.0.3/drivers/spi/Kconfig
+===================================================================
+--- linux-3.0.3.orig/drivers/spi/Kconfig	2011-10-05 12:30:33.608838362 +0200
++++ linux-3.0.3/drivers/spi/Kconfig	2011-10-05 12:41:56.864867570 +0200
+@@ -219,6 +219,10 @@
+ 	  This drivers supports the MPC52xx SPI controller in master SPI
+ 	  mode.
+ 
++config SPI_FALCON
++	tristate "Falcon SPI controller support"
++	depends on SOC_FALCON
++
+ config SPI_MPC52xx_PSC
+ 	tristate "Freescale MPC52xx PSC SPI controller"
+ 	depends on PPC_MPC52xx && EXPERIMENTAL
+Index: linux-3.0.3/drivers/spi/Makefile
+===================================================================
+--- linux-3.0.3.orig/drivers/spi/Makefile	2011-10-05 12:30:33.608838362 +0200
++++ linux-3.0.3/drivers/spi/Makefile	2011-10-05 12:41:56.884867571 +0200
+@@ -56,6 +56,7 @@
+ obj-$(CONFIG_SPI_SH_MSIOF)		+= spi_sh_msiof.o
+ obj-$(CONFIG_SPI_STMP3XXX)		+= spi_stmp.o
+ obj-$(CONFIG_SPI_NUC900)		+= spi_nuc900.o
++obj-$(CONFIG_SPI_FALCON)		+= spi-falcon.o
+ 
+ # special build for s3c24xx spi driver with fiq support
+ spi_s3c24xx_hw-y			:= spi_s3c24xx.o
+Index: linux-3.0.3/drivers/spi/spi-falcon.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-3.0.3/drivers/spi/spi-falcon.c	2011-10-05 12:30:34.600838405 +0200
+@@ -0,0 +1,477 @@
++/*
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ *
++ *  Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
++ */
++
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/spi/spi.h>
++#include <linux/delay.h>
++#include <linux/workqueue.h>
++
++#include <lantiq_soc.h>
++
++#define DRV_NAME			"falcon_spi"
++
++#define FALCON_SPI_XFER_BEGIN		(1 << 0)
++#define FALCON_SPI_XFER_END		(1 << 1)
++
++/* Bus Read Configuration Register0 */
++#define LTQ_BUSRCON0	0x00000010
++/* Bus Write Configuration Register0 */
++#define LTQ_BUSWCON0	0x00000018
++/* Serial Flash Configuration Register */
++#define LTQ_SFCON	0x00000080
++/* Serial Flash Time Register */
++#define LTQ_SFTIME	0x00000084
++/* Serial Flash Status Register */
++#define LTQ_SFSTAT	0x00000088
++/* Serial Flash Command Register */
++#define LTQ_SFCMD	0x0000008C
++/* Serial Flash Address Register */
++#define LTQ_SFADDR	0x00000090
++/* Serial Flash Data Register */
++#define LTQ_SFDATA	0x00000094
++/* Serial Flash I/O Control Register */
++#define LTQ_SFIO	0x00000098
++/* EBU Clock Control Register */
++#define LTQ_EBUCC	0x000000C4
++
++/* Dummy Phase Length */
++#define SFCMD_DUMLEN_OFFSET	16
++#define SFCMD_DUMLEN_MASK	0x000F0000
++/* Chip Select */
++#define SFCMD_CS_OFFSET		24
++#define SFCMD_CS_MASK		0x07000000
++/* field offset */
++#define SFCMD_ALEN_OFFSET	20
++#define SFCMD_ALEN_MASK		0x00700000
++/* SCK Rise-edge Position */
++#define SFTIME_SCKR_POS_OFFSET	8
++#define SFTIME_SCKR_POS_MASK	0x00000F00
++/* SCK Period */
++#define SFTIME_SCK_PER_OFFSET	0
++#define SFTIME_SCK_PER_MASK	0x0000000F
++/* SCK Fall-edge Position */
++#define SFTIME_SCKF_POS_OFFSET	12
++#define SFTIME_SCKF_POS_MASK	0x0000F000
++/* Device Size */
++#define SFCON_DEV_SIZE_A23_0	0x03000000
++#define SFCON_DEV_SIZE_MASK	0x0F000000
++/* Read Data Position */
++#define SFTIME_RD_POS_MASK	0x000F0000
++/* Data Output */
++#define SFIO_UNUSED_WD_MASK	0x0000000F
++/* Command Opcode mask */
++#define SFCMD_OPC_MASK		0x000000FF
++/* dlen bytes of data to write */
++#define SFCMD_DIR_WRITE		0x00000100
++/* Data Length offset */
++#define SFCMD_DLEN_OFFSET	9
++/* Command Error */
++#define SFSTAT_CMD_ERR		0x20000000
++/* Access Command Pending */
++#define SFSTAT_CMD_PEND		0x00400000
++/* Frequency set to 100MHz. */
++#define EBUCC_EBUDIV_SELF100	0x00000001
++/* Serial Flash */
++#define BUSRCON0_AGEN_SERIAL_FLASH	0xF0000000
++/* 8-bit multiplexed */
++#define BUSRCON0_PORTW_8_BIT_MUX	0x00000000
++/* Serial Flash */
++#define BUSWCON0_AGEN_SERIAL_FLASH	0xF0000000
++/* Chip Select after opcode */
++#define SFCMD_KEEP_CS_KEEP_SELECTED	0x00008000
++
++struct falcon_spi {
++	u32 sfcmd; /* for caching of opcode, direction, ... */
++	struct spi_master *master;
++};
++
++int
++falcon_spi_xfer(struct spi_device *spi,
++		    struct spi_transfer *t,
++		    unsigned long flags)
++{
++	struct device *dev = &spi->dev;
++	struct falcon_spi *priv = spi_master_get_devdata(spi->master);
++	const u8 *txp = t->tx_buf;
++	u8 *rxp = t->rx_buf;
++	unsigned int bytelen = ((8 * t->len + 7) / 8);
++	unsigned int len, alen, dumlen;
++	u32 val;
++	enum {
++		state_init,
++		state_command_prepare,
++		state_write,
++		state_read,
++		state_disable_cs,
++		state_end
++	} state = state_init;
++
++	do {
++		switch (state) {
++		case state_init: /* detect phase of upper layer sequence */
++		{
++			/* initial write ? */
++			if (flags & FALCON_SPI_XFER_BEGIN) {
++				if (!txp) {
++					dev_err(dev,
++						"BEGIN without tx data!\n");
++					return -1;
++				}
++				/*
++				 * Prepare the parts of the sfcmd register,
++				 * which should not
++				 * change during a sequence!
++				 * Only exception are the length fields,
++				 * especially alen and dumlen.
++				 */
++
++				priv->sfcmd = ((spi->chip_select
++						<< SFCMD_CS_OFFSET)
++					       & SFCMD_CS_MASK);
++				priv->sfcmd |= SFCMD_KEEP_CS_KEEP_SELECTED;
++				priv->sfcmd |= *txp;
++				txp++;
++				bytelen--;
++				if (bytelen) {
++					/* more data:
++					 * maybe address and/or dummy */
++					state = state_command_prepare;
++					break;
++				} else {
++					dev_dbg(dev, "write cmd %02X\n",
++						priv->sfcmd & SFCMD_OPC_MASK);
++				}
++			}
++			/* continued write ? */
++			if (txp && bytelen) {
++				state = state_write;
++				break;
++			}
++			/* read data? */
++			if (rxp && bytelen) {
++				state = state_read;
++				break;
++			}
++			/* end of sequence? */
++			if (flags & FALCON_SPI_XFER_END)
++				state = state_disable_cs;
++			else
++				state = state_end;
++			break;
++		}
++		case state_command_prepare: /* collect tx data for
++					       address and dummy phase */
++		{
++			/* txp is valid, already checked */
++			val = 0;
++			alen = 0;
++			dumlen = 0;
++			while (bytelen > 0) {
++				if (alen < 3) {
++					val = (val<<8)|(*txp++);
++					alen++;
++				} else if ((dumlen < 15) && (*txp == 0)) {
++					/*
++					 * assume dummy bytes are set to 0
++					 * from upper layer
++					 */
++					dumlen++;
++					txp++;
++				} else
++					break;
++				bytelen--;
++			}
++			priv->sfcmd &= ~(SFCMD_ALEN_MASK | SFCMD_DUMLEN_MASK);
++			priv->sfcmd |= (alen << SFCMD_ALEN_OFFSET) |
++					 (dumlen << SFCMD_DUMLEN_OFFSET);
++			if (alen > 0)
++				ltq_ebu_w32(val, LTQ_SFADDR);
++
++			dev_dbg(dev, "write cmd %02X, alen=%d "
++				"(addr=%06X) dumlen=%d\n",
++				priv->sfcmd & SFCMD_OPC_MASK,
++				alen, val, dumlen);
++
++			if (bytelen > 0) {
++				/* continue with write */
++				state = state_write;
++			} else if (flags & FALCON_SPI_XFER_END) {
++				/* end of sequence? */
++				state = state_disable_cs;
++			} else {
++				/* go to end and expect another
++				 * call (read or write) */
++				state = state_end;
++			}
++			break;
++		}
++		case state_write:
++		{
++			/* txp still valid */
++			priv->sfcmd |= SFCMD_DIR_WRITE;
++			len = 0;
++			val = 0;
++			do {
++				if (bytelen--)
++					val |= (*txp++) << (8 * len++);
++				if ((flags & FALCON_SPI_XFER_END)
++				    && (bytelen == 0)) {
++					priv->sfcmd &=
++						~SFCMD_KEEP_CS_KEEP_SELECTED;
++				}
++				if ((len == 4) || (bytelen == 0)) {
++					ltq_ebu_w32(val, LTQ_SFDATA);
++					ltq_ebu_w32(priv->sfcmd
++						| (len<<SFCMD_DLEN_OFFSET),
++						LTQ_SFCMD);
++					len = 0;
++					val = 0;
++					priv->sfcmd &= ~(SFCMD_ALEN_MASK
++							 | SFCMD_DUMLEN_MASK);
++				}
++			} while (bytelen);
++			state = state_end;
++			break;
++		}
++		case state_read:
++		{
++			/* read data */
++			priv->sfcmd &= ~SFCMD_DIR_WRITE;
++			do {
++				if ((flags & FALCON_SPI_XFER_END)
++				    && (bytelen <= 4)) {
++					priv->sfcmd &=
++						~SFCMD_KEEP_CS_KEEP_SELECTED;
++				}
++				len = (bytelen > 4) ? 4 : bytelen;
++				bytelen -= len;
++				ltq_ebu_w32(priv->sfcmd
++					|(len<<SFCMD_DLEN_OFFSET), LTQ_SFCMD);
++				priv->sfcmd &= ~(SFCMD_ALEN_MASK
++						 | SFCMD_DUMLEN_MASK);
++				do {
++					val = ltq_ebu_r32(LTQ_SFSTAT);
++					if (val & SFSTAT_CMD_ERR) {
++						/* reset error status */
++						dev_err(dev, "SFSTAT: CMD_ERR "
++							"(%x)\n", val);
++						ltq_ebu_w32(SFSTAT_CMD_ERR,
++							LTQ_SFSTAT);
++						return -1;
++					}
++				} while (val & SFSTAT_CMD_PEND);
++				val = ltq_ebu_r32(LTQ_SFDATA);
++				do {
++					*rxp = (val & 0xFF);
++					rxp++;
++					val >>= 8;
++					len--;
++				} while (len);
++			} while (bytelen);
++			state = state_end;
++			break;
++		}
++		case state_disable_cs:
++		{
++			priv->sfcmd &= ~SFCMD_KEEP_CS_KEEP_SELECTED;
++			ltq_ebu_w32(priv->sfcmd | (0 << SFCMD_DLEN_OFFSET),
++				LTQ_SFCMD);
++			val = ltq_ebu_r32(LTQ_SFSTAT);
++			if (val & SFSTAT_CMD_ERR) {
++				/* reset error status */
++				dev_err(dev, "SFSTAT: CMD_ERR (%x)\n", val);
++				ltq_ebu_w32(SFSTAT_CMD_ERR, LTQ_SFSTAT);
++				return -1;
++			}
++			state = state_end;
++			break;
++		}
++		case state_end:
++			break;
++		}
++	} while (state != state_end);
++
++	return 0;
++}
++
++static int
++falcon_spi_setup(struct spi_device *spi)
++{
++	struct device *dev = &spi->dev;
++	const u32 ebuclk = CLOCK_100M;
++	unsigned int i;
++	unsigned long flags;
++
++	dev_dbg(dev, "setup\n");
++
++	if (spi->master->bus_num > 0 || spi->chip_select > 0)
++		return -ENODEV;
++
++	spin_lock_irqsave(&ebu_lock, flags);
++
++	if (ebuclk < spi->max_speed_hz) {
++		/* set EBU clock to 100 MHz */
++		ltq_sys1_w32_mask(0, EBUCC_EBUDIV_SELF100, LTQ_EBUCC);
++		i = 1; /* divider */
++	} else {
++		/* set EBU clock to 50 MHz */
++		ltq_sys1_w32_mask(EBUCC_EBUDIV_SELF100, 0, LTQ_EBUCC);
++
++		/* search for suitable divider */
++		for (i = 1; i < 7; i++) {
++			if (ebuclk / i <= spi->max_speed_hz)
++				break;
++		}
++	}
++
++	/* setup period of serial clock */
++	ltq_ebu_w32_mask(SFTIME_SCKF_POS_MASK
++		     | SFTIME_SCKR_POS_MASK
++		     | SFTIME_SCK_PER_MASK,
++		     (i << SFTIME_SCKR_POS_OFFSET)
++		     | (i << (SFTIME_SCK_PER_OFFSET + 1)),
++		     LTQ_SFTIME);
++
++	/* set some bits of unused_wd, to not trigger HOLD/WP
++	 * signals on non QUAD flashes */
++	ltq_ebu_w32((SFIO_UNUSED_WD_MASK & (0x8 | 0x4)), LTQ_SFIO);
++
++	ltq_ebu_w32(BUSRCON0_AGEN_SERIAL_FLASH | BUSRCON0_PORTW_8_BIT_MUX,
++		LTQ_BUSRCON0);
++	ltq_ebu_w32(BUSWCON0_AGEN_SERIAL_FLASH, LTQ_BUSWCON0);
++	/* set address wrap around to maximum for 24-bit addresses */
++	ltq_ebu_w32_mask(SFCON_DEV_SIZE_MASK, SFCON_DEV_SIZE_A23_0, LTQ_SFCON);
++
++	spin_unlock_irqrestore(&ebu_lock, flags);
++
++	return 0;
++}
++
++static int
++falcon_spi_transfer(struct spi_device *spi, struct spi_message *m)
++{
++	struct falcon_spi *priv = spi_master_get_devdata(spi->master);
++	struct spi_transfer *t;
++	unsigned long spi_flags;
++	unsigned long flags;
++	int ret = 0;
++
++	priv->sfcmd = 0;
++	m->actual_length = 0;
++
++	spi_flags = FALCON_SPI_XFER_BEGIN;
++	list_for_each_entry(t, &m->transfers, transfer_list) {
++		if (list_is_last(&t->transfer_list, &m->transfers))
++			spi_flags |= FALCON_SPI_XFER_END;
++
++		spin_lock_irqsave(&ebu_lock, flags);
++		ret = falcon_spi_xfer(spi, t, spi_flags);
++		spin_unlock_irqrestore(&ebu_lock, flags);
++
++		if (ret)
++			break;
++
++		m->actual_length += t->len;
++
++		if (t->delay_usecs || t->cs_change)
++			BUG();
++
++		spi_flags = 0;
++	}
++
++	m->status = ret;
++	m->complete(m->context);
++
++	return 0;
++}
++
++static void
++falcon_spi_cleanup(struct spi_device *spi)
++{
++	struct device *dev = &spi->dev;
++
++	dev_dbg(dev, "cleanup\n");
++}
++
++static int __devinit
++falcon_spi_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct falcon_spi *priv;
++	struct spi_master *master;
++	int ret;
++
++	dev_dbg(dev, "probing\n");
++
++	master = spi_alloc_master(&pdev->dev, sizeof(*priv));
++	if (!master) {
++		dev_err(dev, "no memory for spi_master\n");
++		return -ENOMEM;
++	}
++
++	priv = spi_master_get_devdata(master);
++	priv->master = master;
++
++	master->mode_bits = SPI_MODE_3;
++	master->num_chipselect = 1;
++	master->bus_num = 0;
++
++	master->setup = falcon_spi_setup;
++	master->transfer = falcon_spi_transfer;
++	master->cleanup = falcon_spi_cleanup;
++
++	platform_set_drvdata(pdev, priv);
++
++	ret = spi_register_master(master);
++	if (ret)
++		spi_master_put(master);
++
++	return ret;
++}
++
++static int __devexit
++falcon_spi_remove(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct falcon_spi *priv = platform_get_drvdata(pdev);
++
++	dev_dbg(dev, "removed\n");
++
++	spi_unregister_master(priv->master);
++
++	return 0;
++}
++
++static struct platform_driver falcon_spi_driver = {
++	.probe	= falcon_spi_probe,
++	.remove	= __devexit_p(falcon_spi_remove),
++	.driver = {
++		.name	= DRV_NAME,
++		.owner	= THIS_MODULE
++	}
++};
++
++static int __init
++falcon_spi_init(void)
++{
++	return platform_driver_register(&falcon_spi_driver);
++}
++
++static void __exit
++falcon_spi_exit(void)
++{
++	platform_driver_unregister(&falcon_spi_driver);
++}
++
++module_init(falcon_spi_init);
++module_exit(falcon_spi_exit);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("Lantiq Falcon SPI controller driver");
+Index: linux-3.0.3/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
+===================================================================
+--- linux-3.0.3.orig/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h	2011-10-05 12:38:16.176858136 +0200
++++ linux-3.0.3/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h	2011-10-05 12:39:54.936862358 +0200
+@@ -48,6 +48,10 @@
+ 
+ #define LTQ_EBU_MODCON  0x000C
+ 
++/* I2C */
++#define LTQ_I2C_BASE_ADDR	0x1E200000
++#define LTQ_I2C_SIZE		0x00010000
++
+ /* GPIO */
+ #define LTQ_GPIO0_BASE_ADDR     0x1D810000
+ #define LTQ_GPIO0_SIZE          0x0080
+@@ -92,6 +96,7 @@
+ 
+ /* Activation Status Register */
+ #define ACTS_ASC1_ACT	0x00000800
++#define ACTS_I2C_ACT	0x00004000
+ #define ACTS_P0		0x00010000
+ #define ACTS_P1		0x00010000
+ #define ACTS_P2		0x00020000
diff --git a/target/linux/lantiq/patches-3.0/410-spi2.patch b/target/linux/lantiq/patches-3.0/0014-MIPS-lantiq-adds-xway-spi.patch
index e7909caecd..0fe4f5479a 100644
--- a/target/linux/lantiq/patches-3.0/410-spi2.patch
+++ b/target/linux/lantiq/patches-3.0/0014-MIPS-lantiq-adds-xway-spi.patch
@@ -1,42 +1,96 @@
-From: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
-Date: Thu, 3 Mar 2011 17:15:30 +0000 (+0100)
-Subject: SPI: lantiq: Add driver for Lantiq SoC SPI controller
-X-Git-Url: http://nbd.name/gitweb.cgi?p=lantiq.git;a=commitdiff_plain;h=653c95b8b9066c9c6ac08bd64d0ceee439e9fd90;hp=3d21b04682ae8eb1c1965aba39d1796e8c5ad84b
+From e29263339db41d49d79482c93463c4c0cbe764d7 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 30 Sep 2011 14:23:42 +0200
+Subject: [PATCH 14/24] MIPS: lantiq: adds xway spi
 
-SPI: lantiq: Add driver for Lantiq SoC SPI controller
-
-Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
 ---
+ .../mips/include/asm/mach-lantiq/lantiq_platform.h |    9 +
+ .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h |    2 +
+ .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |    1 +
+ drivers/spi/Kconfig                                |    8 +
+ drivers/spi/Makefile                               |    2 +-
+ drivers/spi/spi-xway.c                             | 1062 ++++++++++++++++++++
+ 6 files changed, 1083 insertions(+), 1 deletions(-)
+ create mode 100644 drivers/spi/spi-xway.c
 
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -202,6 +202,14 @@ config SPI_IMX
- 	  This enables using the Freescale i.MX SPI controllers in master
- 	  mode.
+Index: linux-3.0.3/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
+===================================================================
+--- linux-3.0.3.orig/arch/mips/include/asm/mach-lantiq/lantiq_platform.h	2011-08-17 19:57:16.000000000 +0200
++++ linux-3.0.3/arch/mips/include/asm/mach-lantiq/lantiq_platform.h	2011-10-04 20:05:23.962311503 +0200
+@@ -50,4 +50,13 @@
+ 	int mii_mode;
+ };
+ 
++
++struct ltq_spi_platform_data {
++	u16 num_chipselect;
++};
++
++struct ltq_spi_controller_data {
++	unsigned gpio;
++};
++
+ #endif
+Index: linux-3.0.3/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
+===================================================================
+--- linux-3.0.3.orig/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h	2011-08-17 19:57:16.000000000 +0200
++++ linux-3.0.3/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h	2011-10-04 20:05:23.962311503 +0200
+@@ -27,6 +27,8 @@
+ 
+ #define LTQ_SSC_TIR		(INT_NUM_IM0_IRL0 + 15)
+ #define LTQ_SSC_RIR		(INT_NUM_IM0_IRL0 + 14)
++#define LTQ_SSC_TIR_AR9		(INT_NUM_IM0_IRL0 + 14)
++#define LTQ_SSC_RIR_AR9		(INT_NUM_IM0_IRL0 + 15)
+ #define LTQ_SSC_EIR		(INT_NUM_IM0_IRL0 + 16)
  
-+config SPI_LANTIQ
-+	tristate "Lantiq SoC SPI controller"
-+	depends on SOC_TYPE_XWAY
+ #define LTQ_MEI_DYING_GASP_INT	(INT_NUM_IM1_IRL0 + 21)
+Index: linux-3.0.3/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+===================================================================
+--- linux-3.0.3.orig/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h	2011-10-04 20:03:54.934307699 +0200
++++ linux-3.0.3/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h	2011-10-04 20:05:23.966311504 +0200
+@@ -81,6 +81,7 @@
+ 
+ #define PMU_DMA			0x0020
+ #define PMU_USB			0x8041
++#define PMU_SPI			0x0100
+ #define PMU_LED			0x0800
+ #define PMU_GPT			0x1000
+ #define PMU_PPE			0x2000
+Index: linux-3.0.3/drivers/spi/Kconfig
+===================================================================
+--- linux-3.0.3.orig/drivers/spi/Kconfig	2011-10-04 20:05:07.030310779 +0200
++++ linux-3.0.3/drivers/spi/Kconfig	2011-10-04 20:05:23.966311504 +0200
+@@ -433,6 +433,14 @@
+ 	help
+ 	  SPI driver for Nuvoton NUC900 series ARM SoCs
+ 
++config SPI_XWAY
++	tristate "Lantiq XWAY SPI controller"
++	depends on LANTIQ && SOC_TYPE_XWAY
 +	select SPI_BITBANG
 +	help
 +	  This driver supports the Lantiq SoC SPI controller in master
 +	  mode.
 +
- config SPI_LM70_LLP
- 	tristate "Parallel port adapter for LM70 eval board (DEVELOPMENT)"
- 	depends on PARPORT && EXPERIMENTAL
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -27,6 +27,7 @@ obj-$(CONFIG_SPI_EP93XX)		+= ep93xx_spi.
- obj-$(CONFIG_SPI_GPIO)			+= spi_gpio.o
- obj-$(CONFIG_SPI_GPIO_OLD)		+= spi_gpio_old.o
- obj-$(CONFIG_SPI_IMX)			+= spi_imx.o
-+obj-$(CONFIG_SPI_LANTIQ)		+= spi_lantiq.o
- obj-$(CONFIG_SPI_LM70_LLP)		+= spi_lm70llp.o
- obj-$(CONFIG_SPI_PXA2XX)		+= pxa2xx_spi.o
- obj-$(CONFIG_SPI_PXA2XX_PCI)		+= pxa2xx_spi_pci.o
---- /dev/null
-+++ b/drivers/spi/spi_lantiq.c
+ #
+ # Add new SPI master controllers in alphabetical order above this line
+ #
+Index: linux-3.0.3/drivers/spi/Makefile
+===================================================================
+--- linux-3.0.3.orig/drivers/spi/Makefile	2011-10-04 20:05:20.000000000 +0200
++++ linux-3.0.3/drivers/spi/Makefile	2011-10-04 20:05:35.802312011 +0200
+@@ -57,6 +57,7 @@
+ obj-$(CONFIG_SPI_STMP3XXX)		+= spi_stmp.o
+ obj-$(CONFIG_SPI_NUC900)		+= spi_nuc900.o
+ obj-$(CONFIG_SPI_FALCON)		+= spi-falcon.o
++obj-$(CONFIG_SPI_XWAY)			+= spi-xway.o
+ 
+ # special build for s3c24xx spi driver with fiq support
+ spi_s3c24xx_hw-y			:= spi_s3c24xx.o
+Index: linux-3.0.3/drivers/spi/spi-xway.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-3.0.3/drivers/spi/spi-xway.c	2011-10-04 20:05:23.966311504 +0200
 @@ -0,0 +1,1062 @@
 +/*
 + * Lantiq SoC SPI controller
diff --git a/target/linux/lantiq/patches-3.0/0015-MIPS-lantiq-adds-etop-support-for-ase-ar9.patch b/target/linux/lantiq/patches-3.0/0015-MIPS-lantiq-adds-etop-support-for-ase-ar9.patch
new file mode 100644
index 0000000000..40ec2bdd2a
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/0015-MIPS-lantiq-adds-etop-support-for-ase-ar9.patch
@@ -0,0 +1,417 @@
+From c7881d8d2b3aed9a90aa37dcf797328a9cfbe7b6 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 10 Aug 2011 15:32:16 +0200
+Subject: [PATCH 15/24] MIPS: lantiq: adds etop support for ase/ar9
+
+Extend the driver to handle the different DMA channel layout for AR9 and
+SoCs. The patch also adds support for the integrated PHY found on Amazon-SE
+and the gigabit switch found inside the AR9.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+---
+ .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h |   22 +---
+ .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |   10 ++
+ arch/mips/lantiq/xway/devices.c                    |   11 +-
+ arch/mips/lantiq/xway/mach-easy50601.c             |    5 +
+ drivers/net/lantiq_etop.c                          |  172 ++++++++++++++++++--
+ 5 files changed, 180 insertions(+), 40 deletions(-)
+
+Index: linux-3.0.3/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
+===================================================================
+--- linux-3.0.3.orig/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h	2011-10-04 20:05:23.000000000 +0200
++++ linux-3.0.3/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h	2011-10-04 20:05:44.146312365 +0200
+@@ -40,26 +40,8 @@
+ 
+ #define MIPS_CPU_TIMER_IRQ		7
+ 
+-#define LTQ_DMA_CH0_INT		(INT_NUM_IM2_IRL0)
+-#define LTQ_DMA_CH1_INT		(INT_NUM_IM2_IRL0 + 1)
+-#define LTQ_DMA_CH2_INT		(INT_NUM_IM2_IRL0 + 2)
+-#define LTQ_DMA_CH3_INT		(INT_NUM_IM2_IRL0 + 3)
+-#define LTQ_DMA_CH4_INT		(INT_NUM_IM2_IRL0 + 4)
+-#define LTQ_DMA_CH5_INT		(INT_NUM_IM2_IRL0 + 5)
+-#define LTQ_DMA_CH6_INT		(INT_NUM_IM2_IRL0 + 6)
+-#define LTQ_DMA_CH7_INT		(INT_NUM_IM2_IRL0 + 7)
+-#define LTQ_DMA_CH8_INT		(INT_NUM_IM2_IRL0 + 8)
+-#define LTQ_DMA_CH9_INT		(INT_NUM_IM2_IRL0 + 9)
+-#define LTQ_DMA_CH10_INT	(INT_NUM_IM2_IRL0 + 10)
+-#define LTQ_DMA_CH11_INT	(INT_NUM_IM2_IRL0 + 11)
+-#define LTQ_DMA_CH12_INT	(INT_NUM_IM2_IRL0 + 25)
+-#define LTQ_DMA_CH13_INT	(INT_NUM_IM2_IRL0 + 26)
+-#define LTQ_DMA_CH14_INT	(INT_NUM_IM2_IRL0 + 27)
+-#define LTQ_DMA_CH15_INT	(INT_NUM_IM2_IRL0 + 28)
+-#define LTQ_DMA_CH16_INT	(INT_NUM_IM2_IRL0 + 29)
+-#define LTQ_DMA_CH17_INT	(INT_NUM_IM2_IRL0 + 30)
+-#define LTQ_DMA_CH18_INT	(INT_NUM_IM2_IRL0 + 16)
+-#define LTQ_DMA_CH19_INT	(INT_NUM_IM2_IRL0 + 21)
++#define LTQ_DMA_ETOP		((ltq_is_ase()) ? \
++				(INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
+ 
+ #define LTQ_PPE_MBOX_INT	(INT_NUM_IM2_IRL0 + 24)
+ 
+Index: linux-3.0.3/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+===================================================================
+--- linux-3.0.3.orig/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h	2011-10-04 20:05:23.000000000 +0200
++++ linux-3.0.3/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h	2011-10-04 20:05:44.146312365 +0200
+@@ -80,6 +80,7 @@
+ #define LTQ_PMU_SIZE		0x1000
+ 
+ #define PMU_DMA			0x0020
++#define PMU_EPHY		0x0080
+ #define PMU_USB			0x8041
+ #define PMU_SPI			0x0100
+ #define PMU_LED			0x0800
+@@ -92,6 +93,10 @@
+ #define LTQ_ETOP_BASE_ADDR	0x1E180000
+ #define LTQ_ETOP_SIZE		0x40000
+ 
++/* GBIT - gigabit switch */
++#define LTQ_GBIT_BASE_ADDR	0x1E108000
++#define LTQ_GBIT_SIZE		0x200
++
+ /* DMA */
+ #define LTQ_DMA_BASE_ADDR	0x1E104100
+ #define LTQ_DMA_SIZE		0x800
+@@ -148,6 +153,11 @@
+ extern void ltq_pmu_disable(unsigned int module);
+ extern void ltq_cgu_enable(unsigned int clk);
+ 
++static inline int ltq_is_ase(void)
++{
++	return (ltq_get_soc_type() == SOC_TYPE_AMAZON_SE);
++}
++
+ static inline int ltq_is_ar9(void)
+ {
+ 	return (ltq_get_soc_type() == SOC_TYPE_AR9);
+Index: linux-3.0.3/arch/mips/lantiq/xway/devices.c
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/xway/devices.c	2011-10-04 20:03:54.000000000 +0200
++++ linux-3.0.3/arch/mips/lantiq/xway/devices.c	2011-10-04 20:05:44.146312365 +0200
+@@ -79,18 +79,23 @@
+ }
+ 
+ /* ethernet */
+-static struct resource ltq_etop_resources =
+-	MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE);
++static struct resource ltq_etop_resources[] = {
++	MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE),
++	MEM_RES("gbit", LTQ_GBIT_BASE_ADDR, LTQ_GBIT_SIZE),
++};
+ 
+ static struct platform_device ltq_etop = {
+ 	.name		= "ltq_etop",
+-	.resource	= &ltq_etop_resources,
++	.resource	= ltq_etop_resources,
+ 	.num_resources	= 1,
+ };
+ 
+ void __init
+ ltq_register_etop(struct ltq_eth_data *eth)
+ {
++	/* only register the gphy on socs that have one */
++	if (ltq_is_ar9() | ltq_is_vr9())
++		ltq_etop.num_resources = 2;
+ 	if (eth) {
+ 		ltq_etop.dev.platform_data = eth;
+ 		platform_device_register(&ltq_etop);
+Index: linux-3.0.3/drivers/net/lantiq_etop.c
+===================================================================
+--- linux-3.0.3.orig/drivers/net/lantiq_etop.c	2011-08-17 19:57:16.000000000 +0200
++++ linux-3.0.3/drivers/net/lantiq_etop.c	2011-10-04 20:05:44.146312365 +0200
+@@ -34,6 +34,7 @@
+ #include <linux/init.h>
+ #include <linux/delay.h>
+ #include <linux/io.h>
++#include <linux/dma-mapping.h>
+ 
+ #include <asm/checksum.h>
+ 
+@@ -69,10 +70,43 @@
+ #define ETOP_MII_REVERSE	0xe
+ #define ETOP_PLEN_UNDER		0x40
+ #define ETOP_CGEN		0x800
++#define ETOP_CFG_MII0		0x01
+ 
+-/* use 2 static channels for TX/RX */
++#define LTQ_GBIT_MDIO_CTL	0xCC
++#define LTQ_GBIT_MDIO_DATA	0xd0
++#define LTQ_GBIT_GCTL0		0x68
++#define LTQ_GBIT_PMAC_HD_CTL	0x8c
++#define LTQ_GBIT_P0_CTL		0x4
++#define LTQ_GBIT_PMAC_RX_IPG	0xa8
++
++#define PMAC_HD_CTL_AS		(1 << 19)
++#define PMAC_HD_CTL_RXSH	(1 << 22)
++
++/* Switch Enable (0=disable, 1=enable) */
++#define GCTL0_SE		0x80000000
++/* Disable MDIO auto polling (0=disable, 1=enable) */
++#define PX_CTL_DMDIO		0x00400000
++
++/* register information for the gbit's MDIO bus */
++#define MDIO_XR9_REQUEST	0x00008000
++#define MDIO_XR9_READ		0x00000800
++#define MDIO_XR9_WRITE		0x00000400
++#define MDIO_XR9_REG_MASK	0x1f
++#define MDIO_XR9_ADDR_MASK	0x1f
++#define MDIO_XR9_RD_MASK	0xffff
++#define MDIO_XR9_REG_OFFSET	0
++#define MDIO_XR9_ADDR_OFFSET	5
++#define MDIO_XR9_WR_OFFSET	16
++
++/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
++#define ltq_has_gbit()		(ltq_is_ar9() || ltq_is_vr9())
++
++/* use 2 static channels for TX/RX
++   depending on the SoC we need to use different DMA channels for ethernet */
+ #define LTQ_ETOP_TX_CHANNEL	1
+-#define LTQ_ETOP_RX_CHANNEL	6
++#define LTQ_ETOP_RX_CHANNEL	((ltq_is_ase()) ? (5) : \
++				((ltq_has_gbit()) ? (0) : (6)))
++
+ #define IS_TX(x)		(x == LTQ_ETOP_TX_CHANNEL)
+ #define IS_RX(x)		(x == LTQ_ETOP_RX_CHANNEL)
+ 
+@@ -81,9 +115,15 @@
+ #define ltq_etop_w32_mask(x, y, z)	\
+ 		ltq_w32_mask(x, y, ltq_etop_membase + (z))
+ 
++#define ltq_gbit_r32(x)		ltq_r32(ltq_gbit_membase + (x))
++#define ltq_gbit_w32(x, y)	ltq_w32(x, ltq_gbit_membase + (y))
++#define ltq_gbit_w32_mask(x, y, z)	\
++		ltq_w32_mask(x, y, ltq_gbit_membase + (z))
++
+ #define DRV_VERSION	"1.0"
+ 
+ static void __iomem *ltq_etop_membase;
++static void __iomem *ltq_gbit_membase;
+ 
+ struct ltq_etop_chan {
+ 	int idx;
+@@ -108,6 +148,9 @@
+ 	spinlock_t lock;
+ };
+ 
++static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
++				int phy_reg, u16 phy_data);
++
+ static int
+ ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
+ {
+@@ -209,7 +252,7 @@
+ ltq_etop_dma_irq(int irq, void *_priv)
+ {
+ 	struct ltq_etop_priv *priv = _priv;
+-	int ch = irq - LTQ_DMA_CH0_INT;
++	int ch = irq - LTQ_DMA_ETOP;
+ 
+ 	napi_schedule(&priv->ch[ch].napi);
+ 	return IRQ_HANDLED;
+@@ -242,26 +285,66 @@
+ 			ltq_etop_free_channel(dev, &priv->ch[i]);
+ }
+ 
++static void
++ltq_etop_gbit_init(void)
++{
++	ltq_pmu_enable(PMU_SWITCH);
++
++	ltq_gpio_request(42, 1, 0, 1, "MDIO");
++	ltq_gpio_request(43, 1, 0, 1, "MDC");
++
++	ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
++	/** Disable MDIO auto polling mode */
++	ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
++	/* set 1522 packet size */
++	ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
++	/* disable pmac & dmac headers */
++	ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
++		LTQ_GBIT_PMAC_HD_CTL);
++	/* Due to traffic halt when burst length 8,
++		replace default IPG value with 0x3B */
++	ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
++}
++
+ static int
+ ltq_etop_hw_init(struct net_device *dev)
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
++	unsigned int mii_mode = priv->pldata->mii_mode;
+ 	int i;
+ 
+ 	ltq_pmu_enable(PMU_PPE);
+ 
+-	switch (priv->pldata->mii_mode) {
++	if (ltq_has_gbit()) {
++		ltq_etop_gbit_init();
++	}
++
++	switch (mii_mode) {
++	case PHY_INTERFACE_MODE_RGMII:
+ 	case PHY_INTERFACE_MODE_RMII:
+ 		ltq_etop_w32_mask(ETOP_MII_MASK,
+ 			ETOP_MII_REVERSE, LTQ_ETOP_CFG);
+ 		break;
+ 
++	case PHY_INTERFACE_MODE_GMII:
+ 	case PHY_INTERFACE_MODE_MII:
+ 		ltq_etop_w32_mask(ETOP_MII_MASK,
+ 			ETOP_MII_NORMAL, LTQ_ETOP_CFG);
+ 		break;
+ 
+ 	default:
++		if (ltq_is_ase()) {
++			ltq_pmu_enable(PMU_EPHY);
++			/* disable external MII */
++			ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
++			/* enable clock for internal PHY */
++			ltq_cgu_enable(CGU_EPHY);
++			/* we need to write this magic to the internal phy to
++			   make it work */
++			ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
++			pr_info("Selected EPHY mode\n");
++			break;
++		}
+ 		netdev_err(dev, "unknown mii mode %d\n",
+ 			priv->pldata->mii_mode);
+ 		return -ENOTSUPP;
+@@ -273,7 +356,7 @@
+ 	ltq_dma_init_port(DMA_PORT_ETOP);
+ 
+ 	for (i = 0; i < MAX_DMA_CHAN; i++) {
+-		int irq = LTQ_DMA_CH0_INT + i;
++		int irq = LTQ_DMA_ETOP + i;
+ 		struct ltq_etop_chan *ch = &priv->ch[i];
+ 
+ 		ch->idx = ch->dma.nr = i;
+@@ -337,6 +420,39 @@
+ };
+ 
+ static int
++ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
++		int phy_reg, u16 phy_data)
++{
++	u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
++		(phy_data << MDIO_XR9_WR_OFFSET) |
++		((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
++		((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
++
++	while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
++		;
++	ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
++	while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
++		;
++	return 0;
++}
++
++static int
++ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
++{
++	u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
++		((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
++		((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
++
++	while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
++		;
++	ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
++	while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
++		;
++	val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
++	return val;
++}
++
++static int
+ ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
+ {
+ 	u32 val = MDIO_REQUEST |
+@@ -377,14 +493,11 @@
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+ 	struct phy_device *phydev = NULL;
+-	int phy_addr;
+ 
+-	for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
+-		if (priv->mii_bus->phy_map[phy_addr]) {
+-			phydev = priv->mii_bus->phy_map[phy_addr];
+-			break;
+-		}
+-	}
++	if (ltq_is_ase())
++		phydev = priv->mii_bus->phy_map[8];
++	else
++		phydev = priv->mii_bus->phy_map[0];
+ 
+ 	if (!phydev) {
+ 		netdev_err(dev, "no PHY found\n");
+@@ -406,6 +519,9 @@
+ 			      | SUPPORTED_Autoneg
+ 			      | SUPPORTED_MII
+ 			      | SUPPORTED_TP);
++	if (ltq_has_gbit())
++		phydev->supported &= SUPPORTED_1000baseT_Half
++					| SUPPORTED_1000baseT_Full;
+ 
+ 	phydev->advertising = phydev->supported;
+ 	priv->phydev = phydev;
+@@ -431,8 +547,13 @@
+ 	}
+ 
+ 	priv->mii_bus->priv = dev;
+-	priv->mii_bus->read = ltq_etop_mdio_rd;
+-	priv->mii_bus->write = ltq_etop_mdio_wr;
++	if (ltq_has_gbit()) {
++		priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
++		priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
++	} else {
++		priv->mii_bus->read = ltq_etop_mdio_rd;
++		priv->mii_bus->write = ltq_etop_mdio_wr;
++	}
+ 	priv->mii_bus->name = "ltq_mii";
+ 	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
+ 	priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
+@@ -522,9 +643,9 @@
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+ 	struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
+ 	struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
+-	int len;
+ 	unsigned long flags;
+ 	u32 byte_offset;
++	int len;
+ 
+ 	len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
+ 
+@@ -698,7 +819,7 @@
+ {
+ 	struct net_device *dev;
+ 	struct ltq_etop_priv *priv;
+-	struct resource *res;
++	struct resource *res, *gbit_res;
+ 	int err;
+ 	int i;
+ 
+@@ -726,6 +847,23 @@
+ 		goto err_out;
+ 	}
+ 
++	if (ltq_has_gbit()) {
++		gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++		if (!gbit_res) {
++			dev_err(&pdev->dev, "failed to get gbit resource\n");
++			err = -ENOENT;
++			goto err_out;
++		}
++		ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev,
++			gbit_res->start, resource_size(gbit_res));
++		if (!ltq_gbit_membase) {
++			dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
++				pdev->id);
++			err = -ENOMEM;
++			goto err_out;
++		}
++	}
++
+ 	dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
+ 	strcpy(dev->name, "eth%d");
+ 	dev->netdev_ops = &ltq_eth_netdev_ops;
diff --git a/target/linux/lantiq/patches-3.0/0016-MIPS-lantiq-adds-xway-nand-driver.patch b/target/linux/lantiq/patches-3.0/0016-MIPS-lantiq-adds-xway-nand-driver.patch
new file mode 100644
index 0000000000..444e9a71c8
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/0016-MIPS-lantiq-adds-xway-nand-driver.patch
@@ -0,0 +1,267 @@
+From e2d5b4ba92289cb0fcc9db741d159ef5eb852d9f Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sat, 27 Aug 2011 20:08:14 +0200
+Subject: [PATCH 16/24] MIPS: lantiq: adds xway nand driver
+
+This patch adds a nand driver for XWAY SoCs. The patch makes use of the
+plat_nand driver. As with the EBU NOR driver merged in 3.0, we have the
+endianess swap problem on read. To workaround this problem we make the
+read_byte() callback available via the plat_nand driver causing the nand
+layer to do byte reads.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+
+TODO : memory ranges
+       cs lines
+       plat dev
+       ebu2 and not ebu1 ?
+---
+ .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |    2 +
+ arch/mips/lantiq/xway/Makefile                     |    2 +-
+ arch/mips/lantiq/xway/nand.c                       |  185 ++++++++++++++++++++
+ drivers/mtd/nand/plat_nand.c                       |    1 +
+ include/linux/mtd/nand.h                           |    1 +
+ 5 files changed, 190 insertions(+), 1 deletions(-)
+ create mode 100644 arch/mips/lantiq/xway/nand.c
+
+diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+index 86ed0d2..729dfa2 100644
+--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+@@ -140,6 +140,8 @@
+ /* register access macros for EBU and CGU */
+ #define ltq_ebu_w32(x, y)	ltq_w32((x), ltq_ebu_membase + (y))
+ #define ltq_ebu_r32(x)		ltq_r32(ltq_ebu_membase + (x))
++#define ltq_ebu_w32_mask(x, y, z) \
++	ltq_w32_mask(x, y, ltq_ebu_membase + (z))
+ #define ltq_cgu_w32(x, y)	ltq_w32((x), ltq_cgu_membase + (y))
+ #define ltq_cgu_r32(x)		ltq_r32(ltq_cgu_membase + (x))
+ 
+diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
+index 6678402..ac7cc34 100644
+--- a/arch/mips/lantiq/xway/Makefile
++++ b/arch/mips/lantiq/xway/Makefile
+@@ -1,4 +1,4 @@
+-obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
++obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o nand.o
+ 
+ obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o
+ obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o
+diff --git a/arch/mips/lantiq/xway/nand.c b/arch/mips/lantiq/xway/nand.c
+new file mode 100644
+index 0000000..ba2443c
+--- /dev/null
++++ b/arch/mips/lantiq/xway/nand.c
+@@ -0,0 +1,185 @@
++/*
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ *
++ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/mtd/physmap.h>
++#include <linux/mtd/nand.h>
++#include <linux/platform_device.h>
++
++#include <lantiq_soc.h>
++#include <lantiq_irq.h>
++#include <lantiq_platform.h>
++
++#include "devices.h"
++
++/* nand registers */
++#define LTQ_EBU_NAND_WAIT       0xB4
++#define LTQ_EBU_NAND_ECC0       0xB8
++#define LTQ_EBU_NAND_ECC_AC     0xBC
++#define LTQ_EBU_NAND_CON        0xB0
++#define LTQ_EBU_ADDSEL1         0x24
++
++/* gpio definitions */
++#define PIN_ALE    13
++#define PIN_CLE    24
++#define PIN_CS1    23
++#define PIN_RDY    48  /* NFLASH_READY */
++#define PIN_RD     49  /* NFLASH_READ_N */
++
++#define NAND_CMD_ALE            (1 << 2)
++#define NAND_CMD_CLE            (1 << 3)
++#define NAND_CMD_CS             (1 << 4)
++#define NAND_WRITE_CMD_RESET    0xff
++#define NAND_WRITE_CMD          (NAND_CMD_CS | NAND_CMD_CLE)
++#define NAND_WRITE_ADDR         (NAND_CMD_CS | NAND_CMD_ALE)
++#define NAND_WRITE_DATA         (NAND_CMD_CS)
++#define NAND_READ_DATA          (NAND_CMD_CS)
++#define NAND_WAIT_WR_C          (1 << 3)
++#define NAND_WAIT_RD            (0x1)
++
++#define ADDSEL1_MASK(x)         (x << 4)
++#define ADDSEL1_REGEN           1
++#define BUSCON1_SETUP           (1 << 22)
++#define BUSCON1_BCGEN_RES       (0x3 << 12)
++#define BUSCON1_WAITWRC2        (2 << 8)
++#define BUSCON1_WAITRDC2        (2 << 6)
++#define BUSCON1_HOLDC1          (1 << 4)
++#define BUSCON1_RECOVC1         (1 << 2)
++#define BUSCON1_CMULT4          1
++#define NAND_CON_NANDM          1
++#define NAND_CON_CSMUX          (1 << 1)
++#define NAND_CON_CS_P           (1 << 4)
++#define NAND_CON_SE_P           (1 << 5)
++#define NAND_CON_WP_P           (1 << 6)
++#define NAND_CON_PRE_P          (1 << 7)
++#define NAND_CON_IN_CS0         0
++#define NAND_CON_OUT_CS0        0
++#define NAND_CON_IN_CS1         (1 << 8)
++#define NAND_CON_OUT_CS1        (1 << 10)
++#define NAND_CON_CE             (1 << 20)
++
++#define NAND_BASE_ADDRESS       (KSEG1 | 0x14000000)
++
++static const char *part_probes[] = { "cmdlinepart", NULL };
++
++static void
++xway_select_chip(struct mtd_info *mtd, int chip)
++{
++	switch (chip) {
++	case -1:
++		ltq_ebu_w32_mask(NAND_CON_CE, 0, LTQ_EBU_NAND_CON);
++		ltq_ebu_w32_mask(NAND_CON_NANDM, 0, LTQ_EBU_NAND_CON);
++		break;
++	case 0:
++		ltq_ebu_w32_mask(0, NAND_CON_NANDM, LTQ_EBU_NAND_CON);
++		ltq_ebu_w32_mask(0, NAND_CON_CE, LTQ_EBU_NAND_CON);
++		/* reset the nand chip */
++		while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0);
++		ltq_w32(NAND_WRITE_CMD_RESET, ((u32*)(NAND_BASE_ADDRESS | NAND_WRITE_CMD)));
++		break;
++	default:
++		BUG();
++	}
++}
++
++static void
++xway_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
++{
++	struct nand_chip *this = mtd->priv;
++
++	if (ctrl & NAND_CTRL_CHANGE) {
++		if(ctrl & NAND_CLE)
++			this->IO_ADDR_W = (void __iomem *)(NAND_BASE_ADDRESS | NAND_WRITE_CMD);
++		else if(ctrl & NAND_ALE)
++			this->IO_ADDR_W = (void __iomem *)(NAND_BASE_ADDRESS | NAND_WRITE_ADDR);
++	}
++
++	if(data != NAND_CMD_NONE) {
++		*(volatile u8*)((u32)this->IO_ADDR_W) = data;
++		while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0);
++	}
++}
++
++static int
++xway_dev_ready(struct mtd_info *mtd)
++{
++	return ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_RD;
++}
++
++void
++nand_write(unsigned int addr, unsigned int val)
++{
++	ltq_w32(val, ((u32*)(NAND_BASE_ADDRESS | addr)));
++	while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0);
++}
++
++unsigned char
++ltq_nand_read_byte(struct mtd_info *mtd)
++{
++	return ltq_r8((void __iomem *)(NAND_BASE_ADDRESS | (NAND_READ_DATA)));
++}
++
++int xway_nand_probe(struct platform_device *pdev)
++{
++//	ltq_gpio_request(PIN_CS1, 1, 0, 1, "NAND_CS1");
++	ltq_gpio_request(PIN_CLE, 1, 0, 1, "NAND_CLE");
++	ltq_gpio_request(PIN_ALE, 1, 0, 1, "NAND_ALE");
++	if (ltq_is_ar9() || ltq_is_vr9()) {
++		ltq_gpio_request(PIN_RDY, 1, 0, 0, "NAND_BSY");
++		ltq_gpio_request(PIN_RD, 1, 0, 1, "NAND_RD");
++	}
++
++	ltq_ebu_w32((NAND_BASE_ADDRESS & 0x1fffff00)
++		| ADDSEL1_MASK(3) | ADDSEL1_REGEN, LTQ_EBU_ADDSEL1);
++
++	ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2
++		| BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1
++		| BUSCON1_CMULT4, LTQ_EBU_BUSCON1);
++
++	ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P
++		| NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P
++		| NAND_CON_IN_CS0 | NAND_CON_OUT_CS0, LTQ_EBU_NAND_CON);
++
++	ltq_w32(NAND_WRITE_CMD_RESET, ((u32*)(NAND_BASE_ADDRESS | NAND_WRITE_CMD)));
++	while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0);
++
++	return 0;
++}
++
++static struct platform_nand_data falcon_flash_nand_data = {
++	.chip = {
++		.nr_chips		= 1,
++		.chip_delay		= 30,
++		.part_probe_types	= part_probes,
++	},
++	.ctrl = {
++		.probe		= xway_nand_probe,
++		.cmd_ctrl	= xway_cmd_ctrl,
++		.dev_ready	= xway_dev_ready,
++		.select_chip	= xway_select_chip,
++		.read_byte = ltq_nand_read_byte,
++	}
++};
++
++static struct resource ltq_nand_res =
++	MEM_RES("nand", 0x14000000, 0x3ffffff);
++
++static struct platform_device ltq_flash_nand = {
++	.name		= "gen_nand",
++	.id		= -1,
++	.num_resources	= 1,
++	.resource	= &ltq_nand_res,
++	.dev		= {
++		.platform_data = &falcon_flash_nand_data,
++	},
++};
++
++void __init
++xway_register_nand(void)
++{
++	platform_device_register(&ltq_flash_nand);
++}
+diff --git a/drivers/mtd/nand/plat_nand.c b/drivers/mtd/nand/plat_nand.c
+index 633c04b..c3e3ef6 100644
+--- a/drivers/mtd/nand/plat_nand.c
++++ b/drivers/mtd/nand/plat_nand.c
+@@ -77,6 +77,7 @@ static int __devinit plat_nand_probe(struct platform_device *pdev)
+ 	data->chip.select_chip = pdata->ctrl.select_chip;
+ 	data->chip.write_buf = pdata->ctrl.write_buf;
+ 	data->chip.read_buf = pdata->ctrl.read_buf;
++	data->chip.read_byte = pdata->ctrl.read_byte;
+ 	data->chip.chip_delay = pdata->chip.chip_delay;
+ 	data->chip.options |= pdata->chip.options;
+ 
+diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
+index c2b9ac4..597e1a0 100644
+--- a/include/linux/mtd/nand.h
++++ b/include/linux/mtd/nand.h
+@@ -656,6 +656,7 @@ struct platform_nand_ctrl {
+ 	void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
+ 	void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
+ 	void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
++	unsigned char (*read_byte)(struct mtd_info *mtd);
+ 	void *priv;
+ };
+ 
+-- 
+1.7.5.4
+
diff --git a/target/linux/lantiq/patches-3.0/430-gptu.patch b/target/linux/lantiq/patches-3.0/0017-MIPS-lantiq-adds-GPTU-driver.patch
index b7448e8b0b..c2101c9e64 100644
--- a/target/linux/lantiq/patches-3.0/430-gptu.patch
+++ b/target/linux/lantiq/patches-3.0/0017-MIPS-lantiq-adds-GPTU-driver.patch
@@ -1,3 +1,190 @@
+From 45dbb232686978816e8148753e12f27caa2b2eb3 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 29 Sep 2011 17:16:38 +0200
+Subject: [PATCH 17/24] MIPS: lantiq: adds GPTU driver
+
+---
+ arch/mips/include/asm/mach-lantiq/lantiq_timer.h |  155 ++++
+ arch/mips/lantiq/xway/Makefile                   |    2 +-
+ arch/mips/lantiq/xway/timer.c                    |  830 ++++++++++++++++++++++
+ 3 files changed, 986 insertions(+), 1 deletions(-)
+ create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h
+ create mode 100644 arch/mips/lantiq/xway/timer.c
+
+diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_timer.h b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
+new file mode 100644
+index 0000000..ef564ab
+--- /dev/null
++++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
+@@ -0,0 +1,155 @@
++#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
++#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
++
++
++/******************************************************************************
++       Copyright (c) 2002, Infineon Technologies.  All rights reserved.
++
++                               No Warranty
++   Because the program is licensed free of charge, there is no warranty for
++   the program, to the extent permitted by applicable law.  Except when
++   otherwise stated in writing the copyright holders and/or other parties
++   provide the program "as is" without warranty of any kind, either
++   expressed or implied, including, but not limited to, the implied
++   warranties of merchantability and fitness for a particular purpose. The
++   entire risk as to the quality and performance of the program is with
++   you.  should the program prove defective, you assume the cost of all
++   necessary servicing, repair or correction.
++
++   In no event unless required by applicable law or agreed to in writing
++   will any copyright holder, or any other party who may modify and/or
++   redistribute the program as permitted above, be liable to you for
++   damages, including any general, special, incidental or consequential
++   damages arising out of the use or inability to use the program
++   (including but not limited to loss of data or data being rendered
++   inaccurate or losses sustained by you or third parties or a failure of
++   the program to operate with any other programs), even if such holder or
++   other party has been advised of the possibility of such damages.
++******************************************************************************/
++
++
++/*
++ * ####################################
++ *              Definition
++ * ####################################
++ */
++
++/*
++ *  Available Timer/Counter Index
++ */
++#define TIMER(n, X)                     (n * 2 + (X ? 1 : 0))
++#define TIMER_ANY                       0x00
++#define TIMER1A                         TIMER(1, 0)
++#define TIMER1B                         TIMER(1, 1)
++#define TIMER2A                         TIMER(2, 0)
++#define TIMER2B                         TIMER(2, 1)
++#define TIMER3A                         TIMER(3, 0)
++#define TIMER3B                         TIMER(3, 1)
++
++/*
++ *  Flag of Timer/Counter
++ *  These flags specify the way in which timer is configured.
++ */
++/*  Bit size of timer/counter.                      */
++#define TIMER_FLAG_16BIT                0x0000
++#define TIMER_FLAG_32BIT                0x0001
++/*  Switch between timer and counter.               */
++#define TIMER_FLAG_TIMER                0x0000
++#define TIMER_FLAG_COUNTER              0x0002
++/*  Stop or continue when overflowing/underflowing. */
++#define TIMER_FLAG_ONCE                 0x0000
++#define TIMER_FLAG_CYCLIC               0x0004
++/*  Count up or counter down.                       */
++#define TIMER_FLAG_UP                   0x0000
++#define TIMER_FLAG_DOWN                 0x0008
++/*  Count on specific level or edge.                */
++#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
++#define TIMER_FLAG_LOW_LEVEL_SENSITIVE  0x0040
++#define TIMER_FLAG_RISE_EDGE            0x0010
++#define TIMER_FLAG_FALL_EDGE            0x0020
++#define TIMER_FLAG_ANY_EDGE             0x0030
++/*  Signal is syncronous to module clock or not.    */
++#define TIMER_FLAG_UNSYNC               0x0000
++#define TIMER_FLAG_SYNC                 0x0080
++/*  Different interrupt handle type.                */
++#define TIMER_FLAG_NO_HANDLE            0x0000
++#if defined(__KERNEL__)
++    #define TIMER_FLAG_CALLBACK_IN_IRQ  0x0100
++#endif  //  defined(__KERNEL__)
++#define TIMER_FLAG_SIGNAL               0x0300
++/*  Internal clock source or external clock source  */
++#define TIMER_FLAG_INT_SRC              0x0000
++#define TIMER_FLAG_EXT_SRC              0x1000
++
++
++/*
++ *  ioctl Command
++ */
++#define GPTU_REQUEST_TIMER              0x01    /*  General method to setup timer/counter.  */
++#define GPTU_FREE_TIMER                 0x02    /*  Free timer/counter.                     */
++#define GPTU_START_TIMER                0x03    /*  Start or resume timer/counter.          */
++#define GPTU_STOP_TIMER                 0x04    /*  Suspend timer/counter.                  */
++#define GPTU_GET_COUNT_VALUE            0x05    /*  Get current count value.                */
++#define GPTU_CALCULATE_DIVIDER          0x06    /*  Calculate timer divider from given freq.*/
++#define GPTU_SET_TIMER                  0x07    /*  Simplified method to setup timer.       */
++#define GPTU_SET_COUNTER                0x08    /*  Simplified method to setup counter.     */
++
++/*
++ *  Data Type Used to Call ioctl
++ */
++struct gptu_ioctl_param {
++    unsigned int                        timer;  /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
++                                                 *  GPTU_SET_COUNTER, this field is ID of expected      *
++                                                 *  timer/counter. If it's zero, a timer/counter would  *
++                                                 *  be dynamically allocated and ID would be stored in  *
++                                                 *  this field.                                         *
++                                                 *  In command GPTU_GET_COUNT_VALUE, this field is      *
++                                                 *  ignored.                                            *
++                                                 *  In other command, this field is ID of timer/counter *
++                                                 *  allocated.                                          */
++    unsigned int                        flag;   /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
++                                                 *  GPTU_SET_COUNTER, this field contains flags to      *
++                                                 *  specify how to configure timer/counter.             *
++                                                 *  In command GPTU_START_TIMER, zero indicate start    *
++                                                 *  and non-zero indicate resume timer/counter.         *
++                                                 *  In other command, this field is ignored.            */
++    unsigned long                       value;  /*  In command GPTU_REQUEST_TIMER, this field contains  *
++                                                 *  init/reload value.                                  *
++                                                 *  In command GPTU_SET_TIMER, this field contains      *
++                                                 *  frequency (0.001Hz) of timer.                       *
++                                                 *  In command GPTU_GET_COUNT_VALUE, current count      *
++                                                 *  value would be stored in this field.                *
++                                                 *  In command GPTU_CALCULATE_DIVIDER, this field       *
++                                                 *  contains frequency wanted, and after calculation,   *
++                                                 *  divider would be stored in this field to overwrite  *
++                                                 *  the frequency.                                      *
++                                                 *  In other command, this field is ignored.            */
++    int                                 pid;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
++                                                 *  if signal is required, this field contains process  *
++                                                 *  ID to which signal would be sent.                   *
++                                                 *  In other command, this field is ignored.            */
++    int                                 sig;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
++                                                 *  if signal is required, this field contains signal   *
++                                                 *  number which would be sent.                         *
++                                                 *  In other command, this field is ignored.            */
++};
++
++/*
++ * ####################################
++ *              Data Type
++ * ####################################
++ */
++typedef void (*timer_callback)(unsigned long arg);
++
++extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
++extern int lq_free_timer(unsigned int);
++extern int lq_start_timer(unsigned int, int);
++extern int lq_stop_timer(unsigned int);
++extern int lq_reset_counter_flags(u32 timer, u32 flags);
++extern int lq_get_count_value(unsigned int, unsigned long *);
++extern u32 lq_cal_divider(unsigned long);
++extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
++extern int lq_set_counter(unsigned int timer, unsigned int flag,
++	u32 reload, unsigned long arg1, unsigned long arg2);
++
++#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
+diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
+index ac7cc34..1f41239 100644
+--- a/arch/mips/lantiq/xway/Makefile
++++ b/arch/mips/lantiq/xway/Makefile
+@@ -1,4 +1,4 @@
+-obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o nand.o
++obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o nand.o timer.o
+ 
+ obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o
+ obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o
+diff --git a/arch/mips/lantiq/xway/timer.c b/arch/mips/lantiq/xway/timer.c
+new file mode 100644
+index 0000000..cac2ea8
 --- /dev/null
 +++ b/arch/mips/lantiq/xway/timer.c
 @@ -0,0 +1,830 @@
@@ -831,169 +1018,6 @@
 +
 +module_init(lq_gptu_init);
 +module_exit(lq_gptu_exit);
---- /dev/null
-+++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
-@@ -0,0 +1,155 @@
-+#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
-+#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
-+
-+
-+/******************************************************************************
-+       Copyright (c) 2002, Infineon Technologies.  All rights reserved.
-+
-+                               No Warranty
-+   Because the program is licensed free of charge, there is no warranty for
-+   the program, to the extent permitted by applicable law.  Except when
-+   otherwise stated in writing the copyright holders and/or other parties
-+   provide the program "as is" without warranty of any kind, either
-+   expressed or implied, including, but not limited to, the implied
-+   warranties of merchantability and fitness for a particular purpose. The
-+   entire risk as to the quality and performance of the program is with
-+   you.  should the program prove defective, you assume the cost of all
-+   necessary servicing, repair or correction.
-+
-+   In no event unless required by applicable law or agreed to in writing
-+   will any copyright holder, or any other party who may modify and/or
-+   redistribute the program as permitted above, be liable to you for
-+   damages, including any general, special, incidental or consequential
-+   damages arising out of the use or inability to use the program
-+   (including but not limited to loss of data or data being rendered
-+   inaccurate or losses sustained by you or third parties or a failure of
-+   the program to operate with any other programs), even if such holder or
-+   other party has been advised of the possibility of such damages.
-+******************************************************************************/
-+
-+
-+/*
-+ * ####################################
-+ *              Definition
-+ * ####################################
-+ */
-+
-+/*
-+ *  Available Timer/Counter Index
-+ */
-+#define TIMER(n, X)                     (n * 2 + (X ? 1 : 0))
-+#define TIMER_ANY                       0x00
-+#define TIMER1A                         TIMER(1, 0)
-+#define TIMER1B                         TIMER(1, 1)
-+#define TIMER2A                         TIMER(2, 0)
-+#define TIMER2B                         TIMER(2, 1)
-+#define TIMER3A                         TIMER(3, 0)
-+#define TIMER3B                         TIMER(3, 1)
-+
-+/*
-+ *  Flag of Timer/Counter
-+ *  These flags specify the way in which timer is configured.
-+ */
-+/*  Bit size of timer/counter.                      */
-+#define TIMER_FLAG_16BIT                0x0000
-+#define TIMER_FLAG_32BIT                0x0001
-+/*  Switch between timer and counter.               */
-+#define TIMER_FLAG_TIMER                0x0000
-+#define TIMER_FLAG_COUNTER              0x0002
-+/*  Stop or continue when overflowing/underflowing. */
-+#define TIMER_FLAG_ONCE                 0x0000
-+#define TIMER_FLAG_CYCLIC               0x0004
-+/*  Count up or counter down.                       */
-+#define TIMER_FLAG_UP                   0x0000
-+#define TIMER_FLAG_DOWN                 0x0008
-+/*  Count on specific level or edge.                */
-+#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
-+#define TIMER_FLAG_LOW_LEVEL_SENSITIVE  0x0040
-+#define TIMER_FLAG_RISE_EDGE            0x0010
-+#define TIMER_FLAG_FALL_EDGE            0x0020
-+#define TIMER_FLAG_ANY_EDGE             0x0030
-+/*  Signal is syncronous to module clock or not.    */
-+#define TIMER_FLAG_UNSYNC               0x0000
-+#define TIMER_FLAG_SYNC                 0x0080
-+/*  Different interrupt handle type.                */
-+#define TIMER_FLAG_NO_HANDLE            0x0000
-+#if defined(__KERNEL__)
-+    #define TIMER_FLAG_CALLBACK_IN_IRQ  0x0100
-+#endif  //  defined(__KERNEL__)
-+#define TIMER_FLAG_SIGNAL               0x0300
-+/*  Internal clock source or external clock source  */
-+#define TIMER_FLAG_INT_SRC              0x0000
-+#define TIMER_FLAG_EXT_SRC              0x1000
-+
-+
-+/*
-+ *  ioctl Command
-+ */
-+#define GPTU_REQUEST_TIMER              0x01    /*  General method to setup timer/counter.  */
-+#define GPTU_FREE_TIMER                 0x02    /*  Free timer/counter.                     */
-+#define GPTU_START_TIMER                0x03    /*  Start or resume timer/counter.          */
-+#define GPTU_STOP_TIMER                 0x04    /*  Suspend timer/counter.                  */
-+#define GPTU_GET_COUNT_VALUE            0x05    /*  Get current count value.                */
-+#define GPTU_CALCULATE_DIVIDER          0x06    /*  Calculate timer divider from given freq.*/
-+#define GPTU_SET_TIMER                  0x07    /*  Simplified method to setup timer.       */
-+#define GPTU_SET_COUNTER                0x08    /*  Simplified method to setup counter.     */
-+
-+/*
-+ *  Data Type Used to Call ioctl
-+ */
-+struct gptu_ioctl_param {
-+    unsigned int                        timer;  /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
-+                                                 *  GPTU_SET_COUNTER, this field is ID of expected      *
-+                                                 *  timer/counter. If it's zero, a timer/counter would  *
-+                                                 *  be dynamically allocated and ID would be stored in  *
-+                                                 *  this field.                                         *
-+                                                 *  In command GPTU_GET_COUNT_VALUE, this field is      *
-+                                                 *  ignored.                                            *
-+                                                 *  In other command, this field is ID of timer/counter *
-+                                                 *  allocated.                                          */
-+    unsigned int                        flag;   /*  In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and  *
-+                                                 *  GPTU_SET_COUNTER, this field contains flags to      *
-+                                                 *  specify how to configure timer/counter.             *
-+                                                 *  In command GPTU_START_TIMER, zero indicate start    *
-+                                                 *  and non-zero indicate resume timer/counter.         *
-+                                                 *  In other command, this field is ignored.            */
-+    unsigned long                       value;  /*  In command GPTU_REQUEST_TIMER, this field contains  *
-+                                                 *  init/reload value.                                  *
-+                                                 *  In command GPTU_SET_TIMER, this field contains      *
-+                                                 *  frequency (0.001Hz) of timer.                       *
-+                                                 *  In command GPTU_GET_COUNT_VALUE, current count      *
-+                                                 *  value would be stored in this field.                *
-+                                                 *  In command GPTU_CALCULATE_DIVIDER, this field       *
-+                                                 *  contains frequency wanted, and after calculation,   *
-+                                                 *  divider would be stored in this field to overwrite  *
-+                                                 *  the frequency.                                      *
-+                                                 *  In other command, this field is ignored.            */
-+    int                                 pid;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
-+                                                 *  if signal is required, this field contains process  *
-+                                                 *  ID to which signal would be sent.                   *
-+                                                 *  In other command, this field is ignored.            */
-+    int                                 sig;    /*  In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER,   *
-+                                                 *  if signal is required, this field contains signal   *
-+                                                 *  number which would be sent.                         *
-+                                                 *  In other command, this field is ignored.            */
-+};
-+
-+/*
-+ * ####################################
-+ *              Data Type
-+ * ####################################
-+ */
-+typedef void (*timer_callback)(unsigned long arg);
-+
-+extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
-+extern int lq_free_timer(unsigned int);
-+extern int lq_start_timer(unsigned int, int);
-+extern int lq_stop_timer(unsigned int);
-+extern int lq_reset_counter_flags(u32 timer, u32 flags);
-+extern int lq_get_count_value(unsigned int, unsigned long *);
-+extern u32 lq_cal_divider(unsigned long);
-+extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
-+extern int lq_set_counter(unsigned int timer, unsigned int flag,
-+	u32 reload, unsigned long arg1, unsigned long arg2);
-+
-+#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
---- a/arch/mips/lantiq/xway/Makefile
-+++ b/arch/mips/lantiq/xway/Makefile
-@@ -1,4 +1,4 @@
--obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
-+obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o timer.o
- 
- obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o
- obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o
+-- 
+1.7.5.4
+
diff --git a/target/linux/lantiq/patches-3.0/440-dwc_otg.patch b/target/linux/lantiq/patches-3.0/0018-MIPS-lantiq-adds-dwc_otg.patch
index 73222ccacd..e30af11582 100644
--- a/target/linux/lantiq/patches-3.0/440-dwc_otg.patch
+++ b/target/linux/lantiq/patches-3.0/0018-MIPS-lantiq-adds-dwc_otg.patch
@@ -1,3 +1,52 @@
+From ffd7924fcc69ff146d62f131d72ef18575bf0227 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 30 Sep 2011 14:37:36 +0200
+Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg
+
+---
+ drivers/usb/Kconfig                     |    2 +
+ drivers/usb/Makefile                    |    2 +
+ drivers/usb/core/hub.c                  |    4 +-
+ drivers/usb/dwc_otg/Kconfig             |   37 +
+ drivers/usb/dwc_otg/Makefile            |   39 +
+ drivers/usb/dwc_otg/dwc_otg_attr.c      |  802 ++++++++
+ drivers/usb/dwc_otg/dwc_otg_attr.h      |   67 +
+ drivers/usb/dwc_otg/dwc_otg_cil.c       | 3025 +++++++++++++++++++++++++++++++
+ drivers/usb/dwc_otg/dwc_otg_cil.h       |  911 ++++++++++
+ drivers/usb/dwc_otg/dwc_otg_cil_ifx.h   |   58 +
+ drivers/usb/dwc_otg/dwc_otg_cil_intr.c  |  708 ++++++++
+ drivers/usb/dwc_otg/dwc_otg_driver.c    | 1274 +++++++++++++
+ drivers/usb/dwc_otg/dwc_otg_driver.h    |   84 +
+ drivers/usb/dwc_otg/dwc_otg_hcd.c       | 2870 +++++++++++++++++++++++++++++
+ drivers/usb/dwc_otg/dwc_otg_hcd.h       |  676 +++++++
+ drivers/usb/dwc_otg/dwc_otg_hcd_intr.c  | 1841 +++++++++++++++++++
+ drivers/usb/dwc_otg/dwc_otg_hcd_queue.c |  794 ++++++++
+ drivers/usb/dwc_otg/dwc_otg_ifx.c       |  100 +
+ drivers/usb/dwc_otg/dwc_otg_ifx.h       |   85 +
+ drivers/usb/dwc_otg/dwc_otg_plat.h      |  269 +++
+ drivers/usb/dwc_otg/dwc_otg_regs.h      | 1797 ++++++++++++++++++
+ 21 files changed, 15443 insertions(+), 2 deletions(-)
+ create mode 100644 drivers/usb/dwc_otg/Kconfig
+ create mode 100644 drivers/usb/dwc_otg/Makefile
+ create mode 100644 drivers/usb/dwc_otg/dwc_otg_attr.c
+ create mode 100644 drivers/usb/dwc_otg/dwc_otg_attr.h
+ create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.c
+ create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.h
+ create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil_ifx.h
+ create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil_intr.c
+ create mode 100644 drivers/usb/dwc_otg/dwc_otg_driver.c
+ create mode 100644 drivers/usb/dwc_otg/dwc_otg_driver.h
+ create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.c
+ create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.h
+ create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
+ create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
+ create mode 100644 drivers/usb/dwc_otg/dwc_otg_ifx.c
+ create mode 100644 drivers/usb/dwc_otg/dwc_otg_ifx.h
+ create mode 100644 drivers/usb/dwc_otg/dwc_otg_plat.h
+ create mode 100644 drivers/usb/dwc_otg/dwc_otg_regs.h
+
+diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
+index 48f1781..b48c1bd 100644
 --- a/drivers/usb/Kconfig
 +++ b/drivers/usb/Kconfig
 @@ -116,6 +116,8 @@ source "drivers/usb/wusbcore/Kconfig"
@@ -9,6 +58,8 @@
  source "drivers/usb/musb/Kconfig"
  
  source "drivers/usb/renesas_usbhs/Kconfig"
+diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
+index 30ddf8d..ba3b993 100644
 --- a/drivers/usb/Makefile
 +++ b/drivers/usb/Makefile
 @@ -28,6 +28,8 @@ obj-$(CONFIG_USB_C67X00_HCD)	+= c67x00/
@@ -20,6 +71,27 @@
  obj-$(CONFIG_USB_ACM)		+= class/
  obj-$(CONFIG_USB_PRINTER)	+= class/
  obj-$(CONFIG_USB_WDM)		+= class/
+diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
+index a428aa0..115ae9a 100644
+--- a/drivers/usb/core/hub.c
++++ b/drivers/usb/core/hub.c
+@@ -2885,11 +2885,11 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1,
+ 		udev->ttport = hdev->ttport;
+ 	} else if (udev->speed != USB_SPEED_HIGH
+ 			&& hdev->speed == USB_SPEED_HIGH) {
+-		if (!hub->tt.hub) {
++/*		if (!hub->tt.hub) {
+ 			dev_err(&udev->dev, "parent hub has no TT\n");
+ 			retval = -EINVAL;
+ 			goto fail;
+-		}
++		}*/
+ 		udev->tt = &hub->tt;
+ 		udev->ttport = port1;
+ 	}
+diff --git a/drivers/usb/dwc_otg/Kconfig b/drivers/usb/dwc_otg/Kconfig
+new file mode 100644
+index 0000000..e018490
 --- /dev/null
 +++ b/drivers/usb/dwc_otg/Kconfig
 @@ -0,0 +1,37 @@
@@ -60,6 +132,9 @@
 +config DWC_OTG_DEBUG
 +        bool "Enable debug mode"
 +        depends on DWC_OTG
+diff --git a/drivers/usb/dwc_otg/Makefile b/drivers/usb/dwc_otg/Makefile
+new file mode 100644
+index 0000000..d4d2355
 --- /dev/null
 +++ b/drivers/usb/dwc_otg/Makefile
 @@ -0,0 +1,39 @@
@@ -102,6 +177,9 @@
 +
 +#obj-$(CONFIG_DWC_OTG_IFX)	:= dwc_otg_ifx.o
 +#dwc_otg_ifx-objs		:= dwc_otg_ifx.o
+diff --git a/drivers/usb/dwc_otg/dwc_otg_attr.c b/drivers/usb/dwc_otg/dwc_otg_attr.c
+new file mode 100644
+index 0000000..4675a5c
 --- /dev/null
 +++ b/drivers/usb/dwc_otg/dwc_otg_attr.c
 @@ -0,0 +1,802 @@
@@ -907,6 +985,9 @@
 +	device_remove_file(_dev, &dev_attr_rd_reg_test);
 +	device_remove_file(_dev, &dev_attr_wr_reg_test);
 +}
+diff --git a/drivers/usb/dwc_otg/dwc_otg_attr.h b/drivers/usb/dwc_otg/dwc_otg_attr.h
+new file mode 100644
+index 0000000..4bbf7df
 --- /dev/null
 +++ b/drivers/usb/dwc_otg/dwc_otg_attr.h
 @@ -0,0 +1,67 @@
@@ -977,6 +1058,9 @@
 +void dwc_otg_attr_remove (struct device *_dev);
 +
 +#endif
+diff --git a/drivers/usb/dwc_otg/dwc_otg_cil.c b/drivers/usb/dwc_otg/dwc_otg_cil.c
+new file mode 100644
+index 0000000..42c69eb
 --- /dev/null
 +++ b/drivers/usb/dwc_otg/dwc_otg_cil.c
 @@ -0,0 +1,3025 @@
@@ -4005,6 +4089,9 @@
 +        _cb->p = _p;
 +}
 +
+diff --git a/drivers/usb/dwc_otg/dwc_otg_cil.h b/drivers/usb/dwc_otg/dwc_otg_cil.h
+new file mode 100644
+index 0000000..bbb9516
 --- /dev/null
 +++ b/drivers/usb/dwc_otg/dwc_otg_cil.h
 @@ -0,0 +1,911 @@
@@ -4919,6 +5006,9 @@
 +
 +
 +#endif
+diff --git a/drivers/usb/dwc_otg/dwc_otg_cil_ifx.h b/drivers/usb/dwc_otg/dwc_otg_cil_ifx.h
+new file mode 100644
+index 0000000..b0298ec
 --- /dev/null
 +++ b/drivers/usb/dwc_otg/dwc_otg_cil_ifx.h
 @@ -0,0 +1,58 @@
@@ -4980,6 +5070,9 @@
 +
 +#endif // __DWC_OTG_CIL_IFX_H__
 +
+diff --git a/drivers/usb/dwc_otg/dwc_otg_cil_intr.c b/drivers/usb/dwc_otg/dwc_otg_cil_intr.c
+new file mode 100644
+index 0000000..d469ab4
 --- /dev/null
 +++ b/drivers/usb/dwc_otg/dwc_otg_cil_intr.c
 @@ -0,0 +1,708 @@
@@ -5691,6 +5784,9 @@
 +        }
 +        return retval;
 +}
+diff --git a/drivers/usb/dwc_otg/dwc_otg_driver.c b/drivers/usb/dwc_otg/dwc_otg_driver.c
+new file mode 100644
+index 0000000..1b0daab
 --- /dev/null
 +++ b/drivers/usb/dwc_otg/dwc_otg_driver.c
 @@ -0,0 +1,1274 @@
@@ -6968,6 +7064,9 @@
 + </td></tr>
 +
 +*/
+diff --git a/drivers/usb/dwc_otg/dwc_otg_driver.h b/drivers/usb/dwc_otg/dwc_otg_driver.h
+new file mode 100644
+index 0000000..7e6940d
 --- /dev/null
 +++ b/drivers/usb/dwc_otg/dwc_otg_driver.h
 @@ -0,0 +1,84 @@
@@ -7055,6 +7154,9 @@
 +//#define dev_dbg(fake, format, arg...) printk(KERN_CRIT __FILE__ ":%d: " format "\n" , __LINE__, ## arg)
 +
 +#endif
+diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd.c b/drivers/usb/dwc_otg/dwc_otg_hcd.c
+new file mode 100644
+index 0000000..ad6bc72
 --- /dev/null
 +++ b/drivers/usb/dwc_otg/dwc_otg_hcd.c
 @@ -0,0 +1,2870 @@
@@ -9928,6 +10030,9 @@
 +#endif
 +}
 +#endif /* DWC_DEVICE_ONLY */
+diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd.h b/drivers/usb/dwc_otg/dwc_otg_hcd.h
+new file mode 100644
+index 0000000..8a20dff
 --- /dev/null
 +++ b/drivers/usb/dwc_otg/dwc_otg_hcd.h
 @@ -0,0 +1,676 @@
@@ -10607,6 +10712,9 @@
 +#endif // DEBUG		
 +#endif // __DWC_HCD_H__
 +#endif /* DWC_DEVICE_ONLY */
+diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
+new file mode 100644
+index 0000000..834b5e0
 --- /dev/null
 +++ b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c
 @@ -0,0 +1,1841 @@
@@ -12451,6 +12559,9 @@
 +}
 +
 +#endif /* DWC_DEVICE_ONLY */
+diff --git a/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
+new file mode 100644
+index 0000000..fcb5ce6
 --- /dev/null
 +++ b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c
 @@ -0,0 +1,794 @@
@@ -13248,6 +13359,9 @@
 +}
 +
 +#endif /* DWC_DEVICE_ONLY */
+diff --git a/drivers/usb/dwc_otg/dwc_otg_ifx.c b/drivers/usb/dwc_otg/dwc_otg_ifx.c
+new file mode 100644
+index 0000000..0a4c209
 --- /dev/null
 +++ b/drivers/usb/dwc_otg/dwc_otg_ifx.c
 @@ -0,0 +1,100 @@
@@ -13351,6 +13465,9 @@
 +void ifx_usb_hc_remove(void)
 +{
 +}
+diff --git a/drivers/usb/dwc_otg/dwc_otg_ifx.h b/drivers/usb/dwc_otg/dwc_otg_ifx.h
+new file mode 100644
+index 0000000..402d7a6
 --- /dev/null
 +++ b/drivers/usb/dwc_otg/dwc_otg_ifx.h
 @@ -0,0 +1,85 @@
@@ -13439,6 +13556,9 @@
 +	ltq_mask_and_ack_irq(&d);
 +}
 +#endif //__DWC_OTG_IFX_H__
+diff --git a/drivers/usb/dwc_otg/dwc_otg_plat.h b/drivers/usb/dwc_otg/dwc_otg_plat.h
+new file mode 100644
+index 0000000..727d0c4
 --- /dev/null
 +++ b/drivers/usb/dwc_otg/dwc_otg_plat.h
 @@ -0,0 +1,269 @@
@@ -13711,6 +13831,9 @@
 +
 +#endif
 +
+diff --git a/drivers/usb/dwc_otg/dwc_otg_regs.h b/drivers/usb/dwc_otg/dwc_otg_regs.h
+new file mode 100644
+index 0000000..397a954
 --- /dev/null
 +++ b/drivers/usb/dwc_otg/dwc_otg_regs.h
 @@ -0,0 +1,1797 @@
@@ -15511,121 +15634,6 @@
 +} dwc_otg_host_if_t;
 +
 +#endif
---- a/arch/mips/lantiq/xway/Makefile
-+++ b/arch/mips/lantiq/xway/Makefile
-@@ -1,5 +1,5 @@
- obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o timer.o
--
-+obj-y += dev-dwc_otg.o
- obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o
- obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o
- 
---- /dev/null
-+++ b/arch/mips/lantiq/xway/dev-dwc_otg.c
-@@ -0,0 +1,70 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/types.h>
-+#include <linux/string.h>
-+#include <linux/mtd/physmap.h>
-+#include <linux/kernel.h>
-+#include <linux/reboot.h>
-+#include <linux/platform_device.h>
-+#include <linux/leds.h>
-+#include <linux/etherdevice.h>
-+#include <linux/reboot.h>
-+#include <linux/time.h>
-+#include <linux/io.h>
-+#include <linux/gpio.h>
-+#include <linux/leds.h>
-+
-+#include <asm/bootinfo.h>
-+#include <asm/irq.h>
-+
-+#include <lantiq_soc.h>
-+#include <lantiq_irq.h>
-+#include <lantiq_platform.h>
-+
-+#define LTQ_USB_IOMEM_BASE 0x1e101000
-+#define LTQ_USB_IOMEM_SIZE 0x00001000
-+
-+static struct resource resources[] =
-+{
-+	[0] = {
-+		.name    = "dwc_otg_membase",
-+		.start   = LTQ_USB_IOMEM_BASE,
-+		.end	 = LTQ_USB_IOMEM_BASE + LTQ_USB_IOMEM_SIZE - 1,
-+		.flags	 = IORESOURCE_MEM,
-+	},
-+	[1] = {
-+		.name    = "dwc_otg_irq",
-+		.start   = LTQ_USB_INT,
-+		.flags   = IORESOURCE_IRQ,
-+	},
-+};
-+
-+static u64 dwc_dmamask = (u32)0x1fffffff;
-+
-+static struct platform_device platform_dev = {
-+	.name = "dwc_otg",
-+	.dev = {
-+		.dma_mask      = &dwc_dmamask,
-+	},
-+	.resource		= resources,
-+	.num_resources		= ARRAY_SIZE(resources),
-+};
-+
-+int __init
-+xway_register_dwc(int pin)
-+{
-+	struct irq_data d;
-+	d.irq = resources[1].start;
-+	ltq_enable_irq(&d);
-+	platform_dev.dev.platform_data = (void*) pin;
-+	return platform_device_register(&platform_dev);
-+}
---- /dev/null
-+++ b/arch/mips/lantiq/xway/dev-dwc_otg.h
-@@ -0,0 +1,17 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#ifndef _LTQ_DEV_DWC_H__
-+#define _LTQ_DEV_DWC_H__
-+
-+#include <lantiq_platform.h>
-+
-+extern void __init xway_register_dwc(int pin);
-+
-+#endif
---- a/drivers/usb/core/hub.c
-+++ b/drivers/usb/core/hub.c
-@@ -2885,11 +2885,11 @@ hub_port_init (struct usb_hub *hub, stru
- 		udev->ttport = hdev->ttport;
- 	} else if (udev->speed != USB_SPEED_HIGH
- 			&& hdev->speed == USB_SPEED_HIGH) {
--		if (!hub->tt.hub) {
-+/*		if (!hub->tt.hub) {
- 			dev_err(&udev->dev, "parent hub has no TT\n");
- 			retval = -EINVAL;
- 			goto fail;
--		}
-+		}*/
- 		udev->tt = &hub->tt;
- 		udev->ttport = port1;
- 	}
+-- 
+1.7.5.4
+
diff --git a/target/linux/lantiq/patches-3.0/250-mt-vpe.patch b/target/linux/lantiq/patches-3.0/0019-MIPS-lantiq-adds-VPE-extensions.patch
index 4a8e8d5534..e11507ce8a 100644
--- a/target/linux/lantiq/patches-3.0/250-mt-vpe.patch
+++ b/target/linux/lantiq/patches-3.0/0019-MIPS-lantiq-adds-VPE-extensions.patch
@@ -1,6 +1,27 @@
+From c6c810d83f0d95f54c3a6b338d219cec7ccef4c9 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 29 Sep 2011 20:30:40 +0200
+Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions
+
+---
+ arch/mips/Kconfig                  |   22 +++
+ arch/mips/include/asm/mipsmtregs.h |   54 +++++++
+ arch/mips/kernel/Makefile          |    3 +-
+ arch/mips/kernel/mips-mt.c         |   97 +++++++++++--
+ arch/mips/kernel/mtsched_proc.c    |  279 ++++++++++++++++++++++++++++++++++++
+ arch/mips/kernel/perf_proc.c       |  191 ++++++++++++++++++++++++
+ arch/mips/kernel/proc.c            |   17 +++
+ arch/mips/kernel/smtc.c            |    7 +
+ arch/mips/kernel/vpe.c             |  250 ++++++++++++++++++++++++++++++++-
+ 9 files changed, 905 insertions(+), 15 deletions(-)
+ create mode 100644 arch/mips/kernel/mtsched_proc.c
+ create mode 100644 arch/mips/kernel/perf_proc.c
+
+diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
+index 0cf5bbd..bf1b76d 100644
 --- a/arch/mips/Kconfig
 +++ b/arch/mips/Kconfig
-@@ -1905,6 +1905,28 @@ config MIPS_VPE_LOADER
+@@ -1903,6 +1903,28 @@ config MIPS_VPE_LOADER
  	  Includes a loader for loading an elf relocatable object
  	  onto another VPE and running it.
  
@@ -29,6 +50,8 @@
  config MIPS_MT_SMTC_IM_BACKSTOP
  	bool "Use per-TC register bits as backstop for inhibited IM bits"
  	depends on MIPS_MT_SMTC
+diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h
+index c9420aa..04bfb4b 100644
 --- a/arch/mips/include/asm/mipsmtregs.h
 +++ b/arch/mips/include/asm/mipsmtregs.h
 @@ -28,14 +28,34 @@
@@ -138,9 +161,11 @@
  
  /* GPR */
  #define read_tc_gpr_sp()		mftgpr(29)
+diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
+index 83bba33..53a9a0a 100644
 --- a/arch/mips/kernel/Makefile
 +++ b/arch/mips/kernel/Makefile
-@@ -86,7 +86,8 @@ obj-$(CONFIG_MIPS32_O32)	+= binfmt_elfo3
+@@ -86,7 +86,8 @@ obj-$(CONFIG_MIPS32_O32)	+= binfmt_elfo32.o scall64-o32.o
  
  obj-$(CONFIG_KGDB)		+= kgdb.o
  obj-$(CONFIG_PROC_FS)		+= proc.o
@@ -150,6 +175,8 @@
  obj-$(CONFIG_64BIT)		+= cpu-bugs64.o
  
  obj-$(CONFIG_I8253)		+= i8253.o
+diff --git a/arch/mips/kernel/mips-mt.c b/arch/mips/kernel/mips-mt.c
+index 594ca69..ad912fc 100644
 --- a/arch/mips/kernel/mips-mt.c
 +++ b/arch/mips/kernel/mips-mt.c
 @@ -21,26 +21,96 @@
@@ -254,7 +281,7 @@
  
  /*
   * Dump new MIPS MT state for the core. Does not leave TCs halted.
-@@ -78,18 +148,18 @@ void mips_mt_regdump(unsigned long mvpct
+@@ -78,18 +148,18 @@ void mips_mt_regdump(unsigned long mvpctl)
  			if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) {
  				printk("  VPE %d\n", i);
  				printk("   VPEControl : %08lx\n",
@@ -290,417 +317,9 @@
  }
  
  /*
---- a/arch/mips/kernel/proc.c
-+++ b/arch/mips/kernel/proc.c
-@@ -7,6 +7,7 @@
- #include <linux/kernel.h>
- #include <linux/sched.h>
- #include <linux/seq_file.h>
-+#include <linux/proc_fs.h>
- #include <asm/bootinfo.h>
- #include <asm/cpu.h>
- #include <asm/cpu-features.h>
-@@ -110,3 +111,19 @@ const struct seq_operations cpuinfo_op =
- 	.stop	= c_stop,
- 	.show	= show_cpuinfo,
- };
-+
-+/*
-+ * Support for MIPS/local /proc hooks in /proc/mips/
-+ */
-+
-+static struct proc_dir_entry *mips_proc = NULL;
-+
-+struct proc_dir_entry *get_mips_proc_dir(void)
-+{
-+       /*
-+        * This ought not to be preemptable.
-+        */
-+       if(mips_proc == NULL)
-+               mips_proc = proc_mkdir("mips", NULL);
-+       return(mips_proc);
-+}
---- a/arch/mips/kernel/smtc.c
-+++ b/arch/mips/kernel/smtc.c
-@@ -1334,6 +1334,13 @@ void smtc_get_new_mmu_context(struct mm_
- 	asid = asid_cache(cpu);
- 
- 	do {
-+#ifdef CONFIG_IFX_VPE_EXT
-+		/* If TLB is shared between AP and RP (AP is running SMTC),
-+		   leave out max ASID i.e., ASID_MASK for RP
-+		 */
-+		if (!nostlb && ((asid & ASID_MASK) == (ASID_MASK - 1)))
-+			asid++;
-+#endif
- 		if (!((asid += ASID_INC) & ASID_MASK) ) {
- 			if (cpu_has_vtag_icache)
- 				flush_icache_all();
---- a/arch/mips/kernel/vpe.c
-+++ b/arch/mips/kernel/vpe.c
-@@ -76,6 +76,58 @@ static struct kspd_notifications kspd_ev
- static int kspd_events_reqd;
- #endif
- 
-+#ifdef CONFIG_IFX_VPE_EXT
-+static int is_sdepgm;
-+extern int stlb;
-+extern int vpe0_wired;
-+extern int vpe1_wired;
-+unsigned int vpe1_load_addr;
-+
-+static int __init load_address(char *str)
-+{
-+	get_option(&str, &vpe1_load_addr);
-+	return 1;
-+}
-+__setup("vpe1_load_addr=", load_address);
-+
-+#include <asm/mipsmtregs.h>
-+#define write_vpe_c0_wired(val)		mttc0(6, 0, val)
-+
-+#ifndef COMMAND_LINE_SIZE
-+#	define COMMAND_LINE_SIZE	512
-+#endif
-+
-+char command_line[COMMAND_LINE_SIZE * 2];
-+
-+static unsigned int vpe1_mem;
-+static int __init vpe1mem(char *str)
-+{
-+	vpe1_mem = memparse(str, &str);
-+	return 1;
-+}
-+__setup("vpe1_mem=", vpe1mem);
-+
-+uint32_t vpe1_wdog_ctr;
-+static int __init wdog_ctr(char *str)
-+{
-+	get_option(&str, &vpe1_wdog_ctr);
-+	return 1;
-+}
-+
-+__setup("vpe1_wdog_ctr_addr=", wdog_ctr);
-+EXPORT_SYMBOL(vpe1_wdog_ctr);
-+
-+uint32_t vpe1_wdog_timeout;
-+static int __init wdog_timeout(char *str)
-+{
-+        get_option(&str, &vpe1_wdog_timeout);
-+        return 1;
-+}
-+
-+__setup("vpe1_wdog_timeout=", wdog_timeout);
-+EXPORT_SYMBOL(vpe1_wdog_timeout);
-+
-+#endif
- /* grab the likely amount of memory we will need. */
- #ifdef CONFIG_MIPS_VPE_LOADER_TOM
- #define P_SIZE (2 * 1024 * 1024)
-@@ -268,6 +320,13 @@ static void *alloc_progmem(unsigned long
- 	void *addr;
- 
- #ifdef CONFIG_MIPS_VPE_LOADER_TOM
-+#ifdef CONFIG_IFX_VPE_EXT
-+	if (vpe1_load_addr) {
-+		memset((void *)vpe1_load_addr, 0, len);
-+		return (void *)vpe1_load_addr;
-+	}
-+#endif
-+
- 	/*
- 	 * This means you must tell Linux to use less memory than you
- 	 * physically have, for example by passing a mem= boot argument.
-@@ -746,6 +805,12 @@ static int vpe_run(struct vpe * v)
- 	}
- 
- 	/* Write the address we want it to start running from in the TCPC register. */
-+#if defined(CONFIG_IFX_VPE_EXT) && 0
-+	if (stlb)
-+		write_vpe_c0_wired(vpe0_wired + vpe1_wired);
-+	else
-+		write_vpe_c0_wired(vpe1_wired);
-+#endif
- 	write_tc_c0_tcrestart((unsigned long)v->__start);
- 	write_tc_c0_tccontext((unsigned long)0);
- 
-@@ -759,6 +824,20 @@ static int vpe_run(struct vpe * v)
- 
- 	write_tc_c0_tchalt(read_tc_c0_tchalt() & ~TCHALT_H);
- 
-+#if defined(CONFIG_IFX_VPE_EXT) && 0
-+	/*
-+	 * $a2 & $a3 are used to pass command line parameters to VPE1. $a2
-+	 * points to the start of the command line string and $a3 points to
-+	 * the end of the string. This convention is identical to the Linux
-+	 * kernel boot parameter passing mechanism. Please note that $a3 is
-+	 * used to pass physical memory size or 0 in SDE tool kit. So, if you
-+	 * are passing comand line parameters through $a2 & $a3 SDE programs
-+	 * don't work as desired.
-+	 */
-+	mttgpr(6, command_line);
-+	mttgpr(7, (command_line + strlen(command_line)));
-+	if (is_sdepgm)
-+#endif
- 	/*
- 	 * The sde-kit passes 'memsize' to __start in $a3, so set something
- 	 * here...  Or set $a3 to zero and define DFLT_STACK_SIZE and
-@@ -833,6 +912,9 @@ static int find_vpe_symbols(struct vpe *
- 	if ( (v->__start == 0) || (v->shared_ptr == NULL))
- 		return -1;
- 
-+#ifdef CONFIG_IFX_VPE_EXT
-+	is_sdepgm = 1;
-+#endif
- 	return 0;
- }
- 
-@@ -994,6 +1076,15 @@ static int vpe_elfload(struct vpe * v)
- 			   (unsigned long)v->load_addr + v->len);
- 
- 	if ((find_vpe_symbols(v, sechdrs, symindex, strtab, &mod)) < 0) {
-+#ifdef CONFIG_IFX_VPE_EXT
-+		if (vpe1_load_addr) {
-+			/* Conversion to KSEG1 is required ??? */
-+			v->__start = KSEG1ADDR(vpe1_load_addr);
-+			is_sdepgm = 0;
-+			return 0;
-+		}
-+#endif
-+
- 		if (v->__start == 0) {
- 			printk(KERN_WARNING "VPE loader: program does not contain "
- 			       "a __start symbol\n");
-@@ -1064,6 +1155,9 @@ static int vpe_open(struct inode *inode,
- 	struct vpe_notifications *not;
- 	struct vpe *v;
- 	int ret;
-+#ifdef CONFIG_IFX_VPE_EXT
-+   int progsize;
-+#endif
- 
- 	if (minor != iminor(inode)) {
- 		/* assume only 1 device at the moment. */
-@@ -1089,7 +1183,12 @@ static int vpe_open(struct inode *inode,
- 		release_progmem(v->load_addr);
- 		cleanup_tc(get_tc(tclimit));
- 	}
--
-+#ifdef CONFIG_IFX_VPE_EXT
-+	progsize = (vpe1_mem  != 0) ? vpe1_mem : P_SIZE;
-+	//printk("progsize = %x\n", progsize);
-+	v->pbuffer = vmalloc(progsize);
-+	v->plen = progsize;
-+#else
- 	/* this of-course trashes what was there before... */
- 	v->pbuffer = vmalloc(P_SIZE);
- 	if (!v->pbuffer) {
-@@ -1097,11 +1196,14 @@ static int vpe_open(struct inode *inode,
- 		return -ENOMEM;
- 	}
- 	v->plen = P_SIZE;
-+#endif
- 	v->load_addr = NULL;
- 	v->len = 0;
- 
-+#if 0
- 	v->uid = filp->f_cred->fsuid;
- 	v->gid = filp->f_cred->fsgid;
-+#endif
- 
- #ifdef CONFIG_MIPS_APSP_KSPD
- 	/* get kspd to tell us when a syscall_exit happens */
-@@ -1349,6 +1451,133 @@ static void kspd_sp_exit( int sp_id)
- 	cleanup_tc(get_tc(sp_id));
- }
- #endif
-+#ifdef CONFIG_IFX_VPE_EXT
-+int32_t vpe1_sw_start(void* sw_start_addr, uint32_t tcmask, uint32_t flags)
-+{
-+	enum vpe_state state;
-+	struct vpe *v = get_vpe(tclimit);
-+	struct vpe_notifications *not;
-+
-+	if (tcmask || flags) {
-+		printk(KERN_WARNING "Currently tcmask and flags should be 0.\
-+				other values not supported\n");
-+		return -1;
-+	}
-+
-+	state = xchg(&v->state, VPE_STATE_INUSE);
-+	if (state != VPE_STATE_UNUSED) {
-+		vpe_stop(v);
-+
-+		list_for_each_entry(not, &v->notify, list) {
-+			not->stop(tclimit);
-+		}
-+	}
-+
-+	v->__start = (unsigned long)sw_start_addr;
-+	is_sdepgm = 0;
-+
-+	if (!vpe_run(v)) {
-+		printk(KERN_DEBUG "VPE loader: VPE1 running successfully\n");
-+		return 0;
-+	}
-+	return -1;
-+}
-+
-+EXPORT_SYMBOL(vpe1_sw_start);
-+
-+int32_t vpe1_sw_stop(uint32_t flags)
-+{
-+	struct vpe *v = get_vpe(tclimit);
-+
-+	if (!vpe_free(v)) {
-+		printk(KERN_DEBUG "RP Stopped\n");
-+		return 0;
-+	}
-+	else
-+		return -1;
-+}
-+
-+EXPORT_SYMBOL(vpe1_sw_stop);
-+
-+uint32_t vpe1_get_load_addr (uint32_t flags)
-+{
-+	return vpe1_load_addr;
-+}
-+
-+EXPORT_SYMBOL(vpe1_get_load_addr);
-+
-+uint32_t vpe1_get_max_mem (uint32_t flags)
-+{
-+	if (!vpe1_mem)
-+		return P_SIZE;
-+	else
-+		return vpe1_mem;
-+}
-+
-+EXPORT_SYMBOL(vpe1_get_max_mem);
-+
-+void* vpe1_get_cmdline_argument(void)
-+{
-+	return saved_command_line;
-+}
-+
-+EXPORT_SYMBOL(vpe1_get_cmdline_argument);
-+
-+int32_t vpe1_set_boot_param(char *field, char *value, char flags)
-+{
-+	char *ptr, string[64];
-+	int start_off, end_off;
-+	if (!field)
-+		return -1;
-+	strcpy(string, field);
-+	if (value) {
-+		strcat(string, "=");
-+		strcat(string, value);
-+		strcat(command_line, " ");
-+		strcat(command_line, string);
-+	}
-+	else {
-+		ptr = strstr(command_line, string);
-+		if (ptr) {
-+			start_off = ptr - command_line;
-+			ptr += strlen(string);
-+			while ((*ptr != ' ') && (*ptr != '\0'))
-+				ptr++;
-+			end_off = ptr - command_line;
-+			command_line[start_off] = '\0';
-+			strcat (command_line, command_line+end_off);
-+		}
-+	}
-+	return 0;
-+}
-+
-+EXPORT_SYMBOL(vpe1_set_boot_param);
-+
-+int32_t vpe1_get_boot_param(char *field, char **value, char flags)
-+{
-+	char *ptr, string[64];
-+	int i = 0;
-+	if (!field)
-+		return -1;
-+	if ((ptr = strstr(command_line, field))) {
-+		ptr += strlen(field) + 1; /* including = */
-+		while ((*ptr != ' ') && (*ptr != '\0'))
-+			string[i++] = *ptr++;
-+		string[i] = '\0';
-+		*value = kmalloc((strlen(string) + 1), GFP_KERNEL);
-+		if (*value != NULL)
-+			strcpy(*value, string);
-+	}
-+	else
-+		*value = NULL;
-+
-+	return 0;
-+}
-+
-+EXPORT_SYMBOL(vpe1_get_boot_param);
-+
-+extern void configure_tlb(void);
-+#endif
- 
- static ssize_t store_kill(struct device *dev, struct device_attribute *attr,
- 			  const char *buf, size_t len)
-@@ -1430,6 +1659,18 @@ static int __init vpe_module_init(void)
- 		printk("VPE loader: not a MIPS MT capable processor\n");
- 		return -ENODEV;
- 	}
-+#ifdef CONFIG_IFX_VPE_EXT
-+#ifndef CONFIG_MIPS_MT_SMTC
-+	configure_tlb();
-+#endif
-+#endif
-+
-+#ifndef CONFIG_MIPS_MT_SMTC
-+	if (!vpelimit)
-+		vpelimit = 1;
-+	if (!tclimit)
-+		tclimit = 1;
-+#endif
- 
- 	if (vpelimit == 0) {
- 		printk(KERN_WARNING "No VPEs reserved for AP/SP, not "
-@@ -1474,10 +1715,12 @@ static int __init vpe_module_init(void)
- 	mtflags = dmt();
- 	vpflags = dvpe();
- 
-+	back_to_back_c0_hazard();
-+
- 	/* Put MVPE's into 'configuration state' */
- 	set_c0_mvpcontrol(MVPCONTROL_VPC);
- 
--	/* dump_mtregs(); */
-+	dump_mtregs();
- 
- 	val = read_c0_mvpconf0();
- 	hw_tcs = (val & MVPCONF0_PTC) + 1;
-@@ -1489,6 +1732,7 @@ static int __init vpe_module_init(void)
- 		 * reschedule send IPIs or similar we might hang.
- 		 */
- 		clear_c0_mvpcontrol(MVPCONTROL_VPC);
-+		back_to_back_c0_hazard();
- 		evpe(vpflags);
- 		emt(mtflags);
- 		local_irq_restore(flags);
-@@ -1514,6 +1758,7 @@ static int __init vpe_module_init(void)
- 			}
- 
- 			v->ntcs = hw_tcs - tclimit;
-+                        write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | 1);
- 
- 			/* add the tc to the list of this vpe's tc's. */
- 			list_add(&t->tc, &v->tc);
-@@ -1582,6 +1827,7 @@ static int __init vpe_module_init(void)
- out_reenable:
- 	/* release config state */
- 	clear_c0_mvpcontrol(MVPCONTROL_VPC);
-+	back_to_back_c0_hazard();
- 
- 	evpe(vpflags);
- 	emt(mtflags);
+diff --git a/arch/mips/kernel/mtsched_proc.c b/arch/mips/kernel/mtsched_proc.c
+new file mode 100644
+index 0000000..4dafded
 --- /dev/null
 +++ b/arch/mips/kernel/mtsched_proc.c
 @@ -0,0 +1,279 @@
@@ -983,6 +602,9 @@
 +
 +/* Automagically create the entry */
 +module_init(init_mtsched_proc);
+diff --git a/arch/mips/kernel/perf_proc.c b/arch/mips/kernel/perf_proc.c
+new file mode 100644
+index 0000000..7eec015
 --- /dev/null
 +++ b/arch/mips/kernel/perf_proc.c
 @@ -0,0 +1,191 @@
@@ -1177,3 +799,423 @@
 +
 +/* Automagically create the entry */
 +module_init(init_perf_proc);
+diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
+index e309665..2de204f 100644
+--- a/arch/mips/kernel/proc.c
++++ b/arch/mips/kernel/proc.c
+@@ -7,6 +7,7 @@
+ #include <linux/kernel.h>
+ #include <linux/sched.h>
+ #include <linux/seq_file.h>
++#include <linux/proc_fs.h>
+ #include <asm/bootinfo.h>
+ #include <asm/cpu.h>
+ #include <asm/cpu-features.h>
+@@ -110,3 +111,19 @@ const struct seq_operations cpuinfo_op = {
+ 	.stop	= c_stop,
+ 	.show	= show_cpuinfo,
+ };
++
++/*
++ * Support for MIPS/local /proc hooks in /proc/mips/
++ */
++
++static struct proc_dir_entry *mips_proc = NULL;
++
++struct proc_dir_entry *get_mips_proc_dir(void)
++{
++       /*
++        * This ought not to be preemptable.
++        */
++       if(mips_proc == NULL)
++               mips_proc = proc_mkdir("mips", NULL);
++       return(mips_proc);
++}
+diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
+index f0895e7..199e853 100644
+--- a/arch/mips/kernel/smtc.c
++++ b/arch/mips/kernel/smtc.c
+@@ -1334,6 +1334,13 @@ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
+ 	asid = asid_cache(cpu);
+ 
+ 	do {
++#ifdef CONFIG_IFX_VPE_EXT
++		/* If TLB is shared between AP and RP (AP is running SMTC),
++		   leave out max ASID i.e., ASID_MASK for RP
++		 */
++		if (!nostlb && ((asid & ASID_MASK) == (ASID_MASK - 1)))
++			asid++;
++#endif
+ 		if (!((asid += ASID_INC) & ASID_MASK) ) {
+ 			if (cpu_has_vtag_icache)
+ 				flush_icache_all();
+diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
+index 3efcb06..742f24b 100644
+--- a/arch/mips/kernel/vpe.c
++++ b/arch/mips/kernel/vpe.c
+@@ -76,6 +76,58 @@ static struct kspd_notifications kspd_events;
+ static int kspd_events_reqd;
+ #endif
+ 
++#ifdef CONFIG_IFX_VPE_EXT
++static int is_sdepgm;
++extern int stlb;
++extern int vpe0_wired;
++extern int vpe1_wired;
++unsigned int vpe1_load_addr;
++
++static int __init load_address(char *str)
++{
++	get_option(&str, &vpe1_load_addr);
++	return 1;
++}
++__setup("vpe1_load_addr=", load_address);
++
++#include <asm/mipsmtregs.h>
++#define write_vpe_c0_wired(val)		mttc0(6, 0, val)
++
++#ifndef COMMAND_LINE_SIZE
++#	define COMMAND_LINE_SIZE	512
++#endif
++
++char command_line[COMMAND_LINE_SIZE * 2];
++
++static unsigned int vpe1_mem;
++static int __init vpe1mem(char *str)
++{
++	vpe1_mem = memparse(str, &str);
++	return 1;
++}
++__setup("vpe1_mem=", vpe1mem);
++
++uint32_t vpe1_wdog_ctr;
++static int __init wdog_ctr(char *str)
++{
++	get_option(&str, &vpe1_wdog_ctr);
++	return 1;
++}
++
++__setup("vpe1_wdog_ctr_addr=", wdog_ctr);
++EXPORT_SYMBOL(vpe1_wdog_ctr);
++
++uint32_t vpe1_wdog_timeout;
++static int __init wdog_timeout(char *str)
++{
++        get_option(&str, &vpe1_wdog_timeout);
++        return 1;
++}
++
++__setup("vpe1_wdog_timeout=", wdog_timeout);
++EXPORT_SYMBOL(vpe1_wdog_timeout);
++
++#endif
+ /* grab the likely amount of memory we will need. */
+ #ifdef CONFIG_MIPS_VPE_LOADER_TOM
+ #define P_SIZE (2 * 1024 * 1024)
+@@ -268,6 +320,13 @@ static void *alloc_progmem(unsigned long len)
+ 	void *addr;
+ 
+ #ifdef CONFIG_MIPS_VPE_LOADER_TOM
++#ifdef CONFIG_IFX_VPE_EXT
++	if (vpe1_load_addr) {
++		memset((void *)vpe1_load_addr, 0, len);
++		return (void *)vpe1_load_addr;
++	}
++#endif
++
+ 	/*
+ 	 * This means you must tell Linux to use less memory than you
+ 	 * physically have, for example by passing a mem= boot argument.
+@@ -746,6 +805,12 @@ static int vpe_run(struct vpe * v)
+ 	}
+ 
+ 	/* Write the address we want it to start running from in the TCPC register. */
++#if defined(CONFIG_IFX_VPE_EXT) && 0
++	if (stlb)
++		write_vpe_c0_wired(vpe0_wired + vpe1_wired);
++	else
++		write_vpe_c0_wired(vpe1_wired);
++#endif
+ 	write_tc_c0_tcrestart((unsigned long)v->__start);
+ 	write_tc_c0_tccontext((unsigned long)0);
+ 
+@@ -759,6 +824,20 @@ static int vpe_run(struct vpe * v)
+ 
+ 	write_tc_c0_tchalt(read_tc_c0_tchalt() & ~TCHALT_H);
+ 
++#if defined(CONFIG_IFX_VPE_EXT) && 0
++	/*
++	 * $a2 & $a3 are used to pass command line parameters to VPE1. $a2
++	 * points to the start of the command line string and $a3 points to
++	 * the end of the string. This convention is identical to the Linux
++	 * kernel boot parameter passing mechanism. Please note that $a3 is
++	 * used to pass physical memory size or 0 in SDE tool kit. So, if you
++	 * are passing comand line parameters through $a2 & $a3 SDE programs
++	 * don't work as desired.
++	 */
++	mttgpr(6, command_line);
++	mttgpr(7, (command_line + strlen(command_line)));
++	if (is_sdepgm)
++#endif
+ 	/*
+ 	 * The sde-kit passes 'memsize' to __start in $a3, so set something
+ 	 * here...  Or set $a3 to zero and define DFLT_STACK_SIZE and
+@@ -833,6 +912,9 @@ static int find_vpe_symbols(struct vpe * v, Elf_Shdr * sechdrs,
+ 	if ( (v->__start == 0) || (v->shared_ptr == NULL))
+ 		return -1;
+ 
++#ifdef CONFIG_IFX_VPE_EXT
++	is_sdepgm = 1;
++#endif
+ 	return 0;
+ }
+ 
+@@ -994,6 +1076,15 @@ static int vpe_elfload(struct vpe * v)
+ 			   (unsigned long)v->load_addr + v->len);
+ 
+ 	if ((find_vpe_symbols(v, sechdrs, symindex, strtab, &mod)) < 0) {
++#ifdef CONFIG_IFX_VPE_EXT
++		if (vpe1_load_addr) {
++			/* Conversion to KSEG1 is required ??? */
++			v->__start = KSEG1ADDR(vpe1_load_addr);
++			is_sdepgm = 0;
++			return 0;
++		}
++#endif
++
+ 		if (v->__start == 0) {
+ 			printk(KERN_WARNING "VPE loader: program does not contain "
+ 			       "a __start symbol\n");
+@@ -1064,6 +1155,9 @@ static int vpe_open(struct inode *inode, struct file *filp)
+ 	struct vpe_notifications *not;
+ 	struct vpe *v;
+ 	int ret;
++#ifdef CONFIG_IFX_VPE_EXT
++   int progsize;
++#endif
+ 
+ 	if (minor != iminor(inode)) {
+ 		/* assume only 1 device at the moment. */
+@@ -1089,7 +1183,12 @@ static int vpe_open(struct inode *inode, struct file *filp)
+ 		release_progmem(v->load_addr);
+ 		cleanup_tc(get_tc(tclimit));
+ 	}
+-
++#ifdef CONFIG_IFX_VPE_EXT
++	progsize = (vpe1_mem  != 0) ? vpe1_mem : P_SIZE;
++	//printk("progsize = %x\n", progsize);
++	v->pbuffer = vmalloc(progsize);
++	v->plen = progsize;
++#else
+ 	/* this of-course trashes what was there before... */
+ 	v->pbuffer = vmalloc(P_SIZE);
+ 	if (!v->pbuffer) {
+@@ -1097,11 +1196,14 @@ static int vpe_open(struct inode *inode, struct file *filp)
+ 		return -ENOMEM;
+ 	}
+ 	v->plen = P_SIZE;
++#endif
+ 	v->load_addr = NULL;
+ 	v->len = 0;
+ 
++#if 0
+ 	v->uid = filp->f_cred->fsuid;
+ 	v->gid = filp->f_cred->fsgid;
++#endif
+ 
+ #ifdef CONFIG_MIPS_APSP_KSPD
+ 	/* get kspd to tell us when a syscall_exit happens */
+@@ -1349,6 +1451,133 @@ static void kspd_sp_exit( int sp_id)
+ 	cleanup_tc(get_tc(sp_id));
+ }
+ #endif
++#ifdef CONFIG_IFX_VPE_EXT
++int32_t vpe1_sw_start(void* sw_start_addr, uint32_t tcmask, uint32_t flags)
++{
++	enum vpe_state state;
++	struct vpe *v = get_vpe(tclimit);
++	struct vpe_notifications *not;
++
++	if (tcmask || flags) {
++		printk(KERN_WARNING "Currently tcmask and flags should be 0.\
++				other values not supported\n");
++		return -1;
++	}
++
++	state = xchg(&v->state, VPE_STATE_INUSE);
++	if (state != VPE_STATE_UNUSED) {
++		vpe_stop(v);
++
++		list_for_each_entry(not, &v->notify, list) {
++			not->stop(tclimit);
++		}
++	}
++
++	v->__start = (unsigned long)sw_start_addr;
++	is_sdepgm = 0;
++
++	if (!vpe_run(v)) {
++		printk(KERN_DEBUG "VPE loader: VPE1 running successfully\n");
++		return 0;
++	}
++	return -1;
++}
++
++EXPORT_SYMBOL(vpe1_sw_start);
++
++int32_t vpe1_sw_stop(uint32_t flags)
++{
++	struct vpe *v = get_vpe(tclimit);
++
++	if (!vpe_free(v)) {
++		printk(KERN_DEBUG "RP Stopped\n");
++		return 0;
++	}
++	else
++		return -1;
++}
++
++EXPORT_SYMBOL(vpe1_sw_stop);
++
++uint32_t vpe1_get_load_addr (uint32_t flags)
++{
++	return vpe1_load_addr;
++}
++
++EXPORT_SYMBOL(vpe1_get_load_addr);
++
++uint32_t vpe1_get_max_mem (uint32_t flags)
++{
++	if (!vpe1_mem)
++		return P_SIZE;
++	else
++		return vpe1_mem;
++}
++
++EXPORT_SYMBOL(vpe1_get_max_mem);
++
++void* vpe1_get_cmdline_argument(void)
++{
++	return saved_command_line;
++}
++
++EXPORT_SYMBOL(vpe1_get_cmdline_argument);
++
++int32_t vpe1_set_boot_param(char *field, char *value, char flags)
++{
++	char *ptr, string[64];
++	int start_off, end_off;
++	if (!field)
++		return -1;
++	strcpy(string, field);
++	if (value) {
++		strcat(string, "=");
++		strcat(string, value);
++		strcat(command_line, " ");
++		strcat(command_line, string);
++	}
++	else {
++		ptr = strstr(command_line, string);
++		if (ptr) {
++			start_off = ptr - command_line;
++			ptr += strlen(string);
++			while ((*ptr != ' ') && (*ptr != '\0'))
++				ptr++;
++			end_off = ptr - command_line;
++			command_line[start_off] = '\0';
++			strcat (command_line, command_line+end_off);
++		}
++	}
++	return 0;
++}
++
++EXPORT_SYMBOL(vpe1_set_boot_param);
++
++int32_t vpe1_get_boot_param(char *field, char **value, char flags)
++{
++	char *ptr, string[64];
++	int i = 0;
++	if (!field)
++		return -1;
++	if ((ptr = strstr(command_line, field))) {
++		ptr += strlen(field) + 1; /* including = */
++		while ((*ptr != ' ') && (*ptr != '\0'))
++			string[i++] = *ptr++;
++		string[i] = '\0';
++		*value = kmalloc((strlen(string) + 1), GFP_KERNEL);
++		if (*value != NULL)
++			strcpy(*value, string);
++	}
++	else
++		*value = NULL;
++
++	return 0;
++}
++
++EXPORT_SYMBOL(vpe1_get_boot_param);
++
++extern void configure_tlb(void);
++#endif
+ 
+ static ssize_t store_kill(struct device *dev, struct device_attribute *attr,
+ 			  const char *buf, size_t len)
+@@ -1430,6 +1659,18 @@ static int __init vpe_module_init(void)
+ 		printk("VPE loader: not a MIPS MT capable processor\n");
+ 		return -ENODEV;
+ 	}
++#ifdef CONFIG_IFX_VPE_EXT
++#ifndef CONFIG_MIPS_MT_SMTC
++	configure_tlb();
++#endif
++#endif
++
++#ifndef CONFIG_MIPS_MT_SMTC
++	if (!vpelimit)
++		vpelimit = 1;
++	if (!tclimit)
++		tclimit = 1;
++#endif
+ 
+ 	if (vpelimit == 0) {
+ 		printk(KERN_WARNING "No VPEs reserved for AP/SP, not "
+@@ -1474,10 +1715,12 @@ static int __init vpe_module_init(void)
+ 	mtflags = dmt();
+ 	vpflags = dvpe();
+ 
++	back_to_back_c0_hazard();
++
+ 	/* Put MVPE's into 'configuration state' */
+ 	set_c0_mvpcontrol(MVPCONTROL_VPC);
+ 
+-	/* dump_mtregs(); */
++	dump_mtregs();
+ 
+ 	val = read_c0_mvpconf0();
+ 	hw_tcs = (val & MVPCONF0_PTC) + 1;
+@@ -1489,6 +1732,7 @@ static int __init vpe_module_init(void)
+ 		 * reschedule send IPIs or similar we might hang.
+ 		 */
+ 		clear_c0_mvpcontrol(MVPCONTROL_VPC);
++		back_to_back_c0_hazard();
+ 		evpe(vpflags);
+ 		emt(mtflags);
+ 		local_irq_restore(flags);
+@@ -1514,6 +1758,7 @@ static int __init vpe_module_init(void)
+ 			}
+ 
+ 			v->ntcs = hw_tcs - tclimit;
++                        write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | 1);
+ 
+ 			/* add the tc to the list of this vpe's tc's. */
+ 			list_add(&t->tc, &v->tc);
+@@ -1582,6 +1827,7 @@ static int __init vpe_module_init(void)
+ out_reenable:
+ 	/* release config state */
+ 	clear_c0_mvpcontrol(MVPCONTROL_VPC);
++	back_to_back_c0_hazard();
+ 
+ 	evpe(vpflags);
+ 	emt(mtflags);
+-- 
+1.7.5.4
+
diff --git a/target/linux/lantiq/patches-3.0/0020-MIPS-lantiq-adds-falcon-VPE-softdog.patch b/target/linux/lantiq/patches-3.0/0020-MIPS-lantiq-adds-falcon-VPE-softdog.patch
new file mode 100644
index 0000000000..9f727cc1e7
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/0020-MIPS-lantiq-adds-falcon-VPE-softdog.patch
@@ -0,0 +1,183 @@
+From e3c377986855f820513edf2924a022a39c363908 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 29 Sep 2011 21:29:14 +0200
+Subject: [PATCH 20/24] MIPS: lantiq: adds falcon VPE softdog
+
+---
+ arch/mips/include/asm/mach-lantiq/falcon/vpe.h |   44 ++++++++++
+ arch/mips/lantiq/falcon/softdog_vpe.c          |  109 ++++++++++++++++++++++++
+ 2 files changed, 153 insertions(+), 0 deletions(-)
+ create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/vpe.h
+ create mode 100644 arch/mips/lantiq/falcon/softdog_vpe.c
+
+Index: linux-3.0.3/arch/mips/include/asm/mach-lantiq/falcon/vpe.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-3.0.3/arch/mips/include/asm/mach-lantiq/falcon/vpe.h	2011-10-05 13:26:22.732981532 +0200
+@@ -0,0 +1,44 @@
++/*
++ *   This program is free software; you can redistribute it and/or modify
++ *   it under the terms of the GNU General Public License as published by
++ *   the Free Software Foundation; either version 2 of the License, or
++ *   (at your option) any later version.
++ *
++ *   This program is distributed in the hope that it will be useful,
++ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *   GNU General Public License for more details.
++ *
++ *   You should have received a copy of the GNU General Public License
++ *   along with this program; if not, write to the Free Software
++ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
++ *
++ *   Copyright (C) 2005 infineon
++ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
++ *
++ */
++#ifndef _IFXMIPS_VPE_H__
++#define _IFXMIPS_VPE_H__
++
++/* For the explanation of the APIs please refer the section "MT APRP Kernel
++ * Programming" in AR9 SW Architecture Specification
++ */
++int32_t vpe1_sw_start(void* sw_start_addr, uint32_t tcmask, uint32_t flags);
++int32_t vpe1_sw_stop(uint32_t flags);
++uint32_t vpe1_get_load_addr (uint32_t flags);
++uint32_t vpe1_get_max_mem (uint32_t flags);
++
++int32_t vpe1_set_boot_param(char *field, char *value, char flags);
++int32_t vpe1_get_boot_param(char *field, char **value, char flags);
++
++/* Watchdog APIs */
++extern unsigned long vpe1_wdog_ctr;
++extern unsigned long vpe1_wdog_timeout;
++
++unsigned long vpe1_sw_wdog_start(unsigned long);
++unsigned long vpe1_sw_wdog_stop(unsigned long);
++
++typedef int (*VPE_SW_WDOG_RESET)(unsigned long wdog_cleared_ok_count);
++int32_t vpe1_sw_wdog_register_reset_handler(VPE_SW_WDOG_RESET reset_fn);
++
++#endif
+Index: linux-3.0.3/arch/mips/lantiq/falcon/softdog_vpe.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-3.0.3/arch/mips/lantiq/falcon/softdog_vpe.c	2011-10-05 13:26:22.736981533 +0200
+@@ -0,0 +1,109 @@
++/*
++** =============================================================================
++** FILE NAME     : softdog_vpe.c
++** MODULES       : LXDB
++** DATE          : 24-03-2008
++** AUTHOR        : LXDB Team
++** DESCRIPTION   : This header file contains the code for the watchdog
++**                 implentation on vpe1 side.
++** REFERENCES    :
++** COPYRIGHT     : Copyright (c) 2008
++**                 Am Campeon 1-12, 85579 Neubiberg, Germany
++** Any use of this software is subject to the conclusion of a respective
++** License agreement. Without such a License agreement no rights to the
++** software are granted
++**
++** HISTORY       :
++** $Date   $Author    $Comment
++** 24-03-2008   LXDB    Initial version
++** ============================================================================
++*/
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/types.h>
++#include <linux/timer.h>
++#include <linux/reboot.h>
++#include <linux/init.h>
++#include <linux/jiffies.h>
++
++#include <falcon/vpe.h>
++
++static unsigned long last_wdog_value;
++static unsigned long vpe1_wdog_cleared;
++
++static unsigned long vpe1_wdog_dead;
++static void watchdog_vpe0_fire(unsigned long); /* Called when vpe0 timer expires */
++static void keep_alive_vpe0(unsigned long);
++VPE_SW_WDOG_RESET reset_local_fn;
++
++
++static struct timer_list watchdog_vpe0_ticktock =
++                TIMER_INITIALIZER(watchdog_vpe0_fire, 0, 0);
++
++static void watchdog_vpe0_fire (unsigned long flags)
++{
++	volatile unsigned long *wdog_ctr_value;
++	wdog_ctr_value = (void*)vpe1_wdog_ctr;
++	if (*wdog_ctr_value == last_wdog_value) { /* VPE1 watchdog expiry handling */
++		vpe1_sw_wdog_stop(flags);
++		vpe1_wdog_dead++;
++		printk(KERN_DEBUG "VPE1 watchdog reset handler called\n");
++	/* Call the reset handler function */
++		reset_local_fn(flags);
++	} else { /* Everything is OK on vpe1 side. Continue. */
++		last_wdog_value = *wdog_ctr_value;
++		vpe1_wdog_cleared++;
++		keep_alive_vpe0(flags);
++	}
++}
++
++int32_t vpe1_sw_wdog_register_reset_handler (VPE_SW_WDOG_RESET reset_fn)
++{
++	reset_local_fn = (VPE_SW_WDOG_RESET)reset_fn;
++	return 0;
++}
++
++static void keep_alive_vpe0(unsigned long flags)
++{
++	mod_timer(&watchdog_vpe0_ticktock, jiffies+ vpe1_wdog_timeout );
++}
++
++unsigned long vpe1_sw_wdog_start(unsigned long flags)
++{
++	volatile unsigned long *wdog_ctr_value;
++	wdog_ctr_value = (void*)vpe1_wdog_ctr;
++	*wdog_ctr_value = 0;
++	last_wdog_value = 0;
++	keep_alive_vpe0(flags);
++	return 0;
++}
++
++unsigned long vpe1_sw_wdog_stop(unsigned long flags)
++{
++	del_timer(&watchdog_vpe0_ticktock);
++	return 0;
++}
++
++static int __init watchdog_vpe1_init(void)
++{
++	/* Nothing to be done here */
++	return 0;
++}
++
++static void __exit watchdog_vpe1_exit(void)
++{
++	unsigned long flags=0;
++	vpe1_sw_wdog_stop(flags);
++}
++
++module_init(watchdog_vpe1_init);
++module_exit(watchdog_vpe1_exit);
++
++EXPORT_SYMBOL(vpe1_sw_wdog_register_reset_handler);
++EXPORT_SYMBOL(vpe1_sw_wdog_start);
++EXPORT_SYMBOL(vpe1_sw_wdog_stop);
++
++MODULE_AUTHOR("LXDB");
++MODULE_DESCRIPTION("Software Watchdog For VPE1");
++MODULE_LICENSE("GPL");
+Index: linux-3.0.3/arch/mips/lantiq/falcon/Makefile
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/falcon/Makefile	2011-10-05 13:38:41.801013127 +0200
++++ linux-3.0.3/arch/mips/lantiq/falcon/Makefile	2011-10-05 13:38:47.341013363 +0200
+@@ -1,2 +1,2 @@
+-obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o
++obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o softdog_vpe.o
+ obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o
diff --git a/target/linux/lantiq/patches-3.0/260-ar9-cache-split.patch b/target/linux/lantiq/patches-3.0/0021-MIPS-lantiq-adds-cache-split.patch
index 5ae2d11569..98cb6bbd7f 100644
--- a/target/linux/lantiq/patches-3.0/260-ar9-cache-split.patch
+++ b/target/linux/lantiq/patches-3.0/0021-MIPS-lantiq-adds-cache-split.patch
@@ -1,6 +1,19 @@
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -1912,6 +1912,28 @@ config IFX_VPE_EXT
+From 0f85e79f6f01f50cb703866a555085a9c65bad2f Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 29 Sep 2011 20:31:54 +0200
+Subject: [PATCH 21/24] MIPS: lantiq: adds cache split
+
+---
+ arch/mips/Kconfig      |   22 ++++++
+ arch/mips/kernel/vpe.c |   66 ++++++++++++++++++
+ arch/mips/mm/c-r4k.c   |  172 ++++++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 260 insertions(+), 0 deletions(-)
+
+Index: linux-3.0.3/arch/mips/Kconfig
+===================================================================
+--- linux-3.0.3.orig/arch/mips/Kconfig	2011-10-05 12:53:54.792898260 +0200
++++ linux-3.0.3/arch/mips/Kconfig	2011-10-05 12:53:54.852898263 +0200
+@@ -1913,6 +1913,28 @@
  	help
  	  IFX included extensions in APRP
  
@@ -29,9 +42,11 @@
  config PERFCTRS
  	bool "34K Performance counters"
  	depends on MIPS_MT && PROC_FS
---- a/arch/mips/kernel/vpe.c
-+++ b/arch/mips/kernel/vpe.c
-@@ -128,6 +128,13 @@ __setup("vpe1_wdog_timeout=", wdog_timeo
+Index: linux-3.0.3/arch/mips/kernel/vpe.c
+===================================================================
+--- linux-3.0.3.orig/arch/mips/kernel/vpe.c	2011-10-05 12:53:54.800898262 +0200
++++ linux-3.0.3/arch/mips/kernel/vpe.c	2011-10-05 12:53:54.852898263 +0200
+@@ -128,6 +128,13 @@
  EXPORT_SYMBOL(vpe1_wdog_timeout);
  
  #endif
@@ -45,7 +60,7 @@
  /* grab the likely amount of memory we will need. */
  #ifdef CONFIG_MIPS_VPE_LOADER_TOM
  #define P_SIZE (2 * 1024 * 1024)
-@@ -866,6 +873,65 @@ static int vpe_run(struct vpe * v)
+@@ -866,6 +873,65 @@
  	/* enable this VPE */
  	write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA);
  
@@ -111,9 +126,11 @@
  	/* clear out any left overs from a previous program */
  	write_vpe_c0_status(0);
  	write_vpe_c0_cause(0);
---- a/arch/mips/mm/c-r4k.c
-+++ b/arch/mips/mm/c-r4k.c
-@@ -1346,6 +1346,106 @@ static int __init setcoherentio(char *st
+Index: linux-3.0.3/arch/mips/mm/c-r4k.c
+===================================================================
+--- linux-3.0.3.orig/arch/mips/mm/c-r4k.c	2011-08-17 19:57:16.000000000 +0200
++++ linux-3.0.3/arch/mips/mm/c-r4k.c	2011-10-05 12:53:54.852898263 +0200
+@@ -1346,6 +1346,106 @@
  __setup("coherentio", setcoherentio);
  #endif
  
@@ -220,7 +237,7 @@
  void __cpuinit r4k_cache_init(void)
  {
  	extern void build_clear_page(void);
-@@ -1365,6 +1465,78 @@ void __cpuinit r4k_cache_init(void)
+@@ -1365,6 +1465,78 @@
  		break;
  	}
  
@@ -299,3 +316,38 @@
  	probe_pcache();
  	setup_scache();
  
+Index: linux-3.0.3/arch/mips/lantiq/setup.c
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/setup.c	2011-10-05 13:20:49.808967301 +0200
++++ linux-3.0.3/arch/mips/lantiq/setup.c	2011-10-05 13:23:27.796974054 +0200
+@@ -18,10 +18,11 @@
+ #include "devices.h"
+ #include "prom.h"
+ 
++/* assume 16M as default incase uboot fails to pass proper ramsize */
++unsigned long physical_memsize = 16L;
++
+ void __init plat_mem_setup(void)
+ {
+-	/* assume 16M as default incase uboot fails to pass proper ramsize */
+-	unsigned long memsize = 16;
+ 	char **envp = (char **) KSEG1ADDR(fw_arg2);
+ 
+ 	ioport_resource.start = IOPORT_RESOURCE_START;
+@@ -35,13 +36,13 @@
+ 		char *e = (char *)KSEG1ADDR(*envp);
+ 		if (!strncmp(e, "memsize=", 8)) {
+ 			e += 8;
+-			if (strict_strtoul(e, 0, &memsize))
++			if (strict_strtoul(e, 0, &physical_memsize))
+ 				pr_warn("bad memsize specified\n");
+ 		}
+ 		envp++;
+ 	}
+-	memsize *= 1024 * 1024;
+-	add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
++	physical_memsize *= 1024 * 1024;
++	add_memory_region(0x00000000, physical_memsize, BOOT_MEM_RAM);
+ }
+ 
+ static int __init
diff --git a/target/linux/lantiq/patches-3.0/240-udp_redirect.patch b/target/linux/lantiq/patches-3.0/0022-MIPS-lantiq-adds-udp-in-kernel-redirect.patch
index 79ecb7c2b2..637cc53312 100644
--- a/target/linux/lantiq/patches-3.0/240-udp_redirect.patch
+++ b/target/linux/lantiq/patches-3.0/0022-MIPS-lantiq-adds-udp-in-kernel-redirect.patch
@@ -1,3 +1,21 @@
+From 14ff975c660696fa636e8d6b58d0abed0ddc72ce Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 29 Sep 2011 20:29:54 +0200
+Subject: [PATCH 22/24] MIPS: lantiq: adds udp in-kernel redirect
+
+---
+ include/linux/udp_redirect.h |   57 +++++++++++++
+ net/Kconfig                  |    6 ++
+ net/ipv4/Makefile            |    3 +
+ net/ipv4/udp.c               |   28 ++++++-
+ net/ipv4/udp_redirect_symb.c |  186 ++++++++++++++++++++++++++++++++++++++++++
+ 5 files changed, 276 insertions(+), 4 deletions(-)
+ create mode 100644 include/linux/udp_redirect.h
+ create mode 100644 net/ipv4/udp_redirect_symb.c
+
+diff --git a/include/linux/udp_redirect.h b/include/linux/udp_redirect.h
+new file mode 100644
+index 0000000..de1e64f
 --- /dev/null
 +++ b/include/linux/udp_redirect.h
 @@ -0,0 +1,57 @@
@@ -58,6 +76,114 @@
 +extern int udpredirect_getfrag(void *p, char * to, int offset,
 +                               int fraglen, int odd, struct sk_buff *skb);
 +#endif
+diff --git a/net/Kconfig b/net/Kconfig
+index a073148..d13e3fa 100644
+--- a/net/Kconfig
++++ b/net/Kconfig
+@@ -72,6 +72,12 @@ config INET
+ 
+ 	  Short answer: say Y.
+ 
++config IFX_UDP_REDIRECT
++	bool "IFX Kernel Packet Interface for UDP redirection"
++	help
++	  You can say Y here if you want to use hooks from kernel for
++	  UDP redirection.
++
+ if INET
+ source "net/ipv4/Kconfig"
+ source "net/ipv6/Kconfig"
+diff --git a/net/ipv4/Makefile b/net/ipv4/Makefile
+index f2dc69c..6badd72 100644
+--- a/net/ipv4/Makefile
++++ b/net/ipv4/Makefile
+@@ -14,6 +14,9 @@ obj-y     := route.o inetpeer.o protocol.o \
+ 	     inet_fragment.o ping.o
+ 
+ obj-$(CONFIG_SYSCTL) += sysctl_net_ipv4.o
++ifneq ($(CONFIG_IFX_UDP_REDIRECT),)
++obj-$(CONFIG_IFX_UDP_REDIRECT) += udp_redirect_symb.o
++endif
+ obj-$(CONFIG_PROC_FS) += proc.o
+ obj-$(CONFIG_IP_MULTIPLE_TABLES) += fib_rules.o
+ obj-$(CONFIG_IP_MROUTE) += ipmr.o
+diff --git a/net/ipv4/udp.c b/net/ipv4/udp.c
+index 1b5a193..4d15cf6 100644
+--- a/net/ipv4/udp.c
++++ b/net/ipv4/udp.c
+@@ -108,6 +108,10 @@
+ #include <trace/events/udp.h>
+ #include "udp_impl.h"
+ 
++#if defined(CONFIG_IFX_UDP_REDIRECT) || defined(CONFIG_IFX_UDP_REDIRECT_MODULE)
++#include <linux/udp_redirect.h>
++#endif
++
+ struct udp_table udp_table __read_mostly;
+ EXPORT_SYMBOL(udp_table);
+ 
+@@ -803,7 +807,7 @@ int udp_sendmsg(struct kiocb *iocb, struct sock *sk, struct msghdr *msg,
+ 	u8  tos;
+ 	int err, is_udplite = IS_UDPLITE(sk);
+ 	int corkreq = up->corkflag || msg->msg_flags&MSG_MORE;
+-	int (*getfrag)(void *, char *, int, int, int, struct sk_buff *);
++	int (*getfrag)(void *, char *, int, int, int, struct sk_buff *) = NULL;
+ 	struct sk_buff *skb;
+ 	struct ip_options_data opt_copy;
+ 
+@@ -820,7 +824,13 @@ int udp_sendmsg(struct kiocb *iocb, struct sock *sk, struct msghdr *msg,
+ 	ipc.opt = NULL;
+ 	ipc.tx_flags = 0;
+ 
+-	getfrag = is_udplite ? udplite_getfrag : ip_generic_getfrag;
++/* UDPREDIRECT */
++#if defined(CONFIG_IFX_UDP_REDIRECT) || defined(CONFIG_IFX_UDP_REDIRECT_MODULE)
++	if(udpredirect_getfrag_fn && sk->sk_user_data == UDP_REDIRECT_MAGIC)
++		getfrag = udpredirect_getfrag_fn;
++	else
++#endif /* IFX_UDP_REDIRECT */
++		getfrag = is_udplite ? udplite_getfrag : ip_generic_getfrag;
+ 
+ 	fl4 = &inet->cork.fl.u.ip4;
+ 	if (up->pending) {
+@@ -1621,6 +1631,7 @@ int __udp4_lib_rcv(struct sk_buff *skb, struct udp_table *udptable,
+ 	struct rtable *rt = skb_rtable(skb);
+ 	__be32 saddr, daddr;
+ 	struct net *net = dev_net(skb->dev);
++	int ret = 0;
+ 
+ 	/*
+ 	 *  Validate the packet.
+@@ -1653,7 +1664,16 @@ int __udp4_lib_rcv(struct sk_buff *skb, struct udp_table *udptable,
+ 	sk = __udp4_lib_lookup_skb(skb, uh->source, uh->dest, udptable);
+ 
+ 	if (sk != NULL) {
+-		int ret = udp_queue_rcv_skb(sk, skb);
++	/* UDPREDIRECT */
++#if defined(CONFIG_IFX_UDP_REDIRECT) || defined(CONFIG_IFX_UDP_REDIRECT_MODULE)
++      if(udp_do_redirect_fn && sk->sk_user_data == UDP_REDIRECT_MAGIC)
++      {
++         udp_do_redirect_fn(sk,skb);
++         kfree_skb(skb);
++         return(0);
++      }
++#endif
++		ret = udp_queue_rcv_skb(sk, skb);
+ 		sock_put(sk);
+ 
+ 		/* a return value > 0 means to resubmit the input, but
+@@ -1950,7 +1970,7 @@ struct proto udp_prot = {
+ 	.clear_sk	   = sk_prot_clear_portaddr_nulls,
+ };
+ EXPORT_SYMBOL(udp_prot);
+-
++EXPORT_SYMBOL(udp_rcv);
+ /* ------------------------------------------------------------------------ */
+ #ifdef CONFIG_PROC_FS
+ 
+diff --git a/net/ipv4/udp_redirect_symb.c b/net/ipv4/udp_redirect_symb.c
+new file mode 100644
+index 0000000..5617e86
 --- /dev/null
 +++ b/net/ipv4/udp_redirect_symb.c
 @@ -0,0 +1,186 @@
@@ -247,102 +373,6 @@
 +EXPORT_SYMBOL(udp_do_redirect_fn);
 +EXPORT_SYMBOL(udpredirect_getfrag_fn);
 +#endif /* CONFIG_IFX_UDP_REDIRECT* */
---- a/net/ipv4/Makefile
-+++ b/net/ipv4/Makefile
-@@ -14,6 +14,9 @@ obj-y     := route.o inetpeer.o protocol
- 	     inet_fragment.o ping.o
- 
- obj-$(CONFIG_SYSCTL) += sysctl_net_ipv4.o
-+ifneq ($(CONFIG_IFX_UDP_REDIRECT),)
-+obj-$(CONFIG_IFX_UDP_REDIRECT) += udp_redirect_symb.o
-+endif
- obj-$(CONFIG_PROC_FS) += proc.o
- obj-$(CONFIG_IP_MULTIPLE_TABLES) += fib_rules.o
- obj-$(CONFIG_IP_MROUTE) += ipmr.o
---- a/net/ipv4/udp.c
-+++ b/net/ipv4/udp.c
-@@ -107,6 +107,10 @@
- #include <net/xfrm.h>
- #include "udp_impl.h"
- 
-+#if defined(CONFIG_IFX_UDP_REDIRECT) || defined(CONFIG_IFX_UDP_REDIRECT_MODULE)
-+#include <linux/udp_redirect.h>
-+#endif
-+
- struct udp_table udp_table __read_mostly;
- EXPORT_SYMBOL(udp_table);
- 
-@@ -802,7 +806,7 @@ int udp_sendmsg(struct kiocb *iocb, stru
- 	u8  tos;
- 	int err, is_udplite = IS_UDPLITE(sk);
- 	int corkreq = up->corkflag || msg->msg_flags&MSG_MORE;
--	int (*getfrag)(void *, char *, int, int, int, struct sk_buff *);
-+	int (*getfrag)(void *, char *, int, int, int, struct sk_buff *) = NULL;
- 	struct sk_buff *skb;
- 	struct ip_options_data opt_copy;
- 
-@@ -819,7 +823,13 @@ int udp_sendmsg(struct kiocb *iocb, stru
- 	ipc.opt = NULL;
- 	ipc.tx_flags = 0;
- 
--	getfrag = is_udplite ? udplite_getfrag : ip_generic_getfrag;
-+/* UDPREDIRECT */
-+#if defined(CONFIG_IFX_UDP_REDIRECT) || defined(CONFIG_IFX_UDP_REDIRECT_MODULE)
-+	if(udpredirect_getfrag_fn && sk->sk_user_data == UDP_REDIRECT_MAGIC)
-+		getfrag = udpredirect_getfrag_fn;
-+	else
-+#endif /* IFX_UDP_REDIRECT */
-+		getfrag = is_udplite ? udplite_getfrag : ip_generic_getfrag;
- 
- 	fl4 = &inet->cork.fl.u.ip4;
- 	if (up->pending) {
-@@ -1619,6 +1629,7 @@ int __udp4_lib_rcv(struct sk_buff *skb,
- 	struct rtable *rt = skb_rtable(skb);
- 	__be32 saddr, daddr;
- 	struct net *net = dev_net(skb->dev);
-+	int ret = 0;
- 
- 	/*
- 	 *  Validate the packet.
-@@ -1651,7 +1662,16 @@ int __udp4_lib_rcv(struct sk_buff *skb,
- 	sk = __udp4_lib_lookup_skb(skb, uh->source, uh->dest, udptable);
- 
- 	if (sk != NULL) {
--		int ret = udp_queue_rcv_skb(sk, skb);
-+	/* UDPREDIRECT */
-+#if defined(CONFIG_IFX_UDP_REDIRECT) || defined(CONFIG_IFX_UDP_REDIRECT_MODULE)
-+      if(udp_do_redirect_fn && sk->sk_user_data == UDP_REDIRECT_MAGIC)
-+      {
-+         udp_do_redirect_fn(sk,skb);
-+         kfree_skb(skb);
-+         return(0);
-+      }
-+#endif
-+		ret = udp_queue_rcv_skb(sk, skb);
- 		sock_put(sk);
- 
- 		/* a return value > 0 means to resubmit the input, but
-@@ -1948,7 +1968,7 @@ struct proto udp_prot = {
- 	.clear_sk	   = sk_prot_clear_portaddr_nulls,
- };
- EXPORT_SYMBOL(udp_prot);
--
-+EXPORT_SYMBOL(udp_rcv);
- /* ------------------------------------------------------------------------ */
- #ifdef CONFIG_PROC_FS
- 
---- a/net/Kconfig
-+++ b/net/Kconfig
-@@ -72,6 +72,12 @@ config INET
- 
- 	  Short answer: say Y.
- 
-+config IFX_UDP_REDIRECT
-+	bool "IFX Kernel Packet Interface for UDP redirection"
-+	help
-+	  You can say Y here if you want to use hooks from kernel for
-+	  UDP redirection.
-+
- if INET
- source "net/ipv4/Kconfig"
- source "net/ipv6/Kconfig"
+-- 
+1.7.5.4
+
diff --git a/target/linux/lantiq/patches-3.0/0023-MIPS-lantiq-adds-basic-vr9-support.patch b/target/linux/lantiq/patches-3.0/0023-MIPS-lantiq-adds-basic-vr9-support.patch
new file mode 100644
index 0000000000..67566f03f6
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/0023-MIPS-lantiq-adds-basic-vr9-support.patch
@@ -0,0 +1,280 @@
+From 780a64cd52209fad15c7133f950b2b2d6b9b59e2 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sat, 27 Aug 2011 21:44:32 +0200
+Subject: [PATCH 23/24] MIPS: lantiq: adds basic vr9 support
+
+---
+ .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h |    2 +
+ arch/mips/lantiq/Kconfig                           |    9 ++
+ arch/mips/lantiq/Platform                          |    1 +
+ arch/mips/lantiq/machtypes.h                       |    3 +
+ arch/mips/lantiq/xway/Kconfig                      |   12 +++
+ arch/mips/lantiq/xway/Makefile                     |    2 +
+ arch/mips/lantiq/xway/clk-vr9.c                    |   78 ++++++++++++++++++++
+ arch/mips/lantiq/xway/mach-fritz.c                 |   74 +++++++++++++++++++
+ arch/mips/lantiq/xway/prom-vr9.c                   |   55 ++++++++++++++
+ arch/mips/pci/Makefile                             |    2 +-
+ 10 files changed, 237 insertions(+), 1 deletions(-)
+ create mode 100644 arch/mips/lantiq/xway/clk-vr9.c
+ create mode 100644 arch/mips/lantiq/xway/mach-fritz.c
+ create mode 100644 arch/mips/lantiq/xway/prom-vr9.c
+
+Index: linux-3.0.3/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
+===================================================================
+--- linux-3.0.3.orig/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h	2011-10-04 20:05:48.000000000 +0200
++++ linux-3.0.3/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h	2011-10-04 20:05:54.234312800 +0200
+@@ -21,6 +21,7 @@
+ #define SOC_ID_ARX188		0x16C
+ #define SOC_ID_ARX168		0x16D
+ #define SOC_ID_ARX182		0x16F
++#define SOC_ID_VRX288		0x1C0
+ 
+ /* SoC Types */
+ #define SOC_TYPE_DANUBE		0x01
+@@ -91,6 +92,7 @@
+ 
+ /* ETOP - ethernet */
+ #define LTQ_ETOP_BASE_ADDR	0x1E180000
++#define LTQ_ETOP_BASE_ADDR_VR9	0x1E200000
+ #define LTQ_ETOP_SIZE		0x40000
+ 
+ /* GBIT - gigabit switch */
+Index: linux-3.0.3/arch/mips/lantiq/Kconfig
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/Kconfig	2011-10-04 20:03:54.000000000 +0200
++++ linux-3.0.3/arch/mips/lantiq/Kconfig	2011-10-04 20:05:54.238312800 +0200
+@@ -1,5 +1,8 @@
+ if LANTIQ
+ 
++config LANTIQ_PCIE
++	bool
++
+ config SOC_TYPE_XWAY
+ 	bool
+ 	default n
+@@ -17,6 +20,12 @@
+ 	select SOC_TYPE_XWAY
+ 	select HW_HAS_PCI
+ 
++config SOC_VR9
++	bool "VR9"
++	select SOC_TYPE_XWAY
++	select HW_HAS_PCI
++	select LANTIQ_PCIE
++
+ config SOC_FALCON
+ 	bool "FALCON"
+ endchoice
+Index: linux-3.0.3/arch/mips/lantiq/Platform
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/Platform	2011-10-04 20:03:54.000000000 +0200
++++ linux-3.0.3/arch/mips/lantiq/Platform	2011-10-04 20:05:54.238312800 +0200
+@@ -6,4 +6,5 @@
+ cflags-$(CONFIG_LANTIQ)		+= -I$(srctree)/arch/mips/include/asm/mach-lantiq
+ load-$(CONFIG_LANTIQ)		= 0xffffffff80002000
+ cflags-$(CONFIG_SOC_TYPE_XWAY)	+= -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
++cflags-$(CONFIG_SOC_TYPE_VR9)	+= -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
+ cflags-$(CONFIG_SOC_FALCON)	+= -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon
+Index: linux-3.0.3/arch/mips/lantiq/machtypes.h
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/machtypes.h	2011-10-04 20:03:54.000000000 +0200
++++ linux-3.0.3/arch/mips/lantiq/machtypes.h	2011-10-04 20:05:54.238312800 +0200
+@@ -20,6 +20,9 @@
+ 	LANTIQ_MACH_EASY98000,		/* Falcon Eval Board, NOR Flash */
+ 	LANTIQ_MACH_EASY98000SF,	/* Falcon Eval Board, Serial Flash */
+ 	LANTIQ_MACH_EASY98000NAND,	/* Falcon Eval Board, NAND Flash */
++
++	/* FRITZ!BOX */
++	LANTIQ_MACH_FRITZ3370,		/* FRITZ!BOX 3370 vdsl cpe */
+ };
+ 
+ #endif
+Index: linux-3.0.3/arch/mips/lantiq/xway/Kconfig
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/xway/Kconfig	2011-08-17 19:57:16.000000000 +0200
++++ linux-3.0.3/arch/mips/lantiq/xway/Kconfig	2011-10-04 20:05:54.238312800 +0200
+@@ -21,3 +21,15 @@
+ endmenu
+ 
+ endif
++
++if SOC_VR9
++
++menu "MIPS Machine"
++
++config LANTIQ_MACH_FRITZ3370
++	bool "Fritz!Box 3370"
++	default y
++
++endmenu
++
++endif
+Index: linux-3.0.3/arch/mips/lantiq/xway/Makefile
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/xway/Makefile	2011-10-04 20:05:50.000000000 +0200
++++ linux-3.0.3/arch/mips/lantiq/xway/Makefile	2011-10-04 20:05:54.238312800 +0200
+@@ -2,6 +2,8 @@
+ 
+ obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o
+ obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o
++obj-$(CONFIG_SOC_VR9) += clk-vr9.o prom-vr9.o
+ 
+ obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
+ obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
++obj-$(CONFIG_LANTIQ_MACH_FRITZ3370) += mach-fritz.o
+Index: linux-3.0.3/arch/mips/lantiq/xway/clk-vr9.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-3.0.3/arch/mips/lantiq/xway/clk-vr9.c	2011-10-04 20:05:54.238312800 +0200
+@@ -0,0 +1,78 @@
++/*
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ *
++ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/io.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/clk.h>
++
++#include <asm/time.h>
++#include <asm/irq.h>
++#include <asm/div64.h>
++
++#include <lantiq_soc.h>
++
++#define CLOCK_62_5M                         62500000
++#define CLOCK_83_5M                         83500000
++#define CLOCK_125M                          125000000
++#define CLOCK_200M                          200000000
++#define CLOCK_250M                          250000000
++#define CLOCK_300M                          300000000
++#define CLOCK_98_304M                       98304000
++#define CLOCK_150M                          150000000
++#define CLOCK_196_608M                      196608000
++#define CLOCK_600M                          600000000
++#define CLOCK_500M                          500000000
++#define CLOCK_393M                          393215332
++#define CLOCK_166M                          166666666
++
++#define LTQ_CGU_SYS	0x0c
++#define LTQ_CGU_IF_CLK	0x24
++
++unsigned int ltq_get_cpu_hz(void)
++{
++	int clks[] = {
++		CLOCK_600M, CLOCK_500M,	CLOCK_393M, CLOCK_333M, CLOCK_125M,
++		CLOCK_125M, CLOCK_196_608M, CLOCK_166M, CLOCK_125M, CLOCK_125M };
++	int val = (ltq_cgu_r32(LTQ_CGU_SYS) >> 4) & 0xf;
++
++	if (val > 9)
++		panic("bad cpu speed\n");
++	if (val == 2)
++		panic("missing workaround\n");
++		//cgu_get_pll1_fosc(); //CLOCK_393M;
++	return clks[val];
++}
++EXPORT_SYMBOL(ltq_get_cpu_hz);
++
++unsigned int ltq_get_fpi_hz(void)
++{
++	int clks[] = {
++		CLOCK_62_5M, CLOCK_62_5M, CLOCK_83_5M, CLOCK_125M, CLOCK_125M,
++		CLOCK_125M, CLOCK_167M, CLOCK_200M, CLOCK_250M, CLOCK_300M,
++		CLOCK_62_5M, CLOCK_98_304M, CLOCK_150M, CLOCK_196_608M };
++	int val = ((ltq_cgu_r32(LTQ_CGU_IF_CLK) >> 25) & 0xf);
++
++	if (val > 13)
++		panic("bad fpi speed\n");
++
++	return clks[val];
++}
++EXPORT_SYMBOL(ltq_get_fpi_hz);
++
++unsigned int ltq_get_io_region_clock(void)
++{
++	return ltq_get_fpi_hz() / 2;
++}
++EXPORT_SYMBOL(ltq_get_io_region_clock);
++
++unsigned int ltq_get_fpi_bus_clock(int fpi)
++{
++	return ltq_get_fpi_hz();
++}
++EXPORT_SYMBOL(ltq_get_fpi_bus_clock);
+Index: linux-3.0.3/arch/mips/lantiq/xway/prom-vr9.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ linux-3.0.3/arch/mips/lantiq/xway/prom-vr9.c	2011-10-04 20:05:54.238312800 +0200
+@@ -0,0 +1,55 @@
++/*
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ *
++ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <asm/bootinfo.h>
++#include <asm/time.h>
++
++#include <lantiq_soc.h>
++
++#include "devices.h"
++#include "../prom.h"
++
++#define SOC_VRX288	"VRX288"
++
++#define PART_SHIFT	12
++#define PART_MASK	0x0FFFFFFF
++#define REV_SHIFT	28
++#define REV_MASK	0xF0000000
++
++void __init ltq_soc_detect(struct ltq_soc_info *i)
++{
++	i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
++	i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
++	sprintf(i->rev_type, "1.%d", i->rev);
++	switch (i->partnum) {
++	case SOC_ID_VRX288:
++		i->name = SOC_VRX288;
++		i->type = SOC_TYPE_VR9;
++		break;
++
++	default:
++		unreachable();
++		break;
++	}
++	printk("%08X\n", i->partnum);
++}
++
++void __init ltq_soc_setup(void)
++{
++	/*
++		reg = IFX_REG_R32(IFX_XBAR_ALWAYS_LAST);
++		reg &= ~ IFX_XBAR_FPI_BURST_EN;
++		IFX_REG_W32(reg, IFX_XBAR_ALWAYS_LAST);
++	*/
++
++	ltq_register_asc(1);
++	ltq_register_gpio();
++	ltq_register_wdt();
++}
+Index: linux-3.0.3/arch/mips/pci/Makefile
+===================================================================
+--- linux-3.0.3.orig/arch/mips/pci/Makefile	2011-08-17 19:57:16.000000000 +0200
++++ linux-3.0.3/arch/mips/pci/Makefile	2011-10-04 20:05:54.238312800 +0200
+@@ -41,7 +41,7 @@
+ obj-$(CONFIG_SIBYTE_BCM112X)	+= fixup-sb1250.o pci-sb1250.o
+ obj-$(CONFIG_SIBYTE_BCM1x80)	+= pci-bcm1480.o pci-bcm1480ht.o
+ obj-$(CONFIG_SNI_RM)		+= fixup-sni.o ops-sni.o
+-obj-$(CONFIG_SOC_XWAY)		+= pci-lantiq.o ops-lantiq.o
++obj-$(CONFIG_LANTIQ)		+= pci-lantiq.o ops-lantiq.o
+ obj-$(CONFIG_TANBAC_TB0219)	+= fixup-tb0219.o
+ obj-$(CONFIG_TANBAC_TB0226)	+= fixup-tb0226.o
+ obj-$(CONFIG_TANBAC_TB0287)	+= fixup-tb0287.o
diff --git a/target/linux/lantiq/patches-3.0/020-xway-fix-mtd.patch b/target/linux/lantiq/patches-3.0/020-xway-fix-mtd.patch
deleted file mode 100644
index d74fcb69d5..0000000000
--- a/target/linux/lantiq/patches-3.0/020-xway-fix-mtd.patch
+++ /dev/null
@@ -1,32 +0,0 @@
---- a/arch/mips/lantiq/xway/mach-easy50601.c
-+++ b/arch/mips/lantiq/xway/mach-easy50601.c
-@@ -32,12 +32,7 @@ static struct mtd_partition easy50601_pa
- 	{
- 		.name	= "linux",
- 		.offset	= 0x20000,
--		.size	= 0xE0000,
--	},
--	{
--		.name	= "rootfs",
--		.offset	= 0x100000,
--		.size	= 0x300000,
-+		.size	= 0x3d0000,
- 	},
- };
- 
---- a/arch/mips/lantiq/xway/mach-easy50712.c
-+++ b/arch/mips/lantiq/xway/mach-easy50712.c
-@@ -34,12 +34,7 @@ static struct mtd_partition easy50712_pa
- 	{
- 		.name	= "linux",
- 		.offset	= 0x20000,
--		.size	= 0xe0000,
--	},
--	{
--		.name	= "rootfs",
--		.offset	= 0x100000,
--		.size	= 0x300000,
-+		.size	= 0x3d0000,
- 	},
- };
- 
diff --git a/target/linux/lantiq/patches-3.0/030-lmo-queue.patch b/target/linux/lantiq/patches-3.0/030-lmo-queue.patch
deleted file mode 100644
index 2cb1d08231..0000000000
--- a/target/linux/lantiq/patches-3.0/030-lmo-queue.patch
+++ /dev/null
@@ -1,71 +0,0 @@
---- a/drivers/mtd/maps/lantiq-flash.c
-+++ b/drivers/mtd/maps/lantiq-flash.c
-@@ -20,6 +20,8 @@
- #include <linux/platform_device.h>
- #include <linux/mtd/physmap.h>
- 
-+#include "../mtdcore.h"
-+
- #include <lantiq_soc.h>
- #include <lantiq_platform.h>
- 
---- a/arch/mips/lantiq/clk.c
-+++ b/arch/mips/lantiq/clk.c
-@@ -100,6 +100,17 @@ void clk_put(struct clk *clk)
- }
- EXPORT_SYMBOL(clk_put);
- 
-+int clk_enable(struct clk *clk)
-+{
-+	/* clocks are always enabled*/
-+	return 0;
-+}
-+
-+void clk_disable(struct clk *clk)
-+{
-+	/* clocks are always enabled*/
-+}
-+
- static inline u32 ltq_get_counter_resolution(void)
- {
- 	u32 res;
---- a/arch/mips/lantiq/irq.c
-+++ b/arch/mips/lantiq/irq.c
-@@ -9,6 +9,7 @@
- 
- #include <linux/interrupt.h>
- #include <linux/ioport.h>
-+#include <linux/module.h>
- 
- #include <asm/bootinfo.h>
- #include <asm/irq_cpu.h>
-@@ -99,6 +100,7 @@ void ltq_mask_and_ack_irq(struct irq_dat
- 	ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier);
- 	ltq_icu_w32((1 << irq_nr), isr);
- }
-+EXPORT_SYMBOL(ltq_mask_and_ack_irq);
- 
- static void ltq_ack_irq(struct irq_data *d)
- {
---- a/arch/mips/lantiq/setup.c
-+++ b/arch/mips/lantiq/setup.c
-@@ -18,6 +18,8 @@
- #include "devices.h"
- #include "prom.h"
- 
-+unsigned long physical_memsize = 0L;
-+
- void __init plat_mem_setup(void)
- {
- 	/* assume 16M as default incase uboot fails to pass proper ramsize */
-@@ -40,8 +42,8 @@ void __init plat_mem_setup(void)
- 		}
- 		envp++;
- 	}
--	memsize *= 1024 * 1024;
--	add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
-+	physical_memsize = memsize * 1024 * 1024;
-+	add_memory_region(0x00000000, physical_memsize, BOOT_MEM_RAM);
- }
- 
- static int __init
diff --git a/target/linux/lantiq/patches-3.0/100-falcon_header.patch b/target/linux/lantiq/patches-3.0/100-falcon_bsp_header.patch
index f4da9ef7ea..4e8ce08365 100644
--- a/target/linux/lantiq/patches-3.0/100-falcon_header.patch
+++ b/target/linux/lantiq/patches-3.0/100-falcon_bsp_header.patch
@@ -1,284 +1,4 @@
 --- /dev/null
-+++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
-@@ -0,0 +1,277 @@
-+/*
-+ *   This program is free software; you can redistribute it and/or modify
-+ *   it under the terms of the GNU General Public License as published by
-+ *   the Free Software Foundation; either version 2 of the License, or
-+ *   (at your option) any later version.
-+ *
-+ *   This program is distributed in the hope that it will be useful,
-+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *   GNU General Public License for more details.
-+ *
-+ *   You should have received a copy of the GNU General Public License
-+ *   along with this program; if not, write to the Free Software
-+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
-+ *
-+ *   Copyright (C) 2010 Lantiq
-+ */
-+#ifndef _FALCON_IRQ__
-+#define _FALCON_IRQ__
-+
-+#define INT_NUM_IRQ0			8
-+#define INT_NUM_IM0_IRL0		(INT_NUM_IRQ0 + 0)
-+#define INT_NUM_IM1_IRL0		(INT_NUM_IM0_IRL0 + 32)
-+#define INT_NUM_IM2_IRL0		(INT_NUM_IM1_IRL0 + 32)
-+#define INT_NUM_IM3_IRL0		(INT_NUM_IM2_IRL0 + 32)
-+#define INT_NUM_IM4_IRL0		(INT_NUM_IM3_IRL0 + 32)
-+#define INT_NUM_EXTRA_START		(INT_NUM_IM4_IRL0 + 32)
-+#define INT_NUM_IM_OFFSET		(INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
-+
-+#define MIPS_CPU_TIMER_IRQ			7
-+
-+/* HOST IF Event Interrupt */
-+#define FALCON_IRQ_HOST				(INT_NUM_IM0_IRL0 + 0)
-+/* HOST IF Mailbox0 Receive Interrupt */
-+#define FALCON_IRQ_HOST_MB0_RX			(INT_NUM_IM0_IRL0 + 1)
-+/* HOST IF Mailbox0 Transmit Interrupt */
-+#define FALCON_IRQ_HOST_MB0_TX			(INT_NUM_IM0_IRL0 + 2)
-+/* HOST IF Mailbox1 Receive Interrupt */
-+#define FALCON_IRQ_HOST_MB1_RX			(INT_NUM_IM0_IRL0 + 3)
-+/* HOST IF Mailbox1 Transmit Interrupt */
-+#define FALCON_IRQ_HOST_MB1_TX			(INT_NUM_IM0_IRL0 + 4)
-+/* I2C Last Single Data Transfer Request */
-+#define FALCON_IRQ_I2C_LSREQ			(INT_NUM_IM0_IRL0 + 8)
-+/* I2C Single Data Transfer Request */
-+#define FALCON_IRQ_I2C_SREQ			(INT_NUM_IM0_IRL0 + 9)
-+/* I2C Last Burst Data Transfer Request */
-+#define FALCON_IRQ_I2C_LBREQ			(INT_NUM_IM0_IRL0 + 10)
-+/* I2C Burst Data Transfer Request */
-+#define FALCON_IRQ_I2C_BREQ			(INT_NUM_IM0_IRL0 + 11)
-+/* I2C Error Interrupt */
-+#define FALCON_IRQ_I2C_I2C_ERR			(INT_NUM_IM0_IRL0 + 12)
-+/* I2C Protocol Interrupt */
-+#define FALCON_IRQ_I2C_I2C_P			(INT_NUM_IM0_IRL0 + 13)
-+/* SSC Transmit Interrupt */
-+#define FALCON_IRQ_SSC_T			(INT_NUM_IM0_IRL0 + 14)
-+/* SSC Receive Interrupt */
-+#define FALCON_IRQ_SSC_R			(INT_NUM_IM0_IRL0 + 15)
-+/* SSC Error Interrupt */
-+#define FALCON_IRQ_SSC_E			(INT_NUM_IM0_IRL0 + 16)
-+/* SSC Frame Interrupt */
-+#define FALCON_IRQ_SSC_F			(INT_NUM_IM0_IRL0 + 17)
-+/* Advanced Encryption Standard Interrupt */
-+#define FALCON_IRQ_AES_AES			(INT_NUM_IM0_IRL0 + 27)
-+/* Secure Hash Algorithm Interrupt */
-+#define FALCON_IRQ_SHA_HASH			(INT_NUM_IM0_IRL0 + 28)
-+/* PCM Receive Interrupt */
-+#define FALCON_IRQ_PCM_RX			(INT_NUM_IM0_IRL0 + 29)
-+/* PCM Transmit Interrupt */
-+#define FALCON_IRQ_PCM_TX			(INT_NUM_IM0_IRL0 + 30)
-+/* PCM Transmit Crash Interrupt */
-+#define FALCON_IRQ_PCM_HW2_CRASH		(INT_NUM_IM0_IRL0 + 31)
-+
-+/* EBU Serial Flash Command Error */
-+#define FALCON_IRQ_EBU_SF_CMDERR		(INT_NUM_IM1_IRL0 + 0)
-+/* EBU Serial Flash Command Overwrite Error */
-+#define FALCON_IRQ_EBU_SF_COVERR		(INT_NUM_IM1_IRL0 + 1)
-+/* EBU Serial Flash Busy */
-+#define FALCON_IRQ_EBU_SF_BUSY			(INT_NUM_IM1_IRL0 + 2)
-+/* External Interrupt from GPIO P0 */
-+#define FALCON_IRQ_GPIO_P0			(INT_NUM_IM1_IRL0 + 4)
-+/* External Interrupt from GPIO P1 */
-+#define FALCON_IRQ_GPIO_P1			(INT_NUM_IM1_IRL0 + 5)
-+/* External Interrupt from GPIO P2 */
-+#define FALCON_IRQ_GPIO_P2			(INT_NUM_IM1_IRL0 + 6)
-+/* External Interrupt from GPIO P3 */
-+#define FALCON_IRQ_GPIO_P3			(INT_NUM_IM1_IRL0 + 7)
-+/* External Interrupt from GPIO P4 */
-+#define FALCON_IRQ_GPIO_P4			(INT_NUM_IM1_IRL0 + 8)
-+/* 8kHz backup interrupt derived from core-PLL */
-+#define FALCON_IRQ_FSC_BKP			(INT_NUM_IM1_IRL0 + 10)
-+/* FSC Timer Interrupt 0 */
-+#define FALCON_IRQ_FSCT_CMP0			(INT_NUM_IM1_IRL0 + 11)
-+/* FSC Timer Interrupt 1 */
-+#define FALCON_IRQ_FSCT_CMP1			(INT_NUM_IM1_IRL0 + 12)
-+/* 8kHz root interrupt derived from GPON interface */
-+#define FALCON_IRQ_FSC_ROOT			(INT_NUM_IM1_IRL0 + 13)
-+/* Time of Day */
-+#define FALCON_IRQ_TOD				(INT_NUM_IM1_IRL0 + 14)
-+/* PMA Interrupt from IntNode of the 200MHz Domain */
-+#define FALCON_IRQ_PMA_200M			(INT_NUM_IM1_IRL0 + 15)
-+/* PMA Interrupt from IntNode of the TX Clk Domain */
-+#define FALCON_IRQ_PMA_TX			(INT_NUM_IM1_IRL0 + 16)
-+/* PMA Interrupt from IntNode of the RX Clk Domain */
-+#define FALCON_IRQ_PMA_RX			(INT_NUM_IM1_IRL0 + 17)
-+/* SYS1 Interrupt */
-+#define FALCON_IRQ_SYS1				(INT_NUM_IM1_IRL0 + 20)
-+/* SYS GPE Interrupt */
-+#define FALCON_IRQ_SYS_GPE			(INT_NUM_IM1_IRL0 + 21)
-+/* Watchdog Access Error Interrupt */
-+#define FALCON_IRQ_WDT_AEIR			(INT_NUM_IM1_IRL0 + 24)
-+/* Watchdog Prewarning Interrupt */
-+#define FALCON_IRQ_WDT_PIR			(INT_NUM_IM1_IRL0 + 25)
-+/* SBIU interrupt */
-+#define FALCON_IRQ_SBIU0			(INT_NUM_IM1_IRL0 + 27)
-+/* FPI Bus Control Unit Interrupt */
-+#define FALCON_IRQ_BCU0				(INT_NUM_IM1_IRL0 + 29)
-+/* DDR Controller Interrupt */
-+#define FALCON_IRQ_DDR				(INT_NUM_IM1_IRL0 + 30)
-+/* Crossbar Error Interrupt */
-+#define FALCON_IRQ_XBAR_ERROR			(INT_NUM_IM1_IRL0 + 31)
-+
-+/* ICTRLL 0 Interrupt */
-+#define FALCON_IRQ_ICTRLL0			(INT_NUM_IM2_IRL0 + 0)
-+/* ICTRLL 1 Interrupt */
-+#define FALCON_IRQ_ICTRLL1			(INT_NUM_IM2_IRL0 + 1)
-+/* ICTRLL 2 Interrupt */
-+#define FALCON_IRQ_ICTRLL2			(INT_NUM_IM2_IRL0 + 2)
-+/* ICTRLL 3 Interrupt */
-+#define FALCON_IRQ_ICTRLL3			(INT_NUM_IM2_IRL0 + 3)
-+/* OCTRLL 0 Interrupt */
-+#define FALCON_IRQ_OCTRLL0			(INT_NUM_IM2_IRL0 + 4)
-+/* OCTRLL 1 Interrupt */
-+#define FALCON_IRQ_OCTRLL1			(INT_NUM_IM2_IRL0 + 5)
-+/* OCTRLL 2 Interrupt */
-+#define FALCON_IRQ_OCTRLL2			(INT_NUM_IM2_IRL0 + 6)
-+/* OCTRLL 3 Interrupt */
-+#define FALCON_IRQ_OCTRLL3			(INT_NUM_IM2_IRL0 + 7)
-+/* OCTRLG Interrupt */
-+#define FALCON_IRQ_OCTRLG			(INT_NUM_IM2_IRL0 + 9)
-+/* IQM Interrupt */
-+#define FALCON_IRQ_IQM				(INT_NUM_IM2_IRL0 + 10)
-+/* FSQM Interrupt */
-+#define FALCON_IRQ_FSQM				(INT_NUM_IM2_IRL0 + 11)
-+/* TMU Interrupt */
-+#define FALCON_IRQ_TMU				(INT_NUM_IM2_IRL0 + 12)
-+/* LINK1 Interrupt */
-+#define FALCON_IRQ_LINK1			(INT_NUM_IM2_IRL0 + 14)
-+/* ICTRLC 0 Interrupt */
-+#define FALCON_IRQ_ICTRLC0			(INT_NUM_IM2_IRL0 + 16)
-+/* ICTRLC 1 Interrupt */
-+#define FALCON_IRQ_ICTRLC1			(INT_NUM_IM2_IRL0 + 17)
-+/* OCTRLC Interrupt */
-+#define FALCON_IRQ_OCTRLC			(INT_NUM_IM2_IRL0 + 18)
-+/* CONFIG Break Interrupt */
-+#define FALCON_IRQ_CONFIG_BREAK			(INT_NUM_IM2_IRL0 + 19)
-+/* CONFIG Interrupt */
-+#define FALCON_IRQ_CONFIG			(INT_NUM_IM2_IRL0 + 20)
-+/* Dispatcher Interrupt */
-+#define FALCON_IRQ_DISP				(INT_NUM_IM2_IRL0 + 21)
-+/* TBM Interrupt */
-+#define FALCON_IRQ_TBM				(INT_NUM_IM2_IRL0 + 22)
-+/* GTC Downstream Interrupt */
-+#define FALCON_IRQ_GTC_DS			(INT_NUM_IM2_IRL0 + 29)
-+/* GTC Upstream Interrupt */
-+#define FALCON_IRQ_GTC_US			(INT_NUM_IM2_IRL0 + 30)
-+/* EIM Interrupt */
-+#define FALCON_IRQ_EIM				(INT_NUM_IM2_IRL0 + 31)
-+
-+/* ASC0 Transmit Interrupt */
-+#define FALCON_IRQ_ASC0_T			(INT_NUM_IM3_IRL0 + 0)
-+/* ASC0 Receive Interrupt */
-+#define FALCON_IRQ_ASC0_R			(INT_NUM_IM3_IRL0 + 1)
-+/* ASC0 Error Interrupt */
-+#define FALCON_IRQ_ASC0_E			(INT_NUM_IM3_IRL0 + 2)
-+/* ASC0 Transmit Buffer Interrupt */
-+#define FALCON_IRQ_ASC0_TB			(INT_NUM_IM3_IRL0 + 3)
-+/* ASC0 Autobaud Start Interrupt */
-+#define FALCON_IRQ_ASC0_ABST			(INT_NUM_IM3_IRL0 + 4)
-+/* ASC0 Autobaud Detection Interrupt */
-+#define FALCON_IRQ_ASC0_ABDET			(INT_NUM_IM3_IRL0 + 5)
-+/* ASC1 Modem Status Interrupt */
-+#define FALCON_IRQ_ASC0_MS			(INT_NUM_IM3_IRL0 + 6)
-+/* ASC0 Soft Flow Control Interrupt */
-+#define FALCON_IRQ_ASC0_SFC			(INT_NUM_IM3_IRL0 + 7)
-+/* ASC1 Transmit Interrupt */
-+#define FALCON_IRQ_ASC1_T			(INT_NUM_IM3_IRL0 + 8)
-+/* ASC1 Receive Interrupt */
-+#define FALCON_IRQ_ASC1_R			(INT_NUM_IM3_IRL0 + 9)
-+/* ASC1 Error Interrupt */
-+#define FALCON_IRQ_ASC1_E			(INT_NUM_IM3_IRL0 + 10)
-+/* ASC1 Transmit Buffer Interrupt */
-+#define FALCON_IRQ_ASC1_TB			(INT_NUM_IM3_IRL0 + 11)
-+/* ASC1 Autobaud Start Interrupt */
-+#define FALCON_IRQ_ASC1_ABST			(INT_NUM_IM3_IRL0 + 12)
-+/* ASC1 Autobaud Detection Interrupt */
-+#define FALCON_IRQ_ASC1_ABDET			(INT_NUM_IM3_IRL0 + 13)
-+/* ASC1 Modem Status Interrupt */
-+#define FALCON_IRQ_ASC1_MS			(INT_NUM_IM3_IRL0 + 14)
-+/* ASC1 Soft Flow Control Interrupt */
-+#define FALCON_IRQ_ASC1_SFC			(INT_NUM_IM3_IRL0 + 15)
-+/* GPTC Timer/Counter 1A Interrupt */
-+#define FALCON_IRQ_GPTC_TC1A			(INT_NUM_IM3_IRL0 + 16)
-+/* GPTC Timer/Counter 1B Interrupt */
-+#define FALCON_IRQ_GPTC_TC1B			(INT_NUM_IM3_IRL0 + 17)
-+/* GPTC Timer/Counter 2A Interrupt */
-+#define FALCON_IRQ_GPTC_TC2A			(INT_NUM_IM3_IRL0 + 18)
-+/* GPTC Timer/Counter 2B Interrupt */
-+#define FALCON_IRQ_GPTC_TC2B			(INT_NUM_IM3_IRL0 + 19)
-+/* GPTC Timer/Counter 3A Interrupt */
-+#define FALCON_IRQ_GPTC_TC3A			(INT_NUM_IM3_IRL0 + 20)
-+/* GPTC Timer/Counter 3B Interrupt */
-+#define FALCON_IRQ_GPTC_TC3B			(INT_NUM_IM3_IRL0 + 21)
-+/* DFEV0, Channel 1 Transmit Interrupt */
-+#define FALCON_IRQ_DFEV0_2TX			(INT_NUM_IM3_IRL0 + 26)
-+/* DFEV0, Channel 1 Receive Interrupt */
-+#define FALCON_IRQ_DFEV0_2RX			(INT_NUM_IM3_IRL0 + 27)
-+/* DFEV0, Channel 1 General Purpose Interrupt */
-+#define FALCON_IRQ_DFEV0_2GP			(INT_NUM_IM3_IRL0 + 28)
-+/* DFEV0, Channel 0 Transmit Interrupt */
-+#define FALCON_IRQ_DFEV0_1TX			(INT_NUM_IM3_IRL0 + 29)
-+/* DFEV0, Channel 0 Receive Interrupt */
-+#define FALCON_IRQ_DFEV0_1RX			(INT_NUM_IM3_IRL0 + 30)
-+/* DFEV0, Channel 0 General Purpose Interrupt */
-+#define FALCON_IRQ_DFEV0_1GP			(INT_NUM_IM3_IRL0 + 31)
-+
-+/* ICTRLL 0 Error */
-+#define FALCON_IRQ_ICTRLL0_ERR			(INT_NUM_IM4_IRL0 + 0)
-+/* ICTRLL 1 Error */
-+#define FALCON_IRQ_ICTRLL1_ERR			(INT_NUM_IM4_IRL0 + 1)
-+/* ICTRLL 2 Error */
-+#define FALCON_IRQ_ICTRLL2_ERR			(INT_NUM_IM4_IRL0 + 2)
-+/* ICTRLL 3 Error */
-+#define FALCON_IRQ_ICTRLL3_ERR			(INT_NUM_IM4_IRL0 + 3)
-+/* OCTRLL 0 Error */
-+#define FALCON_IRQ_OCTRLL0_ERR			(INT_NUM_IM4_IRL0 + 4)
-+/* OCTRLL 1 Error */
-+#define FALCON_IRQ_OCTRLL1_ERR			(INT_NUM_IM4_IRL0 + 5)
-+/* OCTRLL 2 Error */
-+#define FALCON_IRQ_OCTRLL2_ERR			(INT_NUM_IM4_IRL0 + 6)
-+/* OCTRLL 3 Error */
-+#define FALCON_IRQ_OCTRLL3_ERR			(INT_NUM_IM4_IRL0 + 7)
-+/* ICTRLG Error */
-+#define FALCON_IRQ_ICTRLG_ERR			(INT_NUM_IM4_IRL0 + 8)
-+/* OCTRLG Error */
-+#define FALCON_IRQ_OCTRLG_ERR			(INT_NUM_IM4_IRL0 + 9)
-+/* IQM Error */
-+#define FALCON_IRQ_IQM_ERR			(INT_NUM_IM4_IRL0 + 10)
-+/* FSQM Error */
-+#define FALCON_IRQ_FSQM_ERR			(INT_NUM_IM4_IRL0 + 11)
-+/* TMU Error */
-+#define FALCON_IRQ_TMU_ERR			(INT_NUM_IM4_IRL0 + 12)
-+/* MPS Status Interrupt #0 (VPE1 to VPE0) */
-+#define FALCON_IRQ_MPS_IR0			(INT_NUM_IM4_IRL0 + 14)
-+/* MPS Status Interrupt #1 (VPE1 to VPE0) */
-+#define FALCON_IRQ_MPS_IR1			(INT_NUM_IM4_IRL0 + 15)
-+/* MPS Status Interrupt #2 (VPE1 to VPE0) */
-+#define FALCON_IRQ_MPS_IR2			(INT_NUM_IM4_IRL0 + 16)
-+/* MPS Status Interrupt #3 (VPE1 to VPE0) */
-+#define FALCON_IRQ_MPS_IR3			(INT_NUM_IM4_IRL0 + 17)
-+/* MPS Status Interrupt #4 (VPE1 to VPE0) */
-+#define FALCON_IRQ_MPS_IR4			(INT_NUM_IM4_IRL0 + 18)
-+/* MPS Status Interrupt #5 (VPE1 to VPE0) */
-+#define FALCON_IRQ_MPS_IR5			(INT_NUM_IM4_IRL0 + 19)
-+/* MPS Status Interrupt #6 (VPE1 to VPE0) */
-+#define FALCON_IRQ_MPS_IR6			(INT_NUM_IM4_IRL0 + 20)
-+/* MPS Status Interrupt #7 (VPE1 to VPE0) */
-+#define FALCON_IRQ_MPS_IR7			(INT_NUM_IM4_IRL0 + 21)
-+/* MPS Status Interrupt #8 (VPE1 to VPE0) */
-+#define FALCON_IRQ_MPS_IR8			(INT_NUM_IM4_IRL0 + 22)
-+/* VPE0 Exception Level Flag Interrupt */
-+#define FALCON_IRQ_VPE0_EXL			(INT_NUM_IM4_IRL0 + 29)
-+/* VPE0 Error Level Flag Interrupt */
-+#define FALCON_IRQ_VPE0_ERL			(INT_NUM_IM4_IRL0 + 30)
-+/* VPE0 Performance Monitoring Counter Interrupt */
-+#define FALCON_IRQ_VPE0_PMCIR			(INT_NUM_IM4_IRL0 + 31)
-+
-+#endif /* _FALCON_IRQ__ */
---- /dev/null
 +++ b/arch/mips/include/asm/mach-lantiq/falcon/gpon_reg_base.h
 @@ -0,0 +1,376 @@
 +/******************************************************************************
@@ -5818,40 +5538,6 @@
 +
 +#endif /* _icu0_reg_h */
 --- /dev/null
-+++ b/arch/mips/include/asm/mach-lantiq/falcon/irq.h
-@@ -0,0 +1,31 @@
-+/*
-+ *   arch/mips/include/asm/mach-ifxmips/falcon/irq.h
-+ *
-+ *   This program is free software; you can redistribute it and/or modify
-+ *   it under the terms of the GNU General Public License as published by
-+ *   the Free Software Foundation; either version 2 of the License, or
-+ *   (at your option) any later version.
-+ *
-+ *   This program is distributed in the hope that it will be useful,
-+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *   GNU General Public License for more details.
-+ *
-+ *   You should have received a copy of the GNU General Public License
-+ *   along with this program; if not, write to the Free Software
-+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
-+ *
-+ *   Copyright (C) 2010 Lantiq
-+ *
-+ */
-+
-+#ifndef __FALCON_IRQ_H
-+#define __FALCON_IRQ_H
-+
-+#include <falcon_irq.h>
-+
-+#define NR_IRQS 264
-+
-+#include_next <irq.h>
-+
-+#endif
---- /dev/null
 +++ b/arch/mips/include/asm/mach-lantiq/falcon/status_reg.h
 @@ -0,0 +1,529 @@
 +/******************************************************************************
diff --git a/target/linux/lantiq/patches-3.0/110-falcon_board.patch b/target/linux/lantiq/patches-3.0/110-falcon_board.patch
deleted file mode 100644
index ec52d42d41..0000000000
--- a/target/linux/lantiq/patches-3.0/110-falcon_board.patch
+++ /dev/null
@@ -1,2115 +0,0 @@
---- /dev/null
-+++ b/arch/mips/lantiq/falcon/Kconfig
-@@ -0,0 +1,11 @@
-+if SOC_FALCON
-+
-+menu "Mips Machine"
-+
-+config LANTIQ_MACH_EASY98000
-+	bool "Easy98000"
-+	default y
-+
-+endmenu
-+
-+endif
---- /dev/null
-+++ b/arch/mips/lantiq/falcon/Makefile
-@@ -0,0 +1,4 @@
-+obj-y := clk-falcon.o devices.o gpio.o prom.o sysctrl.o reset.o
-+obj-y += softdog_vpe.o
-+obj-$(CONFIG_LANTIQ_MACH_EASY98000) += addon-easy98000.o
-+obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o
---- /dev/null
-+++ b/arch/mips/lantiq/falcon/clk-falcon.c
-@@ -0,0 +1,48 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/init.h>
-+
-+#include <asm/time.h>
-+#include <asm/irq.h>
-+#include <asm/div64.h>
-+
-+#include <lantiq_soc.h>
-+
-+#include <falcon.h>
-+#include <gpon_reg_base.h>
-+#include <sys1_reg.h>
-+
-+static struct gpon_reg_sys1 * const pSYS1 = (struct gpon_reg_sys1 *)GPON_SYS1_BASE;
-+
-+unsigned int
-+ltq_get_io_region_clock(void)
-+{
-+	return 200000000; /* 200 MHz */
-+}
-+EXPORT_SYMBOL(ltq_get_io_region_clock);
-+
-+unsigned int
-+ltq_get_cpu_hz(void)
-+{
-+	if ((ltq_r32(&pSYS1->cpu0cc) & CPU0CC_CPUDIV) == CPU0CC_CPUDIV_SELFHALF)
-+		return 200000000; /* 200 MHz */
-+	else
-+		return 400000000; /* 400 MHz */
-+}
-+EXPORT_SYMBOL(ltq_get_cpu_hz);
-+
-+unsigned int
-+ltq_get_fpi_hz(void)
-+{
-+	return 100000000;
-+}
-+EXPORT_SYMBOL(ltq_get_fpi_hz);
---- /dev/null
-+++ b/arch/mips/lantiq/falcon/devices.c
-@@ -0,0 +1,258 @@
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/types.h>
-+#include <linux/string.h>
-+#include <linux/mtd/physmap.h>
-+#include <linux/kernel.h>
-+#include <linux/reboot.h>
-+#include <linux/platform_device.h>
-+#include <linux/leds.h>
-+#include <linux/etherdevice.h>
-+#include <linux/reboot.h>
-+#include <linux/time.h>
-+#include <linux/io.h>
-+#include <linux/gpio.h>
-+#include <linux/leds.h>
-+#include <linux/spi/spi.h>
-+#include <linux/mtd/nand.h>
-+
-+#include <asm/bootinfo.h>
-+#include <asm/irq.h>
-+
-+#include <lantiq.h>
-+
-+#include <falcon/falcon_irq.h>
-+#include <falcon/gpon_reg_base.h>
-+#include <falcon/ebu_reg.h>
-+#include <falcon/sys1_reg.h>
-+#include <falcon/sys_eth_reg.h>
-+
-+#include <falcon/sysctrl.h>
-+
-+#include "devices.h"
-+
-+unsigned char ltq_ethaddr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-+EXPORT_SYMBOL(ltq_ethaddr);
-+
-+/* create dummy ebu spinlock for drivers shared with XWAY targets */
-+DEFINE_SPINLOCK(ebu_lock);
-+EXPORT_SYMBOL_GPL(ebu_lock);
-+
-+static int __init
-+falcon_set_ethaddr(char *str)
-+{
-+	sscanf(str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
-+		&ltq_ethaddr[0], &ltq_ethaddr[1], &ltq_ethaddr[2],
-+		&ltq_ethaddr[3], &ltq_ethaddr[4], &ltq_ethaddr[5]);
-+	return 0;
-+}
-+__setup("ethaddr=", falcon_set_ethaddr);
-+
-+/* asc ports */
-+static struct resource falcon_asc0_resources[] =
-+{
-+	MEM_RES("asc0",GPON_ASC0_BASE,GPON_ASC0_END),
-+	IRQ_RES("tx",INT_NUM_IM3_IRL0),
-+	IRQ_RES("rx",INT_NUM_IM3_IRL0+1),
-+	IRQ_RES("err",INT_NUM_IM3_IRL0+2),
-+};
-+
-+static struct resource falcon_asc1_resources[] =
-+{
-+	MEM_RES("asc1",GPON_ASC1_BASE,GPON_ASC1_END),
-+	IRQ_RES("tx",INT_NUM_IM3_IRL0+8),
-+	IRQ_RES("rx",INT_NUM_IM3_IRL0+9),
-+	IRQ_RES("err",INT_NUM_IM3_IRL0+10),
-+};
-+
-+void __init falcon_register_asc(int port)
-+{
-+	switch (port) {
-+	case 0:
-+		platform_device_register_simple("ltq_asc", 0,
-+			falcon_asc0_resources, ARRAY_SIZE(falcon_asc0_resources));
-+		break;
-+	case 1:
-+		platform_device_register_simple("ltq_asc", 1,
-+			falcon_asc1_resources, ARRAY_SIZE(falcon_asc1_resources));
-+		break;
-+	default:
-+		break;
-+	}
-+}
-+
-+/* nor flash */
-+static struct resource ltq_nor_resource =
-+	MEM_RES("nor",LTQ_FLASH_START,LTQ_FLASH_START + LTQ_FLASH_MAX - 1);
-+
-+static struct platform_device ltq_nor = {
-+	.name			= "ltq_nor",
-+	.resource		= &ltq_nor_resource,
-+	.num_resources	= 1,
-+};
-+
-+void __init falcon_register_nor(struct physmap_flash_data *data)
-+{
-+	ltq_nor.dev.platform_data = data;
-+	platform_device_register(&ltq_nor);
-+}
-+
-+/* spi flash */
-+static struct resource ltq_spi_resources[] = {
-+	MEM_RES("ebu", GPON_EBU_BASE, GPON_EBU_END),
-+	MEM_RES("sys1", GPON_SYS1_BASE, GPON_SYS1_END)
-+};
-+
-+static struct platform_device ltq_spi = {
-+	.name			= "falcon_spi",
-+	.resource		= ltq_spi_resources,
-+	.num_resources		= ARRAY_SIZE(ltq_spi_resources)
-+};
-+
-+void __init falcon_register_spi_flash(struct spi_board_info *data)
-+{
-+	spi_register_board_info(data, 1);
-+	platform_device_register(&ltq_spi);
-+}
-+
-+/* nand flash */
-+static struct gpon_reg_ebu __iomem *membase_ebu;
-+static const char *part_probes[] = { "cmdlinepart", NULL };
-+
-+static int falcon_nand_ready(struct mtd_info *mtd)
-+{
-+	u32 modcon = __raw_readl(&membase_ebu->modcon);
-+
-+	return (((modcon & (MODCON_STS|MODCON_STSEDGE)) ==
-+						(MODCON_STS|MODCON_STSEDGE)));
-+}
-+
-+/* address lines used for NAND control signals */
-+#define NAND_ADDR_ALE		(1<<16)
-+#define NAND_ADDR_CLE		(1<<17)
-+
-+static void falcon_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-+{
-+	struct nand_chip *this = mtd->priv;
-+	unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
-+
-+	if (ctrl & NAND_CTRL_CHANGE) {
-+		nandaddr &= ~(NAND_ADDR_ALE | NAND_ADDR_CLE);
-+
-+		if (ctrl & NAND_CLE)
-+			nandaddr |= NAND_ADDR_CLE;
-+		if (ctrl & NAND_ALE)
-+			nandaddr |= NAND_ADDR_ALE;
-+
-+		this->IO_ADDR_W = (void __iomem *) nandaddr;
-+	}
-+
-+	if (cmd != NAND_CMD_NONE)
-+		writeb(cmd, this->IO_ADDR_W);
-+}
-+
-+static struct platform_nand_data falcon_flash_nand_data = {
-+	.chip = {
-+		.nr_chips		= 1,
-+		.chip_delay		= 25,
-+		.part_probe_types 	= part_probes,
-+	},
-+	.ctrl = {
-+		.cmd_ctrl 		= falcon_hwcontrol,
-+		.dev_ready		= falcon_nand_ready,
-+	}
-+};
-+
-+static struct resource ltq_nand_resources[] = {
-+	MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_START + LTQ_FLASH_MAX - 1),
-+	MEM_RES("ebu", GPON_EBU_BASE, GPON_EBU_END),
-+};
-+
-+static struct platform_device ltq_flash_nand = {
-+	.name		= "gen_nand",
-+	.id		= -1,
-+	.num_resources	= ARRAY_SIZE(ltq_nand_resources),
-+	.resource	= ltq_nand_resources,
-+	.dev		= {
-+		.platform_data = &falcon_flash_nand_data,
-+	},
-+};
-+
-+void __init falcon_register_nand(void)
-+{
-+	membase_ebu = ioremap_nocache(ltq_nand_resources[1].start,
-+			resource_size(&ltq_nand_resources[1]));
-+
-+	if (membase_ebu)
-+		platform_device_register(&ltq_flash_nand);
-+}
-+
-+/* watchdog */
-+static struct resource falcon_wdt_resource =
-+	MEM_RES("watchdog",GPON_WDT_BASE,GPON_WDT_END);
-+
-+void __init falcon_register_wdt(void)
-+{
-+	platform_device_register_simple("ltq_wdt", 0, &falcon_wdt_resource, 1);
-+}
-+
-+/* gpio */
-+#define DECLARE_GPIO_RES(port) \
-+static struct resource falcon_gpio ## port ## _resources[] = { \
-+	MEM_RES("gpio"#port,GPON_GPIO ## port ## _BASE,GPON_GPIO ## port ## _END), \
-+	MEM_RES("padctrl"#port,GPON_PADCTRL ## port ## _BASE,GPON_PADCTRL ## port ## _END), \
-+	IRQ_RES("gpio_mux"#port,FALCON_IRQ_GPIO_P ## port ) \
-+}
-+DECLARE_GPIO_RES(0);
-+DECLARE_GPIO_RES(1);
-+DECLARE_GPIO_RES(2);
-+#ifdef REGISTER_ALL_GPIO_PORTS
-+#if NR_IRQS < 328
-+#error NR_IRQS to low for all gpio irqs
-+#endif
-+DECLARE_GPIO_RES(3);
-+DECLARE_GPIO_RES(4);
-+#endif
-+
-+void __init falcon_register_gpio(void)
-+{
-+	platform_device_register_simple("falcon_gpio", 0,
-+		falcon_gpio0_resources, ARRAY_SIZE(falcon_gpio0_resources));
-+	platform_device_register_simple("falcon_gpio", 1,
-+		falcon_gpio1_resources, ARRAY_SIZE(falcon_gpio1_resources));
-+	platform_device_register_simple("falcon_gpio", 2,
-+		falcon_gpio2_resources, ARRAY_SIZE(falcon_gpio2_resources));
-+	sys1_hw_activate(ACTS_PADCTRL1 | ACTS_P1);
-+	sys_eth_hw_activate(SYS_ETH_ACTS_PADCTRL0 | SYS_ETH_ACTS_PADCTRL2 |
-+		SYS_ETH_ACTS_P0 | SYS_ETH_ACTS_P2);
-+
-+#ifdef REGISTER_ALL_GPIO_PORTS
-+	/* optional gpio ports: not registered,
-+	   as the pins are EBU specific and always used by linux */
-+	platform_device_register_simple("falcon_gpio", 3,
-+		falcon_gpio3_resources, ARRAY_SIZE(falcon_gpio3_resources));
-+	platform_device_register_simple("falcon_gpio", 4,
-+		falcon_gpio4_resources, ARRAY_SIZE(falcon_gpio4_resources));
-+	sys1_hw_activate(ACTS_PADCTRL3 | ACTS_PADCTRL4 | ACTS_P3 | ACTS_P4);
-+#endif
-+}
-+
-+static struct resource falcon_i2c_resources[] = {
-+	MEM_RES("i2c", GPON_I2C_BASE,GPON_I2C_END),
-+	IRQ_RES("i2c_lb", FALCON_IRQ_I2C_LBREQ),
-+	IRQ_RES("i2c_b", FALCON_IRQ_I2C_BREQ),
-+	IRQ_RES("i2c_err", FALCON_IRQ_I2C_I2C_ERR),
-+	IRQ_RES("i2c_p", FALCON_IRQ_I2C_I2C_P),
-+};
-+
-+void __init falcon_register_i2c(void)
-+{
-+	platform_device_register_simple("i2c-falcon", 0,
-+		falcon_i2c_resources, ARRAY_SIZE(falcon_i2c_resources));
-+	sys1_hw_activate(ACTS_I2C_ACT);
-+}
-+
-+void __init falcon_register_crypto(void)
-+{
-+	platform_device_register_simple("ltq_falcon_deu", 0, NULL, 0);
-+}
---- /dev/null
-+++ b/arch/mips/lantiq/falcon/devices.h
-@@ -0,0 +1,22 @@
-+#ifndef _FALCON_DEVICES_H__
-+#define _FALCON_DEVICES_H__
-+
-+#include <linux/mtd/physmap.h>
-+#include <linux/spi/spi.h>
-+#include <linux/spi/flash.h>
-+
-+extern void __init falcon_register_asc(int port);
-+extern void __init falcon_register_i2c(void);
-+extern void __init falcon_register_spi_flash(struct spi_board_info *data);
-+extern void __init falcon_register_gpio(void);
-+extern void __init falcon_register_nor(struct physmap_flash_data *data);
-+extern void __init falcon_register_nand(void);
-+extern void __init falcon_register_wdt(void);
-+extern void __init falcon_register_crypto(void);
-+
-+#define IRQ_RES(resname,irq) {.name=resname,.start=(irq),.flags=IORESOURCE_IRQ}
-+#define MEM_RES(resname,adr_start,adr_end) \
-+	{ .name=resname, .flags=IORESOURCE_MEM, \
-+	  .start=((adr_start)&~KSEG1),.end=((adr_end)&~KSEG1) }
-+
-+#endif
---- /dev/null
-+++ b/arch/mips/lantiq/falcon/prom.c
-@@ -0,0 +1,52 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/clk.h>
-+#include <asm/bootinfo.h>
-+#include <asm/time.h>
-+
-+#include <lantiq_soc.h>
-+
-+#include <falcon.h>
-+
-+#include <falcon/gpon_reg_base.h>
-+#include <falcon/status_reg.h>
-+#include <falcon/sys1_reg.h>
-+
-+#include "../prom.h"
-+
-+static struct gpon_reg_status * const pSTATUS = (struct gpon_reg_status *)GPON_STATUS_BASE;
-+
-+#define SOC_FALCON		"Falcon"
-+
-+void __init
-+ltq_soc_setup(void)
-+{
-+	/* not used */
-+}
-+
-+void __init
-+ltq_soc_detect(struct ltq_soc_info *i)
-+{
-+	i->partnum = (ltq_r32(&pSTATUS->chipid) & STATUS_CHIPID_PARTNR_MASK) >> STATUS_CHIPID_PARTNR_OFFSET;
-+	i->rev = (ltq_r32(&pSTATUS->chipid) & STATUS_CHIPID_VERSION_MASK) >> STATUS_CHIPID_VERSION_OFFSET;
-+	switch (i->partnum)
-+	{
-+	case SOC_ID_FALCON:
-+		i->name = SOC_FALCON;
-+		i->type = SOC_TYPE_FALCON;
-+		break;
-+
-+	default:
-+		printk(KERN_ERR "unknown partnum : 0x%08X\n", i->partnum);
-+		while(1) {	};
-+		break;
-+	}
-+}
---- /dev/null
-+++ b/arch/mips/lantiq/falcon/sysctrl.c
-@@ -0,0 +1,381 @@
-+/*
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ *
-+ * Copyright (C) 2010 Thomas Langer, Lantiq Deutschland
-+ */
-+
-+#include <linux/cpu.h>
-+#include <linux/init.h>
-+#include <linux/kernel.h>
-+#include <linux/pm.h>
-+#include <linux/io.h>
-+#include <linux/ioport.h>
-+#include <linux/clk.h>
-+#include <asm/reboot.h>
-+
-+#include <falcon/gpon_reg_base.h>
-+#include <falcon/status_reg.h>
-+#include <falcon/sys1_reg.h>
-+#include <falcon/sys_eth_reg.h>
-+#include <falcon/sys_gpe_reg.h>
-+
-+#include <falcon/sysctrl.h>
-+
-+/* mapping to linux hw-accessor routines */
-+#define reg_r32(reg)			__raw_readl(reg)
-+#define reg_w32(val, reg)		__raw_writel(val, reg)
-+#define reg_w32_mask(clear, set, reg)	reg_w32((reg_r32(reg) & ~(clear)) | (set), reg)
-+
-+static struct gpon_reg_sys1 * const sys1 = (struct gpon_reg_sys1 *)GPON_SYS1_BASE;
-+static struct gpon_reg_sys_eth * const sys_eth = (struct gpon_reg_sys_eth *)GPON_SYS_ETH_BASE;
-+static struct gpon_reg_sys_gpe * const sys_gpe = (struct gpon_reg_sys_gpe *)GPON_SYS_GPE_BASE;
-+static struct gpon_reg_status * const status = (struct gpon_reg_status *)GPON_STATUS_BASE;
-+
-+/**
-+ * Activate the selected module(s)
-+ * Enables the clock of the module and activates the module itself.
-+ *
-+ * \param[in]   mask    bitmask of module(s), as for registers SYS1.ACT
-+ * \return void
-+ */
-+void sys1_hw_activate(u32 mask)
-+{
-+	sys1_w32(mask, clken);
-+	sys1_w32(mask, act);
-+
-+	while ( (sys1_r32(acts) & mask) != mask) {
-+		/*NOP;*/
-+	};
-+}
-+EXPORT_SYMBOL(sys1_hw_activate);
-+
-+/**
-+ * Deactivate the selected module(s)
-+ * Disables the clock of the module and deactivates the module itself.
-+ *
-+ * \param[in]   mask    bitmask of module(s), as for registers SYS1.DEACT
-+ * \return void
-+ */
-+void sys1_hw_deactivate(u32 mask)
-+{
-+	sys1_w32(mask, clkclr);
-+	sys1_w32(mask, deact);
-+
-+	while ( (sys1_r32(acts) & mask) != 0) {
-+		/*NOP;*/
-+	};
-+}
-+EXPORT_SYMBOL(sys1_hw_deactivate);
-+
-+/**
-+ * Clock enable for the selected module(s)
-+ * Enables the clock of the module.
-+ *
-+ * \param[in]   mask    bitmask of module(s), as for registers SYS1.CLKEN
-+ * \return void
-+ */
-+void sys1_hw_clk_enable(u32 mask)
-+{
-+	sys1_w32(mask, clken);
-+
-+	while ( (sys1_r32(clks) & mask) != mask) {
-+		/*NOP;*/
-+	};
-+}
-+EXPORT_SYMBOL(sys1_hw_clk_enable);
-+
-+/**
-+ * Clock disable for the selected module(s)
-+ * disables the clock of the module.
-+ *
-+ * \param[in]   mask    bitmask of module(s), as for registers SYS1.CLKCLR
-+ * \return void
-+ */
-+void sys1_hw_clk_disable(u32 mask)
-+{
-+	sys1_w32(mask, clkclr);
-+
-+	while ( (sys1_r32(clks) & mask) != 0) {
-+		/*NOP;*/
-+	};
-+}
-+EXPORT_SYMBOL(sys1_hw_clk_disable);
-+
-+/**
-+ * Reboots the selected module(s)
-+ * Triggers the reboot of the module.
-+ *
-+ * \param[in]   mask    bitmask of module(s), as for registers SYS1.RBT
-+ * \return void
-+ */
-+void sys1_hw_activate_or_reboot(u32 mask)
-+{
-+	u32 acts = sys1_r32(acts);
-+	/* is not already active? */
-+	if ((~acts & mask) != 0)
-+		sys1_hw_activate(~acts & mask);
-+	sys1_w32(acts & mask, rbt);
-+	while ( (sys1_r32(acts) & mask) != mask) {
-+		/*NOP;*/
-+	};
-+}
-+EXPORT_SYMBOL(sys1_hw_activate_or_reboot);
-+
-+/**
-+ * Activate the selected module(s)
-+ * Enables the clock of the module and activates the module itself.
-+ *
-+ * \param[in]   mask    bitmask of module(s), as for registers SYS_ETH.ACT
-+ * \return void
-+ */
-+void sys_eth_hw_activate(u32 mask)
-+{
-+	sys_eth_w32(mask, clken);
-+	sys_eth_w32(mask, act);
-+
-+	while ( (sys_eth_r32(acts) & mask) != mask) {
-+		/*NOP;*/
-+	};
-+}
-+EXPORT_SYMBOL(sys_eth_hw_activate);
-+
-+/**
-+ * Deactivate the selected module(s)
-+ * Disables the clock of the module and deactivates the module itself.
-+ *
-+ * \param[in]   mask    bitmask of module(s), as for registers SYS_ETH.DEACT
-+ * \return void
-+ */
-+void sys_eth_hw_deactivate(u32 mask)
-+{
-+	sys_eth_w32(mask, clkclr);
-+	sys_eth_w32(mask, deact);
-+
-+	while ( (sys_eth_r32(acts) & mask) != 0) {
-+		/*NOP;*/
-+	};
-+}
-+EXPORT_SYMBOL(sys_eth_hw_deactivate);
-+
-+/**
-+ * Clock enable for the selected module(s)
-+ * Enables the clock of the module.
-+ *
-+ * \param[in]   mask    bitmask of module(s), as for registers SYS_ETH.CLKEN
-+ * \return void
-+ */
-+void sys_eth_hw_clk_enable(u32 mask)
-+{
-+	sys_eth_w32(mask, clken);
-+
-+	while ( (sys_eth_r32(clks) & mask) != mask) {
-+		/*NOP;*/
-+	};
-+}
-+EXPORT_SYMBOL(sys_eth_hw_clk_enable);
-+
-+/**
-+ * Clock disable for the selected module(s)
-+ * disables the clock of the module.
-+ *
-+ * \param[in]   mask    bitmask of module(s), as for registers SYS_ETH.CLKCLR
-+ * \return void
-+ */
-+void sys_eth_hw_clk_disable(u32 mask)
-+{
-+	sys_eth_w32(mask, clkclr);
-+
-+	while ( (sys_eth_r32(clks) & mask) != 0) {
-+		/*NOP;*/
-+	};
-+}
-+EXPORT_SYMBOL(sys_eth_hw_clk_disable);
-+
-+/**
-+ * Reboots the selected module(s)
-+ * Triggers the reboot of the module.
-+ *
-+ * \param[in]   mask    bitmask of module(s), as for registers SYS_ETH.RBT
-+ * \return void
-+ */
-+void sys_eth_hw_activate_or_reboot(u32 mask)
-+{
-+	u32 acts = sys_eth_r32(acts);
-+	/* is not already active? */
-+	if ((~acts & mask) != 0)
-+		sys_eth_hw_activate(~acts & mask);
-+	sys_eth_w32(acts & mask, rbt);
-+	while ( (sys_eth_r32(acts) & mask) != mask) {
-+		/*NOP;*/
-+	};
-+}
-+EXPORT_SYMBOL(sys_eth_hw_activate_or_reboot);
-+
-+static int gpe_clk_is_enabled(void)
-+{
-+	u32 rd_data;
-+
-+	rd_data = sys1_r32(infrac);
-+	if (rd_data & (1<<(INFRAC_GP_OFFSET+1)))
-+		return 1;
-+	return 0;
-+}
-+
-+static void enable_gpe_clk(void)
-+{
-+	u32 aeFreq;
-+	u32 rd_data;
-+	u32 rd_data_to_keep;
-+	int i;
-+
-+	if (gpe_clk_is_enabled())
-+		/* clock already active, no need to change here */
-+		return;
-+
-+	if (status_r32(config) == 0)
-+		aeFreq = 1; /* use 625MHz on unfused chip */
-+	else
-+		aeFreq = (status_r32(config) & STATUS_CONFIG_GPEFREQ_MASK) >> STATUS_CONFIG_GPEFREQ_OFFSET;
-+	rd_data = sys1_r32(infrac);
-+	/* clear gpe-fsel and enable bits */
-+	rd_data_to_keep = rd_data & ~(7<<(INFRAC_GP_OFFSET+1));
-+
-+	/* set new fsel */
-+	sys1_w32(rd_data_to_keep | (aeFreq<<(INFRAC_GP_OFFSET+2)), infrac);
-+
-+	for (i = 0; i <10; i++) /* wait 10 cycles */
-+		{}
-+
-+	/* keep new fsel and enable */
-+	sys1_w32(rd_data_to_keep | (aeFreq<<(INFRAC_GP_OFFSET+2)) |
-+		(1<<(INFRAC_GP_OFFSET+1)), infrac);
-+	for (i = 0; i <100; i++) /* wait 100 cycles */
-+		{}
-+}
-+
-+/**
-+ * Activate the selected module(s)
-+ * Enables the clock of the module and activates the module itself.
-+ *
-+ * \param[in]   mask    bitmask of module(s), as for registers SYS_GPE.ACT
-+ * \return void
-+ */
-+void sys_gpe_hw_activate(u32 mask)
-+{
-+	enable_gpe_clk();
-+	sys_gpe_w32(mask, clken);
-+	sys_gpe_w32(mask, act);
-+
-+	while ( (sys_gpe_r32(acts) & mask) != mask) {
-+		/*NOP;*/
-+	};
-+}
-+EXPORT_SYMBOL(sys_gpe_hw_activate);
-+
-+/**
-+ * Deactivate the selected module(s)
-+ * Disables the clock of the module and deactivates the module itself.
-+ *
-+ * \param[in]   mask    bitmask of module(s), as for registers SYS_GPE.DEACT
-+ * \return void
-+ */
-+void sys_gpe_hw_deactivate(u32 mask)
-+{
-+	enable_gpe_clk();
-+	sys_gpe_w32(mask, clkclr);
-+	sys_gpe_w32(mask, deact);
-+
-+	while ( (sys_gpe_r32(acts) & mask) != 0) {
-+		/*NOP;*/
-+	};
-+}
-+EXPORT_SYMBOL(sys_gpe_hw_deactivate);
-+
-+/**
-+ * Clock enable for the selected module(s)
-+ * Enables the clock of the module.
-+ *
-+ * \param[in]   mask    bitmask of module(s), as for registers SYS_GPE.CLKEN
-+ * \return void
-+ */
-+void sys_gpe_hw_clk_enable(u32 mask)
-+{
-+	enable_gpe_clk();
-+	sys_gpe_w32(mask, clken);
-+
-+	while ( (sys_gpe_r32(clks) & mask) != mask) {
-+		/*NOP;*/
-+	};
-+}
-+EXPORT_SYMBOL(sys_gpe_hw_clk_enable);
-+
-+/**
-+ * Clock disable for the selected module(s)
-+ * disables the clock of the module.
-+ *
-+ * \param[in]   mask    bitmask of module(s), as for registers SYS_GPE.CLKCLR
-+ * \return void
-+ */
-+void sys_gpe_hw_clk_disable(u32 mask)
-+{
-+	enable_gpe_clk();
-+	sys_gpe_w32(mask, clkclr);
-+
-+	while ( (sys_gpe_r32(clks) & mask) != 0) {
-+		/*NOP;*/
-+	};
-+}
-+EXPORT_SYMBOL(sys_gpe_hw_clk_disable);
-+
-+/**
-+ * Reboots the selected module(s)
-+ * Triggers the reboot of the module.
-+ *
-+ * \param[in]   mask    bitmask of module(s), as for registers SYS_GPE.RBT
-+ * \return void
-+ */
-+void sys_gpe_hw_activate_or_reboot(u32 mask)
-+{
-+	u32 acts;
-+	enable_gpe_clk();
-+	acts = sys_gpe_r32(acts);
-+	/* is not already active? */
-+	if ((~acts & mask) != 0)
-+		sys_gpe_hw_activate(~acts & mask);
-+	sys_gpe_w32(acts & mask, rbt);
-+	while ( (sys_gpe_r32(acts) & mask) != mask) {
-+		/*NOP;*/
-+	};
-+}
-+EXPORT_SYMBOL(sys_gpe_hw_activate_or_reboot);
-+
-+/**
-+ * Retrieve activation status of the selected hardware module(s)
-+ *
-+ * \param[in]   mask    bitmask of module(s), as for registers SYS_GPE.RBT
-+ * \return int 1 - if hardware module(s) is activated (including clock)
-+ */
-+ int sys_gpe_hw_is_activated(u32 mask)
-+{
-+	if (gpe_clk_is_enabled() == 0)
-+		return 0;
-+
-+	if ((sys_gpe_r32(clks) & mask) != mask)
-+		return 0;
-+
-+	return ((sys_gpe_r32(acts) & mask) == mask);
-+}
-+EXPORT_SYMBOL(sys_gpe_hw_is_activated);
---- /dev/null
-+++ b/arch/mips/lantiq/falcon/gpio.c
-@@ -0,0 +1,505 @@
-+/*
-+ *   This program is free software; you can redistribute it and/or modify
-+ *   it under the terms of the GNU General Public License as published by
-+ *   the Free Software Foundation; either version 2 of the License, or
-+ *   (at your option) any later version.
-+ *
-+ *   This program is distributed in the hope that it will be useful,
-+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *   GNU General Public License for more details.
-+ *
-+ *   You should have received a copy of the GNU General Public License
-+ *   along with this program; if not, write to the Free Software
-+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
-+ *
-+ *   Copyright (C) 2010 Thomas Langer, Lantiq Deutschland
-+ */
-+
-+/**
-+	TODO:
-+		- add locking?
-+		- provide mask of available pins per platform_data
-+*/
-+
-+#include <linux/module.h>
-+#include <linux/types.h>
-+#include <linux/errno.h>
-+#include <linux/init.h>
-+#include <linux/seq_file.h>
-+#include <linux/platform_device.h>
-+#include <linux/uaccess.h>
-+#include <linux/gpio.h>
-+#include <linux/irq.h>
-+#include <linux/interrupt.h>
-+#include <linux/slab.h>
-+
-+#include <falcon.h>
-+#include <falcon/falcon_irq.h>
-+
-+#include <linux/version.h>
-+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35))
-+#define for_each_set_bit for_each_bit
-+#endif
-+
-+#define gpio_r32(reg)			__raw_readl(reg)
-+#define gpio_w32(val, reg)			__raw_writel(val, reg)
-+#define gpio_w32_mask(clear, set, reg)	gpio_w32((gpio_r32(reg) & ~(clear)) | (set), reg)
-+
-+#define MAX_PORTS			5
-+#define PINS_PER_PORT			32
-+
-+/** register structure for padctrl
-+    (mainly needed for mux control) */
-+typedef struct gpon_padctrl_s
-+{
-+	/** Multiplexer Control Register
-+	    The value 0 (the reset-value) is always the default function corresponding to the pad's name. The value 1 selects always the GPIO functionality (if available). */
-+	unsigned int muxc[32];
-+	/** Pull Up Enable Register */
-+	unsigned int puen; /* 0x00000080 */
-+	/** Pull Down Enable Register */
-+	unsigned int pden; /* 0x00000084 */
-+	/** Slew Rate Control Register */
-+	unsigned int src; /* 0x00000088 */
-+	/** Drive Current Control Register */
-+	unsigned int dcc; /* 0x0000008C */
-+	/** Reserved */
-+	unsigned int res_0[24]; /* 0x00000090 */
-+	/** Pad Control Availability Register */
-+	unsigned int avail; /* 0x000000F0 */
-+} gpon_padctrl0_t;
-+
-+/** register structure for gpio port */
-+typedef struct gpon_gpio_s
-+{
-+	/** Data Output Register
-+	    Via this register the output values of the different bits can be set if they are switched as outputs. */
-+	unsigned int out; /* 0x00000000 */
-+	/** Data Input Register
-+	    Via this register the input values of the different bits can be observed. */
-+	unsigned int in; /* 0x00000004 */
-+	/** Direction Register
-+	    Via this register the input direction of the different bits can be determined. */
-+	unsigned int dir; /* 0x00000008 */
-+	/** Reserved */
-+	unsigned int res_0[3]; /* 0x0000000C */
-+	/** External Interrupt Control Register 0 */
-+	unsigned int exintcr0; /* 0x00000018 */
-+	/** External Interrupt Control Register 1 */
-+	unsigned int exintcr1; /* 0x0000001C */
-+	/** IRN Capture Register
-+	    This register shows the currently active interrupt events masked with the corresponding enable bits of the IRNEN register. The interrupts can be acknowledged by a write operation. */
-+	unsigned int irncr; /* 0x00000020 */
-+	/** IRN Interrupt Control Register
-+	    A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
-+	unsigned int irnicr; /* 0x00000024 */
-+	/** IRN Interrupt Enable Register
-+	    This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IRNCR register and are not signalled via the interrupt line towards the controller. */
-+	unsigned int irnen; /* 0x00000028 */
-+	/** IRN Interrupt Configuration Register
-+	    Configures the interrupts bitwise to be edge-senstivie or level-sensitive. */
-+	unsigned int irncfg; /* 0x0000002C */
-+	/** IRN Interrupt Enable Set Register
-+	    The corresponding bit in the IRNEN register can be set with an atomic access. */
-+	unsigned int irnenset; /* 0x00000030 */
-+	/** IRN Interrupt Enable Clear Register
-+	    The corresponding bit in the IRNEN register can be cleared with an atomic access. */
-+	unsigned int irnenclr; /* 0x00000034 */
-+	/** Reserved */
-+	unsigned int res_1[2]; /* 0x00000038 */
-+	/** Output Set Register
-+	    This register can be used to set certain bits within the OUT register without touching the other bits. */
-+	unsigned int outset; /* 0x00000040 */
-+	/** Output Clear Register
-+	    This register can be used to clear certain bits within the OUT register without touching the other bits. */
-+	unsigned int outclr; /* 0x00000044 */
-+	/** Direction Set Register
-+	    This register can be used to set certain bits within the DIR register without touching the other bits. */
-+	unsigned int dirset; /* 0x00000048 */
-+	/** Direction Clear Register
-+	    This register can be used to clear certain bits within the DIR register without touching the other bits. */
-+	unsigned int dirclr; /* 0x0000004C */
-+} gpon_gpio_t;
-+
-+struct falcon_gpio_port {
-+	struct gpio_chip gpio_chip;
-+	gpon_padctrl0_t __iomem *pad;
-+	gpon_gpio_t __iomem *port;
-+	struct resource	*pad_req;   /* resources requested */
-+	struct resource *port_req;
-+	unsigned int irq_base;
-+	unsigned int chained_irq;
-+};
-+
-+static struct falcon_gpio_port ltq_gpio_port[MAX_PORTS];
-+
-+static int gpio_exported = 0;
-+static int __init gpio_export_setup(char *str)
-+{
-+	get_option(&str, &gpio_exported);
-+	return 1;
-+}
-+__setup("gpio_exported=", gpio_export_setup);
-+
-+static inline struct falcon_gpio_port *to_falcon_gpio_port(struct gpio_chip *chip)
-+{
-+	return container_of(chip, struct falcon_gpio_port, gpio_chip);
-+}
-+
-+static int falcon_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
-+{
-+	struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
-+	gpio_w32(1<<offset, &gpio_port->port->dirclr);
-+	return 0;
-+}
-+
-+static void falcon_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
-+{
-+	struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
-+	if (value)
-+		gpio_w32(1<<offset, &gpio_port->port->outset);
-+	else
-+		gpio_w32(1<<offset, &gpio_port->port->outclr);
-+}
-+
-+static int falcon_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value)
-+{
-+	struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
-+	falcon_gpio_set(chip, offset, value);
-+	gpio_w32(1<<offset, &gpio_port->port->dirset);
-+	return 0;
-+}
-+
-+static int falcon_gpio_get(struct gpio_chip *chip, unsigned int offset)
-+{
-+	struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
-+	if ((gpio_r32(&gpio_port->port->dir) >> offset) & 1)
-+		return (gpio_r32(&gpio_port->port->out) >> offset) & 1;
-+	else
-+		return (gpio_r32(&gpio_port->port->in) >> offset) & 1;
-+}
-+
-+static int falcon_gpio_request(struct gpio_chip *chip, unsigned offset)
-+{
-+	struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
-+	if ( (gpio_r32(&gpio_port->pad->avail) >> offset) & 1) {
-+		if (gpio_r32(&gpio_port->pad->muxc[offset]) > 1)
-+			return -EBUSY;
-+		/* switch on gpio function */
-+		gpio_w32(1, &gpio_port->pad->muxc[offset]);
-+		return 0;
-+	}
-+
-+	return -ENODEV;
-+}
-+
-+static void falcon_gpio_free(struct gpio_chip *chip, unsigned offset)
-+{
-+	struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
-+	if ( (gpio_r32(&gpio_port->pad->avail) >> offset) & 1) {
-+		if (gpio_r32(&gpio_port->pad->muxc[offset]) > 1)
-+			return;
-+		/* switch off gpio function */
-+		gpio_w32(0, &gpio_port->pad->muxc[offset]);
-+	}
-+}
-+
-+static int falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-+{
-+	struct falcon_gpio_port *gpio_port = to_falcon_gpio_port(chip);
-+	/* no checks: this functions is only registered with valid irq_base */
-+	return gpio_port->irq_base + offset;
-+}
-+
-+static void falcon_gpio_disable_irq(struct irq_data *d)
-+{
-+	struct falcon_gpio_port *gpio_port = irq_get_chip_data(d->irq);
-+	unsigned int offset = d->irq-gpio_port->irq_base;
-+	gpio_w32(1<<offset, &gpio_port->port->irnenclr);
-+}
-+
-+static void falcon_gpio_enable_irq(struct irq_data *d)
-+{
-+	struct falcon_gpio_port *gpio_port = irq_get_chip_data(d->irq);
-+	unsigned int offset = d->irq-gpio_port->irq_base;
-+
-+	if (gpio_r32(&gpio_port->pad->muxc[offset]) < 1) {
-+		/* switch on gpio function */
-+		gpio_w32(1, &gpio_port->pad->muxc[offset]);
-+	}
-+
-+	gpio_w32(1<<offset, &gpio_port->port->irnenset);
-+}
-+
-+static void falcon_gpio_ack_irq(struct irq_data *d)
-+{
-+	struct falcon_gpio_port *gpio_port = irq_get_chip_data(d->irq);
-+	unsigned int offset = d->irq-gpio_port->irq_base;
-+	gpio_w32(1<<offset, &gpio_port->port->irncr);
-+}
-+
-+static void falcon_gpio_mask_and_ack_irq(struct irq_data *d)
-+{
-+	struct falcon_gpio_port *gpio_port = irq_get_chip_data(d->irq);
-+	unsigned int offset = d->irq-gpio_port->irq_base;
-+	gpio_w32(1<<offset, &gpio_port->port->irnenclr);
-+	gpio_w32(1<<offset, &gpio_port->port->irncr);
-+}
-+
-+int ltq_gpio_mux_set(unsigned int pin, unsigned int mux)
-+{
-+	int port = pin / 100;
-+	int offset = pin % 100;
-+	struct falcon_gpio_port *gpio_port;
-+
-+	if (offset >= PINS_PER_PORT || port >= MAX_PORTS)
-+		return -EINVAL;
-+
-+	gpio_port = &ltq_gpio_port[port];
-+	gpio_w32(mux, &gpio_port->pad->muxc[offset]);
-+
-+	return 0;
-+}
-+EXPORT_SYMBOL(ltq_gpio_mux_set);
-+
-+int ltq_gpio_request(unsigned int pin, unsigned int alt0,
-+		     unsigned int alt1, unsigned int dir, const char *name)
-+{
-+	int port = pin / 100;
-+	int offset = pin % 100;
-+	unsigned int mux = (alt0 & 1) + (alt1 & 1) * 2;
-+
-+	if (offset >= PINS_PER_PORT || port >= MAX_PORTS)
-+		return -EINVAL;
-+
-+	if (gpio_request(pin, name)) {
-+		pr_err("failed to setup lantiq gpio: %s\n", name);
-+		return -EBUSY;
-+	}
-+
-+	if (dir)
-+		gpio_direction_output(pin, 1);
-+	else
-+		gpio_direction_input(pin);
-+
-+	return ltq_gpio_mux_set(pin, mux);
-+}
-+EXPORT_SYMBOL(ltq_gpio_request);
-+
-+static struct irq_chip falcon_gpio_irq_chip;
-+static int falcon_gpio_irq_type(struct irq_data *d, unsigned int type)
-+{
-+	struct falcon_gpio_port *gpio_port = irq_get_chip_data(d->irq);
-+	unsigned int offset = d->irq-gpio_port->irq_base;
-+	unsigned int mask = 1 << offset;
-+
-+	if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
-+		return 0;
-+
-+	if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) {
-+		/* level triggered */
-+		gpio_w32_mask(0, mask, &gpio_port->port->irncfg);
-+		irq_set_chip_and_handler_name(d->irq,
-+				&falcon_gpio_irq_chip, handle_level_irq, "mux");
-+	} else {
-+		/* edge triggered */
-+		gpio_w32_mask(mask, 0, &gpio_port->port->irncfg);
-+		irq_set_chip_and_handler_name(d->irq,
-+				&falcon_gpio_irq_chip, handle_simple_irq, "mux");
-+	}
-+
-+	if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
-+		gpio_w32_mask(mask, 0, &gpio_port->port->exintcr0);
-+		gpio_w32_mask(0, mask, &gpio_port->port->exintcr1);
-+	} else {
-+		if ((type & (IRQ_TYPE_EDGE_RISING |IRQ_TYPE_LEVEL_HIGH)) != 0) {
-+			/* positive logic: rising edge, high level */
-+			gpio_w32_mask(mask, 0, &gpio_port->port->exintcr0);
-+		} else {
-+			/* negative logic: falling edge, low level */
-+			gpio_w32_mask(0, mask, &gpio_port->port->exintcr0);
-+		}
-+		gpio_w32_mask(mask, 0, &gpio_port->port->exintcr1);
-+	}
-+
-+	return gpio_direction_input(gpio_port->gpio_chip.base + offset);
-+}
-+
-+static void falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
-+{
-+	struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc);
-+	unsigned long irncr;
-+	int offset;
-+
-+	irncr = gpio_r32(&gpio_port->port->irncr);
-+	/* acknowledge interrupt */
-+	gpio_w32(irncr, &gpio_port->port->irncr);
-+
-+	desc->irq_data.chip->irq_ack(&desc->irq_data);
-+
-+	for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio)
-+		generic_handle_irq(gpio_port->irq_base + offset);
-+}
-+
-+static struct irq_chip falcon_gpio_irq_chip = {
-+	.name = "gpio_irq_mux",
-+	.irq_mask = falcon_gpio_disable_irq,
-+	.irq_unmask = falcon_gpio_enable_irq,
-+	.irq_ack = falcon_gpio_ack_irq,
-+	.irq_mask_ack = falcon_gpio_mask_and_ack_irq,
-+	.irq_set_type = falcon_gpio_irq_type,
-+};
-+
-+static struct irqaction gpio_cascade = {
-+	.handler = no_action,
-+	.flags = IRQF_DISABLED,
-+	.name = "gpio_cascade",
-+};
-+
-+static int falcon_gpio_probe(struct platform_device *pdev)
-+{
-+	struct falcon_gpio_port *gpio_port;
-+	int ret, i;
-+	struct resource *gpiores, *padres;
-+	int irq;
-+
-+	if (pdev->id >= MAX_PORTS)
-+		return -ENODEV;
-+
-+	gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	padres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+	irq = platform_get_irq(pdev, 0);
-+	if (!gpiores || !padres)
-+		return -ENODEV;
-+
-+	gpio_port = &ltq_gpio_port[pdev->id];
-+	gpio_port->gpio_chip.label = "falcon-gpio";
-+	gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input;
-+	gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output;
-+	gpio_port->gpio_chip.get = falcon_gpio_get;
-+	gpio_port->gpio_chip.set = falcon_gpio_set;
-+	gpio_port->gpio_chip.request = falcon_gpio_request;
-+	gpio_port->gpio_chip.free = falcon_gpio_free;
-+	gpio_port->gpio_chip.base = 100 * pdev->id;
-+	gpio_port->gpio_chip.ngpio = 32;
-+	gpio_port->gpio_chip.dev = &pdev->dev;
-+	gpio_port->gpio_chip.exported = gpio_exported;
-+
-+	gpio_port->port_req = request_mem_region(gpiores->start,
-+		resource_size(gpiores), pdev->name);
-+	gpio_port->pad_req = request_mem_region(padres->start,
-+		resource_size(padres), pdev->name);
-+	if (!gpio_port->port_req || !gpio_port->pad_req) {
-+		dev_err(&pdev->dev, "cannot claim register area\n");
-+		ret = -EIO;
-+		goto err;
-+	}
-+
-+	gpio_port->port = ioremap_nocache(gpiores->start,
-+		resource_size(gpiores));
-+	gpio_port->pad = ioremap_nocache(padres->start,
-+		resource_size(padres));
-+	if (!gpio_port->port || !gpio_port->pad) {
-+		dev_err(&pdev->dev, "Could not map io ranges\n");
-+		ret = -ENOMEM;
-+		goto err;
-+	}
-+
-+	if (irq>0) {
-+		/*
-+		 * irq_chip support
-+		 */
-+		gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq;
-+		gpio_port->irq_base = INT_NUM_EXTRA_START + 32 * pdev->id;
-+
-+		for (i = 0; i < 32; i++) {
-+			irq_set_chip_and_handler_name(gpio_port->irq_base + i,
-+				&falcon_gpio_irq_chip, handle_simple_irq, "mux");
-+			irq_set_chip_data(gpio_port->irq_base + i, gpio_port);
-+			/* FIXME: set default cfg to level triggered */
-+			//gpio_w32_mask(0, 1<<i, &gpio_port->port->irncfg);
-+			/* set to negative logic (falling edge, low level) */
-+			gpio_w32_mask(0, 1<<i, &gpio_port->port->exintcr0);
-+		}
-+
-+		gpio_port->chained_irq = irq;
-+		setup_irq(irq, &gpio_cascade);
-+		irq_set_handler_data(irq, gpio_port);
-+		irq_set_chained_handler(irq, falcon_gpio_irq_handler);
-+	}
-+
-+	ret = gpiochip_add(&gpio_port->gpio_chip);
-+	if (ret < 0) {
-+		dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n",
-+			pdev->id, ret);
-+		goto err;
-+	}
-+	platform_set_drvdata(pdev, gpio_port);
-+	return ret;
-+
-+err:
-+	dev_err(&pdev->dev, "Error in gpio_probe %d, %d\n", pdev->id, ret);
-+	if (gpio_port->port_req)
-+		release_resource(gpio_port->port_req);
-+	if (gpio_port->pad_req)
-+		release_resource(gpio_port->pad_req);
-+
-+	if (gpio_port->port)
-+		iounmap(gpio_port->port);
-+	if (gpio_port->pad)
-+		iounmap(gpio_port->pad);
-+	return ret;
-+}
-+
-+static int falcon_gpio_remove(struct platform_device *pdev)
-+{
-+	struct falcon_gpio_port *gpio_port = platform_get_drvdata(pdev);
-+	int ret;
-+
-+	ret = gpiochip_remove(&gpio_port->gpio_chip);
-+	if (gpio_port->port_req)
-+		release_resource(gpio_port->port_req);
-+	if (gpio_port->pad_req)
-+		release_resource(gpio_port->pad_req);
-+	if (gpio_port->port)
-+		iounmap(gpio_port->port);
-+	if (gpio_port->pad)
-+		iounmap(gpio_port->pad);
-+
-+	return ret;
-+}
-+
-+static struct platform_driver falcon_gpio_driver = {
-+	.probe = falcon_gpio_probe,
-+	.remove = __devexit_p(falcon_gpio_remove),
-+	.driver = {
-+		.name = "falcon_gpio",
-+		.owner = THIS_MODULE,
-+	},
-+};
-+
-+int __init falcon_gpio_init(void)
-+{
-+	int ret;
-+
-+	printk(KERN_INFO "FALC(tm) ON GPIO Driver, (C) 2011 Lantiq Deutschland Gmbh\n");
-+	ret = platform_driver_register(&falcon_gpio_driver);
-+	if (ret)
-+		pr_err( "falcon_gpio: Error registering platform driver!");
-+	return ret;
-+}
-+
-+void __exit falcon_gpio_exit(void)
-+{
-+	platform_driver_unregister(&falcon_gpio_driver);
-+}
-+
-+int gpio_to_irq(unsigned int gpio)
-+{
-+	return __gpio_to_irq(gpio);
-+}
-+EXPORT_SYMBOL(gpio_to_irq);
-+
-+module_init(falcon_gpio_init);
-+module_exit(falcon_gpio_exit);
---- /dev/null
-+++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon.h
-@@ -0,0 +1,16 @@
-+/*
-+ *   This program is free software; you can redistribute it and/or modify
-+ *   it under the terms of the GNU General Public License as published by
-+ *   the Free Software Foundation; either version 2 of the License, or
-+ *   (at your option) any later version.
-+ *
-+ *   Copyright (C) 2005 infineon
-+ *   Copyright (C) 2010 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#ifdef CONFIG_SOC_FALCON
-+
-+#include <lantiq_soc.h>
-+#include <falcon/gpon_reg_base.h>
-+
-+#endif
---- /dev/null
-+++ b/arch/mips/lantiq/falcon/reset.c
-@@ -0,0 +1,95 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/io.h>
-+#include <linux/pm.h>
-+#include <asm/reboot.h>
-+#include <linux/module.h>
-+
-+#include <falcon.h>
-+#include <falcon/gpon_reg_base.h>
-+#include <falcon/status_reg.h>
-+#include <falcon/sys1_reg.h>
-+
-+static struct gpon_reg_sys1 * const pSYS1 = (struct gpon_reg_sys1 *)GPON_SYS1_BASE;
-+
-+#define WDT_PW1			0x00BE0000
-+#define WDT_PW2			0x00DC0000
-+#define WDT_REG_BASE		(KSEG1 | 0x1F8803F0)
-+
-+struct gpon_reg_boot {
-+	/* bootrom related virtual registers */
-+	unsigned int rvec;
-+	unsigned int nvec;
-+	unsigned int evec;
-+	unsigned int cp0_status;
-+	unsigned int cp0_epc;
-+	unsigned int cp0_eepc;
-+	unsigned int size;
-+	unsigned int cfg_stat;
-+	/* additional virtual registers */
-+	unsigned int magic0; /* magic for valid reboot */
-+	unsigned int magic1; /*  -"-  */
-+	unsigned int bcount; /* reboot counter, used by u-boot */
-+} * const pBOOT = (struct gpon_reg_boot *)GPON_SBS0RAM_BASE;
-+
-+/* This function is used by the watchdog driver */
-+int ltq_reset_cause(void)
-+{
-+	return 0;
-+}
-+EXPORT_SYMBOL_GPL(ltq_reset_cause);
-+
-+static void
-+ltq_machine_restart(char *command)
-+{
-+	printk(KERN_NOTICE "System restart\n");
-+	local_irq_disable();
-+	/* write magic to signal a valid restart */
-+	ltq_w32(0x4C545100, &pBOOT->magic0); /* 'LTQ\0' */
-+	ltq_w32(0x0051544C, &pBOOT->magic1); /* '\0QTL' */
-+	ltq_w32(0, &pBOOT->rvec); /* reset Bootreg RVEC */
-+	/* reset via watchdog timer, to ensure reset of all hardware components */
-+	ltq_w32(WDT_PW1, (void*)WDT_REG_BASE);
-+	ltq_w32(WDT_PW2 |
-+		(0x3 << 26) | /* PWL */
-+		(0x2 << 24) | /* CLKDIV */
-+		(0x1 << 31) | /* enable */
-+		(1), /* reload */
-+		(void*)WDT_REG_BASE);
-+	for(;;);
-+}
-+
-+static void
-+ltq_machine_halt(void)
-+{
-+	printk(KERN_NOTICE "System halted.\n");
-+	local_irq_disable();
-+	for(;;);
-+}
-+
-+static void
-+ltq_machine_power_off(void)
-+{
-+	printk(KERN_NOTICE "Please turn off the power now.\n");
-+	local_irq_disable();
-+	for(;;);
-+}
-+
-+static int __init
-+mips_reboot_setup(void)
-+{
-+	_machine_restart = ltq_machine_restart;
-+	_machine_halt = ltq_machine_halt;
-+	pm_power_off = ltq_machine_power_off;
-+	return 0;
-+}
-+
-+arch_initcall(mips_reboot_setup);
---- /dev/null
-+++ b/arch/mips/lantiq/falcon/mach-easy98000.c
-@@ -0,0 +1,255 @@
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/leds.h>
-+#include <linux/gpio.h>
-+#include <linux/gpio_buttons.h>
-+#include <linux/etherdevice.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/mtd/physmap.h>
-+#include <linux/input.h>
-+#include <linux/interrupt.h>
-+#include <linux/dm9000.h>
-+#include <linux/i2c.h>
-+#include <linux/i2c-gpio.h>
-+#include <linux/spi/spi.h>
-+#include <linux/spi/spi_gpio.h>
-+#include <linux/spi/eeprom.h>
-+
-+#include "../machtypes.h"
-+
-+#include "devices.h"
-+#include "dev-leds-gpio.h"
-+
-+#define EASY98000_GPIO_LED_0 9
-+#define EASY98000_GPIO_LED_1 10
-+#define EASY98000_GPIO_LED_2 11
-+#define EASY98000_GPIO_LED_3 12
-+#define EASY98000_GPIO_LED_4 13
-+#define EASY98000_GPIO_LED_5 14
-+
-+extern unsigned char ltq_ethaddr[6];
-+
-+static struct mtd_partition easy98000_nor_partitions[] =
-+{
-+	{
-+		.name	= "uboot",
-+		.offset	= 0x0,
-+		.size	= 0x40000,
-+	},
-+	{
-+		.name	= "uboot_env",
-+		.offset	= 0x40000,
-+		.size	= 0x40000,	/* 2 sectors for redundant env. */
-+	},
-+	{
-+		.name	= "linux",
-+		.offset	= 0x80000,
-+		.size	= 0xF80000,	/* map only 16 MiB */
-+	},
-+};
-+
-+static struct physmap_flash_data easy98000_nor_flash_data = {
-+	.nr_parts	= ARRAY_SIZE(easy98000_nor_partitions),
-+	.parts		= easy98000_nor_partitions,
-+};
-+
-+static struct flash_platform_data easy98000_spi_flash_platform_data = {
-+	.name = "sflash",
-+	.parts = easy98000_nor_partitions,
-+	.nr_parts = ARRAY_SIZE(easy98000_nor_partitions)
-+};
-+
-+static struct spi_board_info easy98000_spi_flash_data __initdata = {
-+	.modalias		= "m25p80",
-+	.bus_num		= 0,
-+	.chip_select		= 0,
-+	.max_speed_hz		= 10 * 1000 * 1000,
-+	.mode			= SPI_MODE_3,
-+	.platform_data		= &easy98000_spi_flash_platform_data
-+};
-+
-+static struct gpio_led easy98000_leds_gpio[] __initdata = {
-+	{
-+		.name		= "easy98000:green:0",
-+		.gpio		= EASY98000_GPIO_LED_0,
-+		.active_low	= 0,
-+	}, {
-+		.name		= "easy98000:green:1",
-+		.gpio		= EASY98000_GPIO_LED_1,
-+		.active_low	= 0,
-+	}, {
-+		.name		= "easy98000:green:2",
-+		.gpio		= EASY98000_GPIO_LED_2,
-+		.active_low	= 0,
-+	}, {
-+		.name		= "easy98000:green:3",
-+		.gpio		= EASY98000_GPIO_LED_3,
-+		.active_low	= 0,
-+	}, {
-+		.name		= "easy98000:green:4",
-+		.gpio		= EASY98000_GPIO_LED_4,
-+		.active_low	= 0,
-+	}, {
-+		.name		= "easy98000:green:5",
-+		.gpio		= EASY98000_GPIO_LED_5,
-+		.active_low	= 0,
-+	}
-+};
-+
-+#define CONFIG_DM9000_BASE		0x14000000
-+#define DM9000_IO			(CONFIG_DM9000_BASE + 3)
-+#define DM9000_DATA			(CONFIG_DM9000_BASE + 1)
-+
-+static struct dm9000_plat_data dm9000_plat_data = {
-+	.flags = DM9000_PLATF_8BITONLY,
-+	//.dev_addr = { }, /* possibility to provide an ethernet address for the chip */
-+};
-+
-+static struct resource dm9000_resources[] = {
-+	MEM_RES("dm9000_io", DM9000_IO, DM9000_IO),
-+	MEM_RES("dm9000_data", DM9000_DATA, DM9000_DATA),
-+	[2] = {
-+		/* with irq (210 -> gpio 110) the driver is very unreliable */
-+		.start	= -1,		/* use polling */
-+		.end	= -1,
-+		.flags	= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
-+	},
-+};
-+
-+static struct platform_device dm9000_platform = {
-+	.name = "dm9000",
-+	.id = 0,
-+	.num_resources	= ARRAY_SIZE(dm9000_resources),
-+	.resource	= dm9000_resources,
-+	.dev = {
-+		.platform_data = (void *) &dm9000_plat_data,
-+	}
-+};
-+
-+extern int easy98000_addon_has_dm9000(void);
-+static void __init register_davicom(void)
-+{
-+	if (!easy98000_addon_has_dm9000())
-+		return;
-+
-+	if (!is_valid_ether_addr(ltq_ethaddr))
-+		random_ether_addr(dm9000_plat_data.dev_addr);
-+	else {
-+		memcpy(dm9000_plat_data.dev_addr, ltq_ethaddr, 6);
-+		/* change to "Locally Administered Address" */
-+		dm9000_plat_data.dev_addr[0] |= 0x2;
-+	}
-+	platform_device_register(&dm9000_platform);
-+}
-+
-+static struct i2c_gpio_platform_data easy98000_i2c_gpio_data = {
-+	.sda_pin	= 107,
-+	.scl_pin	= 108,
-+};
-+
-+static struct platform_device easy98000_i2c_gpio_device = {
-+	.name		= "i2c-gpio",
-+	.id		= 0,
-+	.dev = {
-+		.platform_data	= &easy98000_i2c_gpio_data,
-+	}
-+};
-+
-+void __init register_easy98000_cpld(void)
-+{
-+	platform_device_register_simple("easy98000_cpld_led", 0, NULL, 0);
-+	platform_device_register_simple("easy98000_addon", 0, NULL, 0);
-+}
-+
-+/* setup gpio based spi bus/device for access to the eeprom on the board */
-+#define SPI_GPIO_MRST	102
-+#define SPI_GPIO_MTSR	103
-+#define SPI_GPIO_CLK	104
-+#define SPI_GPIO_CS0	105
-+#define SPI_GPIO_CS1	106
-+#define SPI_GPIO_BUS_NUM	1
-+
-+static struct spi_gpio_platform_data easy98000_spi_gpio_data = {
-+	.sck		= SPI_GPIO_CLK,
-+	.mosi		= SPI_GPIO_MTSR,
-+	.miso		= SPI_GPIO_MRST,
-+	.num_chipselect	= 2,
-+};
-+
-+static struct platform_device easy98000_spi_gpio_device = {
-+	.name			= "spi_gpio",
-+	.id			= SPI_GPIO_BUS_NUM,
-+	.dev.platform_data	= &easy98000_spi_gpio_data,
-+};
-+
-+static struct spi_eeprom at25160n = {
-+	.byte_len	= 16 * 1024 / 8,
-+	.name		= "at25160n",
-+	.page_size	= 32,
-+	.flags		= EE_ADDR2,
-+};
-+
-+static struct spi_board_info easy98000_spi_gpio_devices __initdata = {
-+	.modalias		= "at25",
-+	.bus_num		= SPI_GPIO_BUS_NUM,
-+	.max_speed_hz		= 1000 * 1000,
-+	.mode			= SPI_MODE_3,
-+	.chip_select		= 1,
-+	.controller_data	= (void *) SPI_GPIO_CS1,
-+	.platform_data		= &at25160n,
-+};
-+
-+static void __init easy98000_spi_gpio_init(void)
-+{
-+	spi_register_board_info(&easy98000_spi_gpio_devices, 1);
-+	platform_device_register(&easy98000_spi_gpio_device);
-+}
-+
-+static void __init easy98000_init_common(void)
-+{
-+	falcon_register_asc(0);
-+	falcon_register_gpio();
-+	falcon_register_wdt();
-+	falcon_register_i2c();
-+	platform_device_register(&easy98000_i2c_gpio_device);
-+	register_davicom();
-+	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(easy98000_leds_gpio),
-+					easy98000_leds_gpio);
-+	register_easy98000_cpld();
-+	falcon_register_crypto();
-+	easy98000_spi_gpio_init();
-+}
-+
-+static void __init easy98000_init(void)
-+{
-+	easy98000_init_common();
-+	falcon_register_nor(&easy98000_nor_flash_data);
-+}
-+
-+static void __init easy98000sf_init(void)
-+{
-+	easy98000_init_common();
-+	falcon_register_spi_flash(&easy98000_spi_flash_data);
-+}
-+
-+static void __init easy98000nand_init(void)
-+{
-+	easy98000_init_common();
-+	falcon_register_nand();
-+}
-+
-+MIPS_MACHINE(LANTIQ_MACH_EASY98000,
-+			"EASY98000",
-+			"EASY98000 Eval Board",
-+			easy98000_init);
-+
-+MIPS_MACHINE(LANTIQ_MACH_EASY98000SF,
-+			"EASY98000SF",
-+			"EASY98000 Eval Board (Serial Flash)",
-+			easy98000sf_init);
-+
-+MIPS_MACHINE(LANTIQ_MACH_EASY98000NAND,
-+			"EASY98000NAND",
-+			"EASY98000 Eval Board (NAND Flash)",
-+			easy98000nand_init);
---- /dev/null
-+++ b/arch/mips/lantiq/falcon/softdog_vpe.c
-@@ -0,0 +1,109 @@
-+/*
-+** =============================================================================
-+** FILE NAME     : softdog_vpe.c
-+** MODULES       : LXDB
-+** DATE          : 24-03-2008
-+** AUTHOR        : LXDB Team
-+** DESCRIPTION   : This header file contains the code for the watchdog
-+**                 implentation on vpe1 side.
-+** REFERENCES    :
-+** COPYRIGHT     : Copyright (c) 2008
-+**                 Am Campeon 1-12, 85579 Neubiberg, Germany
-+** Any use of this software is subject to the conclusion of a respective
-+** License agreement. Without such a License agreement no rights to the
-+** software are granted
-+**
-+** HISTORY       :
-+** $Date   $Author    $Comment
-+** 24-03-2008   LXDB    Initial version
-+** ============================================================================
-+*/
-+
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/types.h>
-+#include <linux/timer.h>
-+#include <linux/reboot.h>
-+#include <linux/init.h>
-+#include <linux/jiffies.h>
-+
-+#include <falcon/vpe.h>
-+
-+static unsigned long last_wdog_value;
-+static unsigned long vpe1_wdog_cleared;
-+
-+static unsigned long vpe1_wdog_dead;
-+static void watchdog_vpe0_fire(unsigned long); /* Called when vpe0 timer expires */
-+static void keep_alive_vpe0(unsigned long);
-+VPE_SW_WDOG_RESET reset_local_fn;
-+
-+
-+static struct timer_list watchdog_vpe0_ticktock =
-+                TIMER_INITIALIZER(watchdog_vpe0_fire, 0, 0);
-+
-+static void watchdog_vpe0_fire (unsigned long flags)
-+{
-+	volatile unsigned long *wdog_ctr_value;
-+	wdog_ctr_value = (void*)vpe1_wdog_ctr;
-+	if (*wdog_ctr_value == last_wdog_value) { /* VPE1 watchdog expiry handling */
-+		vpe1_sw_wdog_stop(flags);
-+		vpe1_wdog_dead++;
-+		printk(KERN_DEBUG "VPE1 watchdog reset handler called\n");
-+	/* Call the reset handler function */
-+		reset_local_fn(flags);
-+	} else { /* Everything is OK on vpe1 side. Continue. */
-+		last_wdog_value = *wdog_ctr_value;
-+		vpe1_wdog_cleared++;
-+		keep_alive_vpe0(flags);
-+	}
-+}
-+
-+int32_t vpe1_sw_wdog_register_reset_handler (VPE_SW_WDOG_RESET reset_fn)
-+{
-+	reset_local_fn = (VPE_SW_WDOG_RESET)reset_fn;
-+	return 0;
-+}
-+
-+static void keep_alive_vpe0(unsigned long flags)
-+{
-+	mod_timer(&watchdog_vpe0_ticktock, jiffies+ vpe1_wdog_timeout );
-+}
-+
-+unsigned long vpe1_sw_wdog_start(unsigned long flags)
-+{
-+	volatile unsigned long *wdog_ctr_value;
-+	wdog_ctr_value = (void*)vpe1_wdog_ctr;
-+	*wdog_ctr_value = 0;
-+	last_wdog_value = 0;
-+	keep_alive_vpe0(flags);
-+	return 0;
-+}
-+
-+unsigned long vpe1_sw_wdog_stop(unsigned long flags)
-+{
-+	del_timer(&watchdog_vpe0_ticktock);
-+	return 0;
-+}
-+
-+static int __init watchdog_vpe1_init(void)
-+{
-+	/* Nothing to be done here */
-+	return 0;
-+}
-+
-+static void __exit watchdog_vpe1_exit(void)
-+{
-+	unsigned long flags=0;
-+	vpe1_sw_wdog_stop(flags);
-+}
-+
-+module_init(watchdog_vpe1_init);
-+module_exit(watchdog_vpe1_exit);
-+
-+EXPORT_SYMBOL(vpe1_sw_wdog_register_reset_handler);
-+EXPORT_SYMBOL(vpe1_sw_wdog_start);
-+EXPORT_SYMBOL(vpe1_sw_wdog_stop);
-+
-+MODULE_AUTHOR("LXDB");
-+MODULE_DESCRIPTION("Software Watchdog For VPE1");
-+MODULE_LICENSE("GPL");
---- /dev/null
-+++ b/arch/mips/include/asm/mach-lantiq/falcon/vpe.h
-@@ -0,0 +1,44 @@
-+/*
-+ *   This program is free software; you can redistribute it and/or modify
-+ *   it under the terms of the GNU General Public License as published by
-+ *   the Free Software Foundation; either version 2 of the License, or
-+ *   (at your option) any later version.
-+ *
-+ *   This program is distributed in the hope that it will be useful,
-+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *   GNU General Public License for more details.
-+ *
-+ *   You should have received a copy of the GNU General Public License
-+ *   along with this program; if not, write to the Free Software
-+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
-+ *
-+ *   Copyright (C) 2005 infineon
-+ *   Copyright (C) 2007 John Crispin <blogic@openwrt.org>
-+ *
-+ */
-+#ifndef _IFXMIPS_VPE_H__
-+#define _IFXMIPS_VPE_H__
-+
-+/* For the explanation of the APIs please refer the section "MT APRP Kernel
-+ * Programming" in AR9 SW Architecture Specification
-+ */
-+int32_t vpe1_sw_start(void* sw_start_addr, uint32_t tcmask, uint32_t flags);
-+int32_t vpe1_sw_stop(uint32_t flags);
-+uint32_t vpe1_get_load_addr (uint32_t flags);
-+uint32_t vpe1_get_max_mem (uint32_t flags);
-+
-+int32_t vpe1_set_boot_param(char *field, char *value, char flags);
-+int32_t vpe1_get_boot_param(char *field, char **value, char flags);
-+
-+/* Watchdog APIs */
-+extern unsigned long vpe1_wdog_ctr;
-+extern unsigned long vpe1_wdog_timeout;
-+
-+unsigned long vpe1_sw_wdog_start(unsigned long);
-+unsigned long vpe1_sw_wdog_stop(unsigned long);
-+
-+typedef int (*VPE_SW_WDOG_RESET)(unsigned long wdog_cleared_ok_count);
-+int32_t vpe1_sw_wdog_register_reset_handler(VPE_SW_WDOG_RESET reset_fn);
-+
-+#endif
---- a/arch/mips/lantiq/Kconfig
-+++ b/arch/mips/lantiq/Kconfig
-@@ -16,8 +16,12 @@ config SOC_XWAY
- 	bool "XWAY"
- 	select SOC_TYPE_XWAY
- 	select HW_HAS_PCI
-+
-+config SOC_FALCON
-+	bool "FALCON"
- endchoice
- 
- source "arch/mips/lantiq/xway/Kconfig"
-+source "arch/mips/lantiq/falcon/Kconfig"
- 
- endif
---- a/arch/mips/lantiq/Makefile
-+++ b/arch/mips/lantiq/Makefile
-@@ -9,3 +9,4 @@ obj-y := irq.o setup.o clk.o prom.o devi
- obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
- 
- obj-$(CONFIG_SOC_TYPE_XWAY) += xway/
-+obj-$(CONFIG_SOC_FALCON) += falcon/
---- a/arch/mips/lantiq/Platform
-+++ b/arch/mips/lantiq/Platform
-@@ -6,3 +6,4 @@ platform-$(CONFIG_LANTIQ)	+= lantiq/
- cflags-$(CONFIG_LANTIQ)		+= -I$(srctree)/arch/mips/include/asm/mach-lantiq
- load-$(CONFIG_LANTIQ)		= 0xffffffff80002000
- cflags-$(CONFIG_SOC_TYPE_XWAY)	+= -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
-+cflags-$(CONFIG_SOC_FALCON)	+= -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon
---- a/arch/mips/lantiq/machtypes.h
-+++ b/arch/mips/lantiq/machtypes.h
-@@ -15,6 +15,12 @@ enum lantiq_mach_type {
- 	LTQ_MACH_GENERIC = 0,
- 	LTQ_MACH_EASY50712,	/* Danube evaluation board */
- 	LTQ_MACH_EASY50601,	/* Amazon SE evaluation board */
-+
-+	/* FALCON */
-+	LANTIQ_MACH_EASY98000,		/* Falcon Eval Board, NOR Flash */
-+	LANTIQ_MACH_EASY98000SF,	/* Falcon Eval Board, Serial Flash */
-+	LANTIQ_MACH_EASY98000NAND,	/* Falcon Eval Board, NAND Flash */
-+	LANTIQ_MACH_EASY98020,		/* Falcon Reference Board */
- };
- 
- #endif
---- /dev/null
-+++ b/arch/mips/lantiq/falcon/addon-easy98000.c
-@@ -0,0 +1,212 @@
-+/*
-+ *  EASY98000 CPLD Addon driver
-+ *
-+ *  Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
-+ *
-+ *  This program is free software; you can redistribute it and/or modify it
-+ *  under the terms of the GNU General Public License version 2  as published
-+ *  by the Free Software Foundation.
-+ *
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/version.h>
-+#include <linux/types.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/errno.h>
-+#include <linux/slab.h>
-+#include <linux/proc_fs.h>
-+#include <linux/seq_file.h>
-+
-+struct easy98000_reg_cpld {
-+	u16 cmdreg1;		/* 0x1 */
-+	u16 cmdreg0;		/* 0x0 */
-+	u16 idreg0;		/* 0x3 */
-+	u16 resreg;		/* 0x2 */
-+	u16 intreg;		/* 0x5 */
-+	u16 idreg1;		/* 0x4 */
-+	u16 ledreg;		/* 0x7 */
-+	u16 pcmconconfig;	/* 0x6 */
-+	u16 res0;		/* 0x9 */
-+	u16 ethledreg;		/* 0x8 */
-+	u16 res1[4];		/* 0xa-0xd */
-+	u16 cpld1v;		/* 0xf */
-+	u16 cpld2v;		/* 0xe */
-+};
-+static struct easy98000_reg_cpld * const cpld =
-+	(struct easy98000_reg_cpld *)(KSEG1 | 0x17c00000);
-+#define cpld_r8(reg) (__raw_readw(&cpld->reg) & 0xFF)
-+#define cpld_w8(val, reg) __raw_writew((val) & 0xFF, &cpld->reg)
-+
-+int easy98000_addon_has_dm9000(void)
-+{
-+	if ((cpld_r8(idreg0) & 0xF) == 1)
-+		return 1;
-+	return 0;
-+}
-+
-+#if defined(CONFIG_PROC_FS)
-+typedef void (*cpld_dump) (struct seq_file *s);
-+struct proc_entry {
-+	char *name;
-+	void *callback;
-+};
-+
-+static int cpld_proc_show ( struct seq_file *s, void *p )
-+{
-+	cpld_dump dump = s->private;
-+
-+	if ( dump != NULL )
-+		dump(s);
-+
-+	return 0;
-+}
-+
-+static int cpld_proc_open ( struct inode *inode, struct file *file )
-+{
-+	return single_open ( file, cpld_proc_show, PDE(inode)->data );
-+}
-+
-+static void cpld_versions_get ( struct seq_file *s )
-+{
-+	seq_printf(s, "CPLD1: V%d\n", cpld_r8(cpld1v));
-+	seq_printf(s, "CPLD2: V%d\n", cpld_r8(cpld2v));
-+}
-+
-+static void cpld_ebu_module_get ( struct seq_file *s )
-+{
-+	u8 addon_id;
-+
-+	addon_id = cpld_r8(idreg0) & 0xF;
-+	switch (addon_id) {
-+	case 0xF: /* nothing connected */
-+		break;
-+	case 1:
-+		seq_printf(s, "Ethernet Controller module (dm9000)\n");
-+		break;
-+	default:
-+		seq_printf(s, "Unknown EBU module (EBU_ID=0x%02X)\n", addon_id);
-+		break;
-+	}
-+}
-+
-+static void cpld_xmii_module_get ( struct seq_file *s )
-+{
-+	u8 addon_id;
-+	char *mod = NULL;
-+
-+	addon_id = cpld_r8(idreg1) & 0xF;
-+	switch (addon_id) {
-+	case 0xF:
-+		mod = "no module";
-+		break;
-+	case 0x1:
-+		mod = "RGMII module";
-+		break;
-+	case 0x4:
-+		mod = "GMII MAC Mode (XWAY TANTOS-3G)";
-+		break;
-+	case 0x6:
-+		mod = "TMII MAC Mode (XWAY TANTOS-3G)";
-+		break;
-+	case 0x8:
-+		mod = "GMII PHY module";
-+		break;
-+	case 0x9:
-+		mod = "MII PHY module";
-+		break;
-+	case 0xA:
-+		mod = "RMII PHY module";
-+		break;
-+	default:
-+		break;
-+	}
-+	if (mod)
-+		seq_printf(s, "%s\n", mod);
-+	else
-+		seq_printf(s, "unknown xMII module (xMII_ID=0x%02X)\n", addon_id);
-+}
-+
-+static struct proc_entry proc_entries[] = {
-+	{"versions",	cpld_versions_get},
-+	{"ebu",		cpld_ebu_module_get},
-+	{"xmii",	cpld_xmii_module_get},
-+};
-+
-+static struct file_operations ops = {
-+	.owner   = THIS_MODULE,
-+	.open    = cpld_proc_open,
-+	.read    = seq_read,
-+	.llseek  = seq_lseek,
-+	.release = single_release,
-+};
-+
-+static void cpld_proc_entry_create(struct proc_dir_entry *parent_node,
-+				   struct proc_entry *proc_entry)
-+{
-+	proc_create_data ( proc_entry->name, (S_IFREG | S_IRUGO), parent_node,
-+			   &ops, proc_entry->callback);
-+}
-+
-+static int cpld_proc_install(void)
-+{
-+	struct proc_dir_entry *driver_proc_node;
-+
-+	driver_proc_node = proc_mkdir("cpld", NULL);
-+	if (driver_proc_node != NULL) {
-+		int i;
-+		for (i = 0; i < ARRAY_SIZE(proc_entries); i++)
-+			cpld_proc_entry_create(driver_proc_node,
-+					      &proc_entries[i]);
-+	} else {
-+		printk("cannot create proc entry");
-+		return -1;
-+	}
-+	return 0;
-+}
-+#else
-+static inline int cpld_proc_install(void) {}
-+#endif
-+
-+static int easy98000_addon_probe(struct platform_device *pdev)
-+{
-+	return cpld_proc_install();
-+}
-+
-+static int easy98000_addon_remove(struct platform_device *pdev)
-+{
-+#if defined(CONFIG_PROC_FS)
-+	char buf[64];
-+	int i;
-+
-+	for (i = 0; i < sizeof(proc_entries) / sizeof(proc_entries[0]); i++) {
-+		sprintf(buf, "cpld/%s", proc_entries[i].name);
-+		remove_proc_entry(buf, 0);
-+	}
-+	remove_proc_entry("cpld", 0);
-+#endif
-+	return 0;
-+}
-+
-+static struct platform_driver easy98000_addon_driver = {
-+	.probe = easy98000_addon_probe,
-+	.remove = __devexit_p(easy98000_addon_remove),
-+	.driver = {
-+		.name = "easy98000_addon",
-+		.owner = THIS_MODULE,
-+	},
-+};
-+
-+int __init easy98000_addon_init(void)
-+{
-+	return platform_driver_register(&easy98000_addon_driver);
-+}
-+
-+void __exit easy98000_addon_exit(void)
-+{
-+	platform_driver_unregister(&easy98000_addon_driver);
-+}
-+
-+module_init(easy98000_addon_init);
-+module_exit(easy98000_addon_exit);
---- a/arch/mips/lantiq/prom.c
-+++ b/arch/mips/lantiq/prom.c
-@@ -45,10 +45,12 @@ static void __init prom_init_cmdline(voi
- 	char **argv = (char **) KSEG1ADDR(fw_arg1);
- 	int i;
- 
-+	arcs_cmdline[0] = '\0';
-+
- 	for (i = 0; i < argc; i++) {
--		char *p = (char *)  KSEG1ADDR(argv[i]);
-+		char *p = (char *) KSEG1ADDR(argv[i]);
- 
--		if (p && *p) {
-+		if (CPHYSADDR(p) && *p) {
- 			strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
- 			strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
- 		}
diff --git a/target/linux/lantiq/patches-3.0/130-falcon-spi-flash.patch b/target/linux/lantiq/patches-3.0/130-falcon-spi-flash.patch
deleted file mode 100644
index cf618e046d..0000000000
--- a/target/linux/lantiq/patches-3.0/130-falcon-spi-flash.patch
+++ /dev/null
@@ -1,497 +0,0 @@
---- a/drivers/spi/Makefile
-+++ b/drivers/spi/Makefile
-@@ -56,6 +56,7 @@ obj-$(CONFIG_SPI_SH_SCI)		+= spi_sh_sci.
- obj-$(CONFIG_SPI_SH_MSIOF)		+= spi_sh_msiof.o
- obj-$(CONFIG_SPI_STMP3XXX)		+= spi_stmp.o
- obj-$(CONFIG_SPI_NUC900)		+= spi_nuc900.o
-+obj-$(CONFIG_SPI_FALCON)		+= spi_falcon.o
- 
- # special build for s3c24xx spi driver with fiq support
- spi_s3c24xx_hw-y			:= spi_s3c24xx.o
---- /dev/null
-+++ b/drivers/spi/spi_falcon.c
-@@ -0,0 +1,471 @@
-+/*
-+ *   This program is free software; you can redistribute it and/or modify
-+ *   it under the terms of the GNU General Public License as published by
-+ *   the Free Software Foundation; either version 2 of the License, or
-+ *   (at your option) any later version.
-+ *
-+ *   This program is distributed in the hope that it will be useful,
-+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ *   GNU General Public License for more details.
-+ *
-+ *   You should have received a copy of the GNU General Public License
-+ *   along with this program; if not, write to the Free Software
-+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/device.h>
-+#include <linux/platform_device.h>
-+#include <linux/spi/spi.h>
-+#include <linux/delay.h>
-+#include <linux/workqueue.h>
-+
-+#include <lantiq.h> /* ebu_lock */
-+#include <falcon/ebu_reg.h>
-+#include <falcon/sys1_reg.h>
-+
-+#define DRV_NAME			"falcon_spi"
-+
-+#define FALCON_SPI_XFER_BEGIN		(1 << 0)
-+#define FALCON_SPI_XFER_END		(1 << 1)
-+
-+/* mapping for access macros */
-+#define reg_r32(reg)			__raw_readl(reg)
-+#define reg_w32(val, reg)		__raw_writel(val, reg)
-+#define reg_w32_mask(clear, set, reg)	reg_w32((reg_r32(reg) \
-+						 & ~(clear)) | (set), reg)
-+#define reg_r32_table(reg, idx)		reg_r32(&((uint32_t *)&reg)[idx])
-+#define reg_w32_table(val, reg, idx)	reg_w32(val, &((uint32_t *)&reg)[idx])
-+
-+#define ebu				(priv->ebu_membase)
-+#define sys1				(priv->sys1_membase)
-+
-+struct falcon_spi {
-+	u32 sfcmd; /* for caching of opcode, direction, ... */
-+
-+	struct spi_master *master;
-+
-+	struct gpon_reg_ebu __iomem *ebu_membase;
-+	struct gpon_reg_sys1 __iomem *sys1_membase;
-+};
-+
-+int falcon_spi_xfer(struct spi_device *spi,
-+		    struct spi_transfer *t,
-+		    unsigned long flags)
-+{
-+	struct device *dev = &spi->dev;
-+	struct falcon_spi *priv = spi_master_get_devdata(spi->master);
-+	const u8 *txp = t->tx_buf;
-+	u8 *rxp = t->rx_buf;
-+	unsigned int bytelen = ((8 * t->len + 7) / 8);
-+	unsigned int len, alen, dumlen;
-+	u32 val;
-+	enum {
-+		state_init,
-+		state_command_prepare,
-+		state_write,
-+		state_read,
-+		state_disable_cs,
-+		state_end
-+	} state = state_init;
-+
-+	do {
-+		switch (state) {
-+		case state_init: /* detect phase of upper layer sequence */
-+		{
-+			/* initial write ? */
-+			if (flags & FALCON_SPI_XFER_BEGIN) {
-+				if (!txp) {
-+					dev_err(dev,
-+						"BEGIN without tx data!\n");
-+					return -1;
-+				}
-+				/*
-+				 * Prepare the parts of the sfcmd register,
-+				 * which should not
-+				 * change during a sequence!
-+				 * Only exception are the length fields,
-+				 * especially alen and dumlen.
-+				 */
-+
-+				priv->sfcmd = ((spi->chip_select
-+						<< SFCMD_CS_OFFSET)
-+					       & SFCMD_CS_MASK);
-+				priv->sfcmd |= SFCMD_KEEP_CS_KEEP_SELECTED;
-+				priv->sfcmd |= *txp;
-+				txp++;
-+				bytelen--;
-+				if (bytelen) {
-+					/* more data:
-+					 * maybe address and/or dummy */
-+					state = state_command_prepare;
-+					break;
-+				} else {
-+					dev_dbg(dev, "write cmd %02X\n",
-+						priv->sfcmd & SFCMD_OPC_MASK);
-+				}
-+			}
-+			/* continued write ? */
-+			if (txp && bytelen) {
-+				state = state_write;
-+				break;
-+			}
-+			/* read data? */
-+			if (rxp && bytelen) {
-+				state = state_read;
-+				break;
-+			}
-+			/* end of sequence? */
-+			if (flags & FALCON_SPI_XFER_END)
-+				state = state_disable_cs;
-+			else
-+				state = state_end;
-+			break;
-+		}
-+		case state_command_prepare: /* collect tx data for
-+					       address and dummy phase */
-+		{
-+			/* txp is valid, already checked */
-+			val = 0;
-+			alen = 0;
-+			dumlen = 0;
-+			while (bytelen > 0) {
-+				if (alen < 3) {
-+					val = (val<<8)|(*txp++);
-+					alen++;
-+				} else if ((dumlen < 15) && (*txp == 0)) {
-+					/*
-+					 * assume dummy bytes are set to 0
-+					 * from upper layer
-+					 */
-+					dumlen++;
-+					txp++;
-+				} else
-+					break;
-+				bytelen--;
-+			}
-+			priv->sfcmd &= ~(SFCMD_ALEN_MASK | SFCMD_DUMLEN_MASK);
-+			priv->sfcmd |= (alen << SFCMD_ALEN_OFFSET) |
-+					 (dumlen << SFCMD_DUMLEN_OFFSET);
-+			if (alen > 0)
-+				ebu_w32(val, sfaddr);
-+
-+			dev_dbg(dev, "write cmd %02X, alen=%d "
-+				"(addr=%06X) dumlen=%d\n",
-+				priv->sfcmd & SFCMD_OPC_MASK,
-+				alen, val, dumlen);
-+
-+			if (bytelen > 0) {
-+				/* continue with write */
-+				state = state_write;
-+			} else if (flags & FALCON_SPI_XFER_END) {
-+				/* end of sequence? */
-+				state = state_disable_cs;
-+			} else {
-+				/* go to end and expect another
-+				 * call (read or write) */
-+				state = state_end;
-+			}
-+			break;
-+		}
-+		case state_write:
-+		{
-+			/* txp still valid */
-+			priv->sfcmd |= SFCMD_DIR_WRITE;
-+			len = 0;
-+			val = 0;
-+			do {
-+				if (bytelen--)
-+					val |= (*txp++) << (8 * len++);
-+				if ((flags & FALCON_SPI_XFER_END)
-+				    && (bytelen == 0)) {
-+					priv->sfcmd &=
-+						~SFCMD_KEEP_CS_KEEP_SELECTED;
-+				}
-+				if ((len == 4) || (bytelen == 0)) {
-+					ebu_w32(val, sfdata);
-+					ebu_w32(priv->sfcmd
-+						| (len<<SFCMD_DLEN_OFFSET),
-+						sfcmd);
-+					len = 0;
-+					val = 0;
-+					priv->sfcmd &= ~(SFCMD_ALEN_MASK
-+							 | SFCMD_DUMLEN_MASK);
-+				}
-+			} while (bytelen);
-+			state = state_end;
-+			break;
-+		}
-+		case state_read:
-+		{
-+			/* read data */
-+			priv->sfcmd &= ~SFCMD_DIR_WRITE;
-+			do {
-+				if ((flags & FALCON_SPI_XFER_END)
-+				    && (bytelen <= 4)) {
-+					priv->sfcmd &=
-+						~SFCMD_KEEP_CS_KEEP_SELECTED;
-+				}
-+				len = (bytelen > 4) ? 4 : bytelen;
-+				bytelen -= len;
-+				ebu_w32(priv->sfcmd
-+					|(len<<SFCMD_DLEN_OFFSET), sfcmd);
-+				priv->sfcmd &= ~(SFCMD_ALEN_MASK
-+						 | SFCMD_DUMLEN_MASK);
-+				do {
-+					val = ebu_r32(sfstat);
-+					if (val & SFSTAT_CMD_ERR) {
-+						/* reset error status */
-+						dev_err(dev, "SFSTAT: CMD_ERR "
-+							"(%x)\n", val);
-+						ebu_w32(SFSTAT_CMD_ERR, sfstat);
-+						return -1;
-+					}
-+				} while (val & SFSTAT_CMD_PEND);
-+				val = ebu_r32(sfdata);
-+				do {
-+					*rxp = (val & 0xFF);
-+					rxp++;
-+					val >>= 8;
-+					len--;
-+				} while (len);
-+			} while (bytelen);
-+			state = state_end;
-+			break;
-+		}
-+		case state_disable_cs:
-+		{
-+			priv->sfcmd &= ~SFCMD_KEEP_CS_KEEP_SELECTED;
-+			ebu_w32(priv->sfcmd | (0<<SFCMD_DLEN_OFFSET), sfcmd);
-+			val = ebu_r32(sfstat);
-+			if (val & SFSTAT_CMD_ERR) {
-+				/* reset error status */
-+				dev_err(dev, "SFSTAT: CMD_ERR (%x)\n", val);
-+				ebu_w32(SFSTAT_CMD_ERR, sfstat);
-+				return -1;
-+			}
-+			state = state_end;
-+			break;
-+		}
-+		case state_end:
-+			break;
-+		}
-+	} while (state != state_end);
-+
-+	return 0;
-+}
-+
-+static int falcon_spi_setup(struct spi_device *spi)
-+{
-+	struct device *dev = &spi->dev;
-+	struct falcon_spi *priv = spi_master_get_devdata(spi->master);
-+	const u32 ebuclk = 100*1000*1000;
-+	unsigned int i;
-+	unsigned long flags;
-+
-+	dev_dbg(dev, "setup\n");
-+
-+	if (spi->master->bus_num > 0 || spi->chip_select > 0)
-+		return -ENODEV;
-+
-+	spin_lock_irqsave(&ebu_lock, flags);
-+
-+	if (ebuclk < spi->max_speed_hz) {
-+		/* set EBU clock to 100 MHz */
-+		sys1_w32_mask(0, EBUCC_EBUDIV_SELF100, ebucc);
-+		i = 1; /* divider */
-+	} else {
-+		/* set EBU clock to 50 MHz */
-+		sys1_w32_mask(EBUCC_EBUDIV_SELF100, 0, ebucc);
-+
-+		/* search for suitable divider */
-+		for (i = 1; i < 7; i++) {
-+			if (ebuclk / i <= spi->max_speed_hz)
-+				break;
-+		}
-+	}
-+
-+	/* setup period of serial clock */
-+	ebu_w32_mask(SFTIME_SCKF_POS_MASK
-+		     | SFTIME_SCKR_POS_MASK
-+		     | SFTIME_SCK_PER_MASK,
-+		     (i << SFTIME_SCKR_POS_OFFSET)
-+		     | (i << (SFTIME_SCK_PER_OFFSET + 1)),
-+		     sftime);
-+
-+	/* set some bits of unused_wd, to not trigger HOLD/WP
-+	 * signals on non QUAD flashes */
-+	ebu_w32((SFIO_UNUSED_WD_MASK & (0x8|0x4)), sfio);
-+
-+	ebu_w32(BUSRCON0_AGEN_SERIAL_FLASH | BUSRCON0_PORTW_8_BIT_MUX,
-+		busrcon0);
-+	ebu_w32(BUSWCON0_AGEN_SERIAL_FLASH, buswcon0);
-+	/* set address wrap around to maximum for 24-bit addresses */
-+	ebu_w32_mask(SFCON_DEV_SIZE_MASK, SFCON_DEV_SIZE_A23_0, sfcon);
-+
-+	spin_unlock_irqrestore(&ebu_lock, flags);
-+
-+	return 0;
-+}
-+
-+static int falcon_spi_transfer(struct spi_device *spi, struct spi_message *m)
-+{
-+	struct falcon_spi *priv = spi_master_get_devdata(spi->master);
-+	struct spi_transfer *t;
-+	unsigned long spi_flags;
-+	unsigned long flags;
-+	int ret = 0;
-+
-+	priv->sfcmd = 0;
-+	m->actual_length = 0;
-+
-+	spi_flags = FALCON_SPI_XFER_BEGIN;
-+	list_for_each_entry(t, &m->transfers, transfer_list) {
-+		if (list_is_last(&t->transfer_list, &m->transfers))
-+			spi_flags |= FALCON_SPI_XFER_END;
-+
-+		spin_lock_irqsave(&ebu_lock, flags);
-+		ret = falcon_spi_xfer(spi, t, spi_flags);
-+		spin_unlock_irqrestore(&ebu_lock, flags);
-+
-+		if (ret)
-+			break;
-+
-+		m->actual_length += t->len;
-+
-+		if (t->delay_usecs || t->cs_change)
-+			BUG();
-+
-+		spi_flags = 0;
-+	}
-+
-+	m->status = ret;
-+	m->complete(m->context);
-+
-+	return 0;
-+}
-+
-+static void falcon_spi_cleanup(struct spi_device *spi)
-+{
-+	struct device *dev = &spi->dev;
-+
-+	dev_dbg(dev, "cleanup\n");
-+}
-+
-+static int __devinit falcon_spi_probe(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct falcon_spi *priv;
-+	struct spi_master *master;
-+	struct resource *memres_ebu, *memres_sys1;
-+	int ret;
-+
-+	dev_dbg(dev, "probing\n");
-+
-+	memres_ebu = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ebu");
-+	memres_sys1 = platform_get_resource_byname(pdev, IORESOURCE_MEM,
-+						   "sys1");
-+
-+	if (!memres_ebu || !memres_sys1) {
-+		dev_err(dev, "no resources\n");
-+		return -ENODEV;
-+	}
-+
-+	master = spi_alloc_master(&pdev->dev, sizeof(*priv));
-+	if (!master) {
-+		dev_err(dev, "no memory for spi_master\n");
-+		return -ENOMEM;
-+	}
-+
-+	priv = spi_master_get_devdata(master);
-+
-+	priv->ebu_membase = ioremap_nocache(memres_ebu->start & ~KSEG1,
-+					    resource_size(memres_ebu));
-+
-+	if (!priv->ebu_membase) {
-+		dev_err(dev, "can't map ebu memory\n");
-+
-+		ret = -ENOMEM;
-+		goto free_master;
-+	}
-+
-+	priv->sys1_membase = ioremap_nocache(memres_sys1->start & ~KSEG1,
-+					    resource_size(memres_sys1));
-+
-+	if (!priv->sys1_membase) {
-+		dev_err(dev, "can't map sys1 memory\n");
-+
-+		ret = -ENOMEM;
-+		goto unmap_ebu;
-+	}
-+
-+	priv->master = master;
-+
-+	master->mode_bits = SPI_MODE_3;
-+	master->num_chipselect = 1;
-+	master->bus_num = 0;
-+
-+	master->setup = falcon_spi_setup;
-+	master->transfer = falcon_spi_transfer;
-+	master->cleanup = falcon_spi_cleanup;
-+
-+	platform_set_drvdata(pdev, priv);
-+
-+	ret = spi_register_master(master);
-+	if (ret)
-+		goto unmap_sys1;
-+
-+	return 0;
-+
-+unmap_sys1:
-+	iounmap(priv->sys1_membase);
-+
-+unmap_ebu:
-+	iounmap(priv->ebu_membase);
-+
-+free_master:
-+	spi_master_put(master);
-+
-+	return ret;
-+}
-+
-+static int __devexit falcon_spi_remove(struct platform_device *pdev)
-+{
-+	struct device *dev = &pdev->dev;
-+	struct falcon_spi *priv = platform_get_drvdata(pdev);
-+
-+	dev_dbg(dev, "removed\n");
-+
-+	spi_unregister_master(priv->master);
-+
-+	iounmap(priv->sys1_membase);
-+	iounmap(priv->ebu_membase);
-+
-+	return 0;
-+}
-+
-+static struct platform_driver falcon_spi_driver = {
-+	.probe	= falcon_spi_probe,
-+	.remove	= __devexit_p(falcon_spi_remove),
-+	.driver = {
-+		.name	= DRV_NAME,
-+		.owner	= THIS_MODULE
-+	}
-+};
-+
-+static int __init falcon_spi_init(void)
-+{
-+	return platform_driver_register(&falcon_spi_driver);
-+}
-+
-+static void __exit falcon_spi_exit(void)
-+{
-+	platform_driver_unregister(&falcon_spi_driver);
-+}
-+
-+module_init(falcon_spi_init);
-+module_exit(falcon_spi_exit);
-+
-+MODULE_LICENSE("GPL");
-+MODULE_DESCRIPTION("Lantiq Falcon SPI controller driver");
---- a/drivers/spi/Kconfig
-+++ b/drivers/spi/Kconfig
-@@ -219,6 +219,10 @@ config SPI_MPC52xx
- 	  This drivers supports the MPC52xx SPI controller in master SPI
- 	  mode.
- 
-+config SPI_FALCON
-+	tristate "Falcon SPI controller support"
-+	depends on SOC_FALCON
-+
- config SPI_MPC52xx_PSC
- 	tristate "Freescale MPC52xx PSC SPI controller"
- 	depends on PPC_MPC52xx && EXPERIMENTAL
diff --git a/target/linux/lantiq/patches-3.0/140-falcon-easy98000-cpld-led.patch b/target/linux/lantiq/patches-3.0/140-falcon-easy98000-cpld-led.patch
deleted file mode 100644
index c93c3e779d..0000000000
--- a/target/linux/lantiq/patches-3.0/140-falcon-easy98000-cpld-led.patch
+++ /dev/null
@@ -1,193 +0,0 @@
---- a/arch/mips/lantiq/falcon/Makefile
-+++ b/arch/mips/lantiq/falcon/Makefile
-@@ -2,3 +2,4 @@ obj-y := clk-falcon.o devices.o gpio.o p
- obj-y += softdog_vpe.o
- obj-$(CONFIG_LANTIQ_MACH_EASY98000) += addon-easy98000.o
- obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o
-+obj-$(CONFIG_LANTIQ_MACH_EASY98000) += dev-leds-easy98000-cpld.o
---- /dev/null
-+++ b/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.c
-@@ -0,0 +1,160 @@
-+/*
-+ *  EASY98000 CPLD LED driver
-+ *
-+ *  Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com>
-+ *
-+ *  This program is free software; you can redistribute it and/or modify it
-+ *  under the terms of the GNU General Public License version 2  as published
-+ *  by the Free Software Foundation.
-+ *
-+ */
-+
-+#include <linux/kernel.h>
-+#include <linux/version.h>
-+#include <linux/types.h>
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/errno.h>
-+#include <linux/leds.h>
-+#include <linux/slab.h>
-+
-+#include "dev-leds-easy98000-cpld.h"
-+
-+const char *led_name[8] = {
-+	"ge0_act",
-+	"ge0_link",
-+	"ge1_act",
-+	"ge1_link",
-+	"fe2_act",
-+	"fe2_link",
-+	"fe3_act",
-+	"fe3_link"
-+};
-+
-+#define cpld_base7			((u16 *)(KSEG1 | 0x17c0000c))
-+#define cpld_base8			((u16 *)(KSEG1 | 0x17c00012))
-+
-+#define ltq_r16(reg)			__raw_readw(reg)
-+#define ltq_w16(val, reg)		__raw_writew(val, reg)
-+
-+struct cpld_led_dev {
-+	struct led_classdev	cdev;
-+	u8			mask;
-+	u16			*base;
-+};
-+
-+struct cpld_led_drvdata {
-+	struct cpld_led_dev	*led_devs;
-+	int			num_leds;
-+};
-+
-+void led_set(u8 mask, u16 *base)
-+{
-+	ltq_w16(ltq_r16(base) | mask, base);
-+}
-+
-+void led_clear(u8 mask, u16 *base)
-+{
-+	ltq_w16(ltq_r16(base) & (~mask), base);
-+}
-+
-+void led_blink_clear(u8 mask, u16 *base)
-+{
-+	led_clear(mask, base);
-+}
-+
-+static void led_brightness(struct led_classdev *led_cdev,
-+			       enum led_brightness value)
-+{
-+	struct cpld_led_dev *led_dev =
-+	    container_of(led_cdev, struct cpld_led_dev, cdev);
-+
-+	if (value)
-+		led_set(led_dev->mask, led_dev->base);
-+	else
-+		led_clear(led_dev->mask, led_dev->base);
-+}
-+
-+static int led_probe(struct platform_device *pdev)
-+{
-+	int i;
-+	char name[32];
-+	struct cpld_led_drvdata *drvdata;
-+	int ret = 0;
-+
-+	drvdata = kzalloc(sizeof(struct cpld_led_drvdata) +
-+			  sizeof(struct cpld_led_dev) * MAX_LED,
-+			  GFP_KERNEL);
-+	if (!drvdata)
-+		return -ENOMEM;
-+
-+	drvdata->led_devs = (struct cpld_led_dev *) &drvdata[1];
-+
-+	for (i = 0; i < MAX_LED; i++) {
-+		struct cpld_led_dev *led_dev = &drvdata->led_devs[i];
-+		led_dev->cdev.brightness_set = led_brightness;
-+		led_dev->cdev.default_trigger = NULL;
-+		led_dev->mask = 1 << (i % 8);
-+		if(i < 8) {
-+			sprintf(name, "easy98000-cpld:%s", led_name[i]);
-+			led_dev->base = cpld_base8;
-+		} else {
-+			sprintf(name, "easy98000-cpld:red:%d", i-8);
-+			led_dev->base = cpld_base7;
-+		}
-+		led_dev->cdev.name = name;
-+		ret = led_classdev_register(&pdev->dev, &led_dev->cdev);
-+		if (ret)
-+			goto err;
-+	}
-+	platform_set_drvdata(pdev, drvdata);
-+	return 0;
-+
-+err:
-+	printk("led_probe: 3\n");
-+	for (i = i - 1; i >= 0; i--)
-+		led_classdev_unregister(&drvdata->led_devs[i].cdev);
-+
-+	kfree(drvdata);
-+	return ret;
-+}
-+
-+static int led_remove(struct platform_device *pdev)
-+{
-+	int i;
-+	struct cpld_led_drvdata *drvdata = platform_get_drvdata(pdev);
-+	for (i = 0; i < MAX_LED; i++)
-+		led_classdev_unregister(&drvdata->led_devs[i].cdev);
-+	kfree(drvdata);
-+	return 0;
-+}
-+
-+static struct platform_driver led_driver = {
-+	.probe = led_probe,
-+	.remove = __devexit_p(led_remove),
-+	.driver = {
-+		   .name = LED_NAME,
-+		   .owner = THIS_MODULE,
-+		   },
-+};
-+
-+int __init easy98000_cpld_led_init(void)
-+{
-+	pr_info(LED_DESC ", Version " LED_VERSION
-+		" (c) Copyright 2011, Lantiq Deutschland GmbH\n");
-+	return platform_driver_register(&led_driver);
-+}
-+
-+void __exit easy98000_cpld_led_exit(void)
-+{
-+	platform_driver_unregister(&led_driver);
-+}
-+
-+module_init(easy98000_cpld_led_init);
-+module_exit(easy98000_cpld_led_exit);
-+
-+MODULE_DESCRIPTION(LED_NAME);
-+MODULE_DESCRIPTION(LED_DESC);
-+MODULE_AUTHOR("Ralph Hempel <ralph.hempel@lantiq.com>");
-+MODULE_LICENSE("GPL v2");
-+
---- /dev/null
-+++ b/arch/mips/lantiq/falcon/dev-leds-easy98000-cpld.h
-@@ -0,0 +1,20 @@
-+/*
-+ *  EASY98000 CPLD LED driver
-+ *
-+ *  Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com>
-+ *
-+ *  This program is free software; you can redistribute it and/or modify it
-+ *  under the terms of the GNU General Public License version 2  as published
-+ *  by the Free Software Foundation.
-+ *
-+ */
-+#ifndef _INCLUDE_EASY98000_CPLD_LED_H_
-+#define _INCLUDE_EASY98000_CPLD_LED_H_
-+
-+#define LED_NAME	"easy98000_cpld_led"
-+#define LED_DESC	"EASY98000 LED driver"
-+#define LED_VERSION	"1.0.0"
-+
-+#define MAX_LED		16
-+
-+#endif	/* _INCLUDE_EASY98000_CPLD_LED_H_ */
diff --git a/target/linux/lantiq/patches-3.0/150-falcon-easy98020.patch b/target/linux/lantiq/patches-3.0/150-falcon-easy98020.patch
deleted file mode 100644
index 7ddf77ab21..0000000000
--- a/target/linux/lantiq/patches-3.0/150-falcon-easy98020.patch
+++ /dev/null
@@ -1,136 +0,0 @@
---- /dev/null
-+++ b/arch/mips/lantiq/falcon/mach-easy98020.c
-@@ -0,0 +1,113 @@
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/leds.h>
-+#include <linux/gpio.h>
-+#include <linux/gpio_buttons.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/input.h>
-+#include <linux/interrupt.h>
-+#include <linux/spi/spi.h>
-+#include <linux/spi/flash.h>
-+#include "../machtypes.h"
-+
-+#include "devices.h"
-+#include "dev-leds-gpio.h"
-+
-+#define EASY98020_GPIO_LED_0 9
-+#define EASY98020_GPIO_LED_1 10
-+#define EASY98020_GPIO_LED_2 11
-+#define EASY98020_GPIO_LED_3 12
-+#define EASY98020_GPIO_LED_GE0_ACT 110
-+#define EASY98020_GPIO_LED_GE0_LINK 109
-+#define EASY98020_GPIO_LED_GE1_ACT 106
-+#define EASY98020_GPIO_LED_GE1_LINK 105
-+
-+extern unsigned char ltq_ethaddr[6];
-+
-+static struct mtd_partition easy98020_spi_partitions[] =
-+{
-+	{
-+		.name	= "uboot",
-+		.offset	= 0x0,
-+		.size	= 0x40000,
-+	},
-+	{
-+		.name	= "uboot_env",
-+		.offset	= 0x40000,
-+		.size	= 0x40000,	/* 2 sectors for redundant env. */
-+	},
-+	{
-+		.name	= "linux",
-+		.offset	= 0x80000,
-+		.size	= 0xF80000,	/* map only 16 MiB */
-+	},
-+};
-+
-+static struct flash_platform_data easy98020_spi_flash_platform_data = {
-+	.name = "sflash",
-+	.parts = easy98020_spi_partitions,
-+	.nr_parts = ARRAY_SIZE(easy98020_spi_partitions)
-+};
-+
-+static struct spi_board_info easy98020_spi_flash_data __initdata = {
-+	.modalias		= "m25p80",
-+	.bus_num		= 0,
-+	.chip_select		= 0,
-+	.max_speed_hz		= 10 * 1000 * 1000,
-+	.mode			= SPI_MODE_3,
-+	.platform_data		= &easy98020_spi_flash_platform_data
-+};
-+
-+static struct gpio_led easy98020_leds_gpio[] __initdata = {
-+	{
-+		.name		= "easy98020:green:0",
-+		.gpio		= EASY98020_GPIO_LED_0,
-+		.active_low	= 0,
-+	}, {
-+		.name		= "easy98020:green:1",
-+		.gpio		= EASY98020_GPIO_LED_1,
-+		.active_low	= 0,
-+	}, {
-+		.name		= "easy98020:green:2",
-+		.gpio		= EASY98020_GPIO_LED_2,
-+		.active_low	= 0,
-+	}, {
-+		.name		= "easy98020:green:3",
-+		.gpio		= EASY98020_GPIO_LED_3,
-+		.active_low	= 0,
-+	}, {
-+		.name		= "easy98020:ge0_act",
-+		.gpio		= EASY98020_GPIO_LED_GE0_ACT,
-+		.active_low	= 0,
-+	}, {
-+		.name		= "easy98020:ge0_link",
-+		.gpio		= EASY98020_GPIO_LED_GE0_LINK,
-+		.active_low	= 0,
-+	}, {
-+		.name		= "easy98020:ge1_act",
-+		.gpio		= EASY98020_GPIO_LED_GE1_ACT,
-+		.active_low	= 0,
-+	}, {
-+		.name		= "easy98020:ge1_link",
-+		.gpio		= EASY98020_GPIO_LED_GE1_LINK,
-+		.active_low	= 0,
-+	}
-+};
-+
-+static void __init easy98020_init(void)
-+{
-+	falcon_register_asc(0);
-+	falcon_register_gpio();
-+	falcon_register_wdt();
-+	falcon_register_i2c();
-+	falcon_register_spi_flash(&easy98020_spi_flash_data);
-+	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(easy98020_leds_gpio),
-+					easy98020_leds_gpio);
-+	falcon_register_crypto();
-+}
-+
-+MIPS_MACHINE(LANTIQ_MACH_EASY98020,
-+			"EASY98020",
-+			"EASY98020 Eval Board",
-+			easy98020_init);
---- a/arch/mips/lantiq/falcon/Kconfig
-+++ b/arch/mips/lantiq/falcon/Kconfig
-@@ -6,6 +6,10 @@ config LANTIQ_MACH_EASY98000
- 	bool "Easy98000"
- 	default y
- 
-+config LANTIQ_MACH_EASY98020
-+	bool "Easy98020"
-+	default y
-+
- endmenu
- 
- endif
---- a/arch/mips/lantiq/falcon/Makefile
-+++ b/arch/mips/lantiq/falcon/Makefile
-@@ -3,3 +3,4 @@ obj-y += softdog_vpe.o
- obj-$(CONFIG_LANTIQ_MACH_EASY98000) += addon-easy98000.o
- obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o
- obj-$(CONFIG_LANTIQ_MACH_EASY98000) += dev-leds-easy98000-cpld.o
-+obj-$(CONFIG_LANTIQ_MACH_EASY98020) += mach-easy98020.o
diff --git a/target/linux/lantiq/patches-3.0/160-falcon-95C3AM1.patch b/target/linux/lantiq/patches-3.0/160-falcon-95C3AM1.patch
deleted file mode 100644
index 7245eb5b62..0000000000
--- a/target/linux/lantiq/patches-3.0/160-falcon-95C3AM1.patch
+++ /dev/null
@@ -1,132 +0,0 @@
---- /dev/null
-+++ b/arch/mips/lantiq/falcon/mach-95C3AM1.c
-@@ -0,0 +1,99 @@
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/i2c-gpio.h>
-+#include "../machtypes.h"
-+
-+#include "devices.h"
-+#include "dev-leds-gpio.h"
-+
-+#define BOARD_95C3AM1_GPIO_LED_0 10
-+#define BOARD_95C3AM1_GPIO_LED_1 11
-+#define BOARD_95C3AM1_GPIO_LED_2 12
-+#define BOARD_95C3AM1_GPIO_LED_3 13
-+
-+extern unsigned char ltq_ethaddr[6];
-+
-+static struct mtd_partition board_95C3AM1_partitions[] =
-+{
-+	{
-+		.name	= "uboot",
-+		.offset	= 0x0,
-+		.size	= 0x40000,
-+	},
-+	{
-+		.name	= "uboot_env",
-+		.offset	= 0x40000,
-+		.size	= 0x40000,	/* 2 sectors for redundant env. */
-+	},
-+	{
-+		.name	= "linux",
-+		.offset	= 0x80000,
-+		.size	= 0xF80000,	/* map only 16 MiB */
-+	},
-+};
-+
-+static struct flash_platform_data board_95C3AM1_flash_platform_data = {
-+	.name = "sflash",
-+	.parts = board_95C3AM1_partitions,
-+	.nr_parts = ARRAY_SIZE(board_95C3AM1_partitions)
-+};
-+
-+static struct spi_board_info board_95C3AM1_flash_data __initdata = {
-+	.modalias		= "m25p80",
-+	.bus_num		= 0,
-+	.chip_select		= 0,
-+	.max_speed_hz		= 10 * 1000 * 1000,
-+	.mode			= SPI_MODE_3,
-+	.platform_data		= &board_95C3AM1_flash_platform_data
-+};
-+
-+static struct gpio_led board_95C3AM1_leds_gpio[] __initdata = {
-+	{
-+		.name		= "power",
-+		.gpio		= BOARD_95C3AM1_GPIO_LED_0,
-+		.active_low	= 0,
-+	}, {
-+		.name		= "optical",
-+		.gpio		= BOARD_95C3AM1_GPIO_LED_1,
-+		.active_low	= 0,
-+	}, {
-+		.name		= "lan",
-+		.gpio		= BOARD_95C3AM1_GPIO_LED_2,
-+		.active_low	= 0,
-+	}, {
-+		.name		= "update",
-+		.gpio		= BOARD_95C3AM1_GPIO_LED_3,
-+		.active_low	= 0,
-+	}
-+};
-+
-+static struct i2c_gpio_platform_data board_95C3AM1_i2c_gpio_data = {
-+	.sda_pin	= 107,
-+	.scl_pin	= 108,
-+};
-+
-+static struct platform_device board_95C3AM1_i2c_gpio_device = {
-+	.name		= "i2c-gpio",
-+	.id		= 0,
-+	.dev = {
-+		.platform_data	= &board_95C3AM1_i2c_gpio_data,
-+	}
-+};
-+
-+static void __init board_95C3AM1_init(void)
-+{
-+	falcon_register_asc(0);
-+	falcon_register_gpio();
-+	falcon_register_wdt();
-+	falcon_register_i2c();
-+	falcon_register_spi_flash(&board_95C3AM1_flash_data);
-+	platform_device_register(&board_95C3AM1_i2c_gpio_device);
-+	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(board_95C3AM1_leds_gpio),
-+						board_95C3AM1_leds_gpio);
-+	falcon_register_crypto();
-+}
-+
-+MIPS_MACHINE(LANTIQ_MACH_95C3AM1,
-+			"95C3AM1",
-+			"95C3AM1 Board",
-+			board_95C3AM1_init);
---- a/arch/mips/lantiq/falcon/Kconfig
-+++ b/arch/mips/lantiq/falcon/Kconfig
-@@ -10,6 +10,10 @@ config LANTIQ_MACH_EASY98020
- 	bool "Easy98020"
- 	default y
- 
-+config LANTIQ_MACH_95C3AM1
-+	bool "95C3AM1"
-+	default y
-+
- endmenu
- 
- endif
---- a/arch/mips/lantiq/falcon/Makefile
-+++ b/arch/mips/lantiq/falcon/Makefile
-@@ -4,3 +4,4 @@ obj-$(CONFIG_LANTIQ_MACH_EASY98000) += a
- obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o
- obj-$(CONFIG_LANTIQ_MACH_EASY98000) += dev-leds-easy98000-cpld.o
- obj-$(CONFIG_LANTIQ_MACH_EASY98020) += mach-easy98020.o
-+obj-$(CONFIG_LANTIQ_MACH_95C3AM1)   += mach-95C3AM1.o
---- a/arch/mips/lantiq/machtypes.h
-+++ b/arch/mips/lantiq/machtypes.h
-@@ -21,6 +21,7 @@ enum lantiq_mach_type {
- 	LANTIQ_MACH_EASY98000SF,	/* Falcon Eval Board, Serial Flash */
- 	LANTIQ_MACH_EASY98000NAND,	/* Falcon Eval Board, NAND Flash */
- 	LANTIQ_MACH_EASY98020,		/* Falcon Reference Board */
-+	LANTIQ_MACH_95C3AM1,		/* Board 95C3AM1 */
- };
- 
- #endif
diff --git a/target/linux/lantiq/patches-3.0/180-falcon-linux3.0.patch b/target/linux/lantiq/patches-3.0/180-falcon-linux3.0.patch
deleted file mode 100644
index 3dd79640e7..0000000000
--- a/target/linux/lantiq/patches-3.0/180-falcon-linux3.0.patch
+++ /dev/null
@@ -1,163 +0,0 @@
---- a/arch/mips/lantiq/irq.c
-+++ b/arch/mips/lantiq/irq.c
-@@ -52,6 +52,7 @@
- #define ltq_eiu_w32(x, y)	ltq_w32((x), ltq_eiu_membase + (y))
- #define ltq_eiu_r32(x)		ltq_r32(ltq_eiu_membase + (x))
- 
-+#ifdef CONFIG_SOC_XWAY
- static unsigned short ltq_eiu_irq[MAX_EIU] = {
- 	LTQ_EIU_IR0,
- 	LTQ_EIU_IR1,
-@@ -60,6 +61,7 @@ static unsigned short ltq_eiu_irq[MAX_EI
- 	LTQ_EIU_IR4,
- 	LTQ_EIU_IR5,
- };
-+#endif
- 
- static struct resource ltq_icu_resource = {
- 	.name	= "icu",
-@@ -68,15 +70,19 @@ static struct resource ltq_icu_resource
- 	.flags	= IORESOURCE_MEM,
- };
- 
-+#ifdef CONFIG_SOC_XWAY
- static struct resource ltq_eiu_resource = {
- 	.name	= "eiu",
- 	.start	= LTQ_EIU_BASE_ADDR,
- 	.end	= LTQ_EIU_BASE_ADDR + LTQ_ICU_SIZE - 1,
- 	.flags	= IORESOURCE_MEM,
- };
-+#endif
- 
- static void __iomem *ltq_icu_membase;
-+#ifdef CONFIG_SOC_XWAY
- static void __iomem *ltq_eiu_membase;
-+#endif
- 
- void ltq_disable_irq(struct irq_data *d)
- {
-@@ -122,6 +128,7 @@ void ltq_enable_irq(struct irq_data *d)
- 	ltq_icu_w32(ltq_icu_r32(ier) | (1 << irq_nr), ier);
- }
- 
-+#ifdef CONFIG_SOC_XWAY
- static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
- {
- 	int i;
-@@ -161,6 +168,7 @@ static void ltq_shutdown_eiu_irq(struct
- 		}
- 	}
- }
-+#endif
- 
- static struct irq_chip ltq_irq_type = {
- 	"icu",
-@@ -172,6 +180,7 @@ static struct irq_chip ltq_irq_type = {
- 	.irq_mask_ack = ltq_mask_and_ack_irq,
- };
- 
-+#ifdef CONFIG_SOC_XWAY
- static struct irq_chip ltq_eiu_type = {
- 	"eiu",
- 	.irq_startup = ltq_startup_eiu_irq,
-@@ -183,6 +192,7 @@ static struct irq_chip ltq_eiu_type = {
- 	.irq_mask = ltq_disable_irq,
- 	.irq_mask_ack = ltq_mask_and_ack_irq,
- };
-+#endif
- 
- static void ltq_hw_irqdispatch(int module)
- {
-@@ -198,10 +208,12 @@ static void ltq_hw_irqdispatch(int modul
- 	irq = __fls(irq);
- 	do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
- 
-+#ifdef CONFIG_SOC_XWAY
- 	/* if this is a EBU irq, we need to ack it or get a deadlock */
- 	if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0))
- 		ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
- 			LTQ_EBU_PCC_ISTAT);
-+#endif
- }
- 
- #define DEFINE_HWx_IRQDISPATCH(x)					\
-@@ -264,6 +276,7 @@ void __init arch_init_irq(void)
- 	if (!ltq_icu_membase)
- 		panic("Failed to remap icu memory\n");
- 
-+#ifdef CONFIG_SOC_XWAY
- 	if (insert_resource(&iomem_resource, &ltq_eiu_resource) < 0)
- 		panic("Failed to insert eiu memory\n");
- 
-@@ -275,6 +288,7 @@ void __init arch_init_irq(void)
- 				resource_size(&ltq_eiu_resource));
- 	if (!ltq_eiu_membase)
- 		panic("Failed to remap eiu memory\n");
-+#endif
- 
- 	/* make sure all irqs are turned off by default */
- 	for (i = 0; i < 5; i++)
-@@ -300,6 +314,7 @@ void __init arch_init_irq(void)
- 
- 	for (i = INT_NUM_IRQ0;
- 		i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
-+#ifdef CONFIG_SOC_XWAY
- 		if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) ||
- 			(i == LTQ_EIU_IR2))
- 			irq_set_chip_and_handler(i, &ltq_eiu_type,
-@@ -310,6 +325,7 @@ void __init arch_init_irq(void)
- 			irq_set_chip_and_handler(i, &ltq_eiu_type,
- 				handle_level_irq);
- 		else
-+#endif
- 			irq_set_chip_and_handler(i, &ltq_irq_type,
- 				handle_level_irq);
- 
---- a/arch/mips/lantiq/clk.c
-+++ b/arch/mips/lantiq/clk.c
-@@ -46,6 +46,7 @@ static struct clk cpu_clk_generic[] = {
- 	},
- };
- 
-+#ifdef CONFIG_SOC_XWAY
- static struct resource ltq_cgu_resource = {
- 	.name	= "cgu",
- 	.start	= LTQ_CGU_BASE_ADDR,
-@@ -55,6 +56,7 @@ static struct resource ltq_cgu_resource
- 
- /* remapped clock register range */
- void __iomem *ltq_cgu_membase;
-+#endif
- 
- void clk_init(void)
- {
-@@ -131,6 +133,7 @@ void __init plat_time_init(void)
- {
- 	struct clk *clk;
- 
-+#ifdef CONFIG_SOC_XWAY
- 	if (insert_resource(&iomem_resource, &ltq_cgu_resource) < 0)
- 		panic("Failed to insert cgu memory\n");
- 
-@@ -144,6 +147,7 @@ void __init plat_time_init(void)
- 		pr_err("Failed to remap cgu memory\n");
- 		unreachable();
- 	}
-+#endif
- 	clk = clk_get(0, "cpu");
- 	mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution();
- 	write_c0_compare(read_c0_count());
---- a/arch/mips/lantiq/early_printk.c
-+++ b/arch/mips/lantiq/early_printk.c
-@@ -13,7 +13,11 @@
- #include <lantiq_soc.h>
- 
- /* no ioremap possible at this early stage, lets use KSEG1 instead  */
-+#ifdef CONFIG_SOC_FALCON
-+#define LTQ_ASC_BASE	KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
-+#else
- #define LTQ_ASC_BASE	KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
-+#endif
- #define ASC_BUF		1024
- #define LTQ_ASC_FSTAT	((u32 *)(LTQ_ASC_BASE + 0x0048))
- #define LTQ_ASC_TBUF	((u32 *)(LTQ_ASC_BASE + 0x0020))
diff --git a/target/linux/lantiq/patches-3.0/190-falcon-fix_include.patch b/target/linux/lantiq/patches-3.0/190-falcon-fix_include.patch
deleted file mode 100644
index 371a94bb5c..0000000000
--- a/target/linux/lantiq/patches-3.0/190-falcon-fix_include.patch
+++ /dev/null
@@ -1,48 +0,0 @@
---- /dev/null
-+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
-@@ -0,0 +1,45 @@
-+/*
-+ *  This program is free software; you can redistribute it and/or modify it
-+ *  under the terms of the GNU General Public License version 2 as published
-+ *  by the Free Software Foundation.
-+ *
-+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#ifndef _LTQ_FALCON_H__
-+#define _LTQ_FALCON_H__
-+
-+#ifdef CONFIG_SOC_FALCON
-+
-+#include <lantiq.h>
-+
-+/* Chip IDs */
-+#define SOC_ID_FALCON		0x01B8
-+
-+/* SoC Types */
-+#define SOC_TYPE_FALCON		0x01
-+
-+/* ASC0/1 - serial port */
-+#define LTQ_ASC0_BASE_ADDR	0x1E100C00
-+#define LTQ_ASC1_BASE_ADDR	0x1E100B00
-+#define LTQ_ASC_SIZE		0x100
-+
-+#define LTQ_ASC_TIR(x)          (INT_NUM_IM3_IRL0 + (x * 8))
-+#define LTQ_ASC_RIR(x)          (INT_NUM_IM3_IRL0 + (x * 8) + 1)
-+#define LTQ_ASC_EIR(x)          (INT_NUM_IM3_IRL0 + (x * 8) + 2)
-+
-+/* ICU - interrupt control unit */
-+#define LTQ_ICU_BASE_ADDR	0x1F880200
-+#define LTQ_ICU_SIZE		0x100
-+
-+/* WDT */
-+#define LTQ_WDT_BASE_ADDR	0x1F8803F0
-+#define LTQ_WDT_SIZE		0x10
-+
-+extern int ltq_gpio_request(unsigned int pin, unsigned int alt0,
-+                          unsigned int alt1, unsigned int dir,
-+                          const char *name);
-+extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux);
-+
-+#endif /* CONFIG_SOC_FALCON */
-+#endif /* _LTQ_XWAY_H__ */
diff --git a/target/linux/lantiq/patches-3.0/200-netif_receive_skb.patch b/target/linux/lantiq/patches-3.0/200-owrt-netif_receive_skb.patch
index 120266c999..120266c999 100644
--- a/target/linux/lantiq/patches-3.0/200-netif_receive_skb.patch
+++ b/target/linux/lantiq/patches-3.0/200-owrt-netif_receive_skb.patch
diff --git a/target/linux/lantiq/patches-3.0/210-mtd_uimage_split.patch b/target/linux/lantiq/patches-3.0/201-owrt-mtd_uimage_split.patch
index 6c6a45ac04..6c6a45ac04 100644
--- a/target/linux/lantiq/patches-3.0/210-mtd_uimage_split.patch
+++ b/target/linux/lantiq/patches-3.0/201-owrt-mtd_uimage_split.patch
diff --git a/target/linux/lantiq/patches-3.0/220-atm_hack.patch b/target/linux/lantiq/patches-3.0/202-owrt-atm.patch
index 7552b1d0cf..3f400f550d 100644
--- a/target/linux/lantiq/patches-3.0/220-atm_hack.patch
+++ b/target/linux/lantiq/patches-3.0/202-owrt-atm.patch
@@ -1,3 +1,23 @@
+Index: linux-3.0.3/arch/mips/lantiq/irq.c
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/irq.c	2011-09-29 20:43:07.000000000 +0200
++++ linux-3.0.3/arch/mips/lantiq/irq.c	2011-09-29 20:45:14.785132132 +0200
+@@ -9,6 +9,7 @@
+ 
+ #include <linux/interrupt.h>
+ #include <linux/ioport.h>
++#include <linux/module.h>
+ 
+ #include <asm/bootinfo.h>
+ #include <asm/irq_cpu.h>
+@@ -102,6 +103,7 @@
+ 	ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier);
+ 	ltq_icu_w32((1 << irq_nr), isr);
+ }
++EXPORT_SYMBOL(ltq_mask_and_ack_irq);
+ 
+ static void ltq_ack_irq(struct irq_data *d)
+ {
 --- a/arch/mips/mm/cache.c
 +++ b/arch/mips/mm/cache.c
 @@ -52,6 +52,8 @@ void (*_dma_cache_wback)(unsigned long s
diff --git a/target/linux/lantiq/patches-3.0/230-cmdline_hack.patch b/target/linux/lantiq/patches-3.0/203-owrt-cmdline.patch
index 8ce57ba0aa..c5f72d2f93 100644
--- a/target/linux/lantiq/patches-3.0/230-cmdline_hack.patch
+++ b/target/linux/lantiq/patches-3.0/203-owrt-cmdline.patch
@@ -1,6 +1,8 @@
---- a/arch/mips/lantiq/prom.c
-+++ b/arch/mips/lantiq/prom.c
-@@ -39,6 +39,34 @@ void prom_free_prom_memory(void)
+Index: linux-3.0.3/arch/mips/lantiq/prom.c
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/prom.c	2011-10-02 15:49:12.000000000 +0200
++++ linux-3.0.3/arch/mips/lantiq/prom.c	2011-10-02 15:50:34.614270672 +0200
+@@ -43,6 +43,34 @@
  {
  }
  
@@ -35,11 +37,11 @@
  static void __init prom_init_cmdline(void)
  {
  	int argc = fw_arg0;
-@@ -55,6 +83,7 @@ static void __init prom_init_cmdline(voi
+@@ -59,6 +87,7 @@
  			strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
  		}
  	}
 +	prom_init_image_cmdline();
  }
  
- void __init prom_init(void)
+ void __iomem *ltq_remap_resource(struct resource *res)
diff --git a/target/linux/lantiq/patches-3.0/170-falcon-dm9000-polling.patch b/target/linux/lantiq/patches-3.0/204-owrt-dm9000-polling.patch
index 64313c5968..64313c5968 100644
--- a/target/linux/lantiq/patches-3.0/170-falcon-dm9000-polling.patch
+++ b/target/linux/lantiq/patches-3.0/204-owrt-dm9000-polling.patch
diff --git a/target/linux/lantiq/patches-3.0/205-owrt-gpio-export.patch b/target/linux/lantiq/patches-3.0/205-owrt-gpio-export.patch
new file mode 100644
index 0000000000..61693c2383
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/205-owrt-gpio-export.patch
@@ -0,0 +1,54 @@
+Index: linux-3.0.3/drivers/gpio/gpiolib.c
+===================================================================
+--- linux-3.0.3.orig/drivers/gpio/gpiolib.c	2011-10-03 00:13:35.359561120 +0200
++++ linux-3.0.3/drivers/gpio/gpiolib.c	2011-10-03 09:52:55.785047081 +0200
+@@ -64,9 +64,9 @@
+ #define GPIO_FLAGS_MASK		((1 << ID_SHIFT) - 1)
+ #define GPIO_TRIGGER_MASK	(BIT(FLAG_TRIG_FALL) | BIT(FLAG_TRIG_RISE))
+ 
+-#ifdef CONFIG_DEBUG_FS
++//#ifdef CONFIG_DEBUG_FS
+ 	const char		*label;
+-#endif
++//#endif
+ };
+ static struct gpio_desc gpio_desc[ARCH_NR_GPIOS];
+ 
+@@ -76,9 +76,9 @@
+ 
+ static inline void desc_set_label(struct gpio_desc *d, const char *label)
+ {
+-#ifdef CONFIG_DEBUG_FS
++//#ifdef CONFIG_DEBUG_FS
+ 	d->label = label;
+-#endif
++//#endif
+ }
+ 
+ /* Warn when drivers omit gpio_request() calls -- legal but ill-advised
+@@ -727,7 +727,8 @@
+ 
+ 	if (desc->chip->names && desc->chip->names[gpio - desc->chip->base])
+ 		ioname = desc->chip->names[gpio - desc->chip->base];
+-
++	else
++		ioname = gpio_desc[gpio].label;
+ 	if (status == 0) {
+ 		struct device	*dev;
+ 
+@@ -1347,11 +1348,11 @@
+ 		return NULL;
+ 	if (test_bit(FLAG_REQUESTED, &gpio_desc[gpio].flags) == 0)
+ 		return NULL;
+-#ifdef CONFIG_DEBUG_FS
++//#ifdef CONFIG_DEBUG_FS
+ 	return gpio_desc[gpio].label;
+-#else
+-	return "?";
+-#endif
++//#else
++//	return "?";
++//#endif
+ }
+ EXPORT_SYMBOL_GPL(gpiochip_is_requested);
+ 
diff --git a/target/linux/lantiq/patches-3.0/210-machtypes.patch b/target/linux/lantiq/patches-3.0/210-machtypes.patch
new file mode 100644
index 0000000000..bf998e4c75
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/210-machtypes.patch
@@ -0,0 +1,325 @@
+Index: linux-3.0.3/arch/mips/lantiq/machtypes.h
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/machtypes.h	2011-10-05 14:32:23.173150836 +0200
++++ linux-3.0.3/arch/mips/lantiq/machtypes.h	2011-10-05 14:32:23.385150846 +0200
+@@ -20,9 +20,33 @@
+ 	LANTIQ_MACH_EASY98000,		/* Falcon Eval Board, NOR Flash */
+ 	LANTIQ_MACH_EASY98000SF,	/* Falcon Eval Board, Serial Flash */
+ 	LANTIQ_MACH_EASY98000NAND,	/* Falcon Eval Board, NAND Flash */
++	LANTIQ_MACH_EASY98020,		/* EASY98020 Eval Board */
++	LANTIQ_MACH_EASY98020_1LAN,	/* EASY98020 Eval Board (1 LAN port) */
++	LANTIQ_MACH_EASY98020_2LAN,	/* EASY98020 Eval Board (2 LAN port) */
++	LANTIQ_MACH_95C3AM1,		/* 95C3AM1 Eval Board */
+ 
+ 	/* FRITZ!BOX */
+ 	LANTIQ_MACH_FRITZ3370,		/* FRITZ!BOX 3370 vdsl cpe */
++
++	/* Arcadyan */
++	LANTIQ_MACH_ARV3527P,		/* Arcor easybox a401 */
++	LANTIQ_MACH_ARV4510PW,		/* Wippies Homebox */
++	LANTIQ_MACH_ARV4518PW,		/* Airties WAV-221, SMC-7908A-ISP */
++	LANTIQ_MACH_ARV4520PW,		/* Airties WAV-281, Arcor EasyboxA800 */
++	LANTIQ_MACH_ARV452CPW,		/* Arcor EasyboxA801 */
++	LANTIQ_MACH_ARV4525PW,		/* Speedport W502V */
++	LANTIQ_MACH_ARV752DPW,		/* Arcor easybox a802 */
++	LANTIQ_MACH_ARV752DPW22,	/* Arcor easybox a803 */
++	LANTIQ_MACH_ARV7518PW,		/* ASTORIA */
++
++	/* Netgear */
++	LANTIQ_MACH_DGN3500B,		/* Netgear DGN3500 */
++
++	/* Gigaset */
++	LANTIQ_MACH_GIGASX76X,		/* Gigaset SX76x */
++
++	/* Buffalo */
++	LANTIQ_MACH_WBMR,		/* WBMR-HP-G300H */
+ };
+ 
+ #endif
+Index: linux-3.0.3/arch/mips/lantiq/xway/Kconfig
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/xway/Kconfig	2011-10-05 14:32:23.173150836 +0200
++++ linux-3.0.3/arch/mips/lantiq/xway/Kconfig	2011-10-05 14:32:23.385150846 +0200
+@@ -6,6 +6,22 @@
+ 	bool "Easy50712 - Danube"
+ 	default y
+ 
++config LANTIQ_MACH_ARV45XX
++	bool "ARV45XX"
++	default y
++
++config LANTIQ_MACH_NETGEAR
++	bool "Netgear"
++	default y
++
++config LANTIQ_MACH_GIGASX76X
++	bool "GIGASX76X"
++	default y
++
++config LANTIQ_MACH_WBMR
++	bool "WBMR-HP-G300H"
++	default y
++
+ endmenu
+ 
+ endif
+Index: linux-3.0.3/arch/mips/lantiq/xway/Makefile
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/xway/Makefile	2011-10-05 14:32:23.173150836 +0200
++++ linux-3.0.3/arch/mips/lantiq/xway/Makefile	2011-10-05 15:46:10.061340080 +0200
+@@ -7,3 +7,7 @@
+ obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
+ obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
+ obj-$(CONFIG_LANTIQ_MACH_FRITZ3370) += mach-fritz.o
++obj-$(CONFIG_LANTIQ_MACH_ARV45XX) += mach-arv45xx.o
++obj-$(CONFIG_LANTIQ_MACH_NETGEAR) += mach-netgear.o
++obj-$(CONFIG_LANTIQ_MACH_GIGASX76X) += mach-gigasx76x.o
++obj-$(CONFIG_LANTIQ_MACH_WBMR) += mach-wbmr.o
+Index: linux-3.0.3/arch/mips/lantiq/falcon/Kconfig
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/falcon/Kconfig	2011-10-05 14:32:22.745150818 +0200
++++ linux-3.0.3/arch/mips/lantiq/falcon/Kconfig	2011-10-05 14:32:23.385150846 +0200
+@@ -6,6 +6,14 @@
+ 	bool "Easy98000"
+ 	default y
+ 
++config LANTIQ_MACH_EASY98020
++	bool "Easy98020"
++	default y
++
++config LANTIQ_MACH_95C3AM1
++	bool "95C3AM1"
++	default y
++
+ endmenu
+ 
+ endif
+Index: linux-3.0.3/arch/mips/lantiq/falcon/Makefile
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/falcon/Makefile	2011-10-05 14:32:23.089150832 +0200
++++ linux-3.0.3/arch/mips/lantiq/falcon/Makefile	2011-10-05 14:32:23.389150846 +0200
+@@ -1,2 +1,6 @@
+ obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o softdog_vpe.o
++obj-$(CONFIG_LANTIQ_MACH_EASY98000) += addon-easy98000.o
++obj-$(CONFIG_LANTIQ_MACH_EASY98000) += dev-leds-easy98000-cpld.o
+ obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o
++obj-$(CONFIG_LANTIQ_MACH_EASY98020) += mach-easy98020.o
++obj-$(CONFIG_LANTIQ_MACH_95C3AM1)   += mach-95C3AM1.o
+Index: linux-3.0.3/arch/mips/lantiq/falcon/mach-easy98000.c
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/falcon/mach-easy98000.c	2011-10-05 15:17:45.445267210 +0200
++++ linux-3.0.3/arch/mips/lantiq/falcon/mach-easy98000.c	2011-10-05 15:45:54.153339399 +0200
+@@ -1,23 +1,38 @@
+-/*
+- *  This program is free software; you can redistribute it and/or modify it
+- *  under the terms of the GNU General Public License version 2 as published
+- *  by the Free Software Foundation.
+- *
+- *  Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
+- *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+- */
+-
++#include <linux/init.h>
+ #include <linux/platform_device.h>
++#include <linux/leds.h>
++#include <linux/gpio.h>
++#include <linux/gpio_buttons.h>
++#include <linux/etherdevice.h>
++#include <linux/mtd/mtd.h>
+ #include <linux/mtd/partitions.h>
++#include <linux/mtd/physmap.h>
++#include <linux/input.h>
++#include <linux/interrupt.h>
++#include <linux/dm9000.h>
++#include <linux/i2c.h>
++#include <linux/i2c-gpio.h>
+ #include <linux/spi/spi.h>
+ #include <linux/spi/spi_gpio.h>
+ #include <linux/spi/eeprom.h>
++#include <falcon/lantiq_soc.h>
+ 
+ #include "../machtypes.h"
+ 
+ #include "devices.h"
++#include "dev-leds-gpio.h"
++
++#define EASY98000_GPIO_LED_0 9
++#define EASY98000_GPIO_LED_1 10
++#define EASY98000_GPIO_LED_2 11
++#define EASY98000_GPIO_LED_3 12
++#define EASY98000_GPIO_LED_4 13
++#define EASY98000_GPIO_LED_5 14
++
++extern unsigned char ltq_ethaddr[6];
+ 
+-static struct mtd_partition easy98000_nor_partitions[] = {
++static struct mtd_partition easy98000_nor_partitions[] =
++{
+ 	{
+ 		.name	= "uboot",
+ 		.offset	= 0x0,
+@@ -35,7 +50,7 @@
+ 	},
+ };
+ 
+-struct physmap_flash_data easy98000_nor_flash_data = {
++static struct physmap_flash_data easy98000_nor_flash_data = {
+ 	.nr_parts	= ARRAY_SIZE(easy98000_nor_partitions),
+ 	.parts		= easy98000_nor_partitions,
+ };
+@@ -55,12 +70,105 @@
+ 	.platform_data		= &easy98000_spi_flash_platform_data
+ };
+ 
++static struct gpio_led easy98000_leds_gpio[] __initdata = {
++	{
++		.name		= "easy98000:green:0",
++		.gpio		= EASY98000_GPIO_LED_0,
++		.active_low	= 0,
++	}, {
++		.name		= "easy98000:green:1",
++		.gpio		= EASY98000_GPIO_LED_1,
++		.active_low	= 0,
++	}, {
++		.name		= "easy98000:green:2",
++		.gpio		= EASY98000_GPIO_LED_2,
++		.active_low	= 0,
++	}, {
++		.name		= "easy98000:green:3",
++		.gpio		= EASY98000_GPIO_LED_3,
++		.active_low	= 0,
++	}, {
++		.name		= "easy98000:green:4",
++		.gpio		= EASY98000_GPIO_LED_4,
++		.active_low	= 0,
++	}, {
++		.name		= "easy98000:green:5",
++		.gpio		= EASY98000_GPIO_LED_5,
++		.active_low	= 0,
++	}
++};
++
++#define CONFIG_DM9000_BASE		0x14000000
++#define DM9000_IO			(CONFIG_DM9000_BASE + 3)
++#define DM9000_DATA			(CONFIG_DM9000_BASE + 1)
++
++static struct dm9000_plat_data dm9000_plat_data = {
++	.flags = DM9000_PLATF_8BITONLY,
++	//.dev_addr = { }, /* possibility to provide an ethernet address for the chip */
++};
++
++static struct resource dm9000_resources[] = {
++	MEM_RES("dm9000_io", DM9000_IO, DM9000_IO),
++	MEM_RES("dm9000_data", DM9000_DATA, DM9000_DATA),
++	[2] = {
++		/* with irq (210 -> gpio 110) the driver is very unreliable */
++		.start	= -1,		/* use polling */
++		.end	= -1,
++		.flags	= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
++	},
++};
++
++static struct platform_device dm9000_platform = {
++	.name = "dm9000",
++	.id = 0,
++	.num_resources	= ARRAY_SIZE(dm9000_resources),
++	.resource	= dm9000_resources,
++	.dev = {
++		.platform_data = (void *) &dm9000_plat_data,
++	}
++};
++
++extern int easy98000_addon_has_dm9000(void);
++static void __init register_davicom(void)
++{
++	if (!easy98000_addon_has_dm9000())
++		return;
++
++	if (!is_valid_ether_addr(ltq_ethaddr))
++		random_ether_addr(dm9000_plat_data.dev_addr);
++	else {
++		memcpy(dm9000_plat_data.dev_addr, ltq_ethaddr, 6);
++		/* change to "Locally Administered Address" */
++		dm9000_plat_data.dev_addr[0] |= 0x2;
++	}
++	platform_device_register(&dm9000_platform);
++}
++
++static struct i2c_gpio_platform_data easy98000_i2c_gpio_data = {
++	.sda_pin	= 107,
++	.scl_pin	= 108,
++};
++
++static struct platform_device easy98000_i2c_gpio_device = {
++	.name		= "i2c-gpio",
++	.id		= 0,
++	.dev = {
++		.platform_data	= &easy98000_i2c_gpio_data,
++	}
++};
++
++void __init register_easy98000_cpld(void)
++{
++	platform_device_register_simple("easy98000_cpld_led", 0, NULL, 0);
++	platform_device_register_simple("easy98000_addon", 0, NULL, 0);
++}
++
+ /* setup gpio based spi bus/device for access to the eeprom on the board */
+-#define SPI_GPIO_MRST		102
+-#define SPI_GPIO_MTSR		103
+-#define SPI_GPIO_CLK		104
+-#define SPI_GPIO_CS0		105
+-#define SPI_GPIO_CS1		106
++#define SPI_GPIO_MRST	102
++#define SPI_GPIO_MTSR	103
++#define SPI_GPIO_CLK	104
++#define SPI_GPIO_CS0	105
++#define SPI_GPIO_CS1	106
+ #define SPI_GPIO_BUS_NUM	1
+ 
+ static struct spi_gpio_platform_data easy98000_spi_gpio_data = {
+@@ -93,29 +201,36 @@
+ 	.platform_data		= &at25160n,
+ };
+ 
+-static void __init
+-easy98000_init_common(void)
++static void __init easy98000_spi_gpio_init(void)
+ {
+ 	spi_register_board_info(&easy98000_spi_gpio_devices, 1);
+ 	platform_device_register(&easy98000_spi_gpio_device);
+ }
+ 
+-static void __init
+-easy98000_init(void)
++static void __init easy98000_init_common(void)
++{
++	falcon_register_i2c();
++	platform_device_register(&easy98000_i2c_gpio_device);
++	register_davicom();
++	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(easy98000_leds_gpio),
++					easy98000_leds_gpio);
++	register_easy98000_cpld();
++	easy98000_spi_gpio_init();
++}
++
++static void __init easy98000_init(void)
+ {
+ 	easy98000_init_common();
+ 	ltq_register_nor(&easy98000_nor_flash_data);
+ }
+ 
+-static void __init
+-easy98000sf_init(void)
++static void __init easy98000sf_init(void)
+ {
+ 	easy98000_init_common();
+ 	falcon_register_spi_flash(&easy98000_spi_flash_data);
+ }
+ 
+-static void __init
+-easy98000nand_init(void)
++static void __init easy98000nand_init(void)
+ {
+ 	easy98000_init_common();
+ 	falcon_register_nand();
diff --git a/target/linux/lantiq/patches-3.0/211-devices.patch b/target/linux/lantiq/patches-3.0/211-devices.patch
new file mode 100644
index 0000000000..a45dfab805
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/211-devices.patch
@@ -0,0 +1,198 @@
+Index: linux-3.0.3/arch/mips/lantiq/devices.c
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/devices.c	2011-10-04 20:03:54.000000000 +0200
++++ linux-3.0.3/arch/mips/lantiq/devices.c	2011-10-04 20:07:28.514316826 +0200
+@@ -20,6 +20,7 @@
+ #include <linux/io.h>
+ #include <linux/gpio.h>
+ #include <linux/leds.h>
++#include <linux/dma-mapping.h>
+ 
+ #include <asm/bootinfo.h>
+ #include <asm/irq.h>
+@@ -102,3 +103,20 @@
+ 	pr_err("kernel is compiled without PCI support\n");
+ }
+ #endif
++
++static unsigned int *cp1_base = 0;
++unsigned int*
++ltq_get_cp1_base(void)
++{
++	return cp1_base;
++}
++EXPORT_SYMBOL(ltq_get_cp1_base);
++
++void __init
++ltq_register_tapi(void)
++{
++#define CP1_SIZE       (1 << 20)
++	dma_addr_t dma;
++	cp1_base =
++		(void*)CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE, &dma, GFP_ATOMIC));
++}
+Index: linux-3.0.3/arch/mips/lantiq/devices.h
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/devices.h	2011-10-04 20:03:54.000000000 +0200
++++ linux-3.0.3/arch/mips/lantiq/devices.h	2011-10-04 20:07:13.362316180 +0200
+@@ -23,5 +23,6 @@
+ extern void ltq_register_wdt(void);
+ extern void ltq_register_asc(int port);
+ extern void ltq_register_pci(struct ltq_pci_data *data);
++extern void ltq_register_tapi(void);
+ 
+ #endif
+Index: linux-3.0.3/arch/mips/lantiq/xway/Makefile
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/xway/Makefile	2011-10-04 20:07:01.000000000 +0200
++++ linux-3.0.3/arch/mips/lantiq/xway/Makefile	2011-10-04 20:07:13.362316180 +0200
+@@ -1,5 +1,7 @@
+ obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o nand.o timer.o
+ 
++obj-y += dev-dwc_otg.o
++
+ obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o
+ obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o
+ obj-$(CONFIG_SOC_VR9) += clk-vr9.o prom-vr9.o
+Index: linux-3.0.3/arch/mips/lantiq/xway/devices.c
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/xway/devices.c	2011-10-04 20:05:44.000000000 +0200
++++ linux-3.0.3/arch/mips/lantiq/xway/devices.c	2011-10-04 20:07:44.070317494 +0200
+@@ -21,6 +21,7 @@
+ #include <linux/io.h>
+ #include <linux/gpio.h>
+ #include <linux/leds.h>
++#include <linux/spi/spi.h>
+ 
+ #include <asm/bootinfo.h>
+ #include <asm/irq.h>
+@@ -101,3 +102,94 @@
+ 		platform_device_register(&ltq_etop);
+ 	}
+ }
++
++/* madwifi */
++int lantiq_emulate_madwifi_eep = 0;
++EXPORT_SYMBOL(lantiq_emulate_madwifi_eep);
++
++void __init
++ltq_register_madwifi_eep(void)
++{
++	lantiq_emulate_madwifi_eep = 1;
++}
++
++/* ebu */
++static struct resource ltq_ebu_resource =
++{
++	.name   = "gpio_ebu",
++	.start  = LTQ_EBU_GPIO_START,
++	.end    = LTQ_EBU_GPIO_START + LTQ_EBU_GPIO_SIZE - 1,
++	.flags  = IORESOURCE_MEM,
++};
++
++static struct platform_device ltq_ebu =
++{
++	.name           = "ltq_ebu",
++	.resource       = &ltq_ebu_resource,
++	.num_resources  = 1,
++};
++
++void __init
++ltq_register_gpio_ebu(unsigned int value)
++{
++	ltq_ebu.dev.platform_data = (void*) value;
++	platform_device_register(&ltq_ebu);
++}
++
++/* gpio buttons */
++static struct gpio_buttons_platform_data ltq_gpio_buttons_platform_data;
++
++static struct platform_device ltq_gpio_buttons_platform_device =
++{
++	.name = "gpio-buttons",
++	.id = 0,
++	.dev = {
++		.platform_data = (void *) &ltq_gpio_buttons_platform_data,
++	},
++};
++
++void __init
++ltq_register_gpio_buttons(struct gpio_button *buttons, int cnt)
++{
++	ltq_gpio_buttons_platform_data.buttons = buttons;
++	ltq_gpio_buttons_platform_data.nbuttons = cnt;
++	platform_device_register(&ltq_gpio_buttons_platform_device);
++}
++
++static struct resource ltq_spi_resources[] = {
++	{
++		.start  = LTQ_SSC_BASE_ADDR,
++		.end    = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1,
++		.flags  = IORESOURCE_MEM,
++	},
++	IRQ_RES(spi_tx, LTQ_SSC_TIR),
++	IRQ_RES(spi_rx, LTQ_SSC_RIR),
++	IRQ_RES(spi_err, LTQ_SSC_EIR),
++};
++
++static struct resource ltq_spi_resources_ar9[] = {
++	{
++		.start  = LTQ_SSC_BASE_ADDR,
++		.end    = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1,
++		.flags  = IORESOURCE_MEM,
++	},
++	IRQ_RES(spi_tx, LTQ_SSC_TIR_AR9),
++	IRQ_RES(spi_rx, LTQ_SSC_RIR_AR9),
++	IRQ_RES(spi_err, LTQ_SSC_EIR),
++};
++
++static struct platform_device ltq_spi = {
++	.name		= "ltq-spi",
++	.resource	= ltq_spi_resources,
++	.num_resources	= ARRAY_SIZE(ltq_spi_resources),
++};
++
++void __init ltq_register_spi(struct ltq_spi_platform_data *pdata,
++		struct spi_board_info const *info, unsigned n)
++{
++	if(ltq_is_ar9())
++		ltq_spi.resource = ltq_spi_resources_ar9;
++	spi_register_board_info(info, n);
++	ltq_spi.dev.platform_data = pdata;
++	platform_device_register(&ltq_spi);
++}
+Index: linux-3.0.3/arch/mips/lantiq/xway/devices.h
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/xway/devices.h	2011-08-17 19:57:16.000000000 +0200
++++ linux-3.0.3/arch/mips/lantiq/xway/devices.h	2011-10-04 20:07:13.366316178 +0200
+@@ -11,10 +11,17 @@
+ 
+ #include "../devices.h"
+ #include <linux/phy.h>
++#include <linux/spi/spi.h>
++#include <linux/gpio_buttons.h>
+ 
+ extern void ltq_register_gpio(void);
+ extern void ltq_register_gpio_stp(void);
+ extern void ltq_register_ase_asc(void);
+ extern void ltq_register_etop(struct ltq_eth_data *eth);
++extern void ltq_register_gpio_ebu(unsigned int value);
++extern void ltq_register_spi(struct ltq_spi_platform_data *pdata,
++	struct spi_board_info const *info, unsigned n);
++extern void ltq_register_madwifi_eep(void);
++extern void ltq_register_gpio_buttons(struct gpio_button *buttons, int cnt);
+ 
+ #endif
+Index: linux-3.0.3/arch/mips/lantiq/Makefile
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/Makefile	2011-10-04 20:03:54.000000000 +0200
++++ linux-3.0.3/arch/mips/lantiq/Makefile	2011-10-04 20:08:10.406318621 +0200
+@@ -4,7 +4,7 @@
+ # under the terms of the GNU General Public License version 2 as published
+ # by the Free Software Foundation.
+ 
+-obj-y := irq.o setup.o clk.o prom.o devices.o
++obj-y := irq.o setup.o clk.o prom.o devices.o dev-leds-gpio.o dev-gpio-buttons.o
+ 
+ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+ 
diff --git a/target/linux/lantiq/patches-3.0/400-spi1.patch b/target/linux/lantiq/patches-3.0/400-spi1.patch
deleted file mode 100644
index c3c9330219..0000000000
--- a/target/linux/lantiq/patches-3.0/400-spi1.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
-Date: Thu, 3 Mar 2011 17:15:58 +0000 (+0100)
-Subject: MIPS: lantiq: Add platform data for Lantiq SoC SPI controller driver
-X-Git-Url: http://nbd.name/gitweb.cgi?p=lantiq.git;a=commitdiff_plain;h=3d21b04682ae8eb1c1965aba39d1796e8c5ad84b;hp=06b420500fe98e37662837e78d8e51aead8aea81
-
-MIPS: lantiq: Add platform data for Lantiq SoC SPI controller driver
-
-Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
----
-
---- a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
-+++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
-@@ -50,4 +50,13 @@ struct ltq_eth_data {
- 	int mii_mode;
- };
- 
-+
-+struct ltq_spi_platform_data {
-+	u16 num_chipselect;
-+};
-+
-+struct ltq_spi_controller_data {
-+	unsigned gpio;
-+};
-+
- #endif
---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
-+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
-@@ -75,6 +75,7 @@
- 
- #define PMU_DMA			0x0020
- #define PMU_USB			0x8041
-+#define PMU_SPI			0x0100
- #define PMU_LED			0x0800
- #define PMU_GPT			0x1000
- #define PMU_PPE			0x2000
diff --git a/target/linux/lantiq/patches-3.0/420-spi3.patch b/target/linux/lantiq/patches-3.0/420-spi3.patch
deleted file mode 100644
index f4bc661a18..0000000000
--- a/target/linux/lantiq/patches-3.0/420-spi3.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
-Date: Thu, 3 Mar 2011 20:42:26 +0000 (+0100)
-Subject: MIPS: lantiq: Add device register helper for SPI controller and devices
-X-Git-Url: http://nbd.name/gitweb.cgi?p=lantiq.git;a=commitdiff_plain;h=b35b07062b718ece9b9cb7b23b12d83a087eafb0;hp=653c95b8b9066c9c6ac08bd64d0ceee439e9fd90
-
-MIPS: lantiq: Add device register helper for SPI controller and devices
-
-Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
----
-
---- a/arch/mips/lantiq/xway/devices.h
-+++ b/arch/mips/lantiq/xway/devices.h
-@@ -11,10 +11,13 @@
- 
- #include "../devices.h"
- #include <linux/phy.h>
-+#include <linux/spi/spi.h>
- 
- extern void ltq_register_gpio(void);
- extern void ltq_register_gpio_stp(void);
- extern void ltq_register_ase_asc(void);
- extern void ltq_register_etop(struct ltq_eth_data *eth);
-+extern void ltq_register_spi(struct ltq_spi_platform_data *pdata,
-+	struct spi_board_info const *info, unsigned n);
- 
- #endif
---- a/arch/mips/lantiq/xway/devices.c
-+++ b/arch/mips/lantiq/xway/devices.c
-@@ -21,6 +21,7 @@
- #include <linux/io.h>
- #include <linux/gpio.h>
- #include <linux/leds.h>
-+#include <linux/spi/spi.h>
- 
- #include <asm/bootinfo.h>
- #include <asm/irq.h>
-@@ -119,3 +120,41 @@ ltq_register_etop(struct ltq_eth_data *e
- 		platform_device_register(&ltq_etop);
- 	}
- }
-+
-+static struct resource ltq_spi_resources[] = {
-+	{
-+		.start  = LTQ_SSC_BASE_ADDR,
-+		.end    = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1,
-+		.flags  = IORESOURCE_MEM,
-+	},
-+	IRQ_RES(spi_tx, LTQ_SSC_TIR),
-+	IRQ_RES(spi_rx, LTQ_SSC_RIR),
-+	IRQ_RES(spi_err, LTQ_SSC_EIR),
-+};
-+
-+static struct resource ltq_spi_resources_ar9[] = {
-+	{
-+		.start  = LTQ_SSC_BASE_ADDR,
-+		.end    = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1,
-+		.flags  = IORESOURCE_MEM,
-+	},
-+	IRQ_RES(spi_tx, LTQ_SSC_TIR_AR9),
-+	IRQ_RES(spi_rx, LTQ_SSC_RIR_AR9),
-+	IRQ_RES(spi_err, LTQ_SSC_EIR),
-+};
-+
-+static struct platform_device ltq_spi = {
-+	.name		= "ltq-spi",
-+	.resource	= ltq_spi_resources,
-+	.num_resources	= ARRAY_SIZE(ltq_spi_resources),
-+};
-+
-+void __init ltq_register_spi(struct ltq_spi_platform_data *pdata,
-+		struct spi_board_info const *info, unsigned n)
-+{
-+	if(ltq_is_ar9())
-+		ltq_spi.resource = ltq_spi_resources_ar9;
-+	spi_register_board_info(info, n);
-+	ltq_spi.dev.platform_data = pdata;
-+	platform_device_register(&ltq_spi);
-+}
---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
-+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
-@@ -27,6 +27,8 @@
- 
- #define LTQ_SSC_TIR		(INT_NUM_IM0_IRL0 + 15)
- #define LTQ_SSC_RIR		(INT_NUM_IM0_IRL0 + 14)
-+#define LTQ_SSC_TIR_AR9		(INT_NUM_IM0_IRL0 + 14)
-+#define LTQ_SSC_RIR_AR9		(INT_NUM_IM0_IRL0 + 15)
- #define LTQ_SSC_EIR		(INT_NUM_IM0_IRL0 + 16)
- 
- #define LTQ_MEI_DYING_GASP_INT	(INT_NUM_IM1_IRL0 + 21)
diff --git a/target/linux/lantiq/patches-3.0/450-mach-arv45xx.patch b/target/linux/lantiq/patches-3.0/450-mach-arv45xx.patch
deleted file mode 100644
index a05d1a519c..0000000000
--- a/target/linux/lantiq/patches-3.0/450-mach-arv45xx.patch
+++ /dev/null
@@ -1,538 +0,0 @@
---- a/arch/mips/lantiq/xway/Kconfig
-+++ b/arch/mips/lantiq/xway/Kconfig
-@@ -6,6 +6,10 @@ config LANTIQ_MACH_EASY50712
- 	bool "Easy50712 - Danube"
- 	default y
- 
-+config LANTIQ_MACH_ARV45XX
-+	bool "ARV45XX"
-+	default y
-+
- endmenu
- 
- endif
---- a/arch/mips/lantiq/xway/Makefile
-+++ b/arch/mips/lantiq/xway/Makefile
-@@ -5,3 +5,4 @@ obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o
- 
- obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
- obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
-+obj-$(CONFIG_LANTIQ_MACH_ARV45XX) += mach-arv45xx.o
---- /dev/null
-+++ b/arch/mips/lantiq/xway/mach-arv45xx.c
-@@ -0,0 +1,495 @@
-+/*
-+ *  This program is free software; you can redistribute it and/or modify it
-+ *  under the terms of the GNU General Public License version 2 as published
-+ *  by the Free Software Foundation.
-+ *
-+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/leds.h>
-+#include <linux/gpio.h>
-+#include <linux/gpio_buttons.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/mtd/physmap.h>
-+#include <linux/input.h>
-+#include <linux/etherdevice.h>
-+#include <linux/ath5k_platform.h>
-+#include <linux/pci.h>
-+
-+#include <lantiq_soc.h>
-+#include <lantiq_platform.h>
-+
-+#include "../machtypes.h"
-+#include "devices.h"
-+#include "dev-leds-gpio.h"
-+#include "dev-dwc_otg.h"
-+
-+static struct mtd_partition arv4510_partitions[] =
-+{
-+	{
-+		.name	= "uboot",
-+		.offset	= 0x0,
-+		.size	= 0x20000,
-+	},
-+	{
-+		.name	= "uboot_env",
-+		.offset	= 0x20000,
-+		.size	= 0x120000,
-+	},
-+	{
-+		.name	= "linux",
-+		.offset	= 0x40000,
-+		.size	= 0xfa0000,
-+	},
-+	{
-+		.name	= "board_config",
-+		.offset	= 0xfe0000,
-+		.size	= 0x20000,
-+	},
-+};
-+
-+static struct mtd_partition arv45xx_partitions[] =
-+{
-+	{
-+		.name	= "uboot",
-+		.offset	= 0x0,
-+		.size	= 0x20000,
-+	},
-+	{
-+		.name	= "uboot_env",
-+		.offset	= 0x20000,
-+		.size	= 0x10000,
-+	},
-+	{
-+		.name	= "linux",
-+		.offset	= 0x30000,
-+		.size	= 0x3c0000,
-+	},
-+	{
-+		.name	= "board_config",
-+		.offset	= 0x3f0000,
-+		.size	= 0x10000,
-+	},
-+};
-+
-+static struct mtd_partition arv75xx_partitions[] =
-+{
-+	{
-+		.name	= "uboot",
-+		.offset	= 0x0,
-+		.size	= 0x10000,
-+	},
-+	{
-+		.name	= "uboot_env",
-+		.offset	= 0x10000,
-+		.size	= 0x10000,
-+	},
-+	{
-+		.name	= "linux",
-+		.offset	= 0x20000,
-+		.size	= 0x7d0000,
-+	},
-+	{
-+		.name	= "board_config",
-+		.offset	= 0x7f0000,
-+		.size	= 0x10000,
-+	},
-+};
-+
-+static struct physmap_flash_data arv4510_flash_data = {
-+	.nr_parts	= ARRAY_SIZE(arv4510_partitions),
-+	.parts		= arv4510_partitions,
-+};
-+
-+static struct physmap_flash_data arv45xx_flash_data = {
-+	.nr_parts	= ARRAY_SIZE(arv45xx_partitions),
-+	.parts		= arv45xx_partitions,
-+};
-+
-+static struct physmap_flash_data arv75xx_flash_data = {
-+	.nr_parts	= ARRAY_SIZE(arv75xx_partitions),
-+	.parts		= arv75xx_partitions,
-+};
-+
-+static struct ltq_pci_data ltq_pci_data = {
-+	.clock  = PCI_CLOCK_EXT,
-+	.gpio   = PCI_GNT1 | PCI_REQ1,
-+	.irq    = {
-+		[14] = INT_NUM_IM0_IRL0 + 22,
-+	},
-+};
-+
-+static struct ltq_eth_data ltq_eth_data = {
-+	.mii_mode	= PHY_INTERFACE_MODE_RMII,
-+};
-+
-+static struct gpio_led
-+arv4510pw_leds_gpio[] __initdata = {
-+	{ .name = "soc:green:foo", .gpio = 4, .active_low = 1, },
-+};
-+
-+static struct gpio_led
-+arv4518pw_leds_gpio[] __initdata = {
-+	{ .name = "soc:green:power", .gpio = 3, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:green:adsl", .gpio = 4, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:green:internet", .gpio = 5, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:green:wlan", .gpio = 6, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:yellow:wps", .gpio = 7, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:red:fail", .gpio = 8, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:green:usb", .gpio = 19, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:green:voip", .gpio = 72, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:green:fxs1", .gpio = 73, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:green:fxs2", .gpio = 74, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:green:fxo", .gpio = 75, .active_low = 1, .default_trigger = "default-on" },
-+};
-+
-+static struct gpio_button
-+arv4518pw_gpio_buttons[] __initdata = {
-+	{ .desc = "wlan", .type = EV_KEY, .code = BTN_0, .threshold = 3, .gpio = 28, .active_low = 1, },
-+	{ .desc = "wps", .type = EV_KEY, .code = BTN_1, .threshold = 3, .gpio = 29, .active_low = 1, },
-+	{ .desc = "reset", .type = EV_KEY, .code = BTN_2, .threshold = 3, .gpio = 30, .active_low = 1, },
-+};
-+
-+static struct gpio_led
-+arv4520pw_leds_gpio[] __initdata = {
-+	{ .name = "soc:blue:power", .gpio = 3, .active_low = 1, },
-+	{ .name = "soc:blue:adsl", .gpio = 4, .active_low = 1, },
-+	{ .name = "soc:blue:internet", .gpio = 5, .active_low = 1, },
-+	{ .name = "soc:red:power", .gpio = 6, .active_low = 1, },
-+	{ .name = "soc:yellow:wps", .gpio = 7, .active_low = 1, },
-+	{ .name = "soc:red:wps", .gpio = 9, .active_low = 1, },
-+	{ .name = "soc:blue:voip", .gpio = 72, .active_low = 1, },
-+	{ .name = "soc:blue:fxs1", .gpio = 73, .active_low = 1, },
-+	{ .name = "soc:blue:fxs2", .gpio = 74, .active_low = 1, },
-+	{ .name = "soc:blue:fxo", .gpio = 75, .active_low = 1, },
-+	{ .name = "soc:blue:voice", .gpio = 76, .active_low = 1, },
-+	{ .name = "soc:blue:usb", .gpio = 77, .active_low = 1, },
-+	{ .name = "soc:blue:wlan", .gpio = 78, .active_low = 1, },
-+};
-+
-+static struct gpio_led
-+arv452cpw_leds_gpio[] __initdata = {
-+	{ .name = "soc:blue:power", .gpio = 3, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:blue:adsl", .gpio = 4, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:blue:isdn", .gpio = 5, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:red:power", .gpio = 6, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:yellow:wps", .gpio = 7, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:red:wps", .gpio = 9, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:blue:fxs1", .gpio = 72, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:blue:fxs2", .gpio = 73, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:blue:wps", .gpio = 74, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:blue:fxo", .gpio = 75, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:blue:voice", .gpio = 76, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:blue:usb", .gpio = 77, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:blue:wlan", .gpio = 78, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:blue:internet", .gpio = 80, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:red:internet", .gpio = 81, .active_low = 1, .default_trigger = "default-on" },
-+};
-+
-+static struct gpio_led
-+arv4525pw_leds_gpio[] __initdata = {
-+	{ .name = "soc:green:festnetz", .gpio = 4, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:green:internet", .gpio = 5, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:green:dsl", .gpio = 6, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:green:wlan", .gpio = 8, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:green:online", .gpio = 9, .active_low = 1, .default_trigger = "default-on" },
-+};
-+
-+static struct gpio_led
-+arv752dpw22_leds_gpio[] __initdata = {
-+	{ .name = "soc:blue:power", .gpio = 3, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:red:internet", .gpio = 5, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:red:power", .gpio = 6, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:red:wps", .gpio = 8, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:red:fxo", .gpio = 75, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:red:voice", .gpio = 76, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:green:usb", .gpio = 77, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:green:wlan", .gpio = 78, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:green:wlan1", .gpio = 79, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:blue:wlan", .gpio = 80, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:blue:wlan1", .gpio = 81, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:green:eth1", .gpio = 83, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:green:eth2", .gpio = 84, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:green:eth3", .gpio = 85, .active_low = 1, .default_trigger = "default-on" },
-+	{ .name = "soc:green:eth4", .gpio = 86, .active_low = 1, .default_trigger = "default-on", },
-+};
-+
-+static struct gpio_button
-+arv752dpw22_gpio_buttons[] __initdata = {
-+	{ .desc = "btn0", .type = EV_KEY, .code = BTN_0, .threshold = 3, .gpio = 12, .active_low = 1, },
-+	{ .desc = "btn1", .type = EV_KEY, .code = BTN_1, .threshold = 3, .gpio = 13, .active_low = 1, },
-+	{ .desc = "btn2", .type = EV_KEY, .code = BTN_2, .threshold = 3, .gpio = 28, .active_low = 1, },
-+};
-+
-+static struct gpio_led
-+arv7518pw_leds_gpio[] __initdata = {
-+	{ .name = "soc:green:power", .gpio = 2, .active_low = 1, },
-+	{ .name = "soc:green:adsl", .gpio = 4, .active_low = 1, },
-+	{ .name = "soc:green:internet", .gpio = 5, .active_low = 1, },
-+	{ .name = "soc:green:wlan", .gpio = 6, .active_low = 1, },
-+	{ .name = "soc:red:internet", .gpio = 8, .active_low = 1, },
-+	{ .name = "soc:green:usb", .gpio = 19, .active_low = 1, },
-+};
-+
-+static struct gpio_button
-+arv7518pw_gpio_buttons[] __initdata = {
-+	{ .desc = "reset", .type = EV_KEY, .code = BTN_0, .threshold = 3, .gpio = 23, .active_low = 1, },
-+	{ .desc = "wlan", .type = EV_KEY, .code = BTN_1, .threshold = 3, .gpio = 25, .active_low = 1, },
-+};
-+
-+static void
-+arv45xx_register_ethernet(void)
-+{
-+#define ARV45XX_BRN_MAC			0x3f0016
-+	memcpy_fromio(&ltq_eth_data.mac.sa_data,
-+		(void *)KSEG1ADDR(LTQ_FLASH_START + ARV45XX_BRN_MAC), 6);
-+	ltq_register_etop(&ltq_eth_data);
-+}
-+
-+static void
-+arv75xx_register_ethernet(void)
-+{
-+#define ARV75XX_BRN_MAC			0x7f0016
-+	memcpy_fromio(&ltq_eth_data.mac.sa_data,
-+		(void *)KSEG1ADDR(LTQ_FLASH_START + ARV75XX_BRN_MAC), 6);
-+	ltq_register_etop(&ltq_eth_data);
-+}
-+
-+static void
-+bewan_register_ethernet(void)
-+{
-+#define BEWAN_BRN_MAC			0x3f0014
-+	memcpy_fromio(&ltq_eth_data.mac.sa_data,
-+		(void *)KSEG1ADDR(LTQ_FLASH_START + BEWAN_BRN_MAC), 6);
-+	ltq_register_etop(&ltq_eth_data);
-+}
-+
-+static u16 arv45xx_ath5k_eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS];
-+static struct ath5k_platform_data arv45xx_ath5k_platform_data;
-+
-+/*static int arv45xx_pci_plat_dev_init(struct pci_dev *dev)
-+{
-+	dev->dev.platform_data = &arv45xx_ath5k_platform_data;
-+	return 0;
-+}
-+*/
-+void __init
-+arv45xx_register_ath5k(void)
-+{
-+#define ARV45XX_BRN_ATH		0x3f0478
-+	int i;
-+	unsigned char eeprom_mac[6];
-+	static u16 eeprom_data[ATH5K_PLAT_EEP_MAX_WORDS];
-+	u32 *p = (u32*)arv45xx_ath5k_eeprom_data;
-+
-+	memcpy_fromio(eeprom_mac,
-+		(void *)KSEG1ADDR(LTQ_FLASH_START + ARV45XX_BRN_MAC), 6);
-+	eeprom_mac[5]++;
-+	memcpy_fromio(arv45xx_ath5k_eeprom_data,
-+		(void *)KSEG1ADDR(LTQ_FLASH_START + ARV45XX_BRN_ATH), ATH5K_PLAT_EEP_MAX_WORDS);
-+	// swap eeprom bytes
-+	for (i = 0; i < ATH5K_PLAT_EEP_MAX_WORDS>>1; i++){
-+		//arv4518_ath5k_eeprom_data[i] = ((eeprom_data[i]&0xff)<<8)|((eeprom_data[i]&0xff00)>>8);
-+		p[i] = ((eeprom_data[(i<<1)+1]&0xff)<<24)|((eeprom_data[(i<<1)+1]&0xff00)<<8)|((eeprom_data[i<<1]&0xff)<<8)|((eeprom_data[i<<1]&0xff00)>>8);
-+		if (i == 0xbf>>1){
-+			// printk ("regdomain: 0x%x --> 0x%x\n", p[i], (p[i] & 0xffff0000)|0x67);
-+			/* regdomain is invalid?? how did original fw convert 
-+			* value to 0x82d4 ??
-+			* for now, force to 0x67 */
-+			p[i] &= 0xffff0000;
-+			p[i] |= 0x67;
-+		}
-+	}
-+	arv45xx_ath5k_platform_data.eeprom_data = arv45xx_ath5k_eeprom_data;
-+	arv45xx_ath5k_platform_data.macaddr = eeprom_mac;
-+	//lqpci_plat_dev_init = arv45xx_pci_plat_dev_init;
-+}
-+
-+static void __init
-+arv3527p_init(void)
-+{
-+	ltq_register_gpio_stp();
-+	//ltq_add_device_leds_gpio(arv3527p_leds_gpio, ARRAY_SIZE(arv3527p_leds_gpio));
-+	ltq_register_nor(&arv45xx_flash_data);
-+	arv45xx_register_ethernet();
-+}
-+
-+MIPS_MACHINE(LANTIQ_MACH_ARV3527P,
-+			"ARV3527P",
-+			"ARV3527P - Arcor Easybox 401",
-+			arv3527p_init);
-+
-+static void __init
-+arv4510pw_init(void)
-+{
-+	ltq_register_gpio_stp();
-+	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(arv4510pw_leds_gpio), arv4510pw_leds_gpio);
-+	ltq_register_nor(&arv4510_flash_data);
-+	ltq_pci_data.irq[12] = (INT_NUM_IM2_IRL0 + 31);
-+	ltq_pci_data.irq[15] = (INT_NUM_IM0_IRL0 + 26);
-+	ltq_pci_data.gpio |= PCI_EXIN2 | PCI_REQ2;
-+	ltq_register_pci(&ltq_pci_data);
-+	bewan_register_ethernet();
-+}
-+
-+MIPS_MACHINE(LANTIQ_MACH_ARV4510PW,
-+			"ARV4510PW",
-+			"ARV4510PW - Wippies Homebox",
-+			arv4510pw_init);
-+
-+static void __init
-+arv4518pw_init(void)
-+{
-+#define ARV4518PW_EBU			0
-+#define ARV4518PW_USB			14
-+#define ARV4518PW_SWITCH_RESET		13
-+
-+	ltq_register_gpio_ebu(ARV4518PW_EBU);
-+	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(arv4518pw_leds_gpio), arv4518pw_leds_gpio);
-+	ltq_register_gpio_buttons(arv4518pw_gpio_buttons, ARRAY_SIZE(arv4518pw_gpio_buttons));
-+	ltq_register_nor(&arv45xx_flash_data);
-+	ltq_pci_data.gpio = PCI_GNT2 | PCI_REQ2;
-+	ltq_register_pci(&ltq_pci_data);
-+	ltq_register_madwifi_eep();
-+	xway_register_dwc(ARV4518PW_USB);
-+	arv45xx_register_ethernet();
-+	arv45xx_register_ath5k();
-+
-+	gpio_request(ARV4518PW_SWITCH_RESET, "switch");
-+	gpio_direction_output(ARV4518PW_SWITCH_RESET, 1);
-+	gpio_export(ARV4518PW_SWITCH_RESET, 0);
-+}
-+
-+MIPS_MACHINE(LANTIQ_MACH_ARV4518PW,
-+			"ARV4518PW",
-+			"ARV4518PW - SMC7908A-ISP, Airties WAV-221",
-+			arv4518pw_init);
-+
-+static void __init
-+arv4520pw_init(void)
-+{
-+#define ARV4520PW_EBU			0x400
-+#define ARV4520PW_USB			28
-+#define ARV4520PW_SWITCH_RESET		82
-+
-+	ltq_register_gpio_ebu(ARV4520PW_EBU);
-+	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(arv4520pw_leds_gpio), arv4520pw_leds_gpio);
-+	ltq_register_nor(&arv45xx_flash_data);
-+	ltq_register_pci(&ltq_pci_data);
-+	ltq_register_tapi();
-+	arv45xx_register_ethernet();
-+	xway_register_dwc(ARV4520PW_USB);
-+
-+	gpio_request(ARV4520PW_SWITCH_RESET, "switch");
-+	gpio_set_value(ARV4520PW_SWITCH_RESET, 1);
-+}
-+
-+MIPS_MACHINE(LANTIQ_MACH_ARV4520PW,
-+			"ARV4520PW",
-+			"ARV4520PW - Airties WAV-281, Arcor A800",
-+			arv4520pw_init);
-+
-+static void __init
-+arv452Cpw_init(void)
-+{
-+#define ARV452CPW_EBU			0x77f
-+#define ARV452CPW_USB			28
-+#define ARV452CPW_RELAY1		31
-+#define ARV452CPW_RELAY2		79
-+#define ARV452CPW_SWITCH_RESET		82
-+
-+	ltq_register_gpio_ebu(ARV452CPW_EBU);
-+	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(arv452cpw_leds_gpio), arv452cpw_leds_gpio);
-+	ltq_register_nor(&arv45xx_flash_data);
-+	ltq_register_pci(&ltq_pci_data);
-+	ltq_register_madwifi_eep();
-+	xway_register_dwc(ARV452CPW_USB);
-+	arv45xx_register_ethernet();
-+	arv45xx_register_ath5k();
-+
-+	gpio_request(ARV452CPW_SWITCH_RESET, "switch");
-+	gpio_set_value(ARV452CPW_SWITCH_RESET, 1);
-+	gpio_export(ARV452CPW_SWITCH_RESET, 0);
-+
-+	gpio_request(ARV452CPW_RELAY1, "relay1");
-+	gpio_direction_output(ARV452CPW_RELAY1, 1);
-+	gpio_export(ARV452CPW_RELAY1, 0);
-+
-+	gpio_request(ARV452CPW_RELAY2, "relay2");
-+	gpio_set_value(ARV452CPW_RELAY2, 1);
-+	gpio_export(ARV452CPW_RELAY2, 0);
-+}
-+
-+MIPS_MACHINE(LANTIQ_MACH_ARV452CPW,
-+			"ARV452CPW",
-+			"ARV452CPW - Arcor A801",
-+			arv452Cpw_init);
-+
-+static void __init
-+arv4525pw_init(void)
-+{
-+	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(arv4525pw_leds_gpio), arv4525pw_leds_gpio);
-+	ltq_register_nor(&arv45xx_flash_data);
-+	ltq_pci_data.clock = PCI_CLOCK_INT;
-+	ltq_register_pci(&ltq_pci_data);
-+	ltq_register_madwifi_eep();
-+	ltq_eth_data.mii_mode = PHY_INTERFACE_MODE_MII;
-+	arv45xx_register_ethernet();
-+}
-+
-+MIPS_MACHINE(LANTIQ_MACH_ARV4525PW,
-+			"ARV4525PW",
-+			"ARV4525PW - Speedport W502V",
-+			arv4525pw_init);
-+
-+static void __init
-+arv7518pw_init(void)
-+{
-+#define ARV7518PW_EBU			0x2
-+#define ARV7518PW_USB			14
-+
-+	ltq_register_gpio_ebu(ARV7518PW_EBU);
-+	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(arv7518pw_leds_gpio), arv7518pw_leds_gpio);
-+	ltq_register_gpio_buttons(arv7518pw_gpio_buttons, ARRAY_SIZE(arv7518pw_gpio_buttons));
-+	ltq_register_nor(&arv75xx_flash_data);
-+	ltq_register_pci(&ltq_pci_data);
-+	ltq_register_tapi();
-+	xway_register_dwc(ARV7518PW_USB);
-+	arv75xx_register_ethernet();
-+	//arv7518_register_ath9k(mac);
-+}
-+
-+MIPS_MACHINE(LANTIQ_MACH_ARV7518PW,
-+			"ARV7518PW",
-+			"ARV7518PW - ASTORIA",
-+			arv7518pw_init);
-+
-+static void __init
-+arv752dpw22_init(void)
-+{
-+#define ARV752DPW22_EBU			0x2
-+#define ARV752DPW22_USB			72
-+#define ARV752DPW22_RELAY		73
-+
-+	ltq_register_gpio_ebu(ARV752DPW22_EBU);
-+	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(arv752dpw22_leds_gpio), arv752dpw22_leds_gpio);
-+	ltq_register_gpio_buttons(arv752dpw22_gpio_buttons, ARRAY_SIZE(arv752dpw22_gpio_buttons));
-+	ltq_register_nor(&arv75xx_flash_data);
-+	ltq_pci_data.irq[15] = (INT_NUM_IM2_IRL0 + 31);
-+	ltq_pci_data.gpio |= PCI_EXIN1 | PCI_REQ2;
-+	ltq_register_pci(&ltq_pci_data);
-+	xway_register_dwc(ARV752DPW22_USB);
-+	arv75xx_register_ethernet();
-+
-+	gpio_request(ARV752DPW22_RELAY, "relay");
-+	gpio_set_value(ARV752DPW22_RELAY, 1);
-+	gpio_export(ARV752DPW22_RELAY, 0);
-+}
-+
-+MIPS_MACHINE(LANTIQ_MACH_ARV752DPW22,
-+			"ARV752DPW22",
-+			"ARV752DPW22 - Arcor A803",
-+			arv752dpw22_init);
---- a/arch/mips/lantiq/machtypes.h
-+++ b/arch/mips/lantiq/machtypes.h
-@@ -22,6 +22,17 @@ enum lantiq_mach_type {
- 	LANTIQ_MACH_EASY98000NAND,	/* Falcon Eval Board, NAND Flash */
- 	LANTIQ_MACH_EASY98020,		/* Falcon Reference Board */
- 	LANTIQ_MACH_95C3AM1,		/* Board 95C3AM1 */
-+
-+	/* Arcadyan */
-+	LANTIQ_MACH_ARV3527P,		/* Arcor easybox a401 */
-+	LANTIQ_MACH_ARV4510PW,		/* Wippies Homebox */
-+	LANTIQ_MACH_ARV4518PW,		/* Airties WAV-221, SMC-7908A-ISP */
-+	LANTIQ_MACH_ARV4520PW,		/* Airties WAV-281, Arcor EasyboxA800 */
-+	LANTIQ_MACH_ARV452CPW,		/* Arcor EasyboxA801 */
-+	LANTIQ_MACH_ARV4525PW,		/* Speedport W502V */
-+	LANTIQ_MACH_ARV752DPW,		/* Arcor easybox a802 */
-+	LANTIQ_MACH_ARV752DPW22,	/* Arcor easybox a803 */
-+	LANTIQ_MACH_ARV7518PW,		/* ASTORIA */
- };
- 
- #endif
diff --git a/target/linux/lantiq/patches-3.0/460-mach-dgn3500.patch b/target/linux/lantiq/patches-3.0/460-mach-dgn3500.patch
deleted file mode 100644
index dc904255f2..0000000000
--- a/target/linux/lantiq/patches-3.0/460-mach-dgn3500.patch
+++ /dev/null
@@ -1,92 +0,0 @@
---- a/arch/mips/lantiq/machtypes.h
-+++ b/arch/mips/lantiq/machtypes.h
-@@ -33,6 +33,9 @@ enum lantiq_mach_type {
- 	LANTIQ_MACH_ARV752DPW,		/* Arcor easybox a802 */
- 	LANTIQ_MACH_ARV752DPW22,	/* Arcor easybox a803 */
- 	LANTIQ_MACH_ARV7518PW,		/* ASTORIA */
-+
-+	/* Netgear */
-+	LANTIQ_MACH_DGN3500B,		/* Netgear DGN3500 */
- };
- 
- #endif
---- a/arch/mips/lantiq/xway/Kconfig
-+++ b/arch/mips/lantiq/xway/Kconfig
-@@ -10,6 +10,10 @@ config LANTIQ_MACH_ARV45XX
- 	bool "ARV45XX"
- 	default y
- 
-+config LANTIQ_MACH_NETGEAR
-+	bool "Netgear"
-+	default y
-+
- endmenu
- 
- endif
---- a/arch/mips/lantiq/xway/Makefile
-+++ b/arch/mips/lantiq/xway/Makefile
-@@ -6,3 +6,4 @@ obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o
- obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
- obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
- obj-$(CONFIG_LANTIQ_MACH_ARV45XX) += mach-arv45xx.o
-+obj-$(CONFIG_LANTIQ_MACH_NETGEAR) += mach-netgear.o
---- /dev/null
-+++ b/arch/mips/lantiq/xway/mach-netgear.c
-@@ -0,0 +1,57 @@
-+/*
-+ *  This program is free software; you can redistribute it and/or modify it
-+ *  under the terms of the GNU General Public License version 2 as published
-+ *  by the Free Software Foundation.
-+ *
-+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/mtd/physmap.h>
-+#include <linux/input.h>
-+#include <linux/phy.h>
-+#include <linux/spi/spi.h>
-+
-+#include <lantiq_soc.h>
-+#include <irq.h>
-+
-+#include "../machtypes.h"
-+#include "devices.h"
-+
-+static struct ltq_pci_data ltq_pci_data = {
-+	.clock	= PCI_CLOCK_INT,
-+	.gpio	= PCI_GNT1 | PCI_REQ1,
-+	.irq	= {
-+		[14] = INT_NUM_IM0_IRL0 + 22,
-+	},
-+};
-+
-+static struct ltq_eth_data ltq_eth_data = {
-+	.mii_mode = PHY_INTERFACE_MODE_MII,
-+};
-+
-+struct spi_board_info spi_info = {
-+	.bus_num        = 0,
-+	.chip_select    = 3,
-+	.max_speed_hz   = 25000000,
-+	.modalias       = "mx25l12805d",
-+};
-+
-+struct ltq_spi_platform_data ltq_spi_data = {
-+	.num_chipselect = 4,
-+};
-+
-+static void __init dgn3500_init(void)
-+{
-+	ltq_register_pci(&ltq_pci_data);
-+	ltq_register_etop(&ltq_eth_data);
-+	ltq_register_spi(&ltq_spi_data, &spi_info, 1);
-+}
-+
-+MIPS_MACHINE(LANTIQ_MACH_DGN3500B,
-+	     "DGN3500B",
-+	     "Netgear DGN3500B",
-+	      dgn3500_init);
diff --git a/target/linux/lantiq/patches-3.0/470-mach-gigasx76x.patch b/target/linux/lantiq/patches-3.0/470-mach-gigasx76x.patch
deleted file mode 100644
index 2c55032a62..0000000000
--- a/target/linux/lantiq/patches-3.0/470-mach-gigasx76x.patch
+++ /dev/null
@@ -1,144 +0,0 @@
---- a/arch/mips/lantiq/xway/Kconfig
-+++ b/arch/mips/lantiq/xway/Kconfig
-@@ -14,6 +14,10 @@ config LANTIQ_MACH_NETGEAR
- 	bool "Netgear"
- 	default y
- 
-+config LANTIQ_MACH_GIGASX76X
-+	bool "GIGASX76X"
-+	default y
-+
- endmenu
- 
- endif
---- a/arch/mips/lantiq/xway/Makefile
-+++ b/arch/mips/lantiq/xway/Makefile
-@@ -7,3 +7,4 @@ obj-$(CONFIG_LANTIQ_MACH_EASY50712) += m
- obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
- obj-$(CONFIG_LANTIQ_MACH_ARV45XX) += mach-arv45xx.o
- obj-$(CONFIG_LANTIQ_MACH_NETGEAR) += mach-netgear.o
-+obj-$(CONFIG_LANTIQ_MACH_GIGASX76X) += mach-gigasx76x.o
---- /dev/null
-+++ b/arch/mips/lantiq/xway/mach-gigasx76x.c
-@@ -0,0 +1,109 @@
-+/*
-+ *  This program is free software; you can redistribute it and/or modify it
-+ *  under the terms of the GNU General Public License version 2 as published
-+ *  by the Free Software Foundation.
-+ *
-+ *  Copyright (C) 2011 Andrej Vlašić
-+ *  Copyright (C) 2011 Luka Perkov
-+ *
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/platform_device.h>
-+#include <linux/leds.h>
-+#include <linux/gpio.h>
-+#include <linux/gpio_buttons.h>
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/mtd/physmap.h>
-+#include <linux/input.h>
-+#include <linux/ath5k_platform.h>
-+#include <linux/pci.h>
-+#include <linux/phy.h>
-+
-+#include <irq.h>
-+
-+#include <lantiq_soc.h>
-+#include <lantiq_platform.h>
-+
-+#include "../machtypes.h"
-+#include "devices.h"
-+#include "dev-dwc_otg.h"
-+#include "dev-leds-gpio.h"
-+
-+static struct mtd_partition gigasx76x_partitions[] =
-+{
-+	{
-+		.name	= "secondary_env",
-+		.offset	= 0xe000,
-+		.size	= 0x2000,
-+	},
-+	{
-+		.name	= "secondary_boot",
-+		.offset	= 0x10000,
-+		.size	= 0x10000,
-+	},
-+	{
-+		.name	= "uboot",
-+		.offset	= 0x20000,
-+		.size	= 0x30000,
-+	},
-+	{
-+		.name	= "linux",
-+		.offset	= 0x50000,
-+		.size	= 0x7a0000,
-+	},
-+	{
-+		.name	= "board_config",
-+		.offset	= 0x7f0000,
-+		.size	= 0x10000,
-+	},
-+};
-+
-+static struct gpio_led
-+gigasx76x_leds_gpio[] __initdata = {
-+	{ .name = "soc:green:usb", .gpio = 50, },
-+	{ .name = "soc:green:wlan", .gpio = 51, },
-+	{ .name = "soc:green:phone2", .gpio = 52, },
-+	{ .name = "soc:green:phone1", .gpio = 53, },
-+	{ .name = "soc:green:line", .gpio = 54, },
-+	{ .name = "soc:green:online", .gpio = 55, },
-+};
-+
-+
-+static struct physmap_flash_data gigasx76x_flash_data = {
-+	.nr_parts	= ARRAY_SIZE(gigasx76x_partitions),
-+	.parts		= gigasx76x_partitions,
-+};
-+
-+static struct ltq_pci_data ltq_pci_data = {
-+	.clock      = PCI_CLOCK_INT,
-+	.gpio   = PCI_GNT1 | PCI_REQ1,
-+	.irq    = {
-+		[14] = INT_NUM_IM0_IRL0 + 22,
-+	},
-+};
-+
-+static struct ltq_eth_data ltq_eth_data = {
-+  .mii_mode = PHY_INTERFACE_MODE_MII,
-+};
-+
-+static void __init
-+gigasx76x_init(void)
-+{
-+#define GIGASX76X_USB			29
-+
-+	ltq_register_gpio_stp();
-+	ltq_register_nor(&gigasx76x_flash_data);
-+	ltq_register_pci(&ltq_pci_data);
-+	ltq_register_etop(&ltq_eth_data);
-+	xway_register_dwc(GIGASX76X_USB);
-+	ltq_register_tapi();
-+	ltq_register_madwifi_eep();
-+	ltq_add_device_leds_gpio(-1, ARRAY_SIZE(gigasx76x_leds_gpio), gigasx76x_leds_gpio);
-+}
-+
-+MIPS_MACHINE(LANTIQ_MACH_GIGASX76X,
-+			"GIGASX76X",
-+			"GIGASX76X - Gigaset SX761,SX762,SX763",
-+			gigasx76x_init);
---- a/arch/mips/lantiq/machtypes.h
-+++ b/arch/mips/lantiq/machtypes.h
-@@ -36,6 +36,9 @@ enum lantiq_mach_type {
- 
- 	/* Netgear */
- 	LANTIQ_MACH_DGN3500B,		/* Netgear DGN3500 */
-+
-+	/* Gigaset */
-+	LANTIQ_MACH_GIGASX76X,		/* Gigaset SX76x */
- };
- 
- #endif
diff --git a/target/linux/lantiq/patches-3.0/480-mach-easy98020.patch b/target/linux/lantiq/patches-3.0/480-mach-easy98020.patch
deleted file mode 100644
index 46bd9db146..0000000000
--- a/target/linux/lantiq/patches-3.0/480-mach-easy98020.patch
+++ /dev/null
@@ -1,27 +0,0 @@
---- a/arch/mips/lantiq/falcon/mach-easy98020.c
-+++ b/arch/mips/lantiq/falcon/mach-easy98020.c
-@@ -111,3 +111,13 @@ MIPS_MACHINE(LANTIQ_MACH_EASY98020,
- 			"EASY98020",
- 			"EASY98020 Eval Board",
- 			easy98020_init);
-+
-+MIPS_MACHINE(LANTIQ_MACH_EASY98020_1LAN,
-+			"EASY98020_1LAN",
-+			"EASY98020 Eval Board (1 LAN port)",
-+			easy98020_init);
-+
-+MIPS_MACHINE(LANTIQ_MACH_EASY98020_2LAN,
-+			"EASY98020_2LAN",
-+			"EASY98020 Eval Board (2 LAN ports)",
-+			easy98020_init);
---- a/arch/mips/lantiq/machtypes.h
-+++ b/arch/mips/lantiq/machtypes.h
-@@ -21,6 +21,8 @@ enum lantiq_mach_type {
- 	LANTIQ_MACH_EASY98000SF,	/* Falcon Eval Board, Serial Flash */
- 	LANTIQ_MACH_EASY98000NAND,	/* Falcon Eval Board, NAND Flash */
- 	LANTIQ_MACH_EASY98020,		/* Falcon Reference Board */
-+	LANTIQ_MACH_EASY98020_1LAN,	/* Falcon Reference Board (1 LAN port) */
-+	LANTIQ_MACH_EASY98020_2LAN,	/* Falcon Reference Board (2 LAN ports) */
- 	LANTIQ_MACH_95C3AM1,		/* Board 95C3AM1 */
- 
- 	/* Arcadyan */
diff --git a/target/linux/lantiq/patches-3.0/510-register_madwifi.patch b/target/linux/lantiq/patches-3.0/510-register_madwifi.patch
deleted file mode 100644
index 9a8575fa7e..0000000000
--- a/target/linux/lantiq/patches-3.0/510-register_madwifi.patch
+++ /dev/null
@@ -1,28 +0,0 @@
---- a/arch/mips/lantiq/xway/devices.c
-+++ b/arch/mips/lantiq/xway/devices.c
-@@ -121,6 +121,16 @@ ltq_register_etop(struct ltq_eth_data *e
- 	}
- }
- 
-+/* madwifi */
-+int lantiq_emulate_madwifi_eep = 0;
-+EXPORT_SYMBOL(lantiq_emulate_madwifi_eep);
-+
-+void __init
-+ltq_register_madwifi_eep(void)
-+{
-+	lantiq_emulate_madwifi_eep = 1;
-+}
-+
- static struct resource ltq_spi_resources[] = {
- 	{
- 		.start  = LTQ_SSC_BASE_ADDR,
---- a/arch/mips/lantiq/xway/devices.h
-+++ b/arch/mips/lantiq/xway/devices.h
-@@ -19,5 +19,6 @@ extern void ltq_register_ase_asc(void);
- extern void ltq_register_etop(struct ltq_eth_data *eth);
- extern void ltq_register_spi(struct ltq_spi_platform_data *pdata,
- 	struct spi_board_info const *info, unsigned n);
-+extern void ltq_register_madwifi_eep(void);
- 
- #endif
diff --git a/target/linux/lantiq/patches-3.0/520-register_buttons.patch b/target/linux/lantiq/patches-3.0/520-register_buttons.patch
deleted file mode 100644
index df48d7cfd9..0000000000
--- a/target/linux/lantiq/patches-3.0/520-register_buttons.patch
+++ /dev/null
@@ -1,46 +0,0 @@
---- a/arch/mips/lantiq/xway/devices.c
-+++ b/arch/mips/lantiq/xway/devices.c
-@@ -131,6 +131,26 @@ ltq_register_madwifi_eep(void)
- 	lantiq_emulate_madwifi_eep = 1;
- }
- 
-+/* gpio buttons */
-+static struct gpio_buttons_platform_data ltq_gpio_buttons_platform_data;
-+
-+static struct platform_device ltq_gpio_buttons_platform_device =
-+{
-+	.name = "gpio-buttons",
-+	.id = 0,
-+	.dev = {
-+		.platform_data = (void *) &ltq_gpio_buttons_platform_data,
-+	},
-+};
-+
-+void __init
-+ltq_register_gpio_buttons(struct gpio_button *buttons, int cnt)
-+{
-+	ltq_gpio_buttons_platform_data.buttons = buttons;
-+	ltq_gpio_buttons_platform_data.nbuttons = cnt;
-+	platform_device_register(&ltq_gpio_buttons_platform_device);
-+}
-+
- static struct resource ltq_spi_resources[] = {
- 	{
- 		.start  = LTQ_SSC_BASE_ADDR,
---- a/arch/mips/lantiq/xway/devices.h
-+++ b/arch/mips/lantiq/xway/devices.h
-@@ -12,6 +12,7 @@
- #include "../devices.h"
- #include <linux/phy.h>
- #include <linux/spi/spi.h>
-+#include <linux/gpio_buttons.h>
- 
- extern void ltq_register_gpio(void);
- extern void ltq_register_gpio_stp(void);
-@@ -20,5 +21,6 @@ extern void ltq_register_etop(struct ltq
- extern void ltq_register_spi(struct ltq_spi_platform_data *pdata,
- 	struct spi_board_info const *info, unsigned n);
- extern void ltq_register_madwifi_eep(void);
-+extern void ltq_register_gpio_buttons(struct gpio_button *buttons, int cnt);
- 
- #endif
diff --git a/target/linux/lantiq/patches-3.0/530-register_tapi.patch b/target/linux/lantiq/patches-3.0/530-register_tapi.patch
deleted file mode 100644
index e2b0b30649..0000000000
--- a/target/linux/lantiq/patches-3.0/530-register_tapi.patch
+++ /dev/null
@@ -1,42 +0,0 @@
---- a/arch/mips/lantiq/devices.c
-+++ b/arch/mips/lantiq/devices.c
-@@ -120,3 +120,20 @@ void __init ltq_register_pci(struct ltq_
- 	pr_err("kernel is compiled without PCI support\n");
- }
- #endif
-+
-+static unsigned int *cp1_base = 0;
-+unsigned int*
-+ltq_get_cp1_base(void)
-+{
-+	return cp1_base;
-+}
-+EXPORT_SYMBOL(ltq_get_cp1_base);
-+
-+void __init
-+ltq_register_tapi(void)
-+{
-+#define CP1_SIZE       (1 << 20)
-+	dma_addr_t dma;
-+	cp1_base =
-+		(void*)CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE, &dma, GFP_ATOMIC));
-+}
---- a/arch/mips/lantiq/devices.h
-+++ b/arch/mips/lantiq/devices.h
-@@ -19,5 +19,6 @@ extern void ltq_register_nor(struct phys
- extern void ltq_register_wdt(void);
- extern void ltq_register_asc(int port);
- extern void ltq_register_pci(struct ltq_pci_data *data);
-+extern void ltq_register_tapi(void);
- 
- #endif
---- a/arch/mips/lantiq/xway/mach-easy50712.c
-+++ b/arch/mips/lantiq/xway/mach-easy50712.c
-@@ -61,6 +61,7 @@ static void __init easy50712_init(void)
- 	ltq_register_nor(&easy50712_flash_data);
- 	ltq_register_pci(&ltq_pci_data);
- 	ltq_register_etop(&ltq_eth_data);
-+	ltq_register_tapi();
- }
- 
- MIPS_MACHINE(LTQ_MACH_EASY50712,
diff --git a/target/linux/lantiq/patches-3.0/540-dev-leds-gpio.patch b/target/linux/lantiq/patches-3.0/540-dev-leds-gpio.patch
deleted file mode 100644
index a66dc0d858..0000000000
--- a/target/linux/lantiq/patches-3.0/540-dev-leds-gpio.patch
+++ /dev/null
@@ -1,95 +0,0 @@
---- /dev/null
-+++ b/arch/mips/include/asm/mach-lantiq/dev-leds-gpio.h
-@@ -0,0 +1,21 @@
-+/*
-+ *  Lantiq GPIO LED device support
-+ *
-+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
-+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ *  This program is free software; you can redistribute it and/or modify it
-+ *  under the terms of the GNU General Public License version 2 as published
-+ *  by the Free Software Foundation.
-+ */
-+
-+#ifndef _LANTIQ_DEV_LEDS_GPIO_H
-+#define _LANTIQ_DEV_LEDS_GPIO_H
-+
-+#include <linux/leds.h>
-+
-+void ltq_add_device_leds_gpio(int id,
-+				 unsigned num_leds,
-+				 struct gpio_led *leds) __init;
-+
-+#endif /* _LANTIQ_DEV_LEDS_GPIO_H */
---- /dev/null
-+++ b/arch/mips/lantiq/dev-leds-gpio.c
-@@ -0,0 +1,57 @@
-+/*
-+ *  Lantiq GPIO LED device support
-+ *
-+ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
-+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
-+ *
-+ *  Parts of this file are based on Atheros' 2.6.15 BSP
-+ *
-+ *  This program is free software; you can redistribute it and/or modify it
-+ *  under the terms of the GNU General Public License version 2 as published
-+ *  by the Free Software Foundation.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/slab.h>
-+#include <linux/platform_device.h>
-+
-+#include "dev-leds-gpio.h"
-+
-+void __init ltq_add_device_leds_gpio(int id, unsigned num_leds,
-+					struct gpio_led *leds)
-+{
-+	struct platform_device *pdev;
-+	struct gpio_led_platform_data pdata;
-+	struct gpio_led *p;
-+	int err;
-+
-+	p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL);
-+	if (!p)
-+		return;
-+
-+	memcpy(p, leds, num_leds * sizeof(*p));
-+
-+	pdev = platform_device_alloc("leds-gpio", id);
-+	if (!pdev)
-+		goto err_free_leds;
-+
-+	memset(&pdata, 0, sizeof(pdata));
-+	pdata.num_leds = num_leds;
-+	pdata.leds = p;
-+
-+	err = platform_device_add_data(pdev, &pdata, sizeof(pdata));
-+	if (err)
-+		goto err_put_pdev;
-+
-+	err = platform_device_add(pdev);
-+	if (err)
-+		goto err_put_pdev;
-+
-+	return;
-+
-+err_put_pdev:
-+	platform_device_put(pdev);
-+
-+err_free_leds:
-+	kfree(p);
-+}
---- a/arch/mips/lantiq/Makefile
-+++ b/arch/mips/lantiq/Makefile
-@@ -4,7 +4,7 @@
- # under the terms of the GNU General Public License version 2 as published
- # by the Free Software Foundation.
- 
--obj-y := irq.o setup.o clk.o prom.o devices.o
-+obj-y := irq.o setup.o clk.o prom.o devices.o dev-leds-gpio.o
- 
- obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
- 
diff --git a/target/linux/lantiq/patches-3.0/550-register_ebu.patch b/target/linux/lantiq/patches-3.0/550-register_ebu.patch
deleted file mode 100644
index 564c166000..0000000000
--- a/target/linux/lantiq/patches-3.0/550-register_ebu.patch
+++ /dev/null
@@ -1,42 +0,0 @@
---- a/arch/mips/lantiq/xway/devices.c
-+++ b/arch/mips/lantiq/xway/devices.c
-@@ -151,6 +151,29 @@ ltq_register_gpio_buttons(struct gpio_bu
- 	platform_device_register(&ltq_gpio_buttons_platform_device);
- }
- 
-+/* ebu */
-+static struct resource ltq_ebu_resource =
-+{
-+	.name   = "gpio_ebu",
-+	.start  = LTQ_EBU_GPIO_START,
-+	.end    = LTQ_EBU_GPIO_START + LTQ_EBU_GPIO_SIZE - 1,
-+	.flags  = IORESOURCE_MEM,
-+};
-+
-+static struct platform_device ltq_ebu =
-+{
-+	.name           = "ltq_ebu",
-+	.resource       = &ltq_ebu_resource,
-+	.num_resources  = 1,
-+};
-+
-+void __init
-+ltq_register_gpio_ebu(unsigned int value)
-+{
-+	ltq_ebu.dev.platform_data = (void*) value;
-+	platform_device_register(&ltq_ebu);
-+}
-+
- static struct resource ltq_spi_resources[] = {
- 	{
- 		.start  = LTQ_SSC_BASE_ADDR,
---- a/arch/mips/lantiq/xway/devices.h
-+++ b/arch/mips/lantiq/xway/devices.h
-@@ -16,6 +16,7 @@
- 
- extern void ltq_register_gpio(void);
- extern void ltq_register_gpio_stp(void);
-+extern void ltq_register_gpio_ebu(unsigned int value);
- extern void ltq_register_ase_asc(void);
- extern void ltq_register_etop(struct ltq_eth_data *eth);
- extern void ltq_register_spi(struct ltq_spi_platform_data *pdata,
diff --git a/target/linux/lantiq/patches-3.0/800-fix-etop.patch b/target/linux/lantiq/patches-3.0/800-fix-etop.patch
new file mode 100644
index 0000000000..c92e08e708
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/800-fix-etop.patch
@@ -0,0 +1,69 @@
+Index: linux-3.0.3/drivers/net/lantiq_etop.c
+===================================================================
+--- linux-3.0.3.orig/drivers/net/lantiq_etop.c	2011-10-07 11:03:00.140000754 +0200
++++ linux-3.0.3/drivers/net/lantiq_etop.c	2011-10-07 11:03:06.088001008 +0200
+@@ -397,7 +397,10 @@
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+ 
+-	return phy_ethtool_gset(priv->phydev, cmd);
++	if (priv->phydev)
++		return phy_ethtool_gset(priv->phydev, cmd);
++	else
++		return 0;
+ }
+ 
+ static int
+@@ -405,7 +408,10 @@
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+ 
+-	return phy_ethtool_sset(priv->phydev, cmd);
++	if (priv->phydev)
++		return phy_ethtool_sset(priv->phydev, cmd);
++	else
++		return 0;
+ }
+ 
+ static int
+@@ -413,7 +419,10 @@
+ {
+ 	struct ltq_etop_priv *priv = netdev_priv(dev);
+ 
+-	return phy_start_aneg(priv->phydev);
++	if (priv->phydev)
++		return phy_start_aneg(priv->phydev);
++	else
++		return 0;
+ }
+ 
+ static const struct ethtool_ops ltq_etop_ethtool_ops = {
+@@ -615,7 +624,8 @@
+ 		ltq_dma_open(&ch->dma);
+ 		napi_enable(&ch->napi);
+ 	}
+-	phy_start(priv->phydev);
++	if (priv->phydev)
++		phy_start(priv->phydev);
+ 	netif_tx_start_all_queues(dev);
+ 	return 0;
+ }
+@@ -627,7 +637,8 @@
+ 	int i;
+ 
+ 	netif_tx_stop_all_queues(dev);
+-	phy_stop(priv->phydev);
++	if (priv->phydev)
++		phy_stop(priv->phydev);
+ 	for (i = 0; i < MAX_DMA_CHAN; i++) {
+ 		struct ltq_etop_chan *ch = &priv->ch[i];
+ 
+@@ -775,7 +786,7 @@
+ 	ltq_etop_set_multicast_list(dev);
+ 	err = ltq_etop_mdio_init(dev);
+ 	if (err)
+-		goto err_netdev;
++		pr_warn("etop: mdio probe failed\n");;
+ 	return 0;
+ 
+ err_netdev:
diff --git a/target/linux/lantiq/patches-3.0/990-fix-asc-drv-timeout.patch b/target/linux/lantiq/patches-3.0/990-backport-3.1-fix-asc-drv-timeout.patch
index ccc01a772d..ccc01a772d 100644
--- a/target/linux/lantiq/patches-3.0/990-fix-asc-drv-timeout.patch
+++ b/target/linux/lantiq/patches-3.0/990-backport-3.1-fix-asc-drv-timeout.patch
diff --git a/target/linux/lantiq/patches-3.0/990-fix-early_printk.patch b/target/linux/lantiq/patches-3.0/990-fix-early_printk.patch
deleted file mode 100644
index 3b3b856907..0000000000
--- a/target/linux/lantiq/patches-3.0/990-fix-early_printk.patch
+++ /dev/null
@@ -1,26 +0,0 @@
---- a/arch/mips/lantiq/early_printk.c
-+++ b/arch/mips/lantiq/early_printk.c
-@@ -20,7 +20,12 @@
- #endif
- #define ASC_BUF		1024
- #define LTQ_ASC_FSTAT	((u32 *)(LTQ_ASC_BASE + 0x0048))
--#define LTQ_ASC_TBUF	((u32 *)(LTQ_ASC_BASE + 0x0020))
-+#ifdef __BIG_ENDIAN
-+#define LTQ_ASC_TBUF	((u8 *)(LTQ_ASC_BASE + 0x0023))
-+#else
-+#define LTQ_ASC_TBUF	((u8 *)(LTQ_ASC_BASE + 0x0020))
-+#endif
-+
- #define TXMASK		0x3F00
- #define TXOFFSET	8
- 
-@@ -30,8 +35,6 @@ void prom_putchar(char c)
- 
- 	local_irq_save(flags);
- 	do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET);
--	if (c == '\n')
--		ltq_w32('\r', LTQ_ASC_TBUF);
--	ltq_w32(c, LTQ_ASC_TBUF);
-+	ltq_w8(c, LTQ_ASC_TBUF);
- 	local_irq_restore(flags);
- }
diff --git a/target/linux/lantiq/patches-3.0/991-backport-3.1-fix-eiu.patch b/target/linux/lantiq/patches-3.0/991-backport-3.1-fix-eiu.patch
new file mode 100644
index 0000000000..03663b50db
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/991-backport-3.1-fix-eiu.patch
@@ -0,0 +1,20 @@
+--- a/arch/mips/lantiq/irq.c
++++ b/arch/mips/lantiq/irq.c
+@@ -132,7 +132,7 @@
+ static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
+ {
+ 	int i;
+-	int irq_nr = d->irq - INT_NUM_IRQ0;
++	int irq_nr = d->irq;
+ 
+ 	ltq_enable_irq(d);
+ 	for (i = 0; i < MAX_EIU; i++) {
+@@ -156,7 +156,7 @@
+ static void ltq_shutdown_eiu_irq(struct irq_data *d)
+ {
+ 	int i;
+-	int irq_nr = d->irq - INT_NUM_IRQ0;
++	int irq_nr = d->irq;
+ 
+ 	ltq_disable_irq(d);
+ 	for (i = 0; i < MAX_EIU; i++) {
diff --git a/target/linux/lantiq/patches-3.0/992-backport-3.1-fix-pci.patch b/target/linux/lantiq/patches-3.0/992-backport-3.1-fix-pci.patch
new file mode 100644
index 0000000000..94a3bc7516
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/992-backport-3.1-fix-pci.patch
@@ -0,0 +1,18 @@
+--- a/arch/mips/pci/pci-lantiq.c
++++ b/arch/mips/pci/pci-lantiq.c
+@@ -171,8 +171,13 @@
+ 	u32 temp_buffer;
+ 
+ 	/* set clock to 33Mhz */
+-	ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR);
+-	ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR);
++	if (ltq_is_ar9()) {
++		ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0x1f00000, LTQ_CGU_IFCCR);
++		ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0xe00000, LTQ_CGU_IFCCR);
++	} else {
++		ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR);
++		ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR);
++	}
+ 
+ 	/* external or internal clock ? */
+ 	if (conf->clock) {
diff --git a/target/linux/lantiq/patches-3.0/993-backport-3.1-fix-mtd.patch b/target/linux/lantiq/patches-3.0/993-backport-3.1-fix-mtd.patch
new file mode 100644
index 0000000000..8a59616425
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/993-backport-3.1-fix-mtd.patch
@@ -0,0 +1,13 @@
+Index: linux-3.0.3/drivers/mtd/maps/lantiq-flash.c
+===================================================================
+--- linux-3.0.3.orig/drivers/mtd/maps/lantiq-flash.c	2011-08-17 19:57:16.000000000 +0200
++++ linux-3.0.3/drivers/mtd/maps/lantiq-flash.c	2011-09-29 20:45:14.785132132 +0200
+@@ -20,6 +20,8 @@
+ #include <linux/platform_device.h>
+ #include <linux/mtd/physmap.h>
+ 
++#include "../mtdcore.h"
++
+ #include <lantiq_soc.h>
+ #include <lantiq_platform.h>
+ 
diff --git a/target/linux/lantiq/patches-3.0/994-backport-3.1-fix-clk.patch b/target/linux/lantiq/patches-3.0/994-backport-3.1-fix-clk.patch
new file mode 100644
index 0000000000..8f72b4e106
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/994-backport-3.1-fix-clk.patch
@@ -0,0 +1,22 @@
+Index: linux-3.0.3/arch/mips/lantiq/clk.c
+===================================================================
+--- linux-3.0.3.orig/arch/mips/lantiq/clk.c	2011-09-29 20:43:07.000000000 +0200
++++ linux-3.0.3/arch/mips/lantiq/clk.c	2011-09-29 20:45:14.785132132 +0200
+@@ -91,6 +91,17 @@
+ }
+ EXPORT_SYMBOL(clk_put);
+ 
++int clk_enable(struct clk *clk)
++{
++	/* clocks are always enabled*/
++	return 0;
++}
++
++void clk_disable(struct clk *clk)
++{
++	/* clocks are always enabled*/
++}
++
+ static inline u32 ltq_get_counter_resolution(void)
+ {
+ 	u32 res;
diff --git a/target/linux/lantiq/patches-3.0/995-backport-3.1-lookup_resource.patch b/target/linux/lantiq/patches-3.0/995-backport-3.1-lookup_resource.patch
new file mode 100644
index 0000000000..76c7135c09
--- /dev/null
+++ b/target/linux/lantiq/patches-3.0/995-backport-3.1-lookup_resource.patch
@@ -0,0 +1,56 @@
+commit 1c388919d89ca35741e9c4d3255adf87f76f0c06
+Author: Geert Uytterhoeven <geert@linux-m68k.org>
+Date:   Sat May 7 20:53:16 2011 +0200
+
+    resources: Add lookup_resource()
+    
+    Add a function to find an existing resource by a resource start address.
+    This allows to implement simple allocators (with a malloc/free-alike API)
+    on top of the resource system.
+    
+    Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
+
+diff --git a/include/linux/ioport.h b/include/linux/ioport.h
+index e9bb22c..63eb429 100644
+--- a/include/linux/ioport.h
++++ b/include/linux/ioport.h
+@@ -132,6 +132,7 @@ extern int allocate_resource(struct resource *root, struct resource *new,
+ 						       resource_size_t,
+ 						       resource_size_t),
+ 			     void *alignf_data);
++struct resource *lookup_resource(struct resource *root, resource_size_t start);
+ int adjust_resource(struct resource *res, resource_size_t start,
+ 		    resource_size_t size);
+ resource_size_t resource_alignment(struct resource *res);
+diff --git a/kernel/resource.c b/kernel/resource.c
+index 3ff4017..3b3cedc 100644
+--- a/kernel/resource.c
++++ b/kernel/resource.c
+@@ -553,6 +553,27 @@ int allocate_resource(struct resource *root, struct resource *new,
+ 
+ EXPORT_SYMBOL(allocate_resource);
+ 
++/**
++ * lookup_resource - find an existing resource by a resource start address
++ * @root: root resource descriptor
++ * @start: resource start address
++ *
++ * Returns a pointer to the resource if found, NULL otherwise
++ */
++struct resource *lookup_resource(struct resource *root, resource_size_t start)
++{
++	struct resource *res;
++
++	read_lock(&resource_lock);
++	for (res = root->child; res; res = res->sibling) {
++		if (res->start == start)
++			break;
++	}
++	read_unlock(&resource_lock);
++
++	return res;
++}
++
+ /*
+  * Insert a resource into the resource tree. If successful, return NULL,
+  * otherwise return the conflicting resource (compare to __request_resource())
diff --git a/target/linux/lantiq/patches-3.0/998-easy98000-asc1.patch b/target/linux/lantiq/patches-3.0/998-easy98000-asc1.patch
deleted file mode 100644
index 6d6aea86ee..0000000000
--- a/target/linux/lantiq/patches-3.0/998-easy98000-asc1.patch
+++ /dev/null
@@ -1,59 +0,0 @@
-activate serial driver for ASC1 if "use_asc1=x" is given on kernel commandline
-mux setup for pins is done via late_initcall, when the gpio driver is initialized
-
-only implemented for EASY98000, generic version t.b.d.
---- a/arch/mips/lantiq/falcon/devices.c
-+++ b/arch/mips/lantiq/falcon/devices.c
-@@ -75,6 +75,7 @@ void __init falcon_register_asc(int port
- 	case 1:
- 		platform_device_register_simple("ltq_asc", 1,
- 			falcon_asc1_resources, ARRAY_SIZE(falcon_asc1_resources));
-+		sys1_hw_activate(ACTS_ASC1_ACT);
- 		break;
- 	default:
- 		break;
---- a/arch/mips/lantiq/falcon/mach-easy98000.c
-+++ b/arch/mips/lantiq/falcon/mach-easy98000.c
-@@ -15,6 +15,7 @@
- #include <linux/spi/spi.h>
- #include <linux/spi/spi_gpio.h>
- #include <linux/spi/eeprom.h>
-+#include <falcon/lantiq_soc.h>
- 
- #include "../machtypes.h"
- 
-@@ -206,9 +207,34 @@ static void __init easy98000_spi_gpio_in
- 	platform_device_register(&easy98000_spi_gpio_device);
- }
- 
-+static int register_asc1 = 0;
-+static int __init parse_asc1(char *p)
-+{
-+	register_asc1 = 1;
-+	return 0;
-+}
-+__setup("use_asc1", parse_asc1);
-+
-+#define MUXC_SIF_RX_PIN		112
-+#define MUXC_SIF_TX_PIN		113
-+
-+static int __init asc1_mux_setup(void)
-+{
-+	if (register_asc1) {
-+		if (ltq_gpio_request(MUXC_SIF_RX_PIN, 1, 1, 0, "asc1-rx"))
-+			return -1;
-+		if (ltq_gpio_request(MUXC_SIF_TX_PIN, 1, 1, 1, "asc1-tx"))
-+			return -1;
-+	}
-+	return 0;
-+}
-+late_initcall(asc1_mux_setup);
-+
- static void __init easy98000_init_common(void)
- {
- 	falcon_register_asc(0);
-+	if (register_asc1)
-+		falcon_register_asc(1);
- 	falcon_register_gpio();
- 	falcon_register_wdt();
- 	falcon_register_i2c();
diff --git a/target/linux/lantiq/danube/config-3.0 b/target/linux/lantiq/vr9/config-default
index 4ea6189bbd..c2fc00146b 100644
--- a/target/linux/lantiq/danube/config-3.0
+++ b/target/linux/lantiq/vr9/config-default
@@ -24,10 +24,7 @@ CONFIG_INPUT_EVDEV=y
 CONFIG_INPUT_POLLDEV=y
 # CONFIG_ISDN is not set
 CONFIG_LANTIQ_ETOP=y
-CONFIG_LANTIQ_MACH_ARV45XX=y
-CONFIG_LANTIQ_MACH_EASY50712=y
-# CONFIG_LANTIQ_MACH_NETGEAR is not set
-CONFIG_LANTIQ_MACH_GIGASX76X=y
+CONFIG_LANTIQ_MACH_FRITZ3370=y
 CONFIG_MACH_NO_WESTBRIDGE=y
 # CONFIG_MINIX_FS_NATIVE_ENDIAN is not set
 CONFIG_NEED_DMA_MAP_STATE=y
@@ -39,9 +36,10 @@ CONFIG_PERF_USE_VMALLOC=y
 # CONFIG_QUOTACTL is not set
 CONFIG_RTL8306_PHY=y
 # CONFIG_SOC_AMAZON_SE is not set
+CONFIG_SOC_VR9=y
 # CONFIG_SOC_FALCON is not set
 CONFIG_SOC_TYPE_XWAY=y
-CONFIG_SOC_XWAY=y
+# CONFIG_SOC_XWAY is not set
 CONFIG_SPI=y
 CONFIG_SPI_BITBANG=y
 # CONFIG_SPI_GPIO is not set
@@ -49,3 +47,4 @@ CONFIG_SPI_LANTIQ=y
 CONFIG_SPI_MASTER=y
 CONFIG_USB_SUPPORT=y
 CONFIG_XZ_DEC=y
+CONFIG_SPI_XWAY=y
diff --git a/target/linux/lantiq/vr9/profiles/000-generic.mk b/target/linux/lantiq/vr9/profiles/000-generic.mk
new file mode 100644
index 0000000000..787a74fba2
--- /dev/null
+++ b/target/linux/lantiq/vr9/profiles/000-generic.mk
@@ -0,0 +1,6 @@
+define Profile/Generic
+  NAME:=Generic - all boards
+  PACKAGES:=kmod-leds-gpio button-hotplug
+endef
+
+$(eval $(call Profile,Generic))
diff --git a/target/linux/lantiq/vr9/target.mk b/target/linux/lantiq/vr9/target.mk
new file mode 100644
index 0000000000..b2e8dfcc44
--- /dev/null
+++ b/target/linux/lantiq/vr9/target.mk
@@ -0,0 +1,10 @@
+ARCH:=mips
+SUBTARGET:=vr9
+BOARDNAME:=VR9
+FEATURES:=squashfs jffs2 atm
+
+DEFAULT_PACKAGES+=kmod-pppoa ppp-mod-pppoa linux-atm atm-tools br2684ctl kmod-ltq-dsl-vr9 ltq-dsl-app swconfig
+
+define Target/Description
+	Lantiq VR9
+endef