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| author | Hauke Mehrtens <hauke@hauke-m.de> | 2017-07-15 18:41:57 +0200 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2017-09-18 18:36:26 +0200 |
| commit | 1422d4435b173d0c80289327095026d7da44b5f1 (patch) | |
| tree | a601e1e0f9a435acde64fc498bb54c2ee865dbf8 /package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch | |
| parent | ea9fab904bcb71033e71b819328d97a6e2b3de36 (diff) | |
| download | upstream-1422d4435b173d0c80289327095026d7da44b5f1.tar.gz upstream-1422d4435b173d0c80289327095026d7da44b5f1.tar.bz2 upstream-1422d4435b173d0c80289327095026d7da44b5f1.zip | |
uboot-sunxi: update to version 2017.07
The deleted patches are already integrated in the upstream U-Boot
version.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Diffstat (limited to 'package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch')
| -rw-r--r-- | package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch b/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch index a402feb3cd..40d79878ad 100644 --- a/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch +++ b/package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch @@ -12,9 +12,9 @@ More specifically, the following settings are now used: * up to 1152MHz: mul=3, div=2 (unchanged) * above 1152MHz: mul=4, div=2 (was: mul=2, div=1) ---- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c -+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c -@@ -122,11 +122,12 @@ void clock_set_pll1(unsigned int clk) +--- a/arch/arm/mach-sunxi/clock_sun6i.c ++++ b/arch/arm/mach-sunxi/clock_sun6i.c +@@ -107,11 +107,12 @@ void clock_set_pll1(unsigned int clk) struct sunxi_ccm_reg * const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; const int p = 0; |