diff options
| author | David Bauer <mail@david-bauer.net> | 2022-03-27 23:12:39 +0200 |
|---|---|---|
| committer | David Bauer <mail@david-bauer.net> | 2022-03-30 17:28:39 +0200 |
| commit | 9a0155bc4fa3642cdf930d50098bc929173f170f (patch) | |
| tree | 3e1387b63be3e1fc8124d5b447d35b1d6273fcc7 /target/linux/ath79/patches-5.15/0039-MIPS-ath79-export-UART1-reference-clock.patch | |
| parent | fc94c0d203d1c97d3dfdd045fb57b1cb7826e491 (diff) | |
| download | upstream-9a0155bc4fa3642cdf930d50098bc929173f170f.tar.gz upstream-9a0155bc4fa3642cdf930d50098bc929173f170f.tar.bz2 upstream-9a0155bc4fa3642cdf930d50098bc929173f170f.zip | |
ath79: add 5.15 support for generic subtarget
Add Kernel 5.15 patches + config. This is currently only available for
the generic subtarget, as it was exclusively tested with this target.
Tested-on: Siemens WS-AP3610, Enterasys WS-AP3705i
Signed-off-by: David Bauer <mail@david-bauer.net>
Diffstat (limited to 'target/linux/ath79/patches-5.15/0039-MIPS-ath79-export-UART1-reference-clock.patch')
| -rw-r--r-- | target/linux/ath79/patches-5.15/0039-MIPS-ath79-export-UART1-reference-clock.patch | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/target/linux/ath79/patches-5.15/0039-MIPS-ath79-export-UART1-reference-clock.patch b/target/linux/ath79/patches-5.15/0039-MIPS-ath79-export-UART1-reference-clock.patch new file mode 100644 index 0000000000..edf888c7e7 --- /dev/null +++ b/target/linux/ath79/patches-5.15/0039-MIPS-ath79-export-UART1-reference-clock.patch @@ -0,0 +1,52 @@ +--- a/arch/mips/ath79/clock.c ++++ b/arch/mips/ath79/clock.c +@@ -40,6 +40,7 @@ static const char * const clk_names[ATH7 + [ATH79_CLK_AHB] = "ahb", + [ATH79_CLK_REF] = "ref", + [ATH79_CLK_MDIO] = "mdio", ++ [ATH79_CLK_UART1] = "uart1", + }; + + static const char * __init ath79_clk_name(int type) +@@ -344,6 +345,9 @@ static void __init ar934x_clocks_init(vo + if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) + ath79_set_clk(ATH79_CLK_MDIO, 100 * 1000 * 1000); + ++ if (clk_ctrl & AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL) ++ ath79_set_clk(ATH79_CLK_UART1, 100 * 1000 * 1000); ++ + iounmap(dpll_base); + } + +@@ -649,6 +653,9 @@ static void __init ath79_clocks_init_dt( + if (!clks[ATH79_CLK_MDIO]) + clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF]; + ++ if (!clks[ATH79_CLK_UART1]) ++ clks[ATH79_CLK_UART1] = clks[ATH79_CLK_REF]; ++ + if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) { + pr_err("%pOF: could not register clk provider\n", np); + goto err_iounmap; +--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h ++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h +@@ -348,6 +348,7 @@ + #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24) + + #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6) ++#define AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL BIT(7) + + #define QCA953X_PLL_CPU_CONFIG_REG 0x00 + #define QCA953X_PLL_DDR_CONFIG_REG 0x04 +--- a/include/dt-bindings/clock/ath79-clk.h ++++ b/include/dt-bindings/clock/ath79-clk.h +@@ -11,7 +11,8 @@ + #define ATH79_CLK_AHB 2 + #define ATH79_CLK_REF 3 + #define ATH79_CLK_MDIO 4 ++#define ATH79_CLK_UART1 5 + +-#define ATH79_CLK_END 5 ++#define ATH79_CLK_END 6 + + #endif /* __DT_BINDINGS_ATH79_CLK_H */ |