ath79: add 5.15 support for generic subtarget

Add Kernel 5.15 patches + config. This is currently only available for
the generic subtarget, as it was exclusively tested with this target.

Tested-on: Siemens WS-AP3610, Enterasys WS-AP3705i

Signed-off-by: David Bauer <mail@david-bauer.net>

1 files changed, 68 insertions, 0 deletions

diff --git a/target/linux/ath79/patches-5.15/410-spi-ath79-Implement-the-spi_mem-interface.patch b/target/linux/ath79/patches-5.15/410-spi-ath79-Implement-the-spi_mem-interface.patch
new file mode 100644
index 0000000000..5746a889e8
--- /dev/null
+++ b/target/linux/ath79/patches-5.15/410-spi-ath79-Implement-the-spi_mem-interface.patch
@@ -0,0 +1,68 @@
+From 8d8cdb4a6ccee5b62cc0dc64651c3946364514dc Mon Sep 17 00:00:00 2001
+From: Luiz Angelo Daros de Luca <luizluca@gmail.com>
+Date: Mon, 10 Feb 2020 16:11:27 -0300
+Subject: [PATCH] spi: ath79: Implement the spi_mem interface
+
+Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
+---
+ drivers/spi/spi-ath79.c | 35 +++++++++++++++++++++++++++++++++++
+ 1 file changed, 35 insertions(+)
+
+--- a/drivers/spi/spi-ath79.c
++++ b/drivers/spi/spi-ath79.c
+@@ -15,6 +15,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/io.h>
+ #include <linux/spi/spi.h>
++#include <linux/spi/spi-mem.h>
+ #include <linux/spi/spi_bitbang.h>
+ #include <linux/bitops.h>
+ #include <linux/clk.h>
+@@ -133,6 +134,39 @@ static u32 ath79_spi_txrx_mode0(struct s
+ 	return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
+ }
+ 
++static int ath79_exec_mem_op(struct spi_mem *mem,
++                              const struct spi_mem_op *op)
++{
++	struct ath79_spi *sp = ath79_spidev_to_sp(mem->spi);
++
++	/* Ensures that reading is performed on device connected
++	   to hardware cs0 */
++	if (mem->spi->chip_select || mem->spi->cs_gpiod)
++		return -ENOTSUPP;
++
++	/* Only use for fast-read op. */
++	if (op->cmd.opcode != 0x0b || op->data.dir != SPI_MEM_DATA_IN ||
++	    op->addr.nbytes != 3 || op->dummy.nbytes != 1)
++		return -ENOTSUPP;
++
++	/* disable GPIO mode */
++	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
++
++	memcpy_fromio(op->data.buf.in, sp->base + op->addr.val, op->data.nbytes);
++
++	/* enable GPIO mode */
++	ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
++
++	/* restore IOC register */
++	ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
++
++	return 0;
++}
++
++static const struct spi_controller_mem_ops ath79_mem_ops = {
++	.exec_op = ath79_exec_mem_op,
++};
++
+ static int ath79_spi_probe(struct platform_device *pdev)
+ {
+ 	struct spi_master *master;
+@@ -165,6 +199,7 @@ static int ath79_spi_probe(struct platfo
+ 		ret = PTR_ERR(sp->base);
+ 		goto err_put_master;
+ 	}
++	master->mem_ops = &ath79_mem_ops;
+ 
+ 	sp->clk = devm_clk_get(&pdev->dev, "ahb");
+ 	if (IS_ERR(sp->clk)) {