diff options
| author | Hauke Mehrtens <hauke@hauke-m.de> | 2020-11-06 20:43:38 +0100 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2020-11-11 00:49:38 +0100 |
| commit | 3a8cfabe0cd11612f776f6e8adec2f17e71e0987 (patch) | |
| tree | 80f1ce94c966186648b5e64a9b342d14eaa1b467 /target/linux/brcm2708/patches-4.9/950-0155-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch | |
| parent | 9cdc02be88d5c25791664b1baaf9a7c1a4382c95 (diff) | |
| download | upstream-3a8cfabe0cd11612f776f6e8adec2f17e71e0987.tar.gz upstream-3a8cfabe0cd11612f776f6e8adec2f17e71e0987.tar.bz2 upstream-3a8cfabe0cd11612f776f6e8adec2f17e71e0987.zip | |
kernel: Update kernel 4.9 to version 4.9.243
Compile and runtime tested on lantiq/xrx200.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Diffstat (limited to 'target/linux/brcm2708/patches-4.9/950-0155-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch')
| -rw-r--r-- | target/linux/brcm2708/patches-4.9/950-0155-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/target/linux/brcm2708/patches-4.9/950-0155-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch b/target/linux/brcm2708/patches-4.9/950-0155-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch index 842e57676b..d4932bd034 100644 --- a/target/linux/brcm2708/patches-4.9/950-0155-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch +++ b/target/linux/brcm2708/patches-4.9/950-0155-clk-bcm2835-Don-t-rate-change-PLLs-on-behalf-of-DSI-.patch @@ -31,7 +31,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> }; struct bcm2835_clock_data { -@@ -1258,7 +1259,7 @@ bcm2835_register_pll_divider(struct bcm2 +@@ -1260,7 +1261,7 @@ bcm2835_register_pll_divider(struct bcm2 init.num_parents = 1; init.name = divider_name; init.ops = &bcm2835_pll_divider_clk_ops; @@ -40,7 +40,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL); if (!divider) -@@ -1481,7 +1482,8 @@ static const struct bcm2835_clk_desc clk +@@ -1483,7 +1484,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLA_CORE, .load_mask = CM_PLLA_LOADCORE, .hold_mask = CM_PLLA_HOLDCORE, @@ -50,7 +50,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [BCM2835_PLLA_PER] = REGISTER_PLL_DIV( .name = "plla_per", .source_pll = "plla", -@@ -1489,7 +1491,8 @@ static const struct bcm2835_clk_desc clk +@@ -1491,7 +1493,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLA_PER, .load_mask = CM_PLLA_LOADPER, .hold_mask = CM_PLLA_HOLDPER, @@ -60,7 +60,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( .name = "plla_dsi0", .source_pll = "plla", -@@ -1505,7 +1508,8 @@ static const struct bcm2835_clk_desc clk +@@ -1507,7 +1510,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLA_CCP2, .load_mask = CM_PLLA_LOADCCP2, .hold_mask = CM_PLLA_HOLDCCP2, @@ -70,7 +70,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> /* PLLB is used for the ARM's clock. */ [BCM2835_PLLB] = REGISTER_PLL( -@@ -1529,7 +1533,8 @@ static const struct bcm2835_clk_desc clk +@@ -1531,7 +1535,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLB_ARM, .load_mask = CM_PLLB_LOADARM, .hold_mask = CM_PLLB_HOLDARM, @@ -80,7 +80,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> /* * PLLC is the core PLL, used to drive the core VPU clock. -@@ -1558,7 +1563,8 @@ static const struct bcm2835_clk_desc clk +@@ -1560,7 +1565,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLC_CORE0, .load_mask = CM_PLLC_LOADCORE0, .hold_mask = CM_PLLC_HOLDCORE0, @@ -90,7 +90,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV( .name = "pllc_core1", .source_pll = "pllc", -@@ -1566,7 +1572,8 @@ static const struct bcm2835_clk_desc clk +@@ -1568,7 +1574,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLC_CORE1, .load_mask = CM_PLLC_LOADCORE1, .hold_mask = CM_PLLC_HOLDCORE1, @@ -100,7 +100,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV( .name = "pllc_core2", .source_pll = "pllc", -@@ -1574,7 +1581,8 @@ static const struct bcm2835_clk_desc clk +@@ -1576,7 +1583,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLC_CORE2, .load_mask = CM_PLLC_LOADCORE2, .hold_mask = CM_PLLC_HOLDCORE2, @@ -110,7 +110,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [BCM2835_PLLC_PER] = REGISTER_PLL_DIV( .name = "pllc_per", .source_pll = "pllc", -@@ -1582,7 +1590,8 @@ static const struct bcm2835_clk_desc clk +@@ -1584,7 +1592,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLC_PER, .load_mask = CM_PLLC_LOADPER, .hold_mask = CM_PLLC_HOLDPER, @@ -120,7 +120,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> /* * PLLD is the display PLL, used to drive DSI display panels. -@@ -1611,7 +1620,8 @@ static const struct bcm2835_clk_desc clk +@@ -1613,7 +1622,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLD_CORE, .load_mask = CM_PLLD_LOADCORE, .hold_mask = CM_PLLD_HOLDCORE, @@ -130,7 +130,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [BCM2835_PLLD_PER] = REGISTER_PLL_DIV( .name = "plld_per", .source_pll = "plld", -@@ -1619,7 +1629,8 @@ static const struct bcm2835_clk_desc clk +@@ -1621,7 +1631,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLD_PER, .load_mask = CM_PLLD_LOADPER, .hold_mask = CM_PLLD_HOLDPER, @@ -140,7 +140,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV( .name = "plld_dsi0", .source_pll = "plld", -@@ -1664,7 +1675,8 @@ static const struct bcm2835_clk_desc clk +@@ -1666,7 +1677,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLH_RCAL, .load_mask = CM_PLLH_LOADRCAL, .hold_mask = 0, @@ -150,7 +150,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV( .name = "pllh_aux", .source_pll = "pllh", -@@ -1672,7 +1684,8 @@ static const struct bcm2835_clk_desc clk +@@ -1674,7 +1686,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLH_AUX, .load_mask = CM_PLLH_LOADAUX, .hold_mask = 0, @@ -160,7 +160,7 @@ Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV( .name = "pllh_pix", .source_pll = "pllh", -@@ -1680,7 +1693,8 @@ static const struct bcm2835_clk_desc clk +@@ -1682,7 +1695,8 @@ static const struct bcm2835_clk_desc clk .a2w_reg = A2W_PLLH_PIX, .load_mask = CM_PLLH_LOADPIX, .hold_mask = 0, |