diff options
| author | Daniel Golle <daniel@makrotopia.org> | 2022-08-15 18:50:10 +0200 |
|---|---|---|
| committer | Daniel Golle <daniel@makrotopia.org> | 2022-08-30 13:36:28 +0100 |
| commit | e504fdae4e1d0e7ae112828ec9f71db6f9821c71 (patch) | |
| tree | f1e506330f0eeeba45f69c0b774ed17773e1cecd /target/linux/generic/pending-5.15/725-net-mtk_sgmii-fix-powering-up-the-SGMII-phy.patch | |
| parent | aab466f422500842adb62ddb7b1357e2e123ebb2 (diff) | |
| download | upstream-e504fdae4e1d0e7ae112828ec9f71db6f9821c71.tar.gz upstream-e504fdae4e1d0e7ae112828ec9f71db6f9821c71.tar.bz2 upstream-e504fdae4e1d0e7ae112828ec9f71db6f9821c71.zip | |
kernel: add pending mtk_sgmii and phy improvements from @lynxis
Add pending patches from Alexander 'lynxis' Couzens which are required
for RealTek NBase-T PHYs or SFP+ cages to work when connected to the
SGMII interface provided by recent MediaTek SoCs [1].
The patches for MT753x fix link speed limitation on CPU ports observed
by many users which is due to reset being carried out wrongly [2].
[1]: https://patchwork.kernel.org/project/netdevbpf/list/?series=669488&state=*
[2]: https://patchwork.kernel.org/project/netdevbpf/list/?series=669486&state=*
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Diffstat (limited to 'target/linux/generic/pending-5.15/725-net-mtk_sgmii-fix-powering-up-the-SGMII-phy.patch')
| -rw-r--r-- | target/linux/generic/pending-5.15/725-net-mtk_sgmii-fix-powering-up-the-SGMII-phy.patch | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/target/linux/generic/pending-5.15/725-net-mtk_sgmii-fix-powering-up-the-SGMII-phy.patch b/target/linux/generic/pending-5.15/725-net-mtk_sgmii-fix-powering-up-the-SGMII-phy.patch new file mode 100644 index 0000000000..0fa357d48f --- /dev/null +++ b/target/linux/generic/pending-5.15/725-net-mtk_sgmii-fix-powering-up-the-SGMII-phy.patch @@ -0,0 +1,39 @@ +From 7f75f43fe2159123baa101fcc8c6faa0b0a4c598 Mon Sep 17 00:00:00 2001 +From: Alexander Couzens <lynxis@fe80.eu> +Date: Sat, 13 Aug 2022 14:48:51 +0200 +Subject: [PATCH 05/10] net: mtk_sgmii: fix powering up the SGMII phy + +There are certain race condition when the SGMII_PHYA_PWD register still +contains 0x9 which prevents the SGMII from working properly. + +The SGMII still shows link but no traffic can flow. + +Signed-off-by: Alexander Couzens <lynxis@fe80.eu> +--- + drivers/net/ethernet/mediatek/mtk_sgmii.c | 8 ++------ + 1 file changed, 2 insertions(+), 6 deletions(-) + +--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c ++++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c +@@ -36,9 +36,7 @@ static int mtk_pcs_setup_mode_an(struct + val |= SGMII_AN_RESTART; + regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val); + +- regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val); +- val &= ~SGMII_PHYA_PWD; +- regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val); ++ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0); + + return 0; + +@@ -70,9 +68,7 @@ static int mtk_pcs_setup_mode_force(stru + regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val); + + /* Release PHYA power down state */ +- regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val); +- val &= ~SGMII_PHYA_PWD; +- regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val); ++ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0); + + return 0; + } |